diff options
Diffstat (limited to 'contrib/llvm/lib/CodeGen/DFAPacketizer.cpp')
| -rw-r--r-- | contrib/llvm/lib/CodeGen/DFAPacketizer.cpp | 89 | 
1 files changed, 43 insertions, 46 deletions
diff --git a/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp b/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp index 7b1b2d64fccc..853b9afa1026 100644 --- a/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp +++ b/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp @@ -23,49 +23,59 @@  //  //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "packets" -  #include "llvm/CodeGen/DFAPacketizer.h" +#include "llvm/CodeGen/MachineFunction.h"  #include "llvm/CodeGen/MachineInstr.h"  #include "llvm/CodeGen/MachineInstrBundle.h" +#include "llvm/CodeGen/ScheduleDAG.h"  #include "llvm/CodeGen/ScheduleDAGInstrs.h" +#include "llvm/MC/MCInstrDesc.h"  #include "llvm/MC/MCInstrItineraries.h" -#include "llvm/Target/TargetInstrInfo.h"  #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetSubtargetInfo.h" +#include <algorithm> +#include <cassert> +#include <iterator> +#include <memory> +#include <vector>  using namespace llvm; +#define DEBUG_TYPE "packets" +  static cl::opt<unsigned> InstrLimit("dfa-instr-limit", cl::Hidden,    cl::init(0), cl::desc("If present, stops packetizing after N instructions")); +  static unsigned InstrCount = 0;  // --------------------------------------------------------------------  // Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp -namespace { -  DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) { -    return (Inp << DFA_MAX_RESOURCES) | FuncUnits; -  } +static DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) { +  return (Inp << DFA_MAX_RESOURCES) | FuncUnits; +} -  /// Return the DFAInput for an instruction class input vector. -  /// This function is used in both DFAPacketizer.cpp and in -  /// DFAPacketizerEmitter.cpp. -  DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) { -    DFAInput InsnInput = 0; -    assert((InsnClass.size() <= DFA_MAX_RESTERMS) && -           "Exceeded maximum number of DFA terms"); -    for (auto U : InsnClass) -      InsnInput = addDFAFuncUnits(InsnInput, U); -    return InsnInput; -  } +/// Return the DFAInput for an instruction class input vector. +/// This function is used in both DFAPacketizer.cpp and in +/// DFAPacketizerEmitter.cpp. +static DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) { +  DFAInput InsnInput = 0; +  assert((InsnClass.size() <= DFA_MAX_RESTERMS) && +         "Exceeded maximum number of DFA terms"); +  for (auto U : InsnClass) +    InsnInput = addDFAFuncUnits(InsnInput, U); +  return InsnInput;  } +  // --------------------------------------------------------------------  DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,                               const DFAStateInput (*SIT)[2],                               const unsigned *SET): -  InstrItins(I), CurrentState(0), DFAStateInputTable(SIT), -  DFAStateEntryTable(SET) { +  InstrItins(I), DFAStateInputTable(SIT), DFAStateEntryTable(SET) {    // Make sure DFA types are large enough for the number of terms & resources.    static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <=                      (8 * sizeof(DFAInput)), @@ -75,7 +85,6 @@ DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,        "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");  } -  // Read the DFA transition table and update CachedTable.  //  // Format of the transition tables: @@ -97,7 +106,6 @@ void DFAPacketizer::ReadTable(unsigned int state) {        DFAStateInputTable[i][1];  } -  // Return the DFAInput for an instruction class.  DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {    // Note: this logic must match that in DFAPacketizerDefs.h for input vectors. @@ -112,16 +120,14 @@ DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {    return InsnInput;  } -  // Return the DFAInput for an instruction class input vector.  DFAInput DFAPacketizer::getInsnInput(const std::vector<unsigned> &InsnClass) {    return getDFAInsnInput(InsnClass);  } -  // Check if the resources occupied by a MCInstrDesc are available in the  // current state. -bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { +bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) {    unsigned InsnClass = MID->getSchedClass();    DFAInput InsnInput = getInsnInput(InsnClass);    UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput); @@ -129,10 +135,9 @@ bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {    return CachedTable.count(StateTrans) != 0;  } -  // Reserve the resources occupied by a MCInstrDesc and change the current  // state to reflect that change. -void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { +void DFAPacketizer::reserveResources(const MCInstrDesc *MID) {    unsigned InsnClass = MID->getSchedClass();    DFAInput InsnInput = getInsnInput(InsnClass);    UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput); @@ -141,24 +146,22 @@ void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {    CurrentState = CachedTable[StateTrans];  } -  // Check if the resources occupied by a machine instruction are available  // in the current state. -bool DFAPacketizer::canReserveResources(llvm::MachineInstr &MI) { -  const llvm::MCInstrDesc &MID = MI.getDesc(); +bool DFAPacketizer::canReserveResources(MachineInstr &MI) { +  const MCInstrDesc &MID = MI.getDesc();    return canReserveResources(&MID);  } -  // Reserve the resources occupied by a machine instruction and change the  // current state to reflect that change. -void DFAPacketizer::reserveResources(llvm::MachineInstr &MI) { -  const llvm::MCInstrDesc &MID = MI.getDesc(); +void DFAPacketizer::reserveResources(MachineInstr &MI) { +  const MCInstrDesc &MID = MI.getDesc();    reserveResources(&MID);  } -  namespace llvm { +  // This class extends ScheduleDAGInstrs and overrides the schedule method  // to build the dependence graph.  class DefaultVLIWScheduler : public ScheduleDAGInstrs { @@ -166,9 +169,11 @@ private:    AliasAnalysis *AA;    /// Ordered list of DAG postprocessing steps.    std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations; +  public:    DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,                         AliasAnalysis *AA); +    // Actual scheduling work.    void schedule() override; @@ -176,11 +181,12 @@ public:    void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {      Mutations.push_back(std::move(Mutation));    } +  protected:    void postprocessDAG();  }; -} +} // end namespace llvm  DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,                                             MachineLoopInfo &MLI, @@ -189,21 +195,18 @@ DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,    CanHandleTerminators = true;  } -  /// Apply each ScheduleDAGMutation step in order.  void DefaultVLIWScheduler::postprocessDAG() {    for (auto &M : Mutations)      M->apply(this);  } -  void DefaultVLIWScheduler::schedule() {    // Build the scheduling graph.    buildSchedGraph(AA);    postprocessDAG();  } -  VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,                                         MachineLoopInfo &mli, AliasAnalysis *aa)      : MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) { @@ -211,15 +214,11 @@ VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,    VLIWScheduler = new DefaultVLIWScheduler(MF, mli, AA);  } -  VLIWPacketizerList::~VLIWPacketizerList() { -  if (VLIWScheduler) -    delete VLIWScheduler; -  if (ResourceTracker) -    delete ResourceTracker; +  delete VLIWScheduler; +  delete ResourceTracker;  } -  // End the current packet, bundle packet instructions and reset DFA state.  void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,                                     MachineBasicBlock::iterator MI) { @@ -239,7 +238,6 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,    DEBUG(dbgs() << "End packet\n");  } -  // Bundle machine instructions into packets.  void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,                                        MachineBasicBlock::iterator BeginItr, @@ -338,7 +336,6 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,    VLIWScheduler->finishBlock();  } -  // Add a DAG mutation object to the ordered list.  void VLIWPacketizerList::addMutation(        std::unique_ptr<ScheduleDAGMutation> Mutation) {  | 
