diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp | 254 |
1 files changed, 215 insertions, 39 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp index 4738a4d32409..29c044b3b729 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -27,6 +27,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/Pass.h" @@ -78,7 +79,9 @@ private: using MISetType = DenseSet<MachineInstr *>; using InstrEvalMap = DenseMap<MachineInstr *, bool>; + MachineRegisterInfo *MRI = nullptr; const HexagonInstrInfo *HII = nullptr; + const HexagonRegisterInfo *HRI = nullptr; MachineDominatorTree *MDT = nullptr; DataFlowGraph *DFG = nullptr; DataFlowGraph::DefStackMap DefM; @@ -88,11 +91,16 @@ private: bool processBlock(NodeAddr<BlockNode *> BA); bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI, NodeAddr<UseNode *> UseN, unsigned UseMOnum); + bool processAddUses(NodeAddr<StmtNode *> AddSN, MachineInstr *AddMI, + const NodeList &UNodeList); + bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI); bool analyzeUses(unsigned DefR, const NodeList &UNodeList, InstrEvalMap &InstrEvalResult, short &SizeInc); bool hasRepForm(MachineInstr &MI, unsigned TfrDefR); bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr &MI, const NodeList &UNodeList); + bool isSafeToExtLR(NodeAddr<StmtNode *> SN, MachineInstr *MI, + unsigned LRExtReg, const NodeList &UNodeList); void getAllRealUses(NodeAddr<StmtNode *> SN, NodeList &UNodeList); bool allValidCandidates(NodeAddr<StmtNode *> SA, NodeList &UNodeList); short getBaseWithLongOffset(const MachineInstr &MI) const; @@ -101,6 +109,7 @@ private: bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum); bool changeAddAsl(NodeAddr<UseNode *> AddAslUN, MachineInstr *AddAslMI, const MachineOperand &ImmOp, unsigned ImmOpNum); + bool isValidOffset(MachineInstr *MI, int Offset); }; } // end anonymous namespace @@ -208,7 +217,7 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, NodeSet Visited, Defs; const auto &P = LV->getAllReachingDefsRec(UR, UN, Visited, Defs); if (!P.second) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Unable to collect all reaching defs for use ***\n" << PrintNode<UseNode*>(UN, *DFG) << '\n' << "The program's complexity may exceed the limits.\n"; @@ -217,7 +226,7 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, } const auto &ReachingDefs = P.first; if (ReachingDefs.size() > 1) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Multiple Reaching Defs found!!! ***\n"; for (auto DI : ReachingDefs) { NodeAddr<UseNode *> DA = DFG->addr<UseNode *>(DI); @@ -235,15 +244,15 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, NodeList &UNodeList) { for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) { - DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG) - << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[DefNode]: " + << Print<NodeAddr<DefNode *>>(DA, *DFG) << "\n"); RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG)); auto UseSet = LV->getAllReachedUses(DR, DA); for (auto UI : UseSet) { NodeAddr<UseNode *> UA = DFG->addr<UseNode *>(UI); - DEBUG({ + LLVM_DEBUG({ NodeAddr<StmtNode *> TempIA = UA.Addr->getOwner(*DFG); dbgs() << "\t\t\t[Reached Use]: " << Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n"; @@ -253,8 +262,8 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, NodeAddr<PhiNode *> PA = UA.Addr->getOwner(*DFG); NodeId id = PA.Id; const Liveness::RefMap &phiUse = LV->getRealUses(id); - DEBUG(dbgs() << "\t\t\t\tphi real Uses" - << Print<Liveness::RefMap>(phiUse, *DFG) << "\n"); + LLVM_DEBUG(dbgs() << "\t\t\t\tphi real Uses" + << Print<Liveness::RefMap>(phiUse, *DFG) << "\n"); if (!phiUse.empty()) { for (auto I : phiUse) { if (!DFG->getPRI().alias(RegisterRef(I.first), DR)) @@ -272,6 +281,153 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, } } +bool HexagonOptAddrMode::isSafeToExtLR(NodeAddr<StmtNode *> SN, + MachineInstr *MI, unsigned LRExtReg, + const NodeList &UNodeList) { + RegisterRef LRExtRR; + NodeId LRExtRegRD = 0; + // Iterate through all the UseNodes in SN and find the reaching def + // for the LRExtReg. + for (NodeAddr<UseNode *> UA : SN.Addr->members_if(DFG->IsUse, *DFG)) { + RegisterRef RR = UA.Addr->getRegRef(*DFG); + if (LRExtReg == RR.Reg) { + LRExtRR = RR; + LRExtRegRD = UA.Addr->getReachingDef(); + } + } + + for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) { + NodeAddr<UseNode *> UA = *I; + NodeAddr<InstrNode *> IA = UA.Addr->getOwner(*DFG); + // The reaching def of LRExtRR at load/store node should be same as the + // one reaching at the SN. + if (UA.Addr->getFlags() & NodeAttrs::PhiRef) + return false; + NodeAddr<RefNode*> AA = LV->getNearestAliasedRef(LRExtRR, IA); + if ((DFG->IsDef(AA) && AA.Id != LRExtRegRD) || + AA.Addr->getReachingDef() != LRExtRegRD) { + LLVM_DEBUG( + dbgs() << "isSafeToExtLR: Returning false; another reaching def\n"); + return false; + } + + MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode(); + NodeAddr<DefNode *> LRExtRegDN = DFG->addr<DefNode *>(LRExtRegRD); + // Reaching Def to LRExtReg can't be a phi. + if ((LRExtRegDN.Addr->getFlags() & NodeAttrs::PhiRef) && + MI->getParent() != UseMI->getParent()) + return false; + } + return true; +} + +bool HexagonOptAddrMode::isValidOffset(MachineInstr *MI, int Offset) { + unsigned AlignMask = 0; + switch (HII->getMemAccessSize(*MI)) { + case HexagonII::MemAccessSize::DoubleWordAccess: + AlignMask = 0x7; + break; + case HexagonII::MemAccessSize::WordAccess: + AlignMask = 0x3; + break; + case HexagonII::MemAccessSize::HalfWordAccess: + AlignMask = 0x1; + break; + case HexagonII::MemAccessSize::ByteAccess: + AlignMask = 0x0; + break; + default: + return false; + } + + if ((AlignMask & Offset) != 0) + return false; + return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); +} + +bool HexagonOptAddrMode::processAddUses(NodeAddr<StmtNode *> AddSN, + MachineInstr *AddMI, + const NodeList &UNodeList) { + + unsigned AddDefR = AddMI->getOperand(0).getReg(); + for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) { + NodeAddr<UseNode *> UN = *I; + NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG); + MachineInstr *MI = SN.Addr->getCode(); + const MCInstrDesc &MID = MI->getDesc(); + if ((!MID.mayLoad() && !MID.mayStore()) || + HII->getAddrMode(*MI) != HexagonII::BaseImmOffset || + HII->isHVXVec(*MI)) + return false; + + MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1) + : MI->getOperand(0); + + if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) + return false; + + MachineOperand OffsetOp = MID.mayLoad() ? MI->getOperand(2) + : MI->getOperand(1); + if (!OffsetOp.isImm()) + return false; + + int64_t newOffset = OffsetOp.getImm() + AddMI->getOperand(2).getImm(); + if (!isValidOffset(MI, newOffset)) + return false; + + // Since we'll be extending the live range of Rt in the following example, + // make sure that is safe. another definition of Rt doesn't exist between 'add' + // and load/store instruction. + // + // Ex: Rx= add(Rt,#10) + // memw(Rx+#0) = Rs + // will be replaced with => memw(Rt+#10) = Rs + unsigned BaseReg = AddMI->getOperand(1).getReg(); + if (!isSafeToExtLR(AddSN, AddMI, BaseReg, UNodeList)) + return false; + } + + // Update all the uses of 'add' with the appropriate base and offset + // values. + bool Changed = false; + for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) { + NodeAddr<UseNode *> UseN = *I; + assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) && + "Found a PhiRef node as a real reached use!!"); + + NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG); + MachineInstr *UseMI = OwnerN.Addr->getCode(); + LLVM_DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber() + << ">]: " << *UseMI << "\n"); + Changed |= updateAddUses(AddMI, UseMI); + } + + if (Changed) + Deleted.insert(AddMI); + + return Changed; +} + +bool HexagonOptAddrMode::updateAddUses(MachineInstr *AddMI, + MachineInstr *UseMI) { + const MachineOperand ImmOp = AddMI->getOperand(2); + const MachineOperand AddRegOp = AddMI->getOperand(1); + unsigned newReg = AddRegOp.getReg(); + const MCInstrDesc &MID = UseMI->getDesc(); + + MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1) + : UseMI->getOperand(0); + MachineOperand &OffsetOp = MID.mayLoad() ? UseMI->getOperand(2) + : UseMI->getOperand(1); + BaseOp.setReg(newReg); + BaseOp.setIsUndef(AddRegOp.isUndef()); + BaseOp.setImplicit(AddRegOp.isImplicit()); + OffsetOp.setImm(ImmOp.getImm() + OffsetOp.getImm()); + MRI->clearKillFlags(newReg); + + return true; +} + bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR, const NodeList &UNodeList, InstrEvalMap &InstrEvalResult, @@ -296,7 +452,7 @@ bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR, } else if (MI.getOpcode() == Hexagon::S2_addasl_rrri) { NodeList AddaslUseList; - DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n"); + LLVM_DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n"); getAllRealUses(SN, AddaslUseList); // Process phi nodes. if (allValidCandidates(SN, AddaslUseList) && @@ -360,8 +516,8 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, } else Changed = false; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -371,8 +527,8 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); OpStart = 4; Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } if (Changed) @@ -413,8 +569,8 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, OpStart = 3; } Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -423,8 +579,8 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); OpStart = 3; Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } if (Changed) for (unsigned i = OpStart; i < OpEnd; ++i) @@ -447,7 +603,7 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN, unsigned ImmOpNum) { NodeAddr<StmtNode *> SA = AddAslUN.Addr->getOwner(*DFG); - DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n"); + LLVM_DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n"); NodeList UNodeList; getAllRealUses(SA, UNodeList); @@ -458,11 +614,11 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN, "Can't transform this 'AddAsl' instruction!"); NodeAddr<StmtNode *> UseIA = UseUN.Addr->getOwner(*DFG); - DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG) - << "\n"); + LLVM_DEBUG(dbgs() << "[InstrNode]: " + << Print<NodeAddr<InstrNode *>>(UseIA, *DFG) << "\n"); MachineInstr *UseMI = UseIA.Addr->getCode(); - DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent()) - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent()) + << ">]: " << *UseMI << "\n"); const MCInstrDesc &UseMID = UseMI->getDesc(); assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset); @@ -534,13 +690,15 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { NodeAddr<StmtNode *> SA = IA; MachineInstr *MI = SA.Addr->getCode(); - if (MI->getOpcode() != Hexagon::A2_tfrsi || - !MI->getOperand(1).isGlobal()) - continue; + if ((MI->getOpcode() != Hexagon::A2_tfrsi || + !MI->getOperand(1).isGlobal()) && + (MI->getOpcode() != Hexagon::A2_addi || + !MI->getOperand(2).isImm() || HII->isConstExtended(*MI))) + continue; - DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) << "]: " - << *MI << "\n\t[InstrNode]: " - << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n'); + LLVM_DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) + << "]: " << *MI << "\n\t[InstrNode]: " + << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n'); NodeList UNodeList; getAllRealUses(SA, UNodeList); @@ -548,6 +706,21 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { if (!allValidCandidates(SA, UNodeList)) continue; + // Analyze all uses of 'add'. If the output of 'add' is used as an address + // in the base+immediate addressing mode load/store instructions, see if + // they can be updated to use the immediate value as an offet. Thus, + // providing us the opportunity to eliminate 'add'. + // Ex: Rx= add(Rt,#12) + // memw(Rx+#0) = Rs + // This can be replaced with memw(Rt+#12) = Rs + // + // This transformation is only performed if all uses can be updated and + // the offset isn't required to be constant extended. + if (MI->getOpcode() == Hexagon::A2_addi) { + Changed |= processAddUses(SA, MI, UNodeList); + continue; + } + short SizeInc = 0; unsigned DefR = MI->getOperand(0).getReg(); InstrEvalMap InstrEvalResult; @@ -561,8 +734,9 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { bool KeepTfr = false; - DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() << "\n"); - DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n"); + LLVM_DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() + << "\n"); + LLVM_DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n"); for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) { NodeAddr<UseNode *> UseN = *I; assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) && @@ -570,8 +744,8 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG); MachineInstr *UseMI = OwnerN.Addr->getCode(); - DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent()) - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent()) + << ">]: " << *UseMI << "\n"); int UseMOnum = -1; unsigned NumOperands = UseMI->getNumOperands(); @@ -580,9 +754,11 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { if (op.isReg() && op.isUse() && DefR == op.getReg()) UseMOnum = j; } - assert(UseMOnum >= 0 && "Invalid reached use!"); + // It is possible that the register will not be found in any operand. + // This could happen, for example, when DefR = R4, but the used + // register is D2. - if (InstrEvalResult[UseMI]) + if (UseMOnum >= 0 && InstrEvalResult[UseMI]) // Change UseMI if replacement is possible. Changed |= xformUseMI(MI, UseMI, UseN, UseMOnum); else @@ -600,27 +776,27 @@ bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; auto &HST = MF.getSubtarget<HexagonSubtarget>(); - auto &MRI = MF.getRegInfo(); + MRI = &MF.getRegInfo(); HII = HST.getInstrInfo(); + HRI = HST.getRegisterInfo(); const auto &MDF = getAnalysis<MachineDominanceFrontier>(); MDT = &getAnalysis<MachineDominatorTree>(); - const auto &TRI = *MF.getSubtarget().getRegisterInfo(); const TargetOperandInfo TOI(*HII); - DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, TOI); + DataFlowGraph G(MF, *HII, *HRI, *MDT, MDF, TOI); // Need to keep dead phis because we can propagate uses of registers into // nodes dominated by those would-be phis. G.build(BuildOptions::KeepDeadPhis); DFG = &G; - Liveness L(MRI, *DFG); + Liveness L(*MRI, *DFG); L.computePhiInfo(); LV = &L; Deleted.clear(); NodeAddr<FuncNode *> FA = DFG->getFunc(); - DEBUG(dbgs() << "==== [RefMap#]=====:\n " - << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n"); + LLVM_DEBUG(dbgs() << "==== [RefMap#]=====:\n " + << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n"); for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG)) Changed |= processBlock(BA); |