diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp | 63 |
1 files changed, 29 insertions, 34 deletions
diff --git a/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp b/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp index 74796954a528..846e3c964f44 100644 --- a/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp @@ -127,7 +127,7 @@ Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM, // Set up the register classes addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); - if (!TM.Options.UseSoftFloat) + if (!Subtarget.useSoftFloat()) setMips16HardFloatLibCalls(); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); @@ -149,7 +149,7 @@ Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM, setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i64, Expand); - computeRegisterProperties(); + computeRegisterProperties(STI.getRegisterInfo()); } const MipsTargetLowering * @@ -522,8 +522,7 @@ MachineBasicBlock *Mips16TargetLowering:: emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = - getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -580,13 +579,12 @@ emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { return BB; } -MachineBasicBlock *Mips16TargetLowering::emitSelT16 - (unsigned Opc1, unsigned Opc2, - MachineInstr *MI, MachineBasicBlock *BB) const { +MachineBasicBlock * +Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, + MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = - getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -645,13 +643,13 @@ MachineBasicBlock *Mips16TargetLowering::emitSelT16 } -MachineBasicBlock *Mips16TargetLowering::emitSeliT16 - (unsigned Opc1, unsigned Opc2, - MachineInstr *MI, MachineBasicBlock *BB) const { +MachineBasicBlock * +Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, + MachineInstr *MI, + MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = - getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -710,14 +708,13 @@ MachineBasicBlock *Mips16TargetLowering::emitSeliT16 } -MachineBasicBlock - *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, - MachineInstr *MI, - MachineBasicBlock *BB) const { +MachineBasicBlock * +Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, + MachineInstr *MI, + MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = - getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); unsigned regX = MI->getOperand(0).getReg(); unsigned regY = MI->getOperand(1).getReg(); MachineBasicBlock *target = MI->getOperand(2).getMBB(); @@ -729,12 +726,11 @@ MachineBasicBlock } MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( - unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, - MachineInstr *MI, MachineBasicBlock *BB) const { + unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, + MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = - getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); unsigned regX = MI->getOperand(0).getReg(); int64_t imm = MI->getOperand(1).getImm(); MachineBasicBlock *target = MI->getOperand(2).getMBB(); @@ -763,13 +759,12 @@ static unsigned Mips16WhichOp8uOr16simm llvm_unreachable("immediate field not usable"); } -MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( - unsigned SltOpc, - MachineInstr *MI, MachineBasicBlock *BB) const { +MachineBasicBlock * +Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr *MI, + MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = - getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); unsigned CC = MI->getOperand(0).getReg(); unsigned regX = MI->getOperand(1).getReg(); unsigned regY = MI->getOperand(2).getReg(); @@ -781,13 +776,13 @@ MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( return BB; } -MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins( - unsigned SltiOpc, unsigned SltiXOpc, - MachineInstr *MI, MachineBasicBlock *BB )const { +MachineBasicBlock * +Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc, + MachineInstr *MI, + MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = - getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); unsigned CC = MI->getOperand(0).getReg(); unsigned regX = MI->getOperand(1).getReg(); int64_t Imm = MI->getOperand(2).getImm(); |