diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 148 |
1 files changed, 132 insertions, 16 deletions
diff --git a/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index 59b7679971cd..7ffe4aff474d 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -179,6 +179,69 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MIB.addReg(ZeroReg); } +static bool isORCopyInst(const MachineInstr &MI) { + switch (MI.getOpcode()) { + default: + break; + case Mips::OR_MM: + case Mips::OR: + if (MI.getOperand(2).getReg() == Mips::ZERO) + return true; + break; + case Mips::OR64: + if (MI.getOperand(2).getReg() == Mips::ZERO_64) + return true; + break; + } + return false; +} + +/// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true +/// if it is WRDSP instruction. +static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) { + switch (MI.getOpcode()) { + default: + return false; + case Mips::WRDSP: + case Mips::WRDSP_MM: + isWrite = true; + break; + case Mips::RDDSP: + case Mips::RDDSP_MM: + isWrite = false; + break; + } + return true; +} + +/// We check for the common case of 'or', as it's MIPS' preferred instruction +/// for GPRs but we have to check the operands to ensure that is the case. +/// Other move instructions for MIPS are directly identifiable. +bool MipsSEInstrInfo::isCopyInstr(const MachineInstr &MI, + const MachineOperand *&Src, + const MachineOperand *&Dest) const { + bool isDSPControlWrite = false; + // Condition is made to match the creation of WRDSP/RDDSP copy instruction + // from copyPhysReg function. + if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) { + if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4)) + return false; + else if (isDSPControlWrite) { + Src = &MI.getOperand(0); + Dest = &MI.getOperand(2); + } else { + Dest = &MI.getOperand(0); + Src = &MI.getOperand(2); + } + return true; + } else if (MI.isMoveReg() || isORCopyInst(MI)) { + Dest = &MI.getOperand(0); + Src = &MI.getOperand(1); + return true; + } + return false; +} + void MipsSEInstrInfo:: storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, @@ -379,28 +442,30 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); break; case Mips::PseudoCVT_D32_W: - expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); + Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; + expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); break; case Mips::PseudoCVT_S_L: expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); break; case Mips::PseudoCVT_D64_W: - expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); + Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; + expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); break; case Mips::PseudoCVT_D64_L: expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); break; case Mips::BuildPairF64: - expandBuildPairF64(MBB, MI, false); + expandBuildPairF64(MBB, MI, isMicroMips, false); break; case Mips::BuildPairF64_64: - expandBuildPairF64(MBB, MI, true); + expandBuildPairF64(MBB, MI, isMicroMips, true); break; case Mips::ExtractElementF64: - expandExtractElementF64(MBB, MI, false); + expandExtractElementF64(MBB, MI, isMicroMips, false); break; case Mips::ExtractElementF64_64: - expandExtractElementF64(MBB, MI, true); + expandExtractElementF64(MBB, MI, isMicroMips, true); break; case Mips::MIPSeh_return32: case Mips::MIPSeh_return64: @@ -425,6 +490,10 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { case Mips::BGEZ: return Mips::BLTZ; case Mips::BLTZ: return Mips::BGEZ; case Mips::BLEZ: return Mips::BGTZ; + case Mips::BGTZ_MM: return Mips::BLEZ_MM; + case Mips::BGEZ_MM: return Mips::BLTZ_MM; + case Mips::BLTZ_MM: return Mips::BGEZ_MM; + case Mips::BLEZ_MM: return Mips::BGTZ_MM; case Mips::BEQ64: return Mips::BNE64; case Mips::BNE64: return Mips::BEQ64; case Mips::BGTZ64: return Mips::BLEZ64; @@ -433,16 +502,40 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { case Mips::BLEZ64: return Mips::BGTZ64; case Mips::BC1T: return Mips::BC1F; case Mips::BC1F: return Mips::BC1T; - case Mips::BEQZC_MM: return Mips::BNEZC_MM; - case Mips::BNEZC_MM: return Mips::BEQZC_MM; + case Mips::BC1T_MM: return Mips::BC1F_MM; + case Mips::BC1F_MM: return Mips::BC1T_MM; + case Mips::BEQZ16_MM: return Mips::BNEZ16_MM; + case Mips::BNEZ16_MM: return Mips::BEQZ16_MM; + case Mips::BEQZC_MM: return Mips::BNEZC_MM; + case Mips::BNEZC_MM: return Mips::BEQZC_MM; case Mips::BEQZC: return Mips::BNEZC; case Mips::BNEZC: return Mips::BEQZC; - case Mips::BEQC: return Mips::BNEC; - case Mips::BNEC: return Mips::BEQC; - case Mips::BGTZC: return Mips::BLEZC; + case Mips::BLEZC: return Mips::BGTZC; case Mips::BGEZC: return Mips::BLTZC; + case Mips::BGEC: return Mips::BLTC; + case Mips::BGTZC: return Mips::BLEZC; case Mips::BLTZC: return Mips::BGEZC; - case Mips::BLEZC: return Mips::BGTZC; + case Mips::BLTC: return Mips::BGEC; + case Mips::BGEUC: return Mips::BLTUC; + case Mips::BLTUC: return Mips::BGEUC; + case Mips::BEQC: return Mips::BNEC; + case Mips::BNEC: return Mips::BEQC; + case Mips::BC1EQZ: return Mips::BC1NEZ; + case Mips::BC1NEZ: return Mips::BC1EQZ; + case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6; + case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6; + case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6; + case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6; + case Mips::BGEC_MMR6: return Mips::BLTC_MMR6; + case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6; + case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6; + case Mips::BLTC_MMR6: return Mips::BGEC_MMR6; + case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6; + case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6; + case Mips::BEQC_MMR6: return Mips::BNEC_MMR6; + case Mips::BNEC_MMR6: return Mips::BEQC_MMR6; + case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6; + case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6; case Mips::BEQZC64: return Mips::BNEZC64; case Mips::BNEZC64: return Mips::BEQZC64; case Mips::BEQC64: return Mips::BNEC64; @@ -459,6 +552,16 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { case Mips::BBIT1: return Mips::BBIT0; case Mips::BBIT032: return Mips::BBIT132; case Mips::BBIT132: return Mips::BBIT032; + case Mips::BZ_B: return Mips::BNZ_B; + case Mips::BZ_H: return Mips::BNZ_H; + case Mips::BZ_W: return Mips::BNZ_W; + case Mips::BZ_D: return Mips::BNZ_D; + case Mips::BZ_V: return Mips::BNZ_V; + case Mips::BNZ_B: return Mips::BZ_B; + case Mips::BNZ_H: return Mips::BZ_H; + case Mips::BNZ_W: return Mips::BZ_W; + case Mips::BNZ_D: return Mips::BZ_D; + case Mips::BNZ_V: return Mips::BZ_V; } } @@ -551,7 +654,13 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || - Opc == Mips::BBIT132) ? Opc : 0; + Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || + Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || + Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || + Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || + Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || + Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || + Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; } void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, @@ -651,6 +760,7 @@ void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + bool isMicroMips, bool FP64) const { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); @@ -682,7 +792,10 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, // We therefore pretend that it reads the bottom 32-bits to // artificially create a dependency and prevent the scheduler // changing the behaviour of the code. - BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg) + BuildMI(MBB, I, dl, + get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) + : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), + DstReg) .addReg(SrcReg); } else BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); @@ -690,7 +803,7 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - bool FP64) const { + bool isMicroMips, bool FP64) const { unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); @@ -735,7 +848,10 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, // We therefore pretend that it reads the bottom 32-bits to // artificially create a dependency and prevent the scheduler // changing the behaviour of the code. - BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg) + BuildMI(MBB, I, dl, + get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) + : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), + DstReg) .addReg(DstReg) .addReg(HiReg); } else if (Subtarget.isABI_FPXX()) |