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Diffstat (limited to 'docs/ReleaseNotes.rst')
| -rw-r--r-- | docs/ReleaseNotes.rst | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index c28a3829bfee..949ec85c270b 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -71,6 +71,13 @@ Non-comprehensive list of changes in this release Changes to the LLVM IR ---------------------- +Changes to the AArch64 Target +----------------------------- + +During this release: + + * Enabled the new GlobalISel instruction selection framework by default at ``-O0``. + Changes to the ARM Target ------------------------- @@ -80,6 +87,28 @@ During this release the ARM target has: isn't the default. +Changes to the Hexagon Target +----------------------------- + +* The Hexagon backend now supports V65 ISA. + +* The ``-mhvx`` option now takes an optional value that specified the ISA + version of the HVX coprocessor. The available values are v60, v62 and v65. + By default, the value is set to be the same as the CPU version. + +* The compiler option ``-mhvx-double`` is deprecated and will be removed in + the next release of the compiler. Programmers should use ``-mhvx-length`` + option to specify the desired vector length: ``-mhvx-length=64b`` for + 64-byte vectors and ``-mhvx-length=128b`` for 128-byte vectors. While the + current default vector length is 64 bytes, users should always specify the + length explicitly, since the default value may change in the future. + +* The target feature ``hvx-double`` is deprecated and will be removed in the + next release. LLVM IR generators should use target features ``hvx-length64b`` + and ``hvx-length128b`` to indicate the vector length. The length should + always be specified when HVX code generation is enabled. + + Changes to the MIPS Target -------------------------- @@ -91,6 +120,15 @@ Changes to the PowerPC Target During this release ... +Changes to the SystemZ Target +----------------------------- + +During this release the SystemZ target has: + +* Added support for 128-bit atomic operations. + +* Added support for the "o" constraint for inline asm statements. + Changes to the X86 Target ------------------------- |