diff options
Diffstat (limited to 'include/llvm/CodeGen')
42 files changed, 401 insertions, 342 deletions
diff --git a/include/llvm/CodeGen/BasicTTIImpl.h b/include/llvm/CodeGen/BasicTTIImpl.h index 32542fa87463..9e33df6b55ec 100644 --- a/include/llvm/CodeGen/BasicTTIImpl.h +++ b/include/llvm/CodeGen/BasicTTIImpl.h @@ -17,11 +17,11 @@ #define LLVM_CODEGEN_BASICTTIIMPL_H #include "llvm/Analysis/LoopInfo.h" +#include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/TargetTransformInfoImpl.h" #include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetSubtargetInfo.h" -#include "llvm/Analysis/TargetLibraryInfo.h" namespace llvm { @@ -117,6 +117,10 @@ public: return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace); } + bool isLSRCostLess(TTI::LSRCost C1, TTI::LSRCost C2) { + return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); + } + int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { TargetLoweringBase::AddrMode AM; @@ -1080,46 +1084,46 @@ public: return 0; } + /// Try to calculate arithmetic and shuffle op costs for reduction operations. + /// We're assuming that reduction operation are performing the following way: + /// 1. Non-pairwise reduction + /// %val1 = shufflevector<n x t> %val, <n x t> %undef, + /// <n x i32> <i32 n/2, i32 n/2 + 1, ..., i32 n, i32 undef, ..., i32 undef> + /// \----------------v-------------/ \----------v------------/ + /// n/2 elements n/2 elements + /// %red1 = op <n x t> %val, <n x t> val1 + /// After this operation we have a vector %red1 where only the first n/2 + /// elements are meaningful, the second n/2 elements are undefined and can be + /// dropped. All other operations are actually working with the vector of + /// length n/2, not n, though the real vector length is still n. + /// %val2 = shufflevector<n x t> %red1, <n x t> %undef, + /// <n x i32> <i32 n/4, i32 n/4 + 1, ..., i32 n/2, i32 undef, ..., i32 undef> + /// \----------------v-------------/ \----------v------------/ + /// n/4 elements 3*n/4 elements + /// %red2 = op <n x t> %red1, <n x t> val2 - working with the vector of + /// length n/2, the resulting vector has length n/4 etc. + /// 2. Pairwise reduction: + /// Everything is the same except for an additional shuffle operation which + /// is used to produce operands for pairwise kind of reductions. + /// %val1 = shufflevector<n x t> %val, <n x t> %undef, + /// <n x i32> <i32 0, i32 2, ..., i32 n-2, i32 undef, ..., i32 undef> + /// \-------------v----------/ \----------v------------/ + /// n/2 elements n/2 elements + /// %val2 = shufflevector<n x t> %val, <n x t> %undef, + /// <n x i32> <i32 1, i32 3, ..., i32 n-1, i32 undef, ..., i32 undef> + /// \-------------v----------/ \----------v------------/ + /// n/2 elements n/2 elements + /// %red1 = op <n x t> %val1, <n x t> val2 + /// Again, the operation is performed on <n x t> vector, but the resulting + /// vector %red1 is <n/2 x t> vector. + /// + /// The cost model should take into account that the actual length of the + /// vector is reduced on each iteration. unsigned getReductionCost(unsigned Opcode, Type *Ty, bool IsPairwise) { assert(Ty->isVectorTy() && "Expect a vector type"); Type *ScalarTy = Ty->getVectorElementType(); unsigned NumVecElts = Ty->getVectorNumElements(); unsigned NumReduxLevels = Log2_32(NumVecElts); - // Try to calculate arithmetic and shuffle op costs for reduction operations. - // We're assuming that reduction operation are performing the following way: - // 1. Non-pairwise reduction - // %val1 = shufflevector<n x t> %val, <n x t> %undef, - // <n x i32> <i32 n/2, i32 n/2 + 1, ..., i32 n, i32 undef, ..., i32 undef> - // \----------------v-------------/ \----------v------------/ - // n/2 elements n/2 elements - // %red1 = op <n x t> %val, <n x t> val1 - // After this operation we have a vector %red1 with only maningfull the - // first n/2 elements, the second n/2 elements are undefined and can be - // dropped. All other operations are actually working with the vector of - // length n/2, not n. though the real vector length is still n. - // %val2 = shufflevector<n x t> %red1, <n x t> %undef, - // <n x i32> <i32 n/4, i32 n/4 + 1, ..., i32 n/2, i32 undef, ..., i32 undef> - // \----------------v-------------/ \----------v------------/ - // n/4 elements 3*n/4 elements - // %red2 = op <n x t> %red1, <n x t> val2 - working with the vector of - // length n/2, the resulting vector has length n/4 etc. - // 2. Pairwise reduction: - // Everything is the same except for an additional shuffle operation which - // is used to produce operands for pairwise kind of reductions. - // %val1 = shufflevector<n x t> %val, <n x t> %undef, - // <n x i32> <i32 0, i32 2, ..., i32 n-2, i32 undef, ..., i32 undef> - // \-------------v----------/ \----------v------------/ - // n/2 elements n/2 elements - // %val2 = shufflevector<n x t> %val, <n x t> %undef, - // <n x i32> <i32 1, i32 3, ..., i32 n-1, i32 undef, ..., i32 undef> - // \-------------v----------/ \----------v------------/ - // n/2 elements n/2 elements - // %red1 = op <n x t> %val1, <n x t> val2 - // Again, the operation is performed on <n x t> vector, but the resulting - // vector %red1 is <n/2 x t> vector. - // - // The cost model should take into account that the actual length of the - // vector is reduced on each iteration. unsigned ArithCost = 0; unsigned ShuffleCost = 0; auto *ConcreteTTI = static_cast<T *>(this); diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index 8de140e91bf3..77c37ac7abea 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -1,4 +1,4 @@ -//=- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-=====// +//===- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -29,17 +29,22 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/ScheduleDAGMutation.h" +#include <cstdint> #include <map> +#include <memory> +#include <utility> +#include <vector> namespace llvm { -class MCInstrDesc; +class DefaultVLIWScheduler; +class InstrItineraryData; +class MachineFunction; class MachineInstr; class MachineLoopInfo; -class MachineDominatorTree; -class InstrItineraryData; -class DefaultVLIWScheduler; +class MCInstrDesc; class SUnit; +class TargetInstrInfo; // -------------------------------------------------------------------- // Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp @@ -64,17 +69,18 @@ class SUnit; #define DFA_MAX_RESTERMS 4 // The max # of AND'ed resource terms. #define DFA_MAX_RESOURCES 16 // The max # of resource bits in one term. -typedef uint64_t DFAInput; -typedef int64_t DFAStateInput; +using DFAInput = uint64_t; +using DFAStateInput = int64_t; + #define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable. // -------------------------------------------------------------------- class DFAPacketizer { private: - typedef std::pair<unsigned, DFAInput> UnsignPair; + using UnsignPair = std::pair<unsigned, DFAInput>; const InstrItineraryData *InstrItins; - int CurrentState; + int CurrentState = 0; const DFAStateInput (*DFAStateInputTable)[2]; const unsigned *DFAStateEntryTable; @@ -101,24 +107,23 @@ public: // Check if the resources occupied by a MCInstrDesc are available in // the current state. - bool canReserveResources(const llvm::MCInstrDesc *MID); + bool canReserveResources(const MCInstrDesc *MID); // Reserve the resources occupied by a MCInstrDesc and change the current // state to reflect that change. - void reserveResources(const llvm::MCInstrDesc *MID); + void reserveResources(const MCInstrDesc *MID); // Check if the resources occupied by a machine instruction are available // in the current state. - bool canReserveResources(llvm::MachineInstr &MI); + bool canReserveResources(MachineInstr &MI); // Reserve the resources occupied by a machine instruction and change the // current state to reflect that change. - void reserveResources(llvm::MachineInstr &MI); + void reserveResources(MachineInstr &MI); const InstrItineraryData *getInstrItins() const { return InstrItins; } }; - // VLIWPacketizerList implements a simple VLIW packetizer using DFA. The // packetizer works on machine basic blocks. For each instruction I in BB, // the packetizer consults the DFA to see if machine resources are available @@ -205,6 +210,6 @@ public: void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation); }; -} // namespace llvm +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_DFAPACKETIZER_H diff --git a/include/llvm/CodeGen/DIE.h b/include/llvm/CodeGen/DIE.h index 4f47ba6e3852..5ed5faa2c415 100644 --- a/include/llvm/CodeGen/DIE.h +++ b/include/llvm/CodeGen/DIE.h @@ -21,10 +21,10 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/iterator.h" #include "llvm/ADT/iterator_range.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/DwarfStringPoolEntry.h" #include "llvm/Support/AlignOf.h" #include "llvm/Support/Allocator.h" -#include "llvm/Support/Dwarf.h" #include <cassert> #include <cstddef> #include <cstdint> diff --git a/include/llvm/CodeGen/ExecutionDepsFix.h b/include/llvm/CodeGen/ExecutionDepsFix.h index 1d5b9684e105..f4db8b7322da 100644 --- a/include/llvm/CodeGen/ExecutionDepsFix.h +++ b/include/llvm/CodeGen/ExecutionDepsFix.h @@ -1,4 +1,4 @@ -//===- llvm/CodeGen/ExecutionDepsFix.h - Execution Dependency Fix -*- C++ -*-=// +//==- llvm/CodeGen/ExecutionDepsFix.h - Execution Dependency Fix -*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -20,19 +20,30 @@ // //===----------------------------------------------------------------------===// - #ifndef LLVM_CODEGEN_EXECUTIONDEPSFIX_H #define LLVM_CODEGEN_EXECUTIONDEPSFIX_H +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/iterator_range.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/LivePhysRegs.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/RegisterClassInfo.h" +#include "llvm/Pass.h" #include "llvm/Support/Allocator.h" +#include "llvm/Support/MathExtras.h" +#include <cassert> +#include <limits> +#include <utility> #include <vector> namespace llvm { +class MachineBasicBlock; +class MachineInstr; +class TargetInstrInfo; + /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track /// of execution domains. /// @@ -50,7 +61,7 @@ namespace llvm { /// domains. struct DomainValue { // Basic reference counting. - unsigned Refs; + unsigned Refs = 0; // Bitmask of available domains. For an open DomainValue, it is the still // possible domains for collapsing. For a collapsed DomainValue it is the @@ -65,6 +76,8 @@ struct DomainValue { // Twiddleable instructions using or defining these registers. SmallVector<MachineInstr*, 8> Instrs; + DomainValue() { clear(); } + // A collapsed DomainValue has no instructions to twiddle - it simply keeps // track of the domains where the registers are already available. bool isCollapsed() const { return Instrs.empty(); } @@ -97,8 +110,6 @@ struct DomainValue { return countTrailingZeros(AvailableDomains); } - DomainValue() : Refs(0) { clear(); } - // Clear this DomainValue and point to next which has all its data. void clear() { AvailableDomains = 0; @@ -136,29 +147,27 @@ class ExecutionDepsFix : public MachineFunctionPass { // Keeps clearance and domain information for all registers. Note that this // is different from the usual definition notion of liveness. The CPU // doesn't care whether or not we consider a register killed. - LiveReg *OutRegs; + LiveReg *OutRegs = nullptr; // Whether we have gotten to this block in primary processing yet. - bool PrimaryCompleted; + bool PrimaryCompleted = false; // The number of predecessors for which primary processing has completed - unsigned IncomingProcessed; + unsigned IncomingProcessed = 0; // The value of `IncomingProcessed` at the start of primary processing - unsigned PrimaryIncoming; + unsigned PrimaryIncoming = 0; // The number of predecessors for which all processing steps are done. - unsigned IncomingCompleted; + unsigned IncomingCompleted = 0; - MBBInfo() - : OutRegs(nullptr), PrimaryCompleted(false), IncomingProcessed(0), - PrimaryIncoming(0), IncomingCompleted(0) {} + MBBInfo() = default; }; - typedef DenseMap<MachineBasicBlock *, MBBInfo> MBBInfoMap; + using MBBInfoMap = DenseMap<MachineBasicBlock *, MBBInfo>; MBBInfoMap MBBInfos; /// List of undefined register reads in this block in forward order. - std::vector<std::pair<MachineInstr*, unsigned> > UndefReads; + std::vector<std::pair<MachineInstr *, unsigned>> UndefReads; /// Storage for register unit liveness. LivePhysRegs LiveRegSet; @@ -166,6 +175,7 @@ class ExecutionDepsFix : public MachineFunctionPass { /// Current instruction number. /// The first instruction in each basic block is 0. int CurInstr; + public: ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC) : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {} @@ -217,4 +227,4 @@ private: } // end namepsace llvm -#endif +#endif // LLVM_CODEGEN_EXECUTIONDEPSFIX_H diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index 57fa0c73d272..74e4179e73e9 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -17,11 +17,12 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineValueType.h" #include "llvm/IR/Attributes.h" -#include "llvm/IR/CallingConv.h" #include "llvm/IR/CallSite.h" +#include "llvm/IR/CallingConv.h" #include "llvm/IR/DebugLoc.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/InstrTypes.h" @@ -30,19 +31,43 @@ #include <algorithm> #include <cstdint> #include <utility> -#include <vector> namespace llvm { +class AllocaInst; +class BasicBlock; +class CallInst; +class Constant; +class ConstantFP; +class DataLayout; +class FunctionLoweringInfo; +class LoadInst; class MachineConstantPool; +class MachineFrameInfo; +class MachineFunction; +class MachineInstr; +class MachineMemOperand; +class MachineOperand; +class MachineRegisterInfo; +class MCContext; +class MCInstrDesc; +class MCSymbol; +class TargetInstrInfo; +class TargetLibraryInfo; +class TargetMachine; +class TargetRegisterClass; +class TargetRegisterInfo; +class Type; +class User; +class Value; /// \brief This is a fast-path instruction selection class that generates poor /// code and doesn't support illegal types or non-trivial lowering, but runs /// quickly. class FastISel { public: - typedef TargetLoweringBase::ArgListEntry ArgListEntry; - typedef TargetLoweringBase::ArgListTy ArgListTy; + using ArgListEntry = TargetLoweringBase::ArgListEntry; + using ArgListTy = TargetLoweringBase::ArgListTy; struct CallLoweringInfo { Type *RetTy = nullptr; bool RetSExt : 1; @@ -202,6 +227,8 @@ protected: MachineInstr *EmitStartPt; public: + virtual ~FastISel(); + /// \brief Return the position of the last instruction emitted for /// materializing constants for use in the current block. MachineInstr *getLastLocalValue() { return LastLocalValue; } @@ -293,8 +320,6 @@ public: /// \brief Reset InsertPt to the given old insert position. void leaveLocalValueArea(SavePoint Old); - virtual ~FastISel(); - protected: explicit FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, @@ -334,7 +359,7 @@ protected: /// \brief This method is called by target-independent code to request that an /// instruction with the given type, opcode, and register and immediate - // operands be emitted. + /// operands be emitted. virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm); diff --git a/include/llvm/CodeGen/FunctionLoweringInfo.h b/include/llvm/CodeGen/FunctionLoweringInfo.h index e7544bd7b70c..7d7c3e8cfd22 100644 --- a/include/llvm/CodeGen/FunctionLoweringInfo.h +++ b/include/llvm/CodeGen/FunctionLoweringInfo.h @@ -1,4 +1,4 @@ -//===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===// +//===- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen ---===// // // The LLVM Compiler Infrastructure // @@ -23,29 +23,28 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/IR/InlineAsm.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/Type.h" +#include "llvm/IR/Value.h" #include "llvm/Support/KnownBits.h" #include "llvm/Target/TargetRegisterInfo.h" +#include <cassert> +#include <utility> #include <vector> namespace llvm { -class AllocaInst; +class Argument; class BasicBlock; class BranchProbabilityInfo; class Function; -class GlobalVariable; class Instruction; -class MachineInstr; -class MachineBasicBlock; class MachineFunction; -class MachineModuleInfo; +class MachineInstr; class MachineRegisterInfo; -class SelectionDAG; class MVT; +class SelectionDAG; class TargetLowering; -class Value; //===--------------------------------------------------------------------===// /// FunctionLoweringInfo - This contains information that is global to a @@ -74,25 +73,24 @@ public: /// A map from swifterror value in a basic block to the virtual register it is /// currently represented by. - llvm::DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned> + DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned> SwiftErrorVRegDefMap; /// A list of upward exposed vreg uses that need to be satisfied by either a /// copy def or a phi node at the beginning of the basic block representing /// the predecessor(s) swifterror value. - llvm::DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned> + DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned> SwiftErrorVRegUpwardsUse; /// The swifterror argument of the current function. const Value *SwiftErrorArg; - typedef SmallVector<const Value*, 1> SwiftErrorValues; + using SwiftErrorValues = SmallVector<const Value*, 1>; /// A function can only have a single swifterror argument. And if it does /// have a swifterror argument, it must be the first entry in /// SwiftErrorVals. SwiftErrorValues SwiftErrorVals; - /// Get or create the swifterror value virtual register in /// SwiftErrorVRegDefMap for this basic block. unsigned getOrCreateSwiftErrorVReg(const MachineBasicBlock *, @@ -118,7 +116,7 @@ public: /// slot), and we track that here. struct StatepointSpillMap { - typedef DenseMap<const Value *, Optional<int>> SlotMapTy; + using SlotMapTy = DenseMap<const Value *, Optional<int>>; /// Maps uniqued llvm IR values to the slots they were spilled in. If a /// value is mapped to None it means we visited the value but didn't spill @@ -172,8 +170,9 @@ public: struct LiveOutInfo { unsigned NumSignBits : 31; unsigned IsValid : 1; - KnownBits Known; - LiveOutInfo() : NumSignBits(0), IsValid(true), Known(1) {} + KnownBits Known = 1; + + LiveOutInfo() : NumSignBits(0), IsValid(true) {} }; /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) @@ -298,4 +297,4 @@ private: } // end namespace llvm -#endif +#endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H diff --git a/include/llvm/CodeGen/GCMetadata.h b/include/llvm/CodeGen/GCMetadata.h index e6afcbc8ded2..ad2599fc120e 100644 --- a/include/llvm/CodeGen/GCMetadata.h +++ b/include/llvm/CodeGen/GCMetadata.h @@ -1,4 +1,4 @@ -//===-- GCMetadata.h - Garbage collector metadata ---------------*- C++ -*-===// +//===- GCMetadata.h - Garbage collector metadata ----------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -36,15 +36,20 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" +#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/GCStrategy.h" #include "llvm/IR/DebugLoc.h" #include "llvm/Pass.h" +#include <algorithm> +#include <cstddef> +#include <cstdint> #include <memory> -#include <utility> +#include <vector> namespace llvm { -class AsmPrinter; + class Constant; +class Function; class MCSymbol; /// GCPoint - Metadata for a collector-safe point in machine code. @@ -62,20 +67,20 @@ struct GCPoint { /// collector. struct GCRoot { int Num; ///< Usually a frame index. - int StackOffset; ///< Offset from the stack pointer. + int StackOffset = -1; ///< Offset from the stack pointer. const Constant *Metadata; ///< Metadata straight from the call ///< to llvm.gcroot. - GCRoot(int N, const Constant *MD) : Num(N), StackOffset(-1), Metadata(MD) {} + GCRoot(int N, const Constant *MD) : Num(N), Metadata(MD) {} }; /// Garbage collection metadata for a single function. Currently, this /// information only applies to GCStrategies which use GCRoot. class GCFunctionInfo { public: - typedef std::vector<GCPoint>::iterator iterator; - typedef std::vector<GCRoot>::iterator roots_iterator; - typedef std::vector<GCRoot>::const_iterator live_iterator; + using iterator = std::vector<GCPoint>::iterator; + using roots_iterator = std::vector<GCRoot>::iterator; + using live_iterator = std::vector<GCRoot>::const_iterator; private: const Function &F; @@ -99,11 +104,9 @@ public: ~GCFunctionInfo(); /// getFunction - Return the function to which this metadata applies. - /// const Function &getFunction() const { return F; } /// getStrategy - Return the GC strategy for the function. - /// GCStrategy &getStrategy() { return S; } /// addStackRoot - Registers a root that lives on the stack. Num is the @@ -126,24 +129,20 @@ public: } /// getFrameSize/setFrameSize - Records the function's frame size. - /// uint64_t getFrameSize() const { return FrameSize; } void setFrameSize(uint64_t S) { FrameSize = S; } /// begin/end - Iterators for safe points. - /// iterator begin() { return SafePoints.begin(); } iterator end() { return SafePoints.end(); } size_t size() const { return SafePoints.size(); } /// roots_begin/roots_end - Iterators for all roots in the function. - /// roots_iterator roots_begin() { return Roots.begin(); } roots_iterator roots_end() { return Roots.end(); } size_t roots_size() const { return Roots.size(); } /// live_begin/live_end - Iterators for live roots at a given safe point. - /// live_iterator live_begin(const iterator &p) { return roots_begin(); } live_iterator live_end(const iterator &p) { return roots_end(); } size_t live_size(const iterator &p) const { return roots_size(); } @@ -166,7 +165,7 @@ public: /// List of per function info objects. In theory, Each of these /// may be associated with a different GC. - typedef std::vector<std::unique_ptr<GCFunctionInfo>> FuncInfoVec; + using FuncInfoVec = std::vector<std::unique_ptr<GCFunctionInfo>>; FuncInfoVec::iterator funcinfo_begin() { return Functions.begin(); } FuncInfoVec::iterator funcinfo_end() { return Functions.end(); } @@ -177,11 +176,11 @@ private: /// Non-owning map to bypass linear search when finding the GCFunctionInfo /// associated with a particular Function. - typedef DenseMap<const Function *, GCFunctionInfo *> finfo_map_type; + using finfo_map_type = DenseMap<const Function *, GCFunctionInfo *>; finfo_map_type FInfoMap; public: - typedef SmallVector<std::unique_ptr<GCStrategy>,1>::const_iterator iterator; + using iterator = SmallVector<std::unique_ptr<GCStrategy>, 1>::const_iterator; static char ID; @@ -202,6 +201,7 @@ public: /// will soon change. GCFunctionInfo &getFunctionInfo(const Function &F); }; -} -#endif +} // end namespace llvm + +#endif // LLVM_CODEGEN_GCMETADATA_H diff --git a/include/llvm/CodeGen/GCMetadataPrinter.h b/include/llvm/CodeGen/GCMetadataPrinter.h index 220847029113..1cc69a7b71af 100644 --- a/include/llvm/CodeGen/GCMetadataPrinter.h +++ b/include/llvm/CodeGen/GCMetadataPrinter.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/GCMetadataPrinter.h - Prints asm GC tables -*- C++ -*-===// +//===- llvm/CodeGen/GCMetadataPrinter.h - Prints asm GC tables --*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -20,45 +20,48 @@ #ifndef LLVM_CODEGEN_GCMETADATAPRINTER_H #define LLVM_CODEGEN_GCMETADATAPRINTER_H -#include "llvm/CodeGen/GCMetadata.h" -#include "llvm/CodeGen/GCStrategy.h" #include "llvm/Support/Registry.h" namespace llvm { +class AsmPrinter; class GCMetadataPrinter; +class GCModuleInfo; +class GCStrategy; +class Module; /// GCMetadataPrinterRegistry - The GC assembly printer registry uses all the /// defaults from Registry. -typedef Registry<GCMetadataPrinter> GCMetadataPrinterRegistry; +using GCMetadataPrinterRegistry = Registry<GCMetadataPrinter>; /// GCMetadataPrinter - Emits GC metadata as assembly code. Instances are /// created, managed, and owned by the AsmPrinter. class GCMetadataPrinter { private: - GCStrategy *S; friend class AsmPrinter; + GCStrategy *S; + protected: // May only be subclassed. GCMetadataPrinter(); -private: +public: GCMetadataPrinter(const GCMetadataPrinter &) = delete; GCMetadataPrinter &operator=(const GCMetadataPrinter &) = delete; + virtual ~GCMetadataPrinter(); -public: GCStrategy &getStrategy() { return *S; } /// Called before the assembly for the module is generated by /// the AsmPrinter (but after target specific hooks.) virtual void beginAssembly(Module &M, GCModuleInfo &Info, AsmPrinter &AP) {} + /// Called after the assembly for the module is generated by /// the AsmPrinter (but before target specific hooks) virtual void finishAssembly(Module &M, GCModuleInfo &Info, AsmPrinter &AP) {} - - virtual ~GCMetadataPrinter(); }; -} -#endif +} // end namespace llvm + +#endif // LLVM_CODEGEN_GCMETADATAPRINTER_H diff --git a/include/llvm/CodeGen/GCStrategy.h b/include/llvm/CodeGen/GCStrategy.h index 5b1fafea25b5..16168e785f81 100644 --- a/include/llvm/CodeGen/GCStrategy.h +++ b/include/llvm/CodeGen/GCStrategy.h @@ -174,7 +174,7 @@ public: /// Note that to use a custom GCMetadataPrinter w/gc.roots, you must also /// register your GCMetadataPrinter subclass with the /// GCMetadataPrinterRegistery as well. -typedef Registry<GCStrategy> GCRegistry; +using GCRegistry = Registry<GCStrategy>; } // end namespace llvm diff --git a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h index 45f25f96ec1f..1a865c3f0dce 100644 --- a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -17,8 +17,8 @@ #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H #include "llvm/ADT/Optional.h" -#include <cstdint> #include <bitset> +#include <cstdint> #include <functional> namespace llvm { diff --git a/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h index 8fecafdc08d0..3148e70b56f8 100644 --- a/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h +++ b/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h @@ -22,8 +22,8 @@ #define LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZEHELPER_H #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" -#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/LowLevelType.h" +#include "llvm/CodeGen/MachineFunctionPass.h" namespace llvm { // Forward declarations. diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 6b662a7f7413..db72f78c8321 100644 --- a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -16,9 +16,9 @@ #include "llvm/CodeGen/GlobalISel/Types.h" +#include "llvm/CodeGen/LowLevelType.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/LowLevelType.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DebugLoc.h" diff --git a/include/llvm/CodeGen/LexicalScopes.h b/include/llvm/CodeGen/LexicalScopes.h index 6c35832f963c..79fa12ec2fbb 100644 --- a/include/llvm/CodeGen/LexicalScopes.h +++ b/include/llvm/CodeGen/LexicalScopes.h @@ -31,12 +31,13 @@ namespace llvm { class MachineBasicBlock; class MachineFunction; class MachineInstr; +class MDNode; //===----------------------------------------------------------------------===// /// InsnRange - This is used to track range of instructions with identical /// lexical scope. /// -typedef std::pair<const MachineInstr *, const MachineInstr *> InsnRange; +using InsnRange = std::pair<const MachineInstr *, const MachineInstr *>; //===----------------------------------------------------------------------===// /// LexicalScope - This class is used to track scope information. diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 40cd146f88f8..f4fa872c7f5b 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -23,9 +23,9 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/IntEqClasses.h" -#include "llvm/ADT/iterator_range.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/iterator_range.h" #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/MC/LaneBitmask.h" #include "llvm/Support/Allocator.h" diff --git a/include/llvm/CodeGen/LiveRegUnits.h b/include/llvm/CodeGen/LiveRegUnits.h index 5de76c8b87bf..fa1ec867ea3d 100644 --- a/include/llvm/CodeGen/LiveRegUnits.h +++ b/include/llvm/CodeGen/LiveRegUnits.h @@ -16,9 +16,9 @@ #define LLVM_CODEGEN_LIVEREGUNITS_H #include "llvm/ADT/BitVector.h" -#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/MC/LaneBitmask.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include <cstdint> namespace llvm { diff --git a/include/llvm/CodeGen/MIRParser/MIRParser.h b/include/llvm/CodeGen/MIRParser/MIRParser.h index dd0780397f42..b631a8c0122a 100644 --- a/include/llvm/CodeGen/MIRParser/MIRParser.h +++ b/include/llvm/CodeGen/MIRParser/MIRParser.h @@ -18,7 +18,6 @@ #ifndef LLVM_CODEGEN_MIRPARSER_MIRPARSER_H #define LLVM_CODEGEN_MIRPARSER_MIRPARSER_H -#include "llvm/CodeGen/MachineFunctionInitializer.h" #include "llvm/IR/Module.h" #include "llvm/Support/MemoryBuffer.h" #include <memory> @@ -27,29 +26,30 @@ namespace llvm { class StringRef; class MIRParserImpl; +class MachineModuleInfo; class SMDiagnostic; /// This class initializes machine functions by applying the state loaded from /// a MIR file. -class MIRParser : public MachineFunctionInitializer { +class MIRParser { std::unique_ptr<MIRParserImpl> Impl; public: MIRParser(std::unique_ptr<MIRParserImpl> Impl); MIRParser(const MIRParser &) = delete; - ~MIRParser() override; + ~MIRParser(); - /// Parse the optional LLVM IR module that's embedded in the MIR file. + /// Parses the optional LLVM IR module in the MIR file. /// /// A new, empty module is created if the LLVM IR isn't present. - /// Returns null if a parsing error occurred. - std::unique_ptr<Module> parseLLVMModule(); + /// \returns nullptr if a parsing error occurred. + std::unique_ptr<Module> parseIRModule(); - /// Initialize the machine function to the state that's described in the MIR - /// file. + /// \brief Parses MachineFunctions in the MIR file and add them to the given + /// MachineModuleInfo \p MMI. /// - /// Return true if error occurred. - bool initializeMachineFunction(MachineFunction &MF) override; + /// \returns true if an error occurred. + bool parseMachineFunctions(Module &M, MachineModuleInfo &MMI); }; /// This function is the main interface to the MIR serialization format parser. diff --git a/include/llvm/CodeGen/MIRYamlMapping.h b/include/llvm/CodeGen/MIRYamlMapping.h index 30e88fe38ac3..1b1ba6a05837 100644 --- a/include/llvm/CodeGen/MIRYamlMapping.h +++ b/include/llvm/CodeGen/MIRYamlMapping.h @@ -72,6 +72,9 @@ template <> struct ScalarTraits<FlowStringValue> { struct BlockStringValue { StringValue Value; + bool operator==(const BlockStringValue &Other) const { + return Value == Other.Value; + } }; template <> struct BlockScalarTraits<BlockStringValue> { @@ -146,6 +149,10 @@ struct VirtualRegisterDefinition { StringValue Class; StringValue PreferredRegister; // TODO: Serialize the target specific register hints. + bool operator==(const VirtualRegisterDefinition &Other) const { + return ID == Other.ID && Class == Other.Class && + PreferredRegister == Other.PreferredRegister; + } }; template <> struct MappingTraits<VirtualRegisterDefinition> { @@ -162,6 +169,10 @@ template <> struct MappingTraits<VirtualRegisterDefinition> { struct MachineFunctionLiveIn { StringValue Register; StringValue VirtualRegister; + bool operator==(const MachineFunctionLiveIn &Other) const { + return Register == Other.Register && + VirtualRegister == Other.VirtualRegister; + } }; template <> struct MappingTraits<MachineFunctionLiveIn> { @@ -196,6 +207,14 @@ struct MachineStackObject { StringValue DebugVar; StringValue DebugExpr; StringValue DebugLoc; + bool operator==(const MachineStackObject &Other) const { + return ID == Other.ID && Name == Other.Name && Type == Other.Type && + Offset == Other.Offset && Size == Other.Size && + Alignment == Other.Alignment && + CalleeSavedRegister == Other.CalleeSavedRegister && + LocalOffset == Other.LocalOffset && DebugVar == Other.DebugVar && + DebugExpr == Other.DebugExpr && DebugLoc == Other.DebugLoc; + } }; template <> struct ScalarEnumerationTraits<MachineStackObject::ObjectType> { @@ -214,13 +233,13 @@ template <> struct MappingTraits<MachineStackObject> { YamlIO.mapOptional( "type", Object.Type, MachineStackObject::DefaultType); // Don't print the default type. - YamlIO.mapOptional("offset", Object.Offset); + YamlIO.mapOptional("offset", Object.Offset, (int64_t)0); if (Object.Type != MachineStackObject::VariableSized) YamlIO.mapRequired("size", Object.Size); - YamlIO.mapOptional("alignment", Object.Alignment); + YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0); YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister, StringValue()); // Don't print it out when it's empty. - YamlIO.mapOptional("local-offset", Object.LocalOffset); + YamlIO.mapOptional("local-offset", Object.LocalOffset, Optional<int64_t>()); YamlIO.mapOptional("di-variable", Object.DebugVar, StringValue()); // Don't print it out when it's empty. YamlIO.mapOptional("di-expression", Object.DebugExpr, @@ -244,6 +263,12 @@ struct FixedMachineStackObject { bool IsImmutable = false; bool IsAliased = false; StringValue CalleeSavedRegister; + bool operator==(const FixedMachineStackObject &Other) const { + return ID == Other.ID && Type == Other.Type && Offset == Other.Offset && + Size == Other.Size && Alignment == Other.Alignment && + IsImmutable == Other.IsImmutable && IsAliased == Other.IsAliased && + CalleeSavedRegister == Other.CalleeSavedRegister; + } }; template <> @@ -261,12 +286,12 @@ template <> struct MappingTraits<FixedMachineStackObject> { YamlIO.mapOptional( "type", Object.Type, FixedMachineStackObject::DefaultType); // Don't print the default type. - YamlIO.mapOptional("offset", Object.Offset); - YamlIO.mapOptional("size", Object.Size); - YamlIO.mapOptional("alignment", Object.Alignment); + YamlIO.mapOptional("offset", Object.Offset, (int64_t)0); + YamlIO.mapOptional("size", Object.Size, (uint64_t)0); + YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0); if (Object.Type != FixedMachineStackObject::SpillSlot) { - YamlIO.mapOptional("isImmutable", Object.IsImmutable); - YamlIO.mapOptional("isAliased", Object.IsAliased); + YamlIO.mapOptional("isImmutable", Object.IsImmutable, false); + YamlIO.mapOptional("isAliased", Object.IsAliased, false); } YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister, StringValue()); // Don't print it out when it's empty. @@ -279,13 +304,17 @@ struct MachineConstantPoolValue { UnsignedValue ID; StringValue Value; unsigned Alignment = 0; + bool operator==(const MachineConstantPoolValue &Other) const { + return ID == Other.ID && Value == Other.Value && + Alignment == Other.Alignment; + } }; template <> struct MappingTraits<MachineConstantPoolValue> { static void mapping(IO &YamlIO, MachineConstantPoolValue &Constant) { YamlIO.mapRequired("id", Constant.ID); - YamlIO.mapOptional("value", Constant.Value); - YamlIO.mapOptional("alignment", Constant.Alignment); + YamlIO.mapOptional("value", Constant.Value, StringValue()); + YamlIO.mapOptional("alignment", Constant.Alignment, (unsigned)0); } }; @@ -293,16 +322,22 @@ struct MachineJumpTable { struct Entry { UnsignedValue ID; std::vector<FlowStringValue> Blocks; + bool operator==(const Entry &Other) const { + return ID == Other.ID && Blocks == Other.Blocks; + } }; MachineJumpTableInfo::JTEntryKind Kind = MachineJumpTableInfo::EK_Custom32; std::vector<Entry> Entries; + bool operator==(const MachineJumpTable &Other) const { + return Kind == Other.Kind && Entries == Other.Entries; + } }; template <> struct MappingTraits<MachineJumpTable::Entry> { static void mapping(IO &YamlIO, MachineJumpTable::Entry &Entry) { YamlIO.mapRequired("id", Entry.ID); - YamlIO.mapOptional("blocks", Entry.Blocks); + YamlIO.mapOptional("blocks", Entry.Blocks, std::vector<FlowStringValue>()); } }; @@ -322,7 +357,8 @@ namespace yaml { template <> struct MappingTraits<MachineJumpTable> { static void mapping(IO &YamlIO, MachineJumpTable &JT) { YamlIO.mapRequired("kind", JT.Kind); - YamlIO.mapOptional("entries", JT.Entries); + YamlIO.mapOptional("entries", JT.Entries, + std::vector<MachineJumpTable::Entry>()); } }; @@ -351,25 +387,43 @@ struct MachineFrameInfo { bool HasMustTailInVarArgFunc = false; StringValue SavePoint; StringValue RestorePoint; + bool operator==(const MachineFrameInfo &Other) const { + return IsFrameAddressTaken == Other.IsFrameAddressTaken && + IsReturnAddressTaken == Other.IsReturnAddressTaken && + HasStackMap == Other.HasStackMap && + HasPatchPoint == Other.HasPatchPoint && + StackSize == Other.StackSize && + OffsetAdjustment == Other.OffsetAdjustment && + MaxAlignment == Other.MaxAlignment && + AdjustsStack == Other.AdjustsStack && HasCalls == Other.HasCalls && + StackProtector == Other.StackProtector && + MaxCallFrameSize == Other.MaxCallFrameSize && + HasOpaqueSPAdjustment == Other.HasOpaqueSPAdjustment && + HasVAStart == Other.HasVAStart && + HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc && + SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint; + } }; template <> struct MappingTraits<MachineFrameInfo> { static void mapping(IO &YamlIO, MachineFrameInfo &MFI) { - YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken); - YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken); - YamlIO.mapOptional("hasStackMap", MFI.HasStackMap); - YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint); - YamlIO.mapOptional("stackSize", MFI.StackSize); - YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment); - YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment); - YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack); - YamlIO.mapOptional("hasCalls", MFI.HasCalls); + YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken, false); + YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken, false); + YamlIO.mapOptional("hasStackMap", MFI.HasStackMap, false); + YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint, false); + YamlIO.mapOptional("stackSize", MFI.StackSize, (uint64_t)0); + YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment, (int)0); + YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment, (unsigned)0); + YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack, false); + YamlIO.mapOptional("hasCalls", MFI.HasCalls, false); YamlIO.mapOptional("stackProtector", MFI.StackProtector, StringValue()); // Don't print it out when it's empty. - YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, ~0u); - YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment); - YamlIO.mapOptional("hasVAStart", MFI.HasVAStart); - YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc); + YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, (unsigned)~0); + YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment, + false); + YamlIO.mapOptional("hasVAStart", MFI.HasVAStart, false); + YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc, + false); YamlIO.mapOptional("savePoint", MFI.SavePoint, StringValue()); // Don't print it out when it's empty. YamlIO.mapOptional("restorePoint", MFI.RestorePoint, @@ -403,22 +457,28 @@ struct MachineFunction { template <> struct MappingTraits<MachineFunction> { static void mapping(IO &YamlIO, MachineFunction &MF) { YamlIO.mapRequired("name", MF.Name); - YamlIO.mapOptional("alignment", MF.Alignment); - YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); - YamlIO.mapOptional("legalized", MF.Legalized); - YamlIO.mapOptional("regBankSelected", MF.RegBankSelected); - YamlIO.mapOptional("selected", MF.Selected); - YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness); - YamlIO.mapOptional("registers", MF.VirtualRegisters); - YamlIO.mapOptional("liveins", MF.LiveIns); - YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters); - YamlIO.mapOptional("frameInfo", MF.FrameInfo); - YamlIO.mapOptional("fixedStack", MF.FixedStackObjects); - YamlIO.mapOptional("stack", MF.StackObjects); - YamlIO.mapOptional("constants", MF.Constants); + YamlIO.mapOptional("alignment", MF.Alignment, (unsigned)0); + YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice, false); + YamlIO.mapOptional("legalized", MF.Legalized, false); + YamlIO.mapOptional("regBankSelected", MF.RegBankSelected, false); + YamlIO.mapOptional("selected", MF.Selected, false); + YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false); + YamlIO.mapOptional("registers", MF.VirtualRegisters, + std::vector<VirtualRegisterDefinition>()); + YamlIO.mapOptional("liveins", MF.LiveIns, + std::vector<MachineFunctionLiveIn>()); + YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters, + Optional<std::vector<FlowStringValue>>()); + YamlIO.mapOptional("frameInfo", MF.FrameInfo, MachineFrameInfo()); + YamlIO.mapOptional("fixedStack", MF.FixedStackObjects, + std::vector<FixedMachineStackObject>()); + YamlIO.mapOptional("stack", MF.StackObjects, + std::vector<MachineStackObject>()); + YamlIO.mapOptional("constants", MF.Constants, + std::vector<MachineConstantPoolValue>()); if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty()) - YamlIO.mapOptional("jumpTable", MF.JumpTableInfo); - YamlIO.mapOptional("body", MF.Body); + YamlIO.mapOptional("jumpTable", MF.JumpTableInfo, MachineJumpTable()); + YamlIO.mapOptional("body", MF.Body, BlockStringValue()); } }; diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index 26ed8bb487a2..051908c40df7 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -19,12 +19,12 @@ #include "llvm/ADT/ilist_node.h" #include "llvm/ADT/iterator_range.h" #include "llvm/ADT/simple_ilist.h" -#include "llvm/CodeGen/MachineInstrBundleIterator.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBundleIterator.h" #include "llvm/IR/DebugLoc.h" -#include "llvm/Support/BranchProbability.h" #include "llvm/MC/LaneBitmask.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Support/BranchProbability.h" #include <cassert> #include <cstdint> #include <functional> diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h index 10125864cd90..f67da7b01c54 100644 --- a/include/llvm/CodeGen/MachineFunction.h +++ b/include/llvm/CodeGen/MachineFunction.h @@ -22,11 +22,11 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/GraphTraits.h" -#include "llvm/ADT/ilist.h" -#include "llvm/ADT/iterator.h" #include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" +#include "llvm/ADT/ilist.h" +#include "llvm/ADT/iterator.h" #include "llvm/Analysis/EHPersonalities.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" diff --git a/include/llvm/CodeGen/MachineFunctionInitializer.h b/include/llvm/CodeGen/MachineFunctionInitializer.h deleted file mode 100644 index 0fbcb480b1ab..000000000000 --- a/include/llvm/CodeGen/MachineFunctionInitializer.h +++ /dev/null @@ -1,38 +0,0 @@ -//=- MachineFunctionInitializer.h - machine function initializer --*- C++ -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file declares an interface that allows custom machine function -// initialization. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_MACHINEFUNCTIONINITIALIZER_H -#define LLVM_CODEGEN_MACHINEFUNCTIONINITIALIZER_H - -namespace llvm { - -class MachineFunction; - -/// This interface provides a way to initialize machine functions after they are -/// created by the machine function analysis pass. -class MachineFunctionInitializer { - virtual void anchor(); - -public: - virtual ~MachineFunctionInitializer() = default; - - /// Initialize the machine function. - /// - /// Return true if error occurred. - virtual bool initializeMachineFunction(MachineFunction &MF) = 0; -}; - -} // end namespace llvm - -#endif // LLVM_CODEGEN_MACHINEFUNCTIONINITIALIZER_H diff --git a/include/llvm/CodeGen/MachineFunctionPass.h b/include/llvm/CodeGen/MachineFunctionPass.h index 653d1175d04b..6d978daa2018 100644 --- a/include/llvm/CodeGen/MachineFunctionPass.h +++ b/include/llvm/CodeGen/MachineFunctionPass.h @@ -19,8 +19,8 @@ #ifndef LLVM_CODEGEN_MACHINEFUNCTIONPASS_H #define LLVM_CODEGEN_MACHINEFUNCTIONPASS_H -#include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/Pass.h" namespace llvm { diff --git a/include/llvm/CodeGen/MachineMemOperand.h b/include/llvm/CodeGen/MachineMemOperand.h index a311124a35ba..4d83f27eac3c 100644 --- a/include/llvm/CodeGen/MachineMemOperand.h +++ b/include/llvm/CodeGen/MachineMemOperand.h @@ -21,7 +21,7 @@ #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/Metadata.h" -#include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*> +#include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*> #include "llvm/Support/AtomicOrdering.h" #include "llvm/Support/DataTypes.h" diff --git a/include/llvm/CodeGen/MachineModuleInfo.h b/include/llvm/CodeGen/MachineModuleInfo.h index d4ac58c3bd22..d64941a9e725 100644 --- a/include/llvm/CodeGen/MachineModuleInfo.h +++ b/include/llvm/CodeGen/MachineModuleInfo.h @@ -47,7 +47,6 @@ class BasicBlock; class CallInst; class Function; class MachineFunction; -class MachineFunctionInitializer; class MMIAddrLabelMap; class Module; class TargetMachine; @@ -126,7 +125,6 @@ class MachineModuleInfo : public ImmutablePass { /// comments in lib/Target/X86/X86FrameLowering.cpp for more details. bool UsesMorestackAddr; - MachineFunctionInitializer *MFInitializer; /// Maps IR Functions to their corresponding MachineFunctions. DenseMap<const Function*, std::unique_ptr<MachineFunction>> MachineFunctions; /// Next unique number available for a MachineFunction. @@ -150,14 +148,13 @@ public: void setModule(const Module *M) { TheModule = M; } const Module *getModule() const { return TheModule; } - void setMachineFunctionInitializer(MachineFunctionInitializer *MFInit) { - MFInitializer = MFInit; - } - /// Returns the MachineFunction constructed for the IR function \p F. - /// Creates a new MachineFunction and runs the MachineFunctionInitializer - /// if none exists yet. - MachineFunction &getMachineFunction(const Function &F); + /// Creates a new MachineFunction if none exists yet. + MachineFunction &getOrCreateMachineFunction(const Function &F); + + /// \bried Returns the MachineFunction associated to IR function \p F if there + /// is one, otherwise nullptr. + MachineFunction *getMachineFunction(const Function &F) const; /// Delete the MachineFunction \p MF and reset the link in the IR Function to /// Machine Function map. diff --git a/include/llvm/CodeGen/MachineModuleInfoImpls.h b/include/llvm/CodeGen/MachineModuleInfoImpls.h index f28a79c5b5cc..61cff3890b75 100644 --- a/include/llvm/CodeGen/MachineModuleInfoImpls.h +++ b/include/llvm/CodeGen/MachineModuleInfoImpls.h @@ -15,9 +15,9 @@ #ifndef LLVM_CODEGEN_MACHINEMODULEINFOIMPLS_H #define LLVM_CODEGEN_MACHINEMODULEINFOIMPLS_H -#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/BinaryFormat/Wasm.h" #include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/Support/Wasm.h" +#include "llvm/CodeGen/ValueTypes.h" namespace llvm { class MCSymbol; diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index e16354088296..2560399bcf54 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -14,8 +14,8 @@ #ifndef LLVM_CODEGEN_MACHINEOPERAND_H #define LLVM_CODEGEN_MACHINEOPERAND_H -#include "llvm/Support/DataTypes.h" #include "llvm/IR/Intrinsics.h" +#include "llvm/Support/DataTypes.h" #include <cassert> namespace llvm { diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h index c027783aae55..8347f00cbc7a 100644 --- a/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/include/llvm/CodeGen/MachineRegisterInfo.h @@ -18,9 +18,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IndexedMap.h" -#include "llvm/ADT/iterator_range.h" #include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/iterator_range.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h" #include "llvm/CodeGen/LowLevelType.h" #include "llvm/CodeGen/MachineBasicBlock.h" @@ -30,13 +30,13 @@ #include "llvm/MC/LaneBitmask.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" -#include <vector> #include <cassert> #include <cstddef> #include <cstdint> #include <iterator> #include <memory> #include <utility> +#include <vector> namespace llvm { diff --git a/include/llvm/CodeGen/RegAllocRegistry.h b/include/llvm/CodeGen/RegAllocRegistry.h index 5c7e9999cc9a..481747dc163e 100644 --- a/include/llvm/CodeGen/RegAllocRegistry.h +++ b/include/llvm/CodeGen/RegAllocRegistry.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/RegAllocRegistry.h -------------------------*- C++ -*-===// +//===- llvm/CodeGen/RegAllocRegistry.h --------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -19,16 +19,16 @@ namespace llvm { +class FunctionPass; + //===----------------------------------------------------------------------===// /// /// RegisterRegAlloc class - Track the registration of register allocators. /// //===----------------------------------------------------------------------===// class RegisterRegAlloc : public MachinePassRegistryNode { - public: - - typedef FunctionPass *(*FunctionPassCtor)(); + using FunctionPassCtor = FunctionPass *(*)(); static MachinePassRegistry Registry; @@ -36,22 +36,26 @@ public: : MachinePassRegistryNode(N, D, (MachinePassCtor)C) { Registry.Add(this); } + ~RegisterRegAlloc() { Registry.Remove(this); } // Accessors. - // RegisterRegAlloc *getNext() const { return (RegisterRegAlloc *)MachinePassRegistryNode::getNext(); } + static RegisterRegAlloc *getList() { return (RegisterRegAlloc *)Registry.getList(); } + static FunctionPassCtor getDefault() { return (FunctionPassCtor)Registry.getDefault(); } + static void setDefault(FunctionPassCtor C) { Registry.setDefault((MachinePassCtor)C); } + static void setListener(MachinePassRegistryListener *L) { Registry.setListener(L); } @@ -59,5 +63,4 @@ public: } // end namespace llvm - -#endif +#endif // LLVM_CODEGEN_REGALLOCREGISTRY_H diff --git a/include/llvm/CodeGen/RegisterPressure.h b/include/llvm/CodeGen/RegisterPressure.h index a3ea41d5236e..e997aaf269e3 100644 --- a/include/llvm/CodeGen/RegisterPressure.h +++ b/include/llvm/CodeGen/RegisterPressure.h @@ -32,7 +32,9 @@ namespace llvm { class LiveIntervals; +class MachineFunction; class MachineInstr; +class MachineRegisterInfo; class RegisterClassInfo; struct RegisterMaskPair { @@ -147,12 +149,14 @@ class PressureDiff { PressureChange PressureChanges[MaxPSets]; - typedef PressureChange* iterator; + using iterator = PressureChange *; + iterator nonconst_begin() { return &PressureChanges[0]; } iterator nonconst_end() { return &PressureChanges[MaxPSets]; } public: - typedef const PressureChange* const_iterator; + using const_iterator = const PressureChange *; + const_iterator begin() const { return &PressureChanges[0]; } const_iterator end() const { return &PressureChanges[MaxPSets]; } @@ -269,7 +273,7 @@ private: } }; - typedef SparseSet<IndexMaskPair> RegSet; + using RegSet = SparseSet<IndexMaskPair>; RegSet Regs; unsigned NumRegUnits; diff --git a/include/llvm/CodeGen/RegisterUsageInfo.h b/include/llvm/CodeGen/RegisterUsageInfo.h index 3f88032cb638..0a04bc6a89f4 100644 --- a/include/llvm/CodeGen/RegisterUsageInfo.h +++ b/include/llvm/CodeGen/RegisterUsageInfo.h @@ -1,4 +1,4 @@ -//==- RegisterUsageInfo.h - Register Usage Informartion Storage -*- C++ -*-===// +//==- RegisterUsageInfo.h - Register Usage Informartion Storage --*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -20,15 +20,15 @@ #define LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H #include "llvm/ADT/DenseMap.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/IR/Function.h" -#include "llvm/IR/Module.h" #include "llvm/Pass.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/raw_ostream.h" +#include <cstdint> +#include <vector> namespace llvm { +class Function; +class TargetMachine; + class PhysicalRegisterUsageInfo : public ImmutablePass { virtual void anchor(); @@ -70,6 +70,7 @@ private: const TargetMachine *TM; }; -} -#endif +} // end namespace llvm + +#endif // LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 97aa2aace822..4d72eda5c71a 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -18,9 +18,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/GraphTraits.h" -#include "llvm/ADT/iterator.h" #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/iterator.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetLowering.h" diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index d62bb9bf0b75..218e22e40234 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -17,10 +17,10 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/PointerIntPair.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SparseMultiSet.h" #include "llvm/ADT/SparseSet.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/ScheduleDAG.h" diff --git a/include/llvm/CodeGen/ScheduleDFS.h b/include/llvm/CodeGen/ScheduleDFS.h index c2013661cfff..d6a8c791392c 100644 --- a/include/llvm/CodeGen/ScheduleDFS.h +++ b/include/llvm/CodeGen/ScheduleDFS.h @@ -17,9 +17,9 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/ScheduleDAG.h" -#include <vector> #include <cassert> #include <cstdint> +#include <vector> namespace llvm { diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index a7a6227664de..badf927d0e95 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===// +//===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -16,7 +16,7 @@ #define LLVM_CODEGEN_SCHEDULERREGISTRY_H #include "llvm/CodeGen/MachinePassRegistry.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/Support/CodeGen.h" namespace llvm { @@ -26,15 +26,13 @@ namespace llvm { /// //===----------------------------------------------------------------------===// -class SelectionDAGISel; class ScheduleDAGSDNodes; -class SelectionDAG; -class MachineBasicBlock; +class SelectionDAGISel; class RegisterScheduler : public MachinePassRegistryNode { public: - typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, - CodeGenOpt::Level); + using FunctionPassCtor = ScheduleDAGSDNodes *(*)(SelectionDAGISel*, + CodeGenOpt::Level); static MachinePassRegistry Registry; @@ -45,13 +43,14 @@ public: // Accessors. - // RegisterScheduler *getNext() const { return (RegisterScheduler *)MachinePassRegistryNode::getNext(); } + static RegisterScheduler *getList() { return (RegisterScheduler *)Registry.getList(); } + static void setListener(MachinePassRegistryListener *L) { Registry.setListener(L); } @@ -103,4 +102,4 @@ ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS, } // end namespace llvm -#endif +#endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 4b1a375abd57..2ef7796a4a07 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -21,12 +21,12 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/FoldingSet.h" -#include "llvm/ADT/ilist.h" -#include "llvm/ADT/iterator.h" -#include "llvm/ADT/iterator_range.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" +#include "llvm/ADT/ilist.h" +#include "llvm/ADT/iterator.h" +#include "llvm/ADT/iterator_range.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/DAGCombine.h" #include "llvm/CodeGen/ISDOpcodes.h" @@ -1229,39 +1229,6 @@ public: AllNodes.insert(Position, AllNodes.remove(N)); } - /// Returns true if the opcode is a commutative binary operation. - static bool isCommutativeBinOp(unsigned Opcode) { - // FIXME: This should get its info from the td file, so that we can include - // target info. - switch (Opcode) { - case ISD::ADD: - case ISD::SMIN: - case ISD::SMAX: - case ISD::UMIN: - case ISD::UMAX: - case ISD::MUL: - case ISD::MULHU: - case ISD::MULHS: - case ISD::SMUL_LOHI: - case ISD::UMUL_LOHI: - case ISD::FADD: - case ISD::FMUL: - case ISD::AND: - case ISD::OR: - case ISD::XOR: - case ISD::SADDO: - case ISD::UADDO: - case ISD::ADDC: - case ISD::ADDE: - case ISD::FMINNUM: - case ISD::FMAXNUM: - case ISD::FMINNAN: - case ISD::FMAXNAN: - return true; - default: return false; - } - } - /// Returns an APFloat semantics tag appropriate for the given type. If VT is /// a vector type, the element semantics are returned. static const fltSemantics &EVTToAPFloatSemantics(EVT VT) { diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 3a4feb322092..0cd26d35a482 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -24,11 +24,11 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/GraphTraits.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/ilist_node.h" #include "llvm/ADT/iterator.h" #include "llvm/ADT/iterator_range.h" -#include "llvm/ADT/SmallPtrSet.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineValueType.h" diff --git a/include/llvm/CodeGen/SlotIndexes.h b/include/llvm/CodeGen/SlotIndexes.h index a275b2721b44..a7b16e7a9ed2 100644 --- a/include/llvm/CodeGen/SlotIndexes.h +++ b/include/llvm/CodeGen/SlotIndexes.h @@ -20,10 +20,10 @@ #define LLVM_CODEGEN_SLOTINDEXES_H #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/ilist.h" #include "llvm/ADT/IntervalMap.h" #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/ilist.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" diff --git a/include/llvm/CodeGen/StackProtector.h b/include/llvm/CodeGen/StackProtector.h index b970de71f862..72de212d0df9 100644 --- a/include/llvm/CodeGen/StackProtector.h +++ b/include/llvm/CodeGen/StackProtector.h @@ -19,18 +19,20 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Triple.h" -#include "llvm/CodeGen/TargetPassConfig.h" -#include "llvm/IR/Dominators.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/ValueMap.h" #include "llvm/Pass.h" -#include "llvm/Target/TargetLowering.h" -#include "llvm/Target/TargetMachine.h" namespace llvm { +class BasicBlock; +class DominatorTree; class Function; +class Instruction; class Module; -class PHINode; +class TargetLoweringBase; +class TargetMachine; +class Type; class StackProtector : public FunctionPass { public: @@ -48,7 +50,7 @@ public: }; /// A mapping of AllocaInsts to their required SSP layout. - typedef ValueMap<const AllocaInst *, SSPLayoutKind> SSPLayoutMap; + using SSPLayoutMap = ValueMap<const AllocaInst *, SSPLayoutKind>; private: const TargetMachine *TM = nullptr; @@ -119,10 +121,7 @@ public: initializeStackProtectorPass(*PassRegistry::getPassRegistry()); } - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired<TargetPassConfig>(); - AU.addPreserved<DominatorTreeWrapperPass>(); - } + void getAnalysisUsage(AnalysisUsage &AU) const override; SSPLayoutKind getSSPLayout(const AllocaInst *AI) const; diff --git a/include/llvm/CodeGen/TailDuplicator.h b/include/llvm/CodeGen/TailDuplicator.h index b667245fd3c0..483c0ab1eec9 100644 --- a/include/llvm/CodeGen/TailDuplicator.h +++ b/include/llvm/CodeGen/TailDuplicator.h @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/TailDuplicator.h ---------------------------*- C++ -*-===// +//===- llvm/CodeGen/TailDuplicator.h ----------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -15,19 +15,27 @@ #ifndef LLVM_CODEGEN_TAILDUPLICATOR_H #define LLVM_CODEGEN_TAILDUPLICATOR_H +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/MachineSSAUpdater.h" #include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include <utility> +#include <vector> namespace llvm { -extern cl::opt<unsigned> TailDupIndirectBranchSize; +class MachineBasicBlock; +class MachineBranchProbabilityInfo; +class MachineFunction; +class MachineInstr; +class MachineModuleInfo; +class MachineRegisterInfo; +class TargetRegisterInfo; /// Utility class to perform tail duplication. class TailDuplicator { @@ -46,7 +54,7 @@ class TailDuplicator { // For each virtual register in SSAUpdateVals keep a list of source virtual // registers. - typedef std::vector<std::pair<MachineBasicBlock *, unsigned>> AvailableValsTy; + using AvailableValsTy = std::vector<std::pair<MachineBasicBlock *, unsigned>>; DenseMap<unsigned, AvailableValsTy> SSAUpdateVals; @@ -62,11 +70,14 @@ public: void initMF(MachineFunction &MF, const MachineBranchProbabilityInfo *MBPI, bool LayoutMode, unsigned TailDupSize = 0); + bool tailDuplicateBlocks(); static bool isSimpleBB(MachineBasicBlock *TailBB); bool shouldTailDuplicate(bool IsSimple, MachineBasicBlock &TailBB); + /// Returns true if TailBB can successfully be duplicated into PredBB bool canTailDuplicate(MachineBasicBlock *TailBB, MachineBasicBlock *PredBB); + /// Tail duplicate a single basic block into its predecessors, and then clean /// up. /// If \p DuplicatePreds is not null, it will be updated to contain the list @@ -77,10 +88,10 @@ public: bool IsSimple, MachineBasicBlock *MBB, MachineBasicBlock *ForcedLayoutPred, SmallVectorImpl<MachineBasicBlock*> *DuplicatedPreds = nullptr, - llvm::function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr); + function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr); private: - typedef TargetInstrInfo::RegSubRegPair RegSubRegPair; + using RegSubRegPair = TargetInstrInfo::RegSubRegPair; void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, MachineBasicBlock *BB); @@ -112,9 +123,9 @@ private: void removeDeadBlock( MachineBasicBlock *MBB, - llvm::function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr); + function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr); }; -} // End llvm namespace +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_TAILDUPLICATOR_H diff --git a/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h b/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h index adf2b3ea1c9b..106a084a95c0 100644 --- a/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h +++ b/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h @@ -41,6 +41,11 @@ public: TargetLoweringObjectFileELF() = default; ~TargetLoweringObjectFileELF() override = default; + /// Emit Obj-C garbage collection and linker options. + void emitModuleFlags(MCStreamer &Streamer, + ArrayRef<Module::ModuleFlagEntry> ModuleFlags, + const TargetMachine &TM) const override; + void emitPersonalityValue(MCStreamer &Streamer, const DataLayout &TM, const MCSymbol *Sym) const override; @@ -149,8 +154,7 @@ public: MCSection *getSectionForJumpTable(const Function &F, const TargetMachine &TM) const override; - /// Emit Obj-C garbage collection and linker options. Only linker option - /// emission is implemented for COFF. + /// Emit Obj-C garbage collection and linker options. void emitModuleFlags(MCStreamer &Streamer, ArrayRef<Module::ModuleFlagEntry> ModuleFlags, const TargetMachine &TM) const override; diff --git a/include/llvm/CodeGen/TargetPassConfig.h b/include/llvm/CodeGen/TargetPassConfig.h index fcf1937c186e..c109b7489cca 100644 --- a/include/llvm/CodeGen/TargetPassConfig.h +++ b/include/llvm/CodeGen/TargetPassConfig.h @@ -119,6 +119,10 @@ protected: /// callers. bool RequireCodeGenSCCOrder; + /// Add the actual instruction selection passes. This does not include + /// preparation passes on IR. + bool addCoreISelPasses(); + public: TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm); // Dummy constructor. @@ -206,6 +210,13 @@ public: /// has not be overriden on the command line with '-regalloc=...' bool usingDefaultRegAlloc() const; + /// High level function that adds all passes necessary to go from llvm IR + /// representation to the MI representation. + /// Adds IR based lowering and target specific optimization passes and finally + /// the core instruction selection passes. + /// \returns true if an error occured, false otherwise. + bool addISelPasses(); + /// Add common target configurable passes that perform LLVM IR to IR /// transforms following machine independent optimization. virtual void addIRPasses(); diff --git a/include/llvm/CodeGen/TargetSchedule.h b/include/llvm/CodeGen/TargetSchedule.h index 4365fca74bf1..f23667976468 100644 --- a/include/llvm/CodeGen/TargetSchedule.h +++ b/include/llvm/CodeGen/TargetSchedule.h @@ -16,6 +16,7 @@ #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H #define LLVM_CODEGEN_TARGETSCHEDULE_H +#include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallVector.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/MCSchedule.h" @@ -123,7 +124,7 @@ public: } #endif - typedef const MCWriteProcResEntry *ProcResIter; + using ProcResIter = const MCWriteProcResEntry *; // \brief Get an iterator into the processor resources consumed by this // scheduling class. diff --git a/include/llvm/CodeGen/VirtRegMap.h b/include/llvm/CodeGen/VirtRegMap.h index d7e92094877d..b9076353fd07 100644 --- a/include/llvm/CodeGen/VirtRegMap.h +++ b/include/llvm/CodeGen/VirtRegMap.h @@ -102,14 +102,7 @@ namespace llvm { /// @brief creates a mapping for the specified virtual register to /// the specified physical register - void assignVirt2Phys(unsigned virtReg, unsigned physReg) { - assert(TargetRegisterInfo::isVirtualRegister(virtReg) && - TargetRegisterInfo::isPhysicalRegister(physReg)); - assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && - "attempt to assign physical register to already mapped " - "virtual register"); - Virt2PhysMap[virtReg] = physReg; - } + void assignVirt2Phys(unsigned virtReg, MCPhysReg physReg); /// @brief clears the specified virtual register's, physical /// register mapping |