diff options
Diffstat (limited to 'include')
62 files changed, 569 insertions, 144 deletions
diff --git a/include/llvm/ADT/DenseSet.h b/include/llvm/ADT/DenseSet.h index 7e5171c3f3a4..b495e25dd5e5 100644 --- a/include/llvm/ADT/DenseSet.h +++ b/include/llvm/ADT/DenseSet.h @@ -17,7 +17,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMapInfo.h" #include "llvm/Support/type_traits.h" -#include <algorithm> +#include <algorithm> #include <cstddef> #include <initializer_list> #include <iterator> diff --git a/include/llvm/Analysis/BasicAliasAnalysis.h b/include/llvm/Analysis/BasicAliasAnalysis.h index fa81539a9d6f..6344e84b58eb 100644 --- a/include/llvm/Analysis/BasicAliasAnalysis.h +++ b/include/llvm/Analysis/BasicAliasAnalysis.h @@ -43,6 +43,7 @@ class LoopInfo; class PHINode; class SelectInst; class TargetLibraryInfo; +class PhiValues; class Value; /// This is the AA result object for the basic, local, and stateless alias @@ -60,19 +61,22 @@ class BasicAAResult : public AAResultBase<BasicAAResult> { AssumptionCache &AC; DominatorTree *DT; LoopInfo *LI; + PhiValues *PV; public: BasicAAResult(const DataLayout &DL, const Function &F, const TargetLibraryInfo &TLI, AssumptionCache &AC, - DominatorTree *DT = nullptr, LoopInfo *LI = nullptr) - : AAResultBase(), DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), LI(LI) {} + DominatorTree *DT = nullptr, LoopInfo *LI = nullptr, + PhiValues *PV = nullptr) + : AAResultBase(), DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), LI(LI), PV(PV) + {} BasicAAResult(const BasicAAResult &Arg) : AAResultBase(Arg), DL(Arg.DL), F(Arg.F), TLI(Arg.TLI), AC(Arg.AC), - DT(Arg.DT), LI(Arg.LI) {} + DT(Arg.DT), LI(Arg.LI), PV(Arg.PV) {} BasicAAResult(BasicAAResult &&Arg) : AAResultBase(std::move(Arg)), DL(Arg.DL), F(Arg.F), TLI(Arg.TLI), - AC(Arg.AC), DT(Arg.DT), LI(Arg.LI) {} + AC(Arg.AC), DT(Arg.DT), LI(Arg.LI), PV(Arg.PV) {} /// Handle invalidation events in the new pass manager. bool invalidate(Function &Fn, const PreservedAnalyses &PA, diff --git a/include/llvm/Analysis/LoopAccessAnalysis.h b/include/llvm/Analysis/LoopAccessAnalysis.h index 0f3f2be9aeb4..d27b3e42bbeb 100644 --- a/include/llvm/Analysis/LoopAccessAnalysis.h +++ b/include/llvm/Analysis/LoopAccessAnalysis.h @@ -682,7 +682,7 @@ bool sortPtrAccesses(ArrayRef<Value *> VL, const DataLayout &DL, SmallVectorImpl<unsigned> &SortedIndices); /// Returns true if the memory operations \p A and \p B are consecutive. -/// This is a simple API that does not depend on the analysis pass. +/// This is a simple API that does not depend on the analysis pass. bool isConsecutiveAccess(Value *A, Value *B, const DataLayout &DL, ScalarEvolution &SE, bool CheckType = true); @@ -734,7 +734,7 @@ private: /// accesses of a loop. /// /// It runs the analysis for a loop on demand. This can be initiated by -/// querying the loop access info via AM.getResult<LoopAccessAnalysis>. +/// querying the loop access info via AM.getResult<LoopAccessAnalysis>. /// getResult return a LoopAccessInfo object. See this class for the /// specifics of what information is provided. class LoopAccessAnalysis diff --git a/include/llvm/Analysis/MemoryDependenceAnalysis.h b/include/llvm/Analysis/MemoryDependenceAnalysis.h index 1c6ec98dfedc..1c40cffc7f67 100644 --- a/include/llvm/Analysis/MemoryDependenceAnalysis.h +++ b/include/llvm/Analysis/MemoryDependenceAnalysis.h @@ -44,6 +44,7 @@ class Instruction; class LoadInst; class PHITransAddr; class TargetLibraryInfo; +class PhiValues; class Value; /// A memory dependence query can return one of three different answers. @@ -360,13 +361,14 @@ private: AssumptionCache &AC; const TargetLibraryInfo &TLI; DominatorTree &DT; + PhiValues &PV; PredIteratorCache PredCache; public: MemoryDependenceResults(AliasAnalysis &AA, AssumptionCache &AC, const TargetLibraryInfo &TLI, - DominatorTree &DT) - : AA(AA), AC(AC), TLI(TLI), DT(DT) {} + DominatorTree &DT, PhiValues &PV) + : AA(AA), AC(AC), TLI(TLI), DT(DT), PV(PV) {} /// Handle invalidation in the new PM. bool invalidate(Function &F, const PreservedAnalyses &PA, diff --git a/include/llvm/Analysis/MustExecute.h b/include/llvm/Analysis/MustExecute.h index 8daf156567cd..97ad76d451ca 100644 --- a/include/llvm/Analysis/MustExecute.h +++ b/include/llvm/Analysis/MustExecute.h @@ -10,7 +10,7 @@ /// Contains a collection of routines for determining if a given instruction is /// guaranteed to execute if a given point in control flow is reached. The most /// common example is an instruction within a loop being provably executed if we -/// branch to the header of it's containing loop. +/// branch to the header of it's containing loop. /// //===----------------------------------------------------------------------===// @@ -58,7 +58,7 @@ void computeLoopSafetyInfo(LoopSafetyInfo *, Loop *); bool isGuaranteedToExecute(const Instruction &Inst, const DominatorTree *DT, const Loop *CurLoop, const LoopSafetyInfo *SafetyInfo); - + } #endif diff --git a/include/llvm/Analysis/TargetTransformInfoImpl.h b/include/llvm/Analysis/TargetTransformInfoImpl.h index e14e2bd44034..d80ae1d6845d 100644 --- a/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -326,7 +326,7 @@ public: bool haveFastSqrt(Type *Ty) { return false; } bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) { return true; } - + unsigned getFPOpCost(Type *Ty) { return TargetTransformInfo::TCC_Basic; } int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, diff --git a/include/llvm/Analysis/ValueTracking.h b/include/llvm/Analysis/ValueTracking.h index e6a219a8045b..c1a91a8e5981 100644 --- a/include/llvm/Analysis/ValueTracking.h +++ b/include/llvm/Analysis/ValueTracking.h @@ -464,7 +464,7 @@ class Value; /// This is equivelent to saying that all instructions within the basic block /// are guaranteed to transfer execution to their successor within the basic /// block. This has the same assumptions w.r.t. undefined behavior as the - /// instruction variant of this function. + /// instruction variant of this function. bool isGuaranteedToTransferExecutionToSuccessor(const BasicBlock *BB); /// Return true if this function can prove that the instruction I diff --git a/include/llvm/BinaryFormat/Dwarf.def b/include/llvm/BinaryFormat/Dwarf.def index 57e259615d0c..944c5dd1c157 100644 --- a/include/llvm/BinaryFormat/Dwarf.def +++ b/include/llvm/BinaryFormat/Dwarf.def @@ -856,6 +856,7 @@ HANDLE_DW_UT(0x06, split_type) // TODO: Add Mach-O and COFF names. // Official DWARF sections. HANDLE_DWARF_SECTION(DebugAbbrev, ".debug_abbrev", "debug-abbrev") +HANDLE_DWARF_SECTION(DebugAddr, ".debug_addr", "debug-addr") HANDLE_DWARF_SECTION(DebugAranges, ".debug_aranges", "debug-aranges") HANDLE_DWARF_SECTION(DebugInfo, ".debug_info", "debug-info") HANDLE_DWARF_SECTION(DebugTypes, ".debug_types", "debug-types") diff --git a/include/llvm/BinaryFormat/ELF.h b/include/llvm/BinaryFormat/ELF.h index 0f3f1939ce68..2e778779117b 100644 --- a/include/llvm/BinaryFormat/ELF.h +++ b/include/llvm/BinaryFormat/ELF.h @@ -413,8 +413,10 @@ enum { // ARM Specific e_flags enum : unsigned { - EF_ARM_SOFT_FLOAT = 0x00000200U, - EF_ARM_VFP_FLOAT = 0x00000400U, + EF_ARM_SOFT_FLOAT = 0x00000200U, // Legacy pre EABI_VER5 + EF_ARM_ABI_FLOAT_SOFT = 0x00000200U, // EABI_VER5 + EF_ARM_VFP_FLOAT = 0x00000400U, // Legacy pre EABI_VER5 + EF_ARM_ABI_FLOAT_HARD = 0x00000400U, // EABI_VER5 EF_ARM_EABI_UNKNOWN = 0x00000000U, EF_ARM_EABI_VER1 = 0x01000000U, EF_ARM_EABI_VER2 = 0x02000000U, diff --git a/include/llvm/CodeGen/GCStrategy.h b/include/llvm/CodeGen/GCStrategy.h index 91604fd2df87..f835bacfb548 100644 --- a/include/llvm/CodeGen/GCStrategy.h +++ b/include/llvm/CodeGen/GCStrategy.h @@ -104,12 +104,12 @@ public: const std::string &getName() const { return Name; } /// By default, write barriers are replaced with simple store - /// instructions. If true, you must provide a custom pass to lower + /// instructions. If true, you must provide a custom pass to lower /// calls to \@llvm.gcwrite. bool customWriteBarrier() const { return CustomWriteBarriers; } /// By default, read barriers are replaced with simple load - /// instructions. If true, you must provide a custom pass to lower + /// instructions. If true, you must provide a custom pass to lower /// calls to \@llvm.gcread. bool customReadBarrier() const { return CustomReadBarriers; } @@ -146,7 +146,7 @@ public: } /// By default, roots are left for the code generator so it can generate a - /// stack map. If true, you must provide a custom pass to lower + /// stack map. If true, you must provide a custom pass to lower /// calls to \@llvm.gcroot. bool customRoots() const { return CustomRoots; } diff --git a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h index 713d72eb4c9b..a8c26082f221 100644 --- a/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h +++ b/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h @@ -786,7 +786,7 @@ public: /// setAction ({G_ADD, 0, LLT::scalar(32)}, Legal); /// setLegalizeScalarToDifferentSizeStrategy( /// G_ADD, 0, widenToLargerTypesAndNarrowToLargest); - /// will end up defining getAction({G_ADD, 0, T}) to return the following + /// will end up defining getAction({G_ADD, 0, T}) to return the following /// actions for different scalar types T: /// LLT::scalar(1)..LLT::scalar(31): {WidenScalar, 0, LLT::scalar(32)} /// LLT::scalar(32): {Legal, 0, LLT::scalar(32)} @@ -814,7 +814,7 @@ public: VectorElementSizeChangeStrategies[OpcodeIdx][TypeIdx] = S; } - /// A SizeChangeStrategy for the common case where legalization for a + /// A SizeChangeStrategy for the common case where legalization for a /// particular operation consists of only supporting a specific set of type /// sizes. E.g. /// setAction ({G_DIV, 0, LLT::scalar(32)}, Legal); diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 983a4e680d5c..ac1673de5f3f 100644 --- a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -942,6 +942,16 @@ public: /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO); + + /// Build and insert \p Res = G_BLOCK_ADDR \p BA + /// + /// G_BLOCK_ADDR computes the address of a basic block. + /// + /// \pre setBasicBlock or setMI must have been called. + /// \pre \p Res must be a generic virtual register of a pointer type. + /// + /// \return The newly created instruction. + MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA); }; /// A CRTP class that contains methods for building instructions that can diff --git a/include/llvm/CodeGen/MachORelocation.h b/include/llvm/CodeGen/MachORelocation.h index 8c9b7a84e5b8..cbb49695af75 100644 --- a/include/llvm/CodeGen/MachORelocation.h +++ b/include/llvm/CodeGen/MachORelocation.h @@ -27,15 +27,15 @@ namespace llvm { uint32_t r_symbolnum; // symbol index if r_extern == 1 else section index bool r_pcrel; // was relocated pc-relative already uint8_t r_length; // length = 2 ^ r_length - bool r_extern; // + bool r_extern; // uint8_t r_type; // if not 0, machine-specific relocation type. bool r_scattered; // 1 = scattered, 0 = non-scattered int32_t r_value; // the value the item to be relocated is referring // to. - public: + public: uint32_t getPackedFields() const { if (r_scattered) - return (1 << 31) | (r_pcrel << 30) | ((r_length & 3) << 28) | + return (1 << 31) | (r_pcrel << 30) | ((r_length & 3) << 28) | ((r_type & 15) << 24) | (r_address & 0x00FFFFFF); else return (r_symbolnum << 8) | (r_pcrel << 7) | ((r_length & 3) << 5) | @@ -45,8 +45,8 @@ namespace llvm { uint32_t getRawAddress() const { return r_address; } MachORelocation(uint32_t addr, uint32_t index, bool pcrel, uint8_t len, - bool ext, uint8_t type, bool scattered = false, - int32_t value = 0) : + bool ext, uint8_t type, bool scattered = false, + int32_t value = 0) : r_address(addr), r_symbolnum(index), r_pcrel(pcrel), r_length(len), r_extern(ext), r_type(type), r_scattered(scattered), r_value(value) {} }; diff --git a/include/llvm/CodeGen/MachineModuleInfo.h b/include/llvm/CodeGen/MachineModuleInfo.h index 6be304fa368b..554e89019b76 100644 --- a/include/llvm/CodeGen/MachineModuleInfo.h +++ b/include/llvm/CodeGen/MachineModuleInfo.h @@ -105,7 +105,7 @@ class MachineModuleInfo : public ImmutablePass { /// basic block's address of label. MMIAddrLabelMap *AddrLabelSymbols; - // TODO: Ideally, what we'd like is to have a switch that allows emitting + // TODO: Ideally, what we'd like is to have a switch that allows emitting // synchronous (precise at call-sites only) CFA into .eh_frame. However, // even under this switch, we'd like .debug_frame to be precise when using // -g. At this moment, there's no way to specify that some CFI directives diff --git a/include/llvm/CodeGen/MachineOutliner.h b/include/llvm/CodeGen/MachineOutliner.h index 4249a99a891b..95bfc24b57ff 100644 --- a/include/llvm/CodeGen/MachineOutliner.h +++ b/include/llvm/CodeGen/MachineOutliner.h @@ -19,6 +19,7 @@ #include "llvm/CodeGen/LiveRegUnits.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/CodeGen/LivePhysRegs.h" namespace llvm { namespace outliner { @@ -74,6 +75,13 @@ public: /// cost model information. LiveRegUnits LRU; + /// Contains the accumulated register liveness information for the + /// instructions in this \p Candidate. + /// + /// This is optionally used by the target to determine which registers have + /// been used across the sequence. + LiveRegUnits UsedInSequence; + /// Return the number of instructions in this Candidate. unsigned getLength() const { return Len; } @@ -137,6 +145,12 @@ public: // outlining candidate. std::for_each(MBB->rbegin(), (MachineBasicBlock::reverse_iterator)front(), [this](MachineInstr &MI) { LRU.stepBackward(MI); }); + + // Walk over the sequence itself and figure out which registers were used + // in the sequence. + UsedInSequence.init(TRI); + std::for_each(front(), std::next(back()), + [this](MachineInstr &MI) { UsedInSequence.accumulate(MI); }); } }; diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 5e7837834ec8..56adc2e2fbfa 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -252,7 +252,7 @@ class TargetRegisterInfo; MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr. public: - SUnit *OrigNode = nullptr; ///< If not this, the node from which this node + SUnit *OrigNode = nullptr; ///< If not this, the node from which this node /// was cloned. (SD scheduling only) const MCSchedClassDesc *SchedClass = diff --git a/include/llvm/CodeGen/StackMaps.h b/include/llvm/CodeGen/StackMaps.h index 3c9850265737..e584a4136e4f 100644 --- a/include/llvm/CodeGen/StackMaps.h +++ b/include/llvm/CodeGen/StackMaps.h @@ -156,7 +156,7 @@ class StatepointOpers { // TODO:: we should change the STATEPOINT representation so that CC and // Flags should be part of meta operands, with args and deopt operands, and // gc operands all prefixed by their length and a type code. This would be - // much more consistent. + // much more consistent. public: // These values are aboolute offsets into the operands of the statepoint // instruction. diff --git a/include/llvm/CodeGen/TargetLowering.h b/include/llvm/CodeGen/TargetLowering.h index d5ff71cf9ac2..40540bd6e1ff 100644 --- a/include/llvm/CodeGen/TargetLowering.h +++ b/include/llvm/CodeGen/TargetLowering.h @@ -718,7 +718,7 @@ public: /// always broken down into scalars in some contexts. This occurs even if the /// vector type is legal. virtual unsigned getVectorTypeBreakdownForCallingConv( - LLVMContext &Context, EVT VT, EVT &IntermediateVT, + LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const { return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, RegisterVT); @@ -1174,7 +1174,7 @@ public: /// are legal for some operations and not for other operations. /// For MIPS all vector types must be passed through the integer register set. virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, - EVT VT) const { + CallingConv::ID CC, EVT VT) const { return getRegisterType(Context, VT); } @@ -1182,6 +1182,7 @@ public: /// this occurs when a vector type is used, as vector are passed through the /// integer register set. virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, + CallingConv::ID CC, EVT VT) const { return getNumRegisters(Context, VT); } @@ -3489,10 +3490,10 @@ public: // SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, - std::vector<SDNode *> *Created) const; + SmallVectorImpl<SDNode *> &Created) const; SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, - std::vector<SDNode *> *Created) const; + SmallVectorImpl<SDNode *> &Created) const; /// Targets may override this function to provide custom SDIV lowering for /// power-of-2 denominators. If the target returns an empty SDValue, LLVM @@ -3500,7 +3501,7 @@ public: /// operations. virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, - std::vector<SDNode *> *Created) const; + SmallVectorImpl<SDNode *> &Created) const; /// Indicate whether this target prefers to combine FDIVs with the same /// divisor. If the transform should never be done, return zero. If the @@ -3690,7 +3691,7 @@ private: /// Given an LLVM IR type and return type attributes, compute the return value /// EVTs and flags, and optionally also the offsets, if the return value is /// being lowered to memory. -void GetReturnInfo(Type *ReturnType, AttributeList attr, +void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl<ISD::OutputArg> &Outs, const TargetLowering &TLI, const DataLayout &DL); diff --git a/include/llvm/CodeGen/TargetPassConfig.h b/include/llvm/CodeGen/TargetPassConfig.h index 5918c524d11c..8f5c9cb8c3fa 100644 --- a/include/llvm/CodeGen/TargetPassConfig.h +++ b/include/llvm/CodeGen/TargetPassConfig.h @@ -16,7 +16,7 @@ #include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" -#include <cassert> +#include <cassert> #include <string> namespace llvm { diff --git a/include/llvm/CodeGen/TargetRegisterInfo.h b/include/llvm/CodeGen/TargetRegisterInfo.h index 538a5845466c..55a8ba630a59 100644 --- a/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/include/llvm/CodeGen/TargetRegisterInfo.h @@ -456,7 +456,7 @@ public: /// stack frame offset. The first register is closest to the incoming stack /// pointer if stack grows down, and vice versa. /// Notice: This function does not take into account disabled CSRs. - /// In most cases you will want to use instead the function + /// In most cases you will want to use instead the function /// getCalleeSavedRegs that is implemented in MachineRegisterInfo. virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const = 0; @@ -518,7 +518,7 @@ public: /// guaranteed to be restored before any uses. This is useful for targets that /// have call sequences where a GOT register may be updated by the caller /// prior to a call and is guaranteed to be restored (also by the caller) - /// after the call. + /// after the call. virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const { return false; diff --git a/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def b/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def index 41c538076798..b5f1cc0198dc 100644 --- a/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def +++ b/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def @@ -143,7 +143,6 @@ CV_SYMBOL(S_MANSLOT , 0x1120) CV_SYMBOL(S_MANMANYREG , 0x1121) CV_SYMBOL(S_MANREGREL , 0x1122) CV_SYMBOL(S_MANMANYREG2 , 0x1123) -CV_SYMBOL(S_UNAMESPACE , 0x1124) CV_SYMBOL(S_DATAREF , 0x1126) CV_SYMBOL(S_ANNOTATIONREF , 0x1128) CV_SYMBOL(S_TOKENREF , 0x1129) @@ -255,6 +254,7 @@ SYMBOL_RECORD_ALIAS(S_GMANDATA , 0x111d, ManagedGlobalData, DataSym) SYMBOL_RECORD(S_LTHREAD32 , 0x1112, ThreadLocalDataSym) SYMBOL_RECORD_ALIAS(S_GTHREAD32 , 0x1113, GlobalTLS, ThreadLocalDataSym) +SYMBOL_RECORD(S_UNAMESPACE , 0x1124, UsingNamespaceSym) #undef CV_SYMBOL #undef SYMBOL_RECORD diff --git a/include/llvm/DebugInfo/CodeView/SymbolRecord.h b/include/llvm/DebugInfo/CodeView/SymbolRecord.h index cf267f23967b..93306824012e 100644 --- a/include/llvm/DebugInfo/CodeView/SymbolRecord.h +++ b/include/llvm/DebugInfo/CodeView/SymbolRecord.h @@ -942,6 +942,19 @@ public: uint32_t RecordOffset; }; +// S_UNAMESPACE +class UsingNamespaceSym : public SymbolRecord { +public: + explicit UsingNamespaceSym(SymbolRecordKind Kind) : SymbolRecord(Kind) {} + explicit UsingNamespaceSym(uint32_t RecordOffset) + : SymbolRecord(SymbolRecordKind::RegRelativeSym), + RecordOffset(RecordOffset) {} + + StringRef Name; + + uint32_t RecordOffset; +}; + // S_ANNOTATION using CVSymbol = CVRecord<SymbolKind>; diff --git a/include/llvm/DebugInfo/DIContext.h b/include/llvm/DebugInfo/DIContext.h index f89eb34fdd77..bbdd5e0d9c3f 100644 --- a/include/llvm/DebugInfo/DIContext.h +++ b/include/llvm/DebugInfo/DIContext.h @@ -154,6 +154,8 @@ enum DIDumpType : unsigned { struct DIDumpOptions { unsigned DumpType = DIDT_All; unsigned RecurseDepth = -1U; + uint16_t Version = 0; // DWARF version to assume when extracting. + uint8_t AddrSize = 4; // Address byte size to assume when extracting. bool ShowAddresses = true; bool ShowChildren = false; bool ShowParents = false; diff --git a/include/llvm/DebugInfo/DWARF/DWARFContext.h b/include/llvm/DebugInfo/DWARF/DWARFContext.h index fe7430c9f04c..f5419fe02421 100644 --- a/include/llvm/DebugInfo/DWARF/DWARFContext.h +++ b/include/llvm/DebugInfo/DWARF/DWARFContext.h @@ -323,6 +323,10 @@ public: /// have initialized the relevant target descriptions. Error loadRegisterInfo(const object::ObjectFile &Obj); + /// Get address size from CUs. + /// TODO: refactor compile_units() to make this const. + uint8_t getCUAddrSize(); + private: /// Return the compile unit which contains instruction with provided /// address. diff --git a/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h b/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h index 10e146b70ec7..1ed087520b30 100644 --- a/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h +++ b/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h @@ -51,6 +51,8 @@ public: /// reflect the absolute address of this pointer. Optional<uint64_t> getEncodedPointer(uint32_t *Offset, uint8_t Encoding, uint64_t AbsPosOffset = 0) const; + + size_t size() const { return Section == nullptr ? 0 : Section->Data.size(); } }; } // end namespace llvm diff --git a/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h b/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h new file mode 100644 index 000000000000..ffbd1b06d1e2 --- /dev/null +++ b/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h @@ -0,0 +1,98 @@ +//===- DWARFDebugAddr.h -------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===------------------------------------------------------------------===// + +#ifndef LLVM_DEBUGINFO_DWARFDEBUGADDR_H +#define LLVM_DEBUGINFO_DWARFDEBUGADDR_H + +#include "llvm/BinaryFormat/Dwarf.h" +#include "llvm/DebugInfo/DIContext.h" +#include "llvm/DebugInfo/DWARF/DWARFDataExtractor.h" +#include "llvm/Support/Errc.h" +#include "llvm/Support/Error.h" +#include <cstdint> +#include <map> +#include <vector> + +namespace llvm { + +class Error; +class raw_ostream; + +/// A class representing an address table as specified in DWARF v5. +/// The table consists of a header followed by an array of address values from +/// .debug_addr section. +class DWARFDebugAddrTable { +public: + struct Header { + /// The total length of the entries for this table, not including the length + /// field itself. + uint32_t Length = 0; + /// The DWARF version number. + uint16_t Version = 5; + /// The size in bytes of an address on the target architecture. For + /// segmented addressing, this is the size of the offset portion of the + /// address. + uint8_t AddrSize; + /// The size in bytes of a segment selector on the target architecture. + /// If the target system uses a flat address space, this value is 0. + uint8_t SegSize = 0; + }; + +private: + dwarf::DwarfFormat Format; + uint32_t HeaderOffset; + Header HeaderData; + uint32_t DataSize = 0; + std::vector<uint64_t> Addrs; + +public: + void clear(); + + /// Extract an entire table, including all addresses. + Error extract(DWARFDataExtractor Data, uint32_t *OffsetPtr, + uint16_t Version, uint8_t AddrSize, + std::function<void(Error)> WarnCallback); + + uint32_t getHeaderOffset() const { return HeaderOffset; } + uint8_t getAddrSize() const { return HeaderData.AddrSize; } + void dump(raw_ostream &OS, DIDumpOptions DumpOpts = {}) const; + + /// Return the address based on a given index. + Expected<uint64_t> getAddrEntry(uint32_t Index) const; + + /// Return the size of the table header including the length + /// but not including the addresses. + uint8_t getHeaderSize() const { + switch (Format) { + case dwarf::DwarfFormat::DWARF32: + return 8; // 4 + 2 + 1 + 1 + case dwarf::DwarfFormat::DWARF64: + return 16; // 12 + 2 + 1 + 1 + } + llvm_unreachable("Invalid DWARF format (expected DWARF32 or DWARF64)"); + } + + /// Returns the length of this table, including the length field, or 0 if the + /// length has not been determined (e.g. because the table has not yet been + /// parsed, or there was a problem in parsing). + uint32_t getLength() const; + + /// Verify that the given length is valid for this table. + bool hasValidLength() const { return getLength() != 0; } + + /// Invalidate Length field to stop further processing. + void invalidateLength() { HeaderData.Length = 0; } + + /// Returns the length of the array of addresses. + uint32_t getDataSize() const; +}; + +} // end namespace llvm + +#endif // LLVM_DEBUGINFO_DWARFDEBUGADDR_H diff --git a/include/llvm/DebugInfo/DWARF/DWARFDie.h b/include/llvm/DebugInfo/DWARF/DWARFDie.h index 6e6b57cbcbd4..c77034f6348f 100644 --- a/include/llvm/DebugInfo/DWARF/DWARFDie.h +++ b/include/llvm/DebugInfo/DWARF/DWARFDie.h @@ -46,7 +46,7 @@ class DWARFDie { public: DWARFDie() = default; - DWARFDie(DWARFUnit *Unit, const DWARFDebugInfoEntry * D) : U(Unit), Die(D) {} + DWARFDie(DWARFUnit *Unit, const DWARFDebugInfoEntry *D) : U(Unit), Die(D) {} bool isValid() const { return U && Die; } explicit operator bool() const { return isValid(); } @@ -82,9 +82,7 @@ public: } /// Returns true for a valid DIE that terminates a sibling chain. - bool isNULL() const { - return getAbbreviationDeclarationPtr() == nullptr; - } + bool isNULL() const { return getAbbreviationDeclarationPtr() == nullptr; } /// Returns true if DIE represents a subprogram (not inlined). bool isSubprogramDIE() const; @@ -129,7 +127,6 @@ public: void dump(raw_ostream &OS, unsigned indent = 0, DIDumpOptions DumpOpts = DIDumpOptions()) const; - /// Convenience zero-argument overload for debugging. LLVM_DUMP_METHOD void dump() const; @@ -275,12 +272,16 @@ public: iterator begin() const; iterator end() const; + + std::reverse_iterator<iterator> rbegin() const; + std::reverse_iterator<iterator> rend() const; + iterator_range<iterator> children() const; }; -class DWARFDie::attribute_iterator : - public iterator_facade_base<attribute_iterator, std::forward_iterator_tag, - const DWARFAttribute> { +class DWARFDie::attribute_iterator + : public iterator_facade_base<attribute_iterator, std::forward_iterator_tag, + const DWARFAttribute> { /// The DWARF DIE we are extracting attributes from. DWARFDie Die; /// The value vended to clients via the operator*() or operator->(). @@ -288,6 +289,9 @@ class DWARFDie::attribute_iterator : /// The attribute index within the abbreviation declaration in Die. uint32_t Index; + friend bool operator==(const attribute_iterator &LHS, + const attribute_iterator &RHS); + /// Update the attribute index and attempt to read the attribute value. If the /// attribute is able to be read, update AttrValue and the Index member /// variable. If the attribute value is not able to be read, an appropriate @@ -303,12 +307,21 @@ public: attribute_iterator &operator--(); explicit operator bool() const { return AttrValue.isValid(); } const DWARFAttribute &operator*() const { return AttrValue; } - bool operator==(const attribute_iterator &X) const { return Index == X.Index; } }; +inline bool operator==(const DWARFDie::attribute_iterator &LHS, + const DWARFDie::attribute_iterator &RHS) { + return LHS.Index == RHS.Index; +} + +inline bool operator!=(const DWARFDie::attribute_iterator &LHS, + const DWARFDie::attribute_iterator &RHS) { + return !(LHS == RHS); +} + inline bool operator==(const DWARFDie &LHS, const DWARFDie &RHS) { return LHS.getDebugInfoEntry() == RHS.getDebugInfoEntry() && - LHS.getDwarfUnit() == RHS.getDwarfUnit(); + LHS.getDwarfUnit() == RHS.getDwarfUnit(); } inline bool operator!=(const DWARFDie &LHS, const DWARFDie &RHS) { @@ -323,11 +336,15 @@ class DWARFDie::iterator : public iterator_facade_base<iterator, std::bidirectional_iterator_tag, const DWARFDie> { DWARFDie Die; + + friend std::reverse_iterator<llvm::DWARFDie::iterator>; + friend bool operator==(const DWARFDie::iterator &LHS, + const DWARFDie::iterator &RHS); + public: iterator() = default; - explicit iterator(DWARFDie D) : Die(D) { - } + explicit iterator(DWARFDie D) : Die(D) {} iterator &operator++() { Die = Die.getSibling(); @@ -339,11 +356,19 @@ public: return *this; } - explicit operator bool() const { return Die.isValid(); } const DWARFDie &operator*() const { return Die; } - bool operator==(const iterator &X) const { return Die == X.Die; } }; +inline bool operator==(const DWARFDie::iterator &LHS, + const DWARFDie::iterator &RHS) { + return LHS.Die == RHS.Die; +} + +inline bool operator!=(const DWARFDie::iterator &LHS, + const DWARFDie::iterator &RHS) { + return !(LHS == RHS); +} + // These inline functions must follow the DWARFDie::iterator definition above // as they use functions from that class. inline DWARFDie::iterator DWARFDie::begin() const { @@ -360,4 +385,80 @@ inline iterator_range<DWARFDie::iterator> DWARFDie::children() const { } // end namespace llvm +namespace std { + +template <> +class reverse_iterator<llvm::DWARFDie::iterator> + : public llvm::iterator_facade_base< + reverse_iterator<llvm::DWARFDie::iterator>, + bidirectional_iterator_tag, const llvm::DWARFDie> { + +private: + llvm::DWARFDie Die; + bool AtEnd; + +public: + reverse_iterator(llvm::DWARFDie::iterator It) + : Die(It.Die), AtEnd(!It.Die.getPreviousSibling()) { + if (!AtEnd) + Die = Die.getPreviousSibling(); + } + + reverse_iterator<llvm::DWARFDie::iterator> &operator++() { + assert(!AtEnd && "Incrementing rend"); + llvm::DWARFDie D = Die.getPreviousSibling(); + if (D) + Die = D; + else + AtEnd = true; + return *this; + } + + reverse_iterator<llvm::DWARFDie::iterator> &operator--() { + if (AtEnd) { + AtEnd = false; + return *this; + } + Die = Die.getSibling(); + assert(!Die.isNULL() && "Decrementing rbegin"); + return *this; + } + + const llvm::DWARFDie &operator*() const { + assert(Die.isValid()); + return Die; + } + + // FIXME: We should be able to specify the equals operator as a friend, but + // that causes the compiler to think the operator overload is ambiguous + // with the friend declaration and the actual definition as candidates. + bool equals(const reverse_iterator<llvm::DWARFDie::iterator> &RHS) const { + return Die == RHS.Die && AtEnd == RHS.AtEnd; + } +}; + +} // namespace std + +namespace llvm { + +inline bool operator==(const std::reverse_iterator<DWARFDie::iterator> &LHS, + const std::reverse_iterator<DWARFDie::iterator> &RHS) { + return LHS.equals(RHS); +} + +inline bool operator!=(const std::reverse_iterator<DWARFDie::iterator> &LHS, + const std::reverse_iterator<DWARFDie::iterator> &RHS) { + return !(LHS == RHS); +} + +inline std::reverse_iterator<DWARFDie::iterator> DWARFDie::rbegin() const { + return llvm::make_reverse_iterator(end()); +} + +inline std::reverse_iterator<DWARFDie::iterator> DWARFDie::rend() const { + return llvm::make_reverse_iterator(begin()); +} + +} // end namespace llvm + #endif // LLVM_DEBUGINFO_DWARFDIE_H diff --git a/include/llvm/ExecutionEngine/Orc/RPCSerialization.h b/include/llvm/ExecutionEngine/Orc/RPCSerialization.h index 569c50602f3a..1e5f6ced597a 100644 --- a/include/llvm/ExecutionEngine/Orc/RPCSerialization.h +++ b/include/llvm/ExecutionEngine/Orc/RPCSerialization.h @@ -14,7 +14,10 @@ #include "llvm/Support/thread.h" #include <map> #include <mutex> +#include <set> #include <sstream> +#include <string> +#include <vector> namespace llvm { namespace orc { @@ -205,6 +208,42 @@ std::mutex RPCTypeName<std::vector<T>>::NameMutex; template <typename T> std::string RPCTypeName<std::vector<T>>::Name; +template <typename T> class RPCTypeName<std::set<T>> { +public: + static const char *getName() { + std::lock_guard<std::mutex> Lock(NameMutex); + if (Name.empty()) + raw_string_ostream(Name) + << "std::set<" << RPCTypeName<T>::getName() << ">"; + return Name.data(); + } + +private: + static std::mutex NameMutex; + static std::string Name; +}; + +template <typename T> std::mutex RPCTypeName<std::set<T>>::NameMutex; +template <typename T> std::string RPCTypeName<std::set<T>>::Name; + +template <typename K, typename V> class RPCTypeName<std::map<K, V>> { +public: + static const char *getName() { + std::lock_guard<std::mutex> Lock(NameMutex); + if (Name.empty()) + raw_string_ostream(Name) + << "std::map<" << RPCTypeNameSequence<K, V>() << ">"; + return Name.data(); + } + +private: + static std::mutex NameMutex; + static std::string Name; +}; + +template <typename K, typename V> +std::mutex RPCTypeName<std::map<K, V>>::NameMutex; +template <typename K, typename V> std::string RPCTypeName<std::map<K, V>>::Name; /// The SerializationTraits<ChannelT, T> class describes how to serialize and /// deserialize an instance of type T to/from an abstract channel of type @@ -527,15 +566,20 @@ public: }; /// SerializationTraits default specialization for std::pair. -template <typename ChannelT, typename T1, typename T2> -class SerializationTraits<ChannelT, std::pair<T1, T2>> { +template <typename ChannelT, typename T1, typename T2, typename T3, typename T4> +class SerializationTraits<ChannelT, std::pair<T1, T2>, std::pair<T3, T4>> { public: - static Error serialize(ChannelT &C, const std::pair<T1, T2> &V) { - return serializeSeq(C, V.first, V.second); + static Error serialize(ChannelT &C, const std::pair<T3, T4> &V) { + if (auto Err = SerializationTraits<ChannelT, T1, T3>::serialize(C, V.first)) + return Err; + return SerializationTraits<ChannelT, T2, T4>::serialize(C, V.second); } - static Error deserialize(ChannelT &C, std::pair<T1, T2> &V) { - return deserializeSeq(C, V.first, V.second); + static Error deserialize(ChannelT &C, std::pair<T3, T4> &V) { + if (auto Err = + SerializationTraits<ChannelT, T1, T3>::deserialize(C, V.first)) + return Err; + return SerializationTraits<ChannelT, T2, T4>::deserialize(C, V.second); } }; @@ -589,6 +633,9 @@ public: /// Deserialize a std::vector<T> to a std::vector<T>. static Error deserialize(ChannelT &C, std::vector<T> &V) { + assert(V.empty() && + "Expected default-constructed vector to deserialize into"); + uint64_t Count = 0; if (auto Err = deserializeSeq(C, Count)) return Err; @@ -602,6 +649,92 @@ public: } }; +template <typename ChannelT, typename T, typename T2> +class SerializationTraits<ChannelT, std::set<T>, std::set<T2>> { +public: + /// Serialize a std::set<T> from std::set<T2>. + static Error serialize(ChannelT &C, const std::set<T2> &S) { + if (auto Err = serializeSeq(C, static_cast<uint64_t>(S.size()))) + return Err; + + for (const auto &E : S) + if (auto Err = SerializationTraits<ChannelT, T, T2>::serialize(C, E)) + return Err; + + return Error::success(); + } + + /// Deserialize a std::set<T> to a std::set<T>. + static Error deserialize(ChannelT &C, std::set<T2> &S) { + assert(S.empty() && "Expected default-constructed set to deserialize into"); + + uint64_t Count = 0; + if (auto Err = deserializeSeq(C, Count)) + return Err; + + while (Count-- != 0) { + T2 Val; + if (auto Err = SerializationTraits<ChannelT, T, T2>::deserialize(C, Val)) + return Err; + + auto Added = S.insert(Val).second; + if (!Added) + return make_error<StringError>("Duplicate element in deserialized set", + orcError(OrcErrorCode::UnknownORCError)); + } + + return Error::success(); + } +}; + +template <typename ChannelT, typename K, typename V, typename K2, typename V2> +class SerializationTraits<ChannelT, std::map<K, V>, std::map<K2, V2>> { +public: + /// Serialize a std::map<K, V> from std::map<K2, V2>. + static Error serialize(ChannelT &C, const std::map<K2, V2> &M) { + if (auto Err = serializeSeq(C, static_cast<uint64_t>(M.size()))) + return Err; + + for (const auto &E : M) { + if (auto Err = + SerializationTraits<ChannelT, K, K2>::serialize(C, E.first)) + return Err; + if (auto Err = + SerializationTraits<ChannelT, V, V2>::serialize(C, E.second)) + return Err; + } + + return Error::success(); + } + + /// Deserialize a std::map<K, V> to a std::map<K, V>. + static Error deserialize(ChannelT &C, std::map<K2, V2> &M) { + assert(M.empty() && "Expected default-constructed map to deserialize into"); + + uint64_t Count = 0; + if (auto Err = deserializeSeq(C, Count)) + return Err; + + while (Count-- != 0) { + std::pair<K2, V2> Val; + if (auto Err = + SerializationTraits<ChannelT, K, K2>::deserialize(C, Val.first)) + return Err; + + if (auto Err = + SerializationTraits<ChannelT, V, V2>::deserialize(C, Val.second)) + return Err; + + auto Added = M.insert(Val).second; + if (!Added) + return make_error<StringError>("Duplicate element in deserialized map", + orcError(OrcErrorCode::UnknownORCError)); + } + + return Error::success(); + } +}; + } // end namespace rpc } // end namespace orc } // end namespace llvm diff --git a/include/llvm/IR/Attributes.td b/include/llvm/IR/Attributes.td index 1019f867aab0..39978c41ac72 100644 --- a/include/llvm/IR/Attributes.td +++ b/include/llvm/IR/Attributes.td @@ -236,3 +236,4 @@ def : MergeRule<"adjustCallerSSPLevel">; def : MergeRule<"adjustCallerStackProbes">; def : MergeRule<"adjustCallerStackProbeSize">; def : MergeRule<"adjustMinLegalVectorWidth">; +def : MergeRule<"adjustNullPointerValidAttr">; diff --git a/include/llvm/IR/Instruction.h b/include/llvm/IR/Instruction.h index a3bf25056ee5..643c2a0761d1 100644 --- a/include/llvm/IR/Instruction.h +++ b/include/llvm/IR/Instruction.h @@ -547,7 +547,7 @@ public: /// may have side effects cannot be removed without semantically changing the /// generated program. bool isSafeToRemove() const; - + /// Return true if the instruction is a variety of EH-block. bool isEHPad() const { switch (getOpcode()) { diff --git a/include/llvm/IR/Instructions.h b/include/llvm/IR/Instructions.h index a2cb84a071f2..9be8bd1a07bc 100644 --- a/include/llvm/IR/Instructions.h +++ b/include/llvm/IR/Instructions.h @@ -4016,7 +4016,7 @@ public: void setDoesNotThrow() { addAttribute(AttributeList::FunctionIndex, Attribute::NoUnwind); } - + /// Return the function called, or null if this is an /// indirect function invocation. /// diff --git a/include/llvm/IR/Intrinsics.td b/include/llvm/IR/Intrinsics.td index 64455573ff19..0cec754dd649 100644 --- a/include/llvm/IR/Intrinsics.td +++ b/include/llvm/IR/Intrinsics.td @@ -541,7 +541,7 @@ let IntrProperties = [IntrInaccessibleMemOnly] in { [ LLVMMatchType<0>, llvm_metadata_ty, llvm_metadata_ty ]>; - def int_experimental_constrained_exp : Intrinsic<[ llvm_anyfloat_ty ], + def int_experimental_constrained_exp : Intrinsic<[ llvm_anyfloat_ty ], [ LLVMMatchType<0>, llvm_metadata_ty, llvm_metadata_ty ]>; diff --git a/include/llvm/IR/IntrinsicsAMDGPU.td b/include/llvm/IR/IntrinsicsAMDGPU.td index 8555db01645f..9f361410b9b8 100644 --- a/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/include/llvm/IR/IntrinsicsAMDGPU.td @@ -1191,7 +1191,7 @@ def int_amdgcn_ds_bpermute : // Deep learning intrinsics. //===----------------------------------------------------------------------===// -// f32 %r = llvm.amdgcn.fdot2(v2f16 %a, v2f16 %b, f32 %c) +// f32 %r = llvm.amdgcn.fdot2(v2f16 %a, v2f16 %b, f32 %c, i1 %clamp) // %r = %a[0] * %b[0] + %a[1] * %b[1] + %c def int_amdgcn_fdot2 : GCCBuiltin<"__builtin_amdgcn_fdot2">, @@ -1200,12 +1200,13 @@ def int_amdgcn_fdot2 : [ llvm_v2f16_ty, // %a llvm_v2f16_ty, // %b - llvm_float_ty // %c + llvm_float_ty, // %c + llvm_i1_ty // %clamp ], [IntrNoMem, IntrSpeculatable] >; -// i32 %r = llvm.amdgcn.sdot2(v2i16 %a, v2i16 %b, i32 %c) +// i32 %r = llvm.amdgcn.sdot2(v2i16 %a, v2i16 %b, i32 %c, i1 %clamp) // %r = %a[0] * %b[0] + %a[1] * %b[1] + %c def int_amdgcn_sdot2 : GCCBuiltin<"__builtin_amdgcn_sdot2">, @@ -1214,12 +1215,13 @@ def int_amdgcn_sdot2 : [ llvm_v2i16_ty, // %a llvm_v2i16_ty, // %b - llvm_i32_ty // %c + llvm_i32_ty, // %c + llvm_i1_ty // %clamp ], [IntrNoMem, IntrSpeculatable] >; -// u32 %r = llvm.amdgcn.udot2(v2u16 %a, v2u16 %b, u32 %c) +// u32 %r = llvm.amdgcn.udot2(v2u16 %a, v2u16 %b, u32 %c, i1 %clamp) // %r = %a[0] * %b[0] + %a[1] * %b[1] + %c def int_amdgcn_udot2 : GCCBuiltin<"__builtin_amdgcn_udot2">, @@ -1228,12 +1230,13 @@ def int_amdgcn_udot2 : [ llvm_v2i16_ty, // %a llvm_v2i16_ty, // %b - llvm_i32_ty // %c + llvm_i32_ty, // %c + llvm_i1_ty // %clamp ], [IntrNoMem, IntrSpeculatable] >; -// i32 %r = llvm.amdgcn.sdot4(v4i8 (as i32) %a, v4i8 (as i32) %b, i32 %c) +// i32 %r = llvm.amdgcn.sdot4(v4i8 (as i32) %a, v4i8 (as i32) %b, i32 %c, i1 %clamp) // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c def int_amdgcn_sdot4 : GCCBuiltin<"__builtin_amdgcn_sdot4">, @@ -1242,12 +1245,13 @@ def int_amdgcn_sdot4 : [ llvm_i32_ty, // %a llvm_i32_ty, // %b - llvm_i32_ty // %c + llvm_i32_ty, // %c + llvm_i1_ty // %clamp ], [IntrNoMem, IntrSpeculatable] >; -// u32 %r = llvm.amdgcn.udot4(v4u8 (as u32) %a, v4u8 (as u32) %b, u32 %c) +// u32 %r = llvm.amdgcn.udot4(v4u8 (as u32) %a, v4u8 (as u32) %b, u32 %c, i1 %clamp) // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c def int_amdgcn_udot4 : GCCBuiltin<"__builtin_amdgcn_udot4">, @@ -1256,12 +1260,13 @@ def int_amdgcn_udot4 : [ llvm_i32_ty, // %a llvm_i32_ty, // %b - llvm_i32_ty // %c + llvm_i32_ty, // %c + llvm_i1_ty // %clamp ], [IntrNoMem, IntrSpeculatable] >; -// i32 %r = llvm.amdgcn.sdot8(v8i4 (as i32) %a, v8i4 (as i32) %b, i32 %c) +// i32 %r = llvm.amdgcn.sdot8(v8i4 (as i32) %a, v8i4 (as i32) %b, i32 %c, i1 %clamp) // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + // %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c def int_amdgcn_sdot8 : @@ -1271,12 +1276,13 @@ def int_amdgcn_sdot8 : [ llvm_i32_ty, // %a llvm_i32_ty, // %b - llvm_i32_ty // %c + llvm_i32_ty, // %c + llvm_i1_ty // %clamp ], [IntrNoMem, IntrSpeculatable] >; -// u32 %r = llvm.amdgcn.udot8(v8u4 (as u32) %a, v8u4 (as u32) %b, u32 %c) +// u32 %r = llvm.amdgcn.udot8(v8u4 (as u32) %a, v8u4 (as u32) %b, u32 %c, i1 %clamp) // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + // %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c def int_amdgcn_udot8 : @@ -1286,7 +1292,8 @@ def int_amdgcn_udot8 : [ llvm_i32_ty, // %a llvm_i32_ty, // %b - llvm_i32_ty // %c + llvm_i32_ty, // %c + llvm_i1_ty // %clamp ], [IntrNoMem, IntrSpeculatable] >; diff --git a/include/llvm/IR/IntrinsicsARM.td b/include/llvm/IR/IntrinsicsARM.td index f25d2f1dbb5d..4e11f9c29dd0 100644 --- a/include/llvm/IR/IntrinsicsARM.td +++ b/include/llvm/IR/IntrinsicsARM.td @@ -275,7 +275,7 @@ def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>; def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>; -def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">, +def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>; def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>; diff --git a/include/llvm/IR/IntrinsicsPowerPC.td b/include/llvm/IR/IntrinsicsPowerPC.td index c4e753af25ca..3433aaa402eb 100644 --- a/include/llvm/IR/IntrinsicsPowerPC.td +++ b/include/llvm/IR/IntrinsicsPowerPC.td @@ -1,10 +1,10 @@ //===- IntrinsicsPowerPC.td - Defines PowerPC intrinsics ---*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines all of the PowerPC-specific intrinsics. @@ -122,21 +122,21 @@ class PowerPC_Vec_FFF_Intrinsic<string GCCIntSuffix> /// PowerPC_Vec_BBB_Intrinsic - A PowerPC intrinsic that takes two v16i8 /// vectors and returns one. These intrinsics have no side effects. -class PowerPC_Vec_BBB_Intrinsic<string GCCIntSuffix> +class PowerPC_Vec_BBB_Intrinsic<string GCCIntSuffix> : PowerPC_Vec_Intrinsic<GCCIntSuffix, [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; /// PowerPC_Vec_HHH_Intrinsic - A PowerPC intrinsic that takes two v8i16 /// vectors and returns one. These intrinsics have no side effects. -class PowerPC_Vec_HHH_Intrinsic<string GCCIntSuffix> +class PowerPC_Vec_HHH_Intrinsic<string GCCIntSuffix> : PowerPC_Vec_Intrinsic<GCCIntSuffix, [llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; /// PowerPC_Vec_WWW_Intrinsic - A PowerPC intrinsic that takes two v4i32 /// vectors and returns one. These intrinsics have no side effects. -class PowerPC_Vec_WWW_Intrinsic<string GCCIntSuffix> +class PowerPC_Vec_WWW_Intrinsic<string GCCIntSuffix> : PowerPC_Vec_Intrinsic<GCCIntSuffix, [llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; @@ -267,7 +267,7 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_altivec_vcmpgtud : GCCBuiltin<"__builtin_altivec_vcmpgtud">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; - + def int_ppc_altivec_vcmpequw : GCCBuiltin<"__builtin_altivec_vcmpequw">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; @@ -283,7 +283,7 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_altivec_vcmpnezw : GCCBuiltin<"__builtin_altivec_vcmpnezw">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; - + def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">, Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; @@ -355,7 +355,7 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_altivec_vcmpnezw_p : GCCBuiltin<"__builtin_altivec_vcmpnezw_p">, Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4i32_ty,llvm_v4i32_ty], [IntrNoMem]>; - + def int_ppc_altivec_vcmpequh_p : GCCBuiltin<"__builtin_altivec_vcmpequh_p">, Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty], [IntrNoMem]>; @@ -474,10 +474,10 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumshs : GCCBuiltin<"__builtin_altivec_vmsumshs">, - Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumubm : GCCBuiltin<"__builtin_altivec_vmsumubm">, - Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v16i8_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">, Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, @@ -544,7 +544,7 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". // Other multiplies. def int_ppc_altivec_vmladduhm : GCCBuiltin<"__builtin_altivec_vmladduhm">, - Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; // Packs. @@ -626,21 +626,21 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". // Add Extended Quadword def int_ppc_altivec_vaddeuqm : GCCBuiltin<"__builtin_altivec_vaddeuqm">, - Intrinsic<[llvm_v1i128_ty], + Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty], [IntrNoMem]>; def int_ppc_altivec_vaddecuq : GCCBuiltin<"__builtin_altivec_vaddecuq">, - Intrinsic<[llvm_v1i128_ty], + Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty], [IntrNoMem]>; // Sub Extended Quadword def int_ppc_altivec_vsubeuqm : GCCBuiltin<"__builtin_altivec_vsubeuqm">, - Intrinsic<[llvm_v1i128_ty], + Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty], [IntrNoMem]>; def int_ppc_altivec_vsubecuq : GCCBuiltin<"__builtin_altivec_vsubecuq">, - Intrinsic<[llvm_v1i128_ty], + Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty], [IntrNoMem]>; } @@ -657,7 +657,7 @@ def int_ppc_altivec_vslw : PowerPC_Vec_WWW_Intrinsic<"vslw">; // Right Shifts. def int_ppc_altivec_vsr : PowerPC_Vec_WWW_Intrinsic<"vsr">; def int_ppc_altivec_vsro : PowerPC_Vec_WWW_Intrinsic<"vsro">; - + def int_ppc_altivec_vsrb : PowerPC_Vec_BBB_Intrinsic<"vsrb">; def int_ppc_altivec_vsrh : PowerPC_Vec_HHH_Intrinsic<"vsrh">; def int_ppc_altivec_vsrw : PowerPC_Vec_WWW_Intrinsic<"vsrw">; @@ -679,10 +679,10 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty], [IntrNoMem]>; def int_ppc_altivec_vperm : GCCBuiltin<"__builtin_altivec_vperm_4si">, - Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">, - Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vgbbd : GCCBuiltin<"__builtin_altivec_vgbbd">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; diff --git a/include/llvm/IR/LegacyPassManagers.h b/include/llvm/IR/LegacyPassManagers.h index 90036c6ce248..f6752f2817ba 100644 --- a/include/llvm/IR/LegacyPassManagers.h +++ b/include/llvm/IR/LegacyPassManagers.h @@ -285,7 +285,7 @@ private: SpecificBumpPtrAllocator<AUFoldingSetNode> AUFoldingSetNodeAllocator; // Maps from a pass to it's associated entry in UniqueAnalysisUsages. Does - // not own the storage associated with either key or value.. + // not own the storage associated with either key or value.. DenseMap<Pass *, AnalysisUsage*> AnUsageMap; /// Collection of PassInfo objects found via analysis IDs and in this top diff --git a/include/llvm/IR/Statepoint.h b/include/llvm/IR/Statepoint.h index c8e905b21a30..8908e1b0d090 100644 --- a/include/llvm/IR/Statepoint.h +++ b/include/llvm/IR/Statepoint.h @@ -325,7 +325,7 @@ public: explicit Statepoint(CallSite CS) : Base(CS) {} }; -/// Common base class for representing values projected from a statepoint. +/// Common base class for representing values projected from a statepoint. /// Currently, the only projections available are gc.result and gc.relocate. class GCProjectionInst : public IntrinsicInst { public: diff --git a/include/llvm/IR/User.h b/include/llvm/IR/User.h index d6a603ce845d..aea31467f2fa 100644 --- a/include/llvm/IR/User.h +++ b/include/llvm/IR/User.h @@ -101,10 +101,10 @@ public: void operator delete(void *Usr); /// Placement delete - required by std, called if the ctor throws. void operator delete(void *Usr, unsigned) { - // Note: If a subclass manipulates the information which is required to calculate the - // Usr memory pointer, e.g. NumUserOperands, the operator delete of that subclass has + // Note: If a subclass manipulates the information which is required to calculate the + // Usr memory pointer, e.g. NumUserOperands, the operator delete of that subclass has // to restore the changed information to the original value, since the dtor of that class - // is not called if the ctor fails. + // is not called if the ctor fails. User::operator delete(Usr); #ifndef LLVM_ENABLE_EXCEPTIONS @@ -113,10 +113,10 @@ public: } /// Placement delete - required by std, called if the ctor throws. void operator delete(void *Usr, unsigned, bool) { - // Note: If a subclass manipulates the information which is required to calculate the - // Usr memory pointer, e.g. NumUserOperands, the operator delete of that subclass has + // Note: If a subclass manipulates the information which is required to calculate the + // Usr memory pointer, e.g. NumUserOperands, the operator delete of that subclass has // to restore the changed information to the original value, since the dtor of that class - // is not called if the ctor fails. + // is not called if the ctor fails. User::operator delete(Usr); #ifndef LLVM_ENABLE_EXCEPTIONS diff --git a/include/llvm/LinkAllIR.h b/include/llvm/LinkAllIR.h index 9a9f3d3a677f..4f4af7187be4 100644 --- a/include/llvm/LinkAllIR.h +++ b/include/llvm/LinkAllIR.h @@ -44,7 +44,7 @@ namespace { llvm::LLVMContext Context; (void)new llvm::Module("", Context); (void)new llvm::UnreachableInst(Context); - (void) llvm::createVerifierPass(); + (void) llvm::createVerifierPass(); } } ForceVMCoreLinking; } diff --git a/include/llvm/MC/MCDwarf.h b/include/llvm/MC/MCDwarf.h index 785f42d2f9d7..2bfaf19cf2c6 100644 --- a/include/llvm/MC/MCDwarf.h +++ b/include/llvm/MC/MCDwarf.h @@ -362,6 +362,13 @@ public: static void Encode(MCContext &Context, MCDwarfLineTableParams Params, int64_t LineDelta, uint64_t AddrDelta, raw_ostream &OS); + /// Utility function to encode a Dwarf pair of LineDelta and AddrDeltas using + /// fixed length operands. + static bool FixedEncode(MCContext &Context, + MCDwarfLineTableParams Params, + int64_t LineDelta, uint64_t AddrDelta, + raw_ostream &OS, uint32_t *Offset, uint32_t *Size); + /// Utility function to emit the encoding to a streamer. static void Emit(MCStreamer *MCOS, MCDwarfLineTableParams Params, int64_t LineDelta, uint64_t AddrDelta); diff --git a/include/llvm/MC/MCFragment.h b/include/llvm/MC/MCFragment.h index 47b35175fec8..c999c9fc4f17 100644 --- a/include/llvm/MC/MCFragment.h +++ b/include/llvm/MC/MCFragment.h @@ -149,6 +149,7 @@ public: case MCFragment::FT_Relaxable: case MCFragment::FT_CompactEncodedInst: case MCFragment::FT_Data: + case MCFragment::FT_Dwarf: return true; } } @@ -232,7 +233,7 @@ public: static bool classof(const MCFragment *F) { MCFragment::FragmentType Kind = F->getKind(); return Kind == MCFragment::FT_Relaxable || Kind == MCFragment::FT_Data || - Kind == MCFragment::FT_CVDefRange; + Kind == MCFragment::FT_CVDefRange || Kind == MCFragment::FT_Dwarf;; } }; @@ -514,7 +515,7 @@ public: } }; -class MCDwarfLineAddrFragment : public MCFragment { +class MCDwarfLineAddrFragment : public MCEncodedFragmentWithFixups<8, 1> { /// LineDelta - the value of the difference between the two line numbers /// between two .loc dwarf directives. int64_t LineDelta; @@ -523,15 +524,11 @@ class MCDwarfLineAddrFragment : public MCFragment { /// make up the address delta between two .loc dwarf directives. const MCExpr *AddrDelta; - SmallString<8> Contents; - public: MCDwarfLineAddrFragment(int64_t LineDelta, const MCExpr &AddrDelta, MCSection *Sec = nullptr) - : MCFragment(FT_Dwarf, false, Sec), LineDelta(LineDelta), - AddrDelta(&AddrDelta) { - Contents.push_back(0); - } + : MCEncodedFragmentWithFixups<8, 1>(FT_Dwarf, false, Sec), + LineDelta(LineDelta), AddrDelta(&AddrDelta) {} /// \name Accessors /// @{ @@ -540,9 +537,6 @@ public: const MCExpr &getAddrDelta() const { return *AddrDelta; } - SmallString<8> &getContents() { return Contents; } - const SmallString<8> &getContents() const { return Contents; } - /// @} static bool classof(const MCFragment *F) { diff --git a/include/llvm/MC/MCInstrAnalysis.h b/include/llvm/MC/MCInstrAnalysis.h index 484f03b4d854..e1673208d875 100644 --- a/include/llvm/MC/MCInstrAnalysis.h +++ b/include/llvm/MC/MCInstrAnalysis.h @@ -64,7 +64,7 @@ public: /// Returns true if at least one of the register writes performed by /// \param Inst implicitly clears the upper portion of all super-registers. - /// + /// /// Example: on X86-64, a write to EAX implicitly clears the upper half of /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit /// instruction implicitly clears the upper portion of the correspondent @@ -87,6 +87,19 @@ public: const MCInst &Inst, APInt &Writes) const; + /// Returns true if \param Inst is a dependency breaking instruction for the + /// given subtarget. + /// + /// The value computed by a dependency breaking instruction is not dependent + /// on the inputs. An example of dependency breaking instruction on X86 is + /// `XOR %eax, %eax`. + /// TODO: In future, we could implement an alternative approach where this + /// method returns `true` if the input instruction is not dependent on + /// some/all of its input operands. An APInt mask could then be used to + /// identify independent operands. + virtual bool isDependencyBreaking(const MCSubtargetInfo &STI, + const MCInst &Inst) const; + /// Given a branch instruction try to get the address the branch /// targets. Return true on success, and the address in Target. virtual bool diff --git a/include/llvm/MC/MCParser/AsmCond.h b/include/llvm/MC/MCParser/AsmCond.h index 8e7bfc521556..a6e0fbd7f337 100644 --- a/include/llvm/MC/MCParser/AsmCond.h +++ b/include/llvm/MC/MCParser/AsmCond.h @@ -15,7 +15,7 @@ namespace llvm { /// AsmCond - Class to support conditional assembly /// /// The conditional assembly feature (.if, .else, .elseif and .endif) is -/// implemented with AsmCond that tells us what we are in the middle of +/// implemented with AsmCond that tells us what we are in the middle of /// processing. Ignore can be either true or false. When true we are ignoring /// the block of code in the middle of a conditional. diff --git a/include/llvm/MC/MCStreamer.h b/include/llvm/MC/MCStreamer.h index 0a5d80c6d778..e4d0dc03b87c 100644 --- a/include/llvm/MC/MCStreamer.h +++ b/include/llvm/MC/MCStreamer.h @@ -297,8 +297,8 @@ public: /// If the comment includes embedded \n's, they will each get the comment /// prefix as appropriate. The added comment should not end with a \n. /// By default, each comment is terminated with an end of line, i.e. the - /// EOL param is set to true by default. If one prefers not to end the - /// comment with a new line then the EOL param should be passed + /// EOL param is set to true by default. If one prefers not to end the + /// comment with a new line then the EOL param should be passed /// with a false value. virtual void AddComment(const Twine &T, bool EOL = true) {} diff --git a/include/llvm/Object/MachO.h b/include/llvm/Object/MachO.h index 531b3d249035..159c1765ab86 100644 --- a/include/llvm/Object/MachO.h +++ b/include/llvm/Object/MachO.h @@ -333,7 +333,7 @@ public: relocation_iterator locrel_begin() const; relocation_iterator locrel_end() const; - + void moveRelocationNext(DataRefImpl &Rel) const override; uint64_t getRelocationOffset(DataRefImpl Rel) const override; symbol_iterator getRelocationSymbol(DataRefImpl Rel) const override; diff --git a/include/llvm/PassAnalysisSupport.h b/include/llvm/PassAnalysisSupport.h index 118718747659..a075eb557472 100644 --- a/include/llvm/PassAnalysisSupport.h +++ b/include/llvm/PassAnalysisSupport.h @@ -231,7 +231,7 @@ AnalysisType &Pass::getAnalysisID(AnalysisID PI) const { // should be a small number, we just do a linear search over a (dense) // vector. Pass *ResultPass = Resolver->findImplPass(PI); - assert(ResultPass && + assert(ResultPass && "getAnalysis*() called on an analysis that was not " "'required' by pass!"); diff --git a/include/llvm/PassRegistry.h b/include/llvm/PassRegistry.h index 93edc12bdc7b..57462138c5ae 100644 --- a/include/llvm/PassRegistry.h +++ b/include/llvm/PassRegistry.h @@ -9,7 +9,7 @@ // // This file defines PassRegistry, a class that is used in the initialization // and registration of passes. At application startup, passes are registered -// with the PassRegistry, which is later provided to the PassManager for +// with the PassRegistry, which is later provided to the PassManager for // dependency resolution and similar tasks. // //===----------------------------------------------------------------------===// diff --git a/include/llvm/ProfileData/Coverage/CoverageMapping.h b/include/llvm/ProfileData/Coverage/CoverageMapping.h index 1ca56dcaf9c5..ecb284d30de0 100644 --- a/include/llvm/ProfileData/Coverage/CoverageMapping.h +++ b/include/llvm/ProfileData/Coverage/CoverageMapping.h @@ -207,7 +207,7 @@ struct CounterMappingRegion { /// A CodeRegion associates some code with a counter CodeRegion, - /// An ExpansionRegion represents a file expansion region that associates + /// An ExpansionRegion represents a file expansion region that associates /// a source range with the expansion of a virtual source file, such as /// for a macro instantiation or #include file. ExpansionRegion, diff --git a/include/llvm/Support/ARMBuildAttributes.h b/include/llvm/Support/ARMBuildAttributes.h index 6c83e447cb24..b8a03765a7c0 100644 --- a/include/llvm/Support/ARMBuildAttributes.h +++ b/include/llvm/Support/ARMBuildAttributes.h @@ -213,6 +213,8 @@ enum { // Tag_ABI_VFP_args, (=28), uleb128 BaseAAPCS = 0, HardFPAAPCS = 1, + ToolChainFPPCS = 2, + CompatibleFPAAPCS = 3, // Tag_FP_HP_extension, (=36), uleb128 AllowHPFP = 1, // Allow use of Half Precision FP diff --git a/include/llvm/Support/DataExtractor.h b/include/llvm/Support/DataExtractor.h index 3a6ada6c77df..2b1639856e79 100644 --- a/include/llvm/Support/DataExtractor.h +++ b/include/llvm/Support/DataExtractor.h @@ -15,7 +15,7 @@ namespace llvm { -/// An auxiliary type to facilitate extraction of 3-byte entities. +/// An auxiliary type to facilitate extraction of 3-byte entities. struct Uint24 { uint8_t Bytes[3]; Uint24(uint8_t U) { diff --git a/include/llvm/Support/GenericDomTree.h b/include/llvm/Support/GenericDomTree.h index 115abc23e2c6..c716e4a4d300 100644 --- a/include/llvm/Support/GenericDomTree.h +++ b/include/llvm/Support/GenericDomTree.h @@ -530,11 +530,10 @@ protected: /// CFG about its children and inverse children. This implies that deletions /// of CFG edges must not delete the CFG nodes before calling this function. /// - /// Batch updates should be generally faster when performing longer sequences - /// of updates than calling insertEdge/deleteEdge manually multiple times, as - /// it can reorder the updates and remove redundant ones internally. - /// The batch updater is also able to detect sequences of zero and exactly one - /// update -- it's optimized to do less work in these cases. + /// The applyUpdates function can reorder the updates and remove redundant + /// ones internally. The batch updater is also able to detect sequences of + /// zero and exactly one update -- it's optimized to do less work in these + /// cases. /// /// Note that for postdominators it automatically takes care of applying /// updates on reverse edges internally (so there's no need to swap the @@ -854,10 +853,15 @@ protected: assert(isReachableFromEntry(B)); assert(isReachableFromEntry(A)); + const unsigned ALevel = A->getLevel(); const DomTreeNodeBase<NodeT> *IDom; - while ((IDom = B->getIDom()) != nullptr && IDom != A && IDom != B) + + // Don't walk nodes above A's subtree. When we reach A's level, we must + // either find A or be in some other subtree not dominated by A. + while ((IDom = B->getIDom()) != nullptr && IDom->getLevel() >= ALevel) B = IDom; // Walk up the tree - return IDom != nullptr; + + return B == A; } /// Wipe this tree's state without releasing any resources. diff --git a/include/llvm/Support/MemoryBuffer.h b/include/llvm/Support/MemoryBuffer.h index 535579ecff53..8933295d4ea4 100644 --- a/include/llvm/Support/MemoryBuffer.h +++ b/include/llvm/Support/MemoryBuffer.h @@ -43,7 +43,6 @@ class MemoryBuffer { const char *BufferStart; // Start of the buffer. const char *BufferEnd; // End of the buffer. - protected: MemoryBuffer() = default; @@ -148,9 +147,6 @@ public: virtual BufferKind getBufferKind() const = 0; MemoryBufferRef getMemBufferRef() const; - -private: - virtual void anchor(); }; /// This class is an extension of MemoryBuffer, which allows copy-on-write diff --git a/include/llvm/Support/SmallVectorMemoryBuffer.h b/include/llvm/Support/SmallVectorMemoryBuffer.h index f43c2fb8f826..c4a600e7f37d 100644 --- a/include/llvm/Support/SmallVectorMemoryBuffer.h +++ b/include/llvm/Support/SmallVectorMemoryBuffer.h @@ -49,6 +49,9 @@ public: init(this->SV.begin(), this->SV.end(), false); } + // Key function. + ~SmallVectorMemoryBuffer() override; + StringRef getBufferIdentifier() const override { return BufferName; } BufferKind getBufferKind() const override { return MemoryBuffer_Malloc; } @@ -56,7 +59,6 @@ public: private: SmallVector<char, 0> SV; std::string BufferName; - void anchor() override; }; } // namespace llvm diff --git a/include/llvm/Support/TargetOpcodes.def b/include/llvm/Support/TargetOpcodes.def index 21f5c7e709b8..63491a5f01d2 100644 --- a/include/llvm/Support/TargetOpcodes.def +++ b/include/llvm/Support/TargetOpcodes.def @@ -470,12 +470,15 @@ HANDLE_TARGET_OPCODE(G_BSWAP) /// Generic AddressSpaceCast. HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) +/// Generic block address +HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) + // TODO: Add more generic opcodes as we move along. /// Marker for the end of the generic opcode. /// This is used to check if an opcode is in the range of the /// generic opcodes. -HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_ADDRSPACE_CAST) +HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BLOCK_ADDR) /// BUILTIN_OP_END - This must be the last enum value in this list. /// The target-specific post-isel opcode values start here. diff --git a/include/llvm/Support/xxhash.h b/include/llvm/Support/xxhash.h index f7ca460188a2..6fd67ff9ce1c 100644 --- a/include/llvm/Support/xxhash.h +++ b/include/llvm/Support/xxhash.h @@ -38,10 +38,12 @@ #ifndef LLVM_SUPPORT_XXHASH_H #define LLVM_SUPPORT_XXHASH_H +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringRef.h" namespace llvm { uint64_t xxHash64(llvm::StringRef Data); +uint64_t xxHash64(llvm::ArrayRef<uint8_t> Data); } #endif diff --git a/include/llvm/Target/GenericOpcodes.td b/include/llvm/Target/GenericOpcodes.td index d72746a0838a..79cc1e4d9eee 100644 --- a/include/llvm/Target/GenericOpcodes.td +++ b/include/llvm/Target/GenericOpcodes.td @@ -131,6 +131,13 @@ def G_ADDRSPACE_CAST : GenericInstruction { let InOperandList = (ins type1:$src); let hasSideEffects = 0; } + +def G_BLOCK_ADDR : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins unknown:$ba); + let hasSideEffects = 0; +} + //------------------------------------------------------------------------------ // Binary ops. //------------------------------------------------------------------------------ diff --git a/include/llvm/Target/TargetCallingConv.td b/include/llvm/Target/TargetCallingConv.td index 3d8639dfe1da..95d2b4226294 100644 --- a/include/llvm/Target/TargetCallingConv.td +++ b/include/llvm/Target/TargetCallingConv.td @@ -1,10 +1,10 @@ //===- TargetCallingConv.td - Target Calling Conventions ---*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the target-independent interfaces with which targets diff --git a/include/llvm/Target/TargetInstrPredicate.td b/include/llvm/Target/TargetInstrPredicate.td index d38279b0d65e..8d57cae02d22 100644 --- a/include/llvm/Target/TargetInstrPredicate.td +++ b/include/llvm/Target/TargetInstrPredicate.td @@ -13,7 +13,7 @@ // an instruction. Each MCInstPredicate class has a well-known semantic, and it // is used by a PredicateExpander to generate code for MachineInstr and/or // MCInst. -// +// // MCInstPredicate definitions can be used to construct MCSchedPredicate // definitions. An MCSchedPredicate can be used in place of a SchedPredicate // when defining SchedReadVariant and SchedWriteVariant used by a processor @@ -63,7 +63,7 @@ // // New MCInstPredicate classes must be added to this file. For each new class // XYZ, an "expandXYZ" method must be added to the PredicateExpander. -// +// //===----------------------------------------------------------------------===// // Forward declarations. diff --git a/include/llvm/Transforms/Scalar/SpeculativeExecution.h b/include/llvm/Transforms/Scalar/SpeculativeExecution.h index 068f81776a03..d00e950222a0 100644 --- a/include/llvm/Transforms/Scalar/SpeculativeExecution.h +++ b/include/llvm/Transforms/Scalar/SpeculativeExecution.h @@ -82,7 +82,7 @@ private: bool considerHoistingFromTo(BasicBlock &FromBlock, BasicBlock &ToBlock); // If true, this pass is a nop unless the target architecture has branch - // divergence. + // divergence. const bool OnlyIfDivergentTarget = false; TargetTransformInfo *TTI = nullptr; diff --git a/include/llvm/Transforms/Utils/CodeExtractor.h b/include/llvm/Transforms/Utils/CodeExtractor.h index fab8334d4c66..0e5254acb0d3 100644 --- a/include/llvm/Transforms/Utils/CodeExtractor.h +++ b/include/llvm/Transforms/Utils/CodeExtractor.h @@ -74,7 +74,7 @@ class Value; /// vararg functions can be extracted. This is safe, if all vararg handling /// code is extracted, including vastart. If AllowAlloca is true, then /// extraction of blocks containing alloca instructions would be possible, - /// however code extractor won't validate whether extraction is legal. + /// however code extractor won't validate whether extraction is legal. CodeExtractor(ArrayRef<BasicBlock *> BBs, DominatorTree *DT = nullptr, bool AggregateArgs = false, BlockFrequencyInfo *BFI = nullptr, BranchProbabilityInfo *BPI = nullptr, diff --git a/include/llvm/Transforms/Utils/FunctionComparator.h b/include/llvm/Transforms/Utils/FunctionComparator.h index 7698a068717a..35ba0950343c 100644 --- a/include/llvm/Transforms/Utils/FunctionComparator.h +++ b/include/llvm/Transforms/Utils/FunctionComparator.h @@ -18,7 +18,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/StringRef.h" #include "llvm/IR/Attributes.h" -#include "llvm/IR/Instructions.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/Operator.h" #include "llvm/IR/ValueMap.h" #include "llvm/Support/AtomicOrdering.h" diff --git a/include/llvm/Transforms/Utils/SymbolRewriter.h b/include/llvm/Transforms/Utils/SymbolRewriter.h index e0caf7741ff3..5f6488e08b5a 100644 --- a/include/llvm/Transforms/Utils/SymbolRewriter.h +++ b/include/llvm/Transforms/Utils/SymbolRewriter.h @@ -134,7 +134,7 @@ public: private: void loadAndParseMapFiles(); - SymbolRewriter::RewriteDescriptorList Descriptors; + SymbolRewriter::RewriteDescriptorList Descriptors; }; } // end namespace llvm |