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-rw-r--r--lib/Basic/Targets/AArch64.cpp2
-rw-r--r--lib/Basic/Targets/ARM.cpp8
-rw-r--r--lib/Basic/Targets/X86.cpp91
-rw-r--r--lib/Basic/Targets/X86.h6
4 files changed, 91 insertions, 16 deletions
diff --git a/lib/Basic/Targets/AArch64.cpp b/lib/Basic/Targets/AArch64.cpp
index 6080cefac744..4d3cd121f705 100644
--- a/lib/Basic/Targets/AArch64.cpp
+++ b/lib/Basic/Targets/AArch64.cpp
@@ -159,7 +159,7 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__ARM_FP_FAST", "1");
Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
- llvm::utostr(Opts.WCharSize ? Opts.WCharSize : 4));
+ Twine(Opts.WCharSize ? Opts.WCharSize : 4));
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
diff --git a/lib/Basic/Targets/ARM.cpp b/lib/Basic/Targets/ARM.cpp
index fe261b774855..6fb0ab41ff5b 100644
--- a/lib/Basic/Targets/ARM.cpp
+++ b/lib/Basic/Targets/ARM.cpp
@@ -582,7 +582,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
// ACLE 6.4.4 LDREX/STREX
if (LDREX)
- Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
+ Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + Twine::utohexstr(LDREX));
// ACLE 6.4.5 CLZ
if (ArchVersion == 5 || (ArchVersion == 6 && CPUProfile != "M") ||
@@ -591,7 +591,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
// ACLE 6.5.1 Hardware Floating Point
if (HW_FP)
- Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
+ Builder.defineMacro("__ARM_FP", "0x" + Twine::utohexstr(HW_FP));
// ACLE predefines.
Builder.defineMacro("__ARM_ACLE", "200");
@@ -672,11 +672,11 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
// current AArch32 NEON implementations do not support double-precision
// floating-point even when it is present in VFP.
Builder.defineMacro("__ARM_NEON_FP",
- "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
+ "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
}
Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
- llvm::utostr(Opts.WCharSize ? Opts.WCharSize : 4));
+ Twine(Opts.WCharSize ? Opts.WCharSize : 4));
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
diff --git a/lib/Basic/Targets/X86.cpp b/lib/Basic/Targets/X86.cpp
index bdf5cdb9407b..3efba26a8373 100644
--- a/lib/Basic/Targets/X86.cpp
+++ b/lib/Basic/Targets/X86.cpp
@@ -132,7 +132,14 @@ bool X86TargetInfo::initFeatureMap(
break;
case CK_Icelake:
- // TODO: Add icelake features here.
+ setFeatureEnabledImpl(Features, "vaes", true);
+ setFeatureEnabledImpl(Features, "gfni", true);
+ setFeatureEnabledImpl(Features, "vpclmulqdq", true);
+ setFeatureEnabledImpl(Features, "avx512bitalg", true);
+ setFeatureEnabledImpl(Features, "avx512vnni", true);
+ setFeatureEnabledImpl(Features, "avx512vbmi2", true);
+ setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
+ setFeatureEnabledImpl(Features, "clwb", true);
LLVM_FALLTHROUGH;
case CK_Cannonlake:
setFeatureEnabledImpl(Features, "avx512ifma", true);
@@ -145,8 +152,10 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "avx512dq", true);
setFeatureEnabledImpl(Features, "avx512bw", true);
setFeatureEnabledImpl(Features, "avx512vl", true);
- setFeatureEnabledImpl(Features, "pku", true);
- setFeatureEnabledImpl(Features, "clwb", true);
+ if (Kind == CK_SkylakeServer) {
+ setFeatureEnabledImpl(Features, "pku", true);
+ setFeatureEnabledImpl(Features, "clwb", true);
+ }
LLVM_FALLTHROUGH;
case CK_SkylakeClient:
setFeatureEnabledImpl(Features, "xsavec", true);
@@ -443,7 +452,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
LLVM_FALLTHROUGH;
case SSE2:
Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
- false;
+ Features["gfni"] = false;
LLVM_FALLTHROUGH;
case SSE3:
Features["sse3"] = false;
@@ -460,7 +469,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
LLVM_FALLTHROUGH;
case AVX:
Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
- Features["xsaveopt"] = false;
+ Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
setXOPLevel(Features, FMA4, false);
LLVM_FALLTHROUGH;
case AVX2:
@@ -470,7 +479,9 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
Features["avx512vl"] = Features["avx512vbmi"] =
- Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
+ Features["avx512ifma"] = Features["avx512vpopcntdq"] =
+ Features["avx512bitalg"] = Features["avx512vnni"] =
+ Features["avx512vbmi2"] = false;
break;
}
}
@@ -572,9 +583,26 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
} else if (Name == "aes") {
if (Enabled)
setSSELevel(Features, SSE2, Enabled);
+ else
+ Features["vaes"] = false;
+ } else if (Name == "vaes") {
+ if (Enabled) {
+ setSSELevel(Features, AVX, Enabled);
+ Features["aes"] = true;
+ }
} else if (Name == "pclmul") {
if (Enabled)
setSSELevel(Features, SSE2, Enabled);
+ else
+ Features["vpclmulqdq"] = false;
+ } else if (Name == "vpclmulqdq") {
+ if (Enabled) {
+ setSSELevel(Features, AVX, Enabled);
+ Features["pclmul"] = true;
+ }
+ } else if (Name == "gfni") {
+ if (Enabled)
+ setSSELevel(Features, SSE2, Enabled);
} else if (Name == "avx") {
setSSELevel(Features, AVX, Enabled);
} else if (Name == "avx2") {
@@ -584,15 +612,17 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
} else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
Name == "avx512vbmi" || Name == "avx512ifma" ||
- Name == "avx512vpopcntdq") {
+ Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
+ Name == "avx512vnni" || Name == "avx512vbmi2") {
if (Enabled)
setSSELevel(Features, AVX512F, Enabled);
- // Enable BWI instruction if VBMI is being enabled.
- if (Name == "avx512vbmi" && Enabled)
+ // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
+ if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
Features["avx512bw"] = true;
- // Also disable VBMI if BWI is being disabled.
+ // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
if (Name == "avx512bw" && !Enabled)
- Features["avx512vbmi"] = false;
+ Features["avx512vbmi"] = Features["avx512vbmi2"] =
+ Features["avx512bitalg"] = false;
} else if (Name == "fma") {
if (Enabled)
setSSELevel(Features, AVX, Enabled);
@@ -636,8 +666,12 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
if (Feature == "+aes") {
HasAES = true;
+ } else if (Feature == "+vaes") {
+ HasVAES = true;
} else if (Feature == "+pclmul") {
HasPCLMUL = true;
+ } else if (Feature == "+vpclmulqdq") {
+ HasVPCLMULQDQ = true;
} else if (Feature == "+lzcnt") {
HasLZCNT = true;
} else if (Feature == "+rdrnd") {
@@ -666,22 +700,30 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasFMA = true;
} else if (Feature == "+f16c") {
HasF16C = true;
+ } else if (Feature == "+gfni") {
+ HasGFNI = true;
} else if (Feature == "+avx512cd") {
HasAVX512CD = true;
} else if (Feature == "+avx512vpopcntdq") {
HasAVX512VPOPCNTDQ = true;
+ } else if (Feature == "+avx512vnni") {
+ HasAVX512VNNI = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
+ } else if (Feature == "+avx512bitalg") {
+ HasAVX512BITALG = true;
} else if (Feature == "+avx512bw") {
HasAVX512BW = true;
} else if (Feature == "+avx512vl") {
HasAVX512VL = true;
} else if (Feature == "+avx512vbmi") {
HasAVX512VBMI = true;
+ } else if (Feature == "+avx512vbmi2") {
+ HasAVX512VBMI2 = true;
} else if (Feature == "+avx512ifma") {
HasAVX512IFMA = true;
} else if (Feature == "+sha") {
@@ -934,9 +976,15 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasAES)
Builder.defineMacro("__AES__");
+ if (HasVAES)
+ Builder.defineMacro("__VAES__");
+
if (HasPCLMUL)
Builder.defineMacro("__PCLMUL__");
+ if (HasVPCLMULQDQ)
+ Builder.defineMacro("__VPCLMULQDQ__");
+
if (HasLZCNT)
Builder.defineMacro("__LZCNT__");
@@ -996,22 +1044,31 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasF16C)
Builder.defineMacro("__F16C__");
+ if (HasGFNI)
+ Builder.defineMacro("__GFNI__");
+
if (HasAVX512CD)
Builder.defineMacro("__AVX512CD__");
if (HasAVX512VPOPCNTDQ)
Builder.defineMacro("__AVX512VPOPCNTDQ__");
+ if (HasAVX512VNNI)
+ Builder.defineMacro("__AVX512VNNI__");
if (HasAVX512ER)
Builder.defineMacro("__AVX512ER__");
if (HasAVX512PF)
Builder.defineMacro("__AVX512PF__");
if (HasAVX512DQ)
Builder.defineMacro("__AVX512DQ__");
+ if (HasAVX512BITALG)
+ Builder.defineMacro("__AVX512BITALG__");
if (HasAVX512BW)
Builder.defineMacro("__AVX512BW__");
if (HasAVX512VL)
Builder.defineMacro("__AVX512VL__");
if (HasAVX512VBMI)
Builder.defineMacro("__AVX512VBMI__");
+ if (HasAVX512VBMI2)
+ Builder.defineMacro("__AVX512VBMI2__");
if (HasAVX512IFMA)
Builder.defineMacro("__AVX512IFMA__");
@@ -1141,12 +1198,15 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("avx512f", true)
.Case("avx512cd", true)
.Case("avx512vpopcntdq", true)
+ .Case("avx512vnni", true)
.Case("avx512er", true)
.Case("avx512pf", true)
.Case("avx512dq", true)
+ .Case("avx512bitalg", true)
.Case("avx512bw", true)
.Case("avx512vl", true)
.Case("avx512vbmi", true)
+ .Case("avx512vbmi2", true)
.Case("avx512ifma", true)
.Case("bmi", true)
.Case("bmi2", true)
@@ -1159,6 +1219,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("fma4", true)
.Case("fsgsbase", true)
.Case("fxsr", true)
+ .Case("gfni", true)
.Case("lwp", true)
.Case("lzcnt", true)
.Case("mmx", true)
@@ -1185,6 +1246,8 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("sse4.2", true)
.Case("sse4a", true)
.Case("tbm", true)
+ .Case("vaes", true)
+ .Case("vpclmulqdq", true)
.Case("x87", true)
.Case("xop", true)
.Case("xsave", true)
@@ -1203,12 +1266,15 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("avx512f", SSELevel >= AVX512F)
.Case("avx512cd", HasAVX512CD)
.Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
+ .Case("avx512vnni", HasAVX512VNNI)
.Case("avx512er", HasAVX512ER)
.Case("avx512pf", HasAVX512PF)
.Case("avx512dq", HasAVX512DQ)
+ .Case("avx512bitalg", HasAVX512BITALG)
.Case("avx512bw", HasAVX512BW)
.Case("avx512vl", HasAVX512VL)
.Case("avx512vbmi", HasAVX512VBMI)
+ .Case("avx512vbmi2", HasAVX512VBMI2)
.Case("avx512ifma", HasAVX512IFMA)
.Case("bmi", HasBMI)
.Case("bmi2", HasBMI2)
@@ -1221,6 +1287,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("fma4", XOPLevel >= FMA4)
.Case("fsgsbase", HasFSGSBASE)
.Case("fxsr", HasFXSR)
+ .Case("gfni", HasGFNI)
.Case("ibt", HasIBT)
.Case("lwp", HasLWP)
.Case("lzcnt", HasLZCNT)
@@ -1249,6 +1316,8 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("sse4.2", SSELevel >= SSE42)
.Case("sse4a", XOPLevel >= SSE4A)
.Case("tbm", HasTBM)
+ .Case("vaes", HasVAES)
+ .Case("vpclmulqdq", HasVPCLMULQDQ)
.Case("x86", true)
.Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
.Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
diff --git a/lib/Basic/Targets/X86.h b/lib/Basic/Targets/X86.h
index b1811593545e..cbd6a2d24fb5 100644
--- a/lib/Basic/Targets/X86.h
+++ b/lib/Basic/Targets/X86.h
@@ -48,7 +48,10 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP;
bool HasAES = false;
+ bool HasVAES = false;
bool HasPCLMUL = false;
+ bool HasVPCLMULQDQ = false;
+ bool HasGFNI = false;
bool HasLZCNT = false;
bool HasRDRND = false;
bool HasFSGSBASE = false;
@@ -65,12 +68,15 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasF16C = false;
bool HasAVX512CD = false;
bool HasAVX512VPOPCNTDQ = false;
+ bool HasAVX512VNNI = false;
bool HasAVX512ER = false;
bool HasAVX512PF = false;
bool HasAVX512DQ = false;
+ bool HasAVX512BITALG = false;
bool HasAVX512BW = false;
bool HasAVX512VL = false;
bool HasAVX512VBMI = false;
+ bool HasAVX512VBMI2 = false;
bool HasAVX512IFMA = false;
bool HasSHA = false;
bool HasMPX = false;
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-10 14:40:51 +0000