diff options
Diffstat (limited to 'lib/CodeGen/GlobalISel/MachineIRBuilder.cpp')
| -rw-r--r-- | lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 797 |
1 files changed, 480 insertions, 317 deletions
diff --git a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 3271b54aa830..1f5611061994 100644 --- a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -10,6 +10,7 @@ /// This file implements the MachineIRBuidler class. //===----------------------------------------------------------------------===// #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" @@ -22,73 +23,72 @@ using namespace llvm; -void MachineIRBuilderBase::setMF(MachineFunction &MF) { +void MachineIRBuilder::setMF(MachineFunction &MF) { State.MF = &MF; State.MBB = nullptr; State.MRI = &MF.getRegInfo(); State.TII = MF.getSubtarget().getInstrInfo(); State.DL = DebugLoc(); State.II = MachineBasicBlock::iterator(); - State.InsertedInstr = nullptr; + State.Observer = nullptr; } -void MachineIRBuilderBase::setMBB(MachineBasicBlock &MBB) { +void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) { State.MBB = &MBB; State.II = MBB.end(); assert(&getMF() == MBB.getParent() && "Basic block is in a different function"); } -void MachineIRBuilderBase::setInstr(MachineInstr &MI) { +void MachineIRBuilder::setInstr(MachineInstr &MI) { assert(MI.getParent() && "Instruction is not part of a basic block"); setMBB(*MI.getParent()); State.II = MI.getIterator(); } -void MachineIRBuilderBase::setInsertPt(MachineBasicBlock &MBB, - MachineBasicBlock::iterator II) { +void MachineIRBuilder::setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; } + +void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB, + MachineBasicBlock::iterator II) { assert(MBB.getParent() == &getMF() && "Basic block is in a different function"); State.MBB = &MBB; State.II = II; } -void MachineIRBuilderBase::recordInsertion(MachineInstr *InsertedInstr) const { - if (State.InsertedInstr) - State.InsertedInstr(InsertedInstr); +void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const { + if (State.Observer) + State.Observer->createdInstr(*InsertedInstr); } -void MachineIRBuilderBase::recordInsertions( - std::function<void(MachineInstr *)> Inserted) { - State.InsertedInstr = std::move(Inserted); +void MachineIRBuilder::setChangeObserver(GISelChangeObserver &Observer) { + State.Observer = &Observer; } -void MachineIRBuilderBase::stopRecordingInsertions() { - State.InsertedInstr = nullptr; -} +void MachineIRBuilder::stopObservingChanges() { State.Observer = nullptr; } //------------------------------------------------------------------------------ // Build instruction variants. //------------------------------------------------------------------------------ -MachineInstrBuilder MachineIRBuilderBase::buildInstr(unsigned Opcode) { +MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) { return insertInstr(buildInstrNoInsert(Opcode)); } -MachineInstrBuilder MachineIRBuilderBase::buildInstrNoInsert(unsigned Opcode) { +MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) { MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); return MIB; } -MachineInstrBuilder MachineIRBuilderBase::insertInstr(MachineInstrBuilder MIB) { +MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { getMBB().insert(getInsertPt(), MIB); recordInsertion(MIB); return MIB; } MachineInstrBuilder -MachineIRBuilderBase::buildDirectDbgValue(unsigned Reg, const MDNode *Variable, - const MDNode *Expr) { +MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -99,8 +99,9 @@ MachineIRBuilderBase::buildDirectDbgValue(unsigned Reg, const MDNode *Variable, /*IsIndirect*/ false, Reg, Variable, Expr)); } -MachineInstrBuilder MachineIRBuilderBase::buildIndirectDbgValue( - unsigned Reg, const MDNode *Variable, const MDNode *Expr) { +MachineInstrBuilder +MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -111,9 +112,9 @@ MachineInstrBuilder MachineIRBuilderBase::buildIndirectDbgValue( /*IsIndirect*/ true, Reg, Variable, Expr)); } -MachineInstrBuilder -MachineIRBuilderBase::buildFIDbgValue(int FI, const MDNode *Variable, - const MDNode *Expr) { +MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI, + const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -126,8 +127,9 @@ MachineIRBuilderBase::buildFIDbgValue(int FI, const MDNode *Variable, .addMetadata(Expr); } -MachineInstrBuilder MachineIRBuilderBase::buildConstDbgValue( - const Constant &C, const MDNode *Variable, const MDNode *Expr) { +MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C, + const MDNode *Variable, + const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert( @@ -149,16 +151,24 @@ MachineInstrBuilder MachineIRBuilderBase::buildConstDbgValue( return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr); } -MachineInstrBuilder MachineIRBuilderBase::buildFrameIndex(unsigned Res, - int Idx) { +MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) { + assert(isa<DILabel>(Label) && "not a label"); + assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) && + "Expected inlined-at fields to agree"); + auto MIB = buildInstr(TargetOpcode::DBG_LABEL); + + return MIB.addMetadata(Label); +} + +MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) { assert(getMRI()->getType(Res).isPointer() && "invalid operand type"); return buildInstr(TargetOpcode::G_FRAME_INDEX) .addDef(Res) .addFrameIndex(Idx); } -MachineInstrBuilder -MachineIRBuilderBase::buildGlobalValue(unsigned Res, const GlobalValue *GV) { +MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res, + const GlobalValue *GV) { assert(getMRI()->getType(Res).isPointer() && "invalid operand type"); assert(getMRI()->getType(Res).getAddressSpace() == GV->getType()->getAddressSpace() && @@ -169,17 +179,14 @@ MachineIRBuilderBase::buildGlobalValue(unsigned Res, const GlobalValue *GV) { .addGlobalAddress(GV); } -void MachineIRBuilderBase::validateBinaryOp(unsigned Res, unsigned Op0, - unsigned Op1) { - assert((getMRI()->getType(Res).isScalar() || - getMRI()->getType(Res).isVector()) && - "invalid operand type"); - assert(getMRI()->getType(Res) == getMRI()->getType(Op0) && - getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch"); +void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0, + const LLT &Op1) { + assert((Res.isScalar() || Res.isVector()) && "invalid operand type"); + assert((Res == Op0 && Res == Op1) && "type mismatch"); } -MachineInstrBuilder MachineIRBuilderBase::buildGEP(unsigned Res, unsigned Op0, - unsigned Op1) { +MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0, + unsigned Op1) { assert(getMRI()->getType(Res).isPointer() && getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch"); assert(getMRI()->getType(Op1).isScalar() && "invalid offset type"); @@ -191,8 +198,8 @@ MachineInstrBuilder MachineIRBuilderBase::buildGEP(unsigned Res, unsigned Op0, } Optional<MachineInstrBuilder> -MachineIRBuilderBase::materializeGEP(unsigned &Res, unsigned Op0, - const LLT &ValueTy, uint64_t Value) { +MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0, + const LLT &ValueTy, uint64_t Value) { assert(Res == 0 && "Res is a result argument"); assert(ValueTy.isScalar() && "invalid offset type"); @@ -208,9 +215,8 @@ MachineIRBuilderBase::materializeGEP(unsigned &Res, unsigned Op0, return buildGEP(Res, Op0, TmpReg); } -MachineInstrBuilder MachineIRBuilderBase::buildPtrMask(unsigned Res, - unsigned Op0, - uint32_t NumBits) { +MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0, + uint32_t NumBits) { assert(getMRI()->getType(Res).isPointer() && getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch"); @@ -220,24 +226,23 @@ MachineInstrBuilder MachineIRBuilderBase::buildPtrMask(unsigned Res, .addImm(NumBits); } -MachineInstrBuilder MachineIRBuilderBase::buildBr(MachineBasicBlock &Dest) { +MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) { return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); } -MachineInstrBuilder MachineIRBuilderBase::buildBrIndirect(unsigned Tgt) { +MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) { assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination"); return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); } -MachineInstrBuilder MachineIRBuilderBase::buildCopy(unsigned Res, unsigned Op) { - assert(getMRI()->getType(Res) == LLT() || getMRI()->getType(Op) == LLT() || - getMRI()->getType(Res) == getMRI()->getType(Op)); - return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::COPY, Res, Op); } -MachineInstrBuilder -MachineIRBuilderBase::buildConstant(unsigned Res, const ConstantInt &Val) { - LLT Ty = getMRI()->getType(Res); +MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, + const ConstantInt &Val) { + LLT Ty = Res.getLLTTy(*getMRI()); assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type"); @@ -246,48 +251,55 @@ MachineIRBuilderBase::buildConstant(unsigned Res, const ConstantInt &Val) { NewVal = ConstantInt::get(getMF().getFunction().getContext(), Val.getValue().sextOrTrunc(Ty.getSizeInBits())); - return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal); + auto MIB = buildInstr(TargetOpcode::G_CONSTANT); + Res.addDefToMIB(*getMRI(), MIB); + MIB.addCImm(NewVal); + return MIB; } -MachineInstrBuilder MachineIRBuilderBase::buildConstant(unsigned Res, - int64_t Val) { +MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, + int64_t Val) { auto IntN = IntegerType::get(getMF().getFunction().getContext(), - getMRI()->getType(Res).getSizeInBits()); + Res.getLLTTy(*getMRI()).getSizeInBits()); ConstantInt *CI = ConstantInt::get(IntN, Val, true); return buildConstant(Res, *CI); } -MachineInstrBuilder -MachineIRBuilderBase::buildFConstant(unsigned Res, const ConstantFP &Val) { - assert(getMRI()->getType(Res).isScalar() && "invalid operand type"); +MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res, + const ConstantFP &Val) { + assert(Res.getLLTTy(*getMRI()).isScalar() && "invalid operand type"); - return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val); + auto MIB = buildInstr(TargetOpcode::G_FCONSTANT); + Res.addDefToMIB(*getMRI(), MIB); + MIB.addFPImm(&Val); + return MIB; } -MachineInstrBuilder MachineIRBuilderBase::buildFConstant(unsigned Res, - double Val) { - LLT DstTy = getMRI()->getType(Res); +MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res, + double Val) { + LLT DstTy = Res.getLLTTy(*getMRI()); auto &Ctx = getMF().getFunction().getContext(); auto *CFP = ConstantFP::get(Ctx, getAPFloatFromSize(Val, DstTy.getSizeInBits())); return buildFConstant(Res, *CFP); } -MachineInstrBuilder MachineIRBuilderBase::buildBrCond(unsigned Tst, - MachineBasicBlock &Dest) { +MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst, + MachineBasicBlock &Dest) { assert(getMRI()->getType(Tst).isScalar() && "invalid operand type"); return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); } -MachineInstrBuilder MachineIRBuilderBase::buildLoad(unsigned Res, unsigned Addr, - MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr, + MachineMemOperand &MMO) { return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO); } -MachineInstrBuilder -MachineIRBuilderBase::buildLoadInstr(unsigned Opcode, unsigned Res, - unsigned Addr, MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode, + unsigned Res, + unsigned Addr, + MachineMemOperand &MMO) { assert(getMRI()->getType(Res).isValid() && "invalid operand type"); assert(getMRI()->getType(Addr).isPointer() && "invalid operand type"); @@ -297,9 +309,8 @@ MachineIRBuilderBase::buildLoadInstr(unsigned Opcode, unsigned Res, .addMemOperand(&MMO); } -MachineInstrBuilder MachineIRBuilderBase::buildStore(unsigned Val, - unsigned Addr, - MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, + MachineMemOperand &MMO) { assert(getMRI()->getType(Val).isValid() && "invalid operand type"); assert(getMRI()->getType(Addr).isPointer() && "invalid operand type"); @@ -309,83 +320,73 @@ MachineInstrBuilder MachineIRBuilderBase::buildStore(unsigned Val, .addMemOperand(&MMO); } -MachineInstrBuilder MachineIRBuilderBase::buildUAdde(unsigned Res, - unsigned CarryOut, - unsigned Op0, unsigned Op1, - unsigned CarryIn) { - assert(getMRI()->getType(Res).isScalar() && "invalid operand type"); - assert(getMRI()->getType(Res) == getMRI()->getType(Op0) && - getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch"); - assert(getMRI()->getType(CarryOut).isScalar() && "invalid operand type"); - assert(getMRI()->getType(CarryOut) == getMRI()->getType(CarryIn) && - "type mismatch"); - - return buildInstr(TargetOpcode::G_UADDE) - .addDef(Res) - .addDef(CarryOut) - .addUse(Op0) - .addUse(Op1) - .addUse(CarryIn); +MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res, + const DstOp &CarryOut, + const SrcOp &Op0, + const SrcOp &Op1, + const SrcOp &CarryIn) { + return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, + {Op0, Op1, CarryIn}); } -MachineInstrBuilder MachineIRBuilderBase::buildAnyExt(unsigned Res, - unsigned Op) { - validateTruncExt(Res, Op, true); - return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_ANYEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildSExt(unsigned Res, unsigned Op) { - validateTruncExt(Res, Op, true); - return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_SEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildZExt(unsigned Res, unsigned Op) { - validateTruncExt(Res, Op, true); - return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_ZEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildExtOrTrunc(unsigned ExtOpc, - unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, + const DstOp &Res, + const SrcOp &Op) { assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || TargetOpcode::G_SEXT == ExtOpc) && "Expecting Extending Opc"); - assert(getMRI()->getType(Res).isScalar() || - getMRI()->getType(Res).isVector()); - assert(getMRI()->getType(Res).isScalar() == getMRI()->getType(Op).isScalar()); + assert(Res.getLLTTy(*getMRI()).isScalar() || + Res.getLLTTy(*getMRI()).isVector()); + assert(Res.getLLTTy(*getMRI()).isScalar() == + Op.getLLTTy(*getMRI()).isScalar()); unsigned Opcode = TargetOpcode::COPY; - if (getMRI()->getType(Res).getSizeInBits() > - getMRI()->getType(Op).getSizeInBits()) + if (Res.getLLTTy(*getMRI()).getSizeInBits() > + Op.getLLTTy(*getMRI()).getSizeInBits()) Opcode = ExtOpc; - else if (getMRI()->getType(Res).getSizeInBits() < - getMRI()->getType(Op).getSizeInBits()) + else if (Res.getLLTTy(*getMRI()).getSizeInBits() < + Op.getLLTTy(*getMRI()).getSizeInBits()) Opcode = TargetOpcode::G_TRUNC; else - assert(getMRI()->getType(Res) == getMRI()->getType(Op)); + assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI())); - return buildInstr(Opcode).addDef(Res).addUse(Op); + return buildInstr(Opcode, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildSExtOrTrunc(unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res, + const SrcOp &Op) { return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildZExtOrTrunc(unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res, + const SrcOp &Op) { return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildAnyExtOrTrunc(unsigned Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res, + const SrcOp &Op) { return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildCast(unsigned Dst, - unsigned Src) { - LLT SrcTy = getMRI()->getType(Src); - LLT DstTy = getMRI()->getType(Dst); +MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst, + const SrcOp &Src) { + LLT SrcTy = Src.getLLTTy(*getMRI()); + LLT DstTy = Dst.getLLTTy(*getMRI()); if (SrcTy == DstTy) return buildCopy(Dst, Src); @@ -399,11 +400,11 @@ MachineInstrBuilder MachineIRBuilderBase::buildCast(unsigned Dst, Opcode = TargetOpcode::G_BITCAST; } - return buildInstr(Opcode).addDef(Dst).addUse(Src); + return buildInstr(Opcode, Dst, Src); } -MachineInstrBuilder -MachineIRBuilderBase::buildExtract(unsigned Res, unsigned Src, uint64_t Index) { +MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src, + uint64_t Index) { #ifndef NDEBUG assert(getMRI()->getType(Src).isValid() && "invalid operand type"); assert(getMRI()->getType(Res).isValid() && "invalid operand type"); @@ -424,8 +425,8 @@ MachineIRBuilderBase::buildExtract(unsigned Res, unsigned Src, uint64_t Index) { .addImm(Index); } -void MachineIRBuilderBase::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, - ArrayRef<uint64_t> Indices) { +void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, + ArrayRef<uint64_t> Indices) { #ifndef NDEBUG assert(Ops.size() == Indices.size() && "incompatible args"); assert(!Ops.empty() && "invalid trivial sequence"); @@ -465,56 +466,67 @@ void MachineIRBuilderBase::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, } } -MachineInstrBuilder MachineIRBuilderBase::buildUndef(unsigned Res) { - return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res); +MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { + return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {}); } -MachineInstrBuilder MachineIRBuilderBase::buildMerge(unsigned Res, - ArrayRef<unsigned> Ops) { - -#ifndef NDEBUG - assert(!Ops.empty() && "invalid trivial sequence"); - LLT Ty = getMRI()->getType(Ops[0]); - for (auto Reg : Ops) - assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list"); - assert(Ops.size() * getMRI()->getType(Ops[0]).getSizeInBits() == - getMRI()->getType(Res).getSizeInBits() && - "input operands do not cover output register"); -#endif +MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res, + ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec); +} - if (Ops.size() == 1) - return buildCast(Res, Ops[0]); +MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res, + const SrcOp &Op) { + // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); + return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op); +} - MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES); - MIB.addDef(Res); - for (unsigned i = 0; i < Ops.size(); ++i) - MIB.addUse(Ops[i]); - return MIB; +MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res, + const SrcOp &Op) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end()); + return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildUnmerge(ArrayRef<unsigned> Res, - unsigned Op) { +MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, + ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec); +} -#ifndef NDEBUG - assert(!Res.empty() && "invalid trivial sequence"); - LLT Ty = getMRI()->getType(Res[0]); - for (auto Reg : Res) - assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list"); - assert(Res.size() * getMRI()->getType(Res[0]).getSizeInBits() == - getMRI()->getType(Op).getSizeInBits() && - "input operands do not cover output register"); -#endif +MachineInstrBuilder +MachineIRBuilder::buildBuildVectorTrunc(const DstOp &Res, + ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec); +} - MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES); - for (unsigned i = 0; i < Res.size(); ++i) - MIB.addDef(Res[i]); - MIB.addUse(Op); - return MIB; +MachineInstrBuilder +MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<unsigned> Ops) { + // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>, + // we need some temporary storage for the DstOp objects. Here we use a + // sufficiently large SmallVector to not go through the heap. + SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end()); + return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec); } -MachineInstrBuilder MachineIRBuilderBase::buildInsert(unsigned Res, - unsigned Src, unsigned Op, - unsigned Index) { +MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src, + unsigned Op, unsigned Index) { assert(Index + getMRI()->getType(Op).getSizeInBits() <= getMRI()->getType(Res).getSizeInBits() && "insertion past the end of a register"); @@ -531,9 +543,9 @@ MachineInstrBuilder MachineIRBuilderBase::buildInsert(unsigned Res, .addImm(Index); } -MachineInstrBuilder MachineIRBuilderBase::buildIntrinsic(Intrinsic::ID ID, - unsigned Res, - bool HasSideEffects) { +MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, + unsigned Res, + bool HasSideEffects) { auto MIB = buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS : TargetOpcode::G_INTRINSIC); @@ -543,133 +555,52 @@ MachineInstrBuilder MachineIRBuilderBase::buildIntrinsic(Intrinsic::ID ID, return MIB; } -MachineInstrBuilder MachineIRBuilderBase::buildTrunc(unsigned Res, - unsigned Op) { - validateTruncExt(Res, Op, false); - return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_TRUNC, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildFPTrunc(unsigned Res, - unsigned Op) { - validateTruncExt(Res, Op, false); - return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op); +MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res, + const SrcOp &Op) { + return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op); } -MachineInstrBuilder MachineIRBuilderBase::buildICmp(CmpInst::Predicate Pred, - unsigned Res, unsigned Op0, - unsigned Op1) { -#ifndef NDEBUG - assert(getMRI()->getType(Op0) == getMRI()->getType(Op0) && "type mismatch"); - assert(CmpInst::isIntPredicate(Pred) && "invalid predicate"); - if (getMRI()->getType(Op0).isScalar() || getMRI()->getType(Op0).isPointer()) - assert(getMRI()->getType(Res).isScalar() && "type mismatch"); - else - assert(getMRI()->getType(Res).isVector() && - getMRI()->getType(Res).getNumElements() == - getMRI()->getType(Op0).getNumElements() && - "type mismatch"); -#endif - - return buildInstr(TargetOpcode::G_ICMP) - .addDef(Res) - .addPredicate(Pred) - .addUse(Op0) - .addUse(Op1); +MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, + const DstOp &Res, + const SrcOp &Op0, + const SrcOp &Op1) { + return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}); } -MachineInstrBuilder MachineIRBuilderBase::buildFCmp(CmpInst::Predicate Pred, - unsigned Res, unsigned Op0, - unsigned Op1) { -#ifndef NDEBUG - assert((getMRI()->getType(Op0).isScalar() || - getMRI()->getType(Op0).isVector()) && - "invalid operand type"); - assert(getMRI()->getType(Op0) == getMRI()->getType(Op1) && "type mismatch"); - assert(CmpInst::isFPPredicate(Pred) && "invalid predicate"); - if (getMRI()->getType(Op0).isScalar()) - assert(getMRI()->getType(Res).isScalar() && "type mismatch"); - else - assert(getMRI()->getType(Res).isVector() && - getMRI()->getType(Res).getNumElements() == - getMRI()->getType(Op0).getNumElements() && - "type mismatch"); -#endif +MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, + const DstOp &Res, + const SrcOp &Op0, + const SrcOp &Op1) { - return buildInstr(TargetOpcode::G_FCMP) - .addDef(Res) - .addPredicate(Pred) - .addUse(Op0) - .addUse(Op1); + return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}); } -MachineInstrBuilder MachineIRBuilderBase::buildSelect(unsigned Res, - unsigned Tst, - unsigned Op0, - unsigned Op1) { -#ifndef NDEBUG - LLT ResTy = getMRI()->getType(Res); - assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) && - "invalid operand type"); - assert(ResTy == getMRI()->getType(Op0) && ResTy == getMRI()->getType(Op1) && - "type mismatch"); - if (ResTy.isScalar() || ResTy.isPointer()) - assert(getMRI()->getType(Tst).isScalar() && "type mismatch"); - else - assert((getMRI()->getType(Tst).isScalar() || - (getMRI()->getType(Tst).isVector() && - getMRI()->getType(Tst).getNumElements() == - getMRI()->getType(Op0).getNumElements())) && - "type mismatch"); -#endif +MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res, + const SrcOp &Tst, + const SrcOp &Op0, + const SrcOp &Op1) { - return buildInstr(TargetOpcode::G_SELECT) - .addDef(Res) - .addUse(Tst) - .addUse(Op0) - .addUse(Op1); + return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}); } MachineInstrBuilder -MachineIRBuilderBase::buildInsertVectorElement(unsigned Res, unsigned Val, - unsigned Elt, unsigned Idx) { -#ifndef NDEBUG - LLT ResTy = getMRI()->getType(Res); - LLT ValTy = getMRI()->getType(Val); - LLT EltTy = getMRI()->getType(Elt); - LLT IdxTy = getMRI()->getType(Idx); - assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type"); - assert(IdxTy.isScalar() && "invalid operand type"); - assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch"); - assert(ResTy.getElementType() == EltTy && "type mismatch"); -#endif - - return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT) - .addDef(Res) - .addUse(Val) - .addUse(Elt) - .addUse(Idx); +MachineIRBuilder::buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, + const SrcOp &Elt, const SrcOp &Idx) { + return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx}); } MachineInstrBuilder -MachineIRBuilderBase::buildExtractVectorElement(unsigned Res, unsigned Val, - unsigned Idx) { -#ifndef NDEBUG - LLT ResTy = getMRI()->getType(Res); - LLT ValTy = getMRI()->getType(Val); - LLT IdxTy = getMRI()->getType(Idx); - assert(ValTy.isVector() && "invalid operand type"); - assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type"); - assert(IdxTy.isScalar() && "invalid operand type"); - assert(ValTy.getElementType() == ResTy && "type mismatch"); -#endif - - return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT) - .addDef(Res) - .addUse(Val) - .addUse(Idx); +MachineIRBuilder::buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, + const SrcOp &Idx) { + return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx}); } -MachineInstrBuilder MachineIRBuilderBase::buildAtomicCmpXchgWithSuccess( +MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess( unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO) { #ifndef NDEBUG @@ -697,9 +628,9 @@ MachineInstrBuilder MachineIRBuilderBase::buildAtomicCmpXchgWithSuccess( } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, - unsigned CmpVal, unsigned NewVal, - MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, + unsigned CmpVal, unsigned NewVal, + MachineMemOperand &MMO) { #ifndef NDEBUG LLT OldValResTy = getMRI()->getType(OldValRes); LLT AddrTy = getMRI()->getType(Addr); @@ -721,10 +652,11 @@ MachineIRBuilderBase::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, .addMemOperand(&MMO); } -MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMW(unsigned Opcode, unsigned OldValRes, - unsigned Addr, unsigned Val, - MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(unsigned Opcode, + unsigned OldValRes, + unsigned Addr, + unsigned Val, + MachineMemOperand &MMO) { #ifndef NDEBUG LLT OldValResTy = getMRI()->getType(OldValRes); LLT AddrTy = getMRI()->getType(Addr); @@ -743,74 +675,75 @@ MachineIRBuilderBase::buildAtomicRMW(unsigned Opcode, unsigned OldValRes, } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val, MMO); } -MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWOr(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(unsigned OldValRes, + unsigned Addr, + unsigned Val, + MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, - unsigned Val, MachineMemOperand &MMO) { +MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, + unsigned Val, MachineMemOperand &MMO) { return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val, MMO); } MachineInstrBuilder -MachineIRBuilderBase::buildBlockAddress(unsigned Res, const BlockAddress *BA) { +MachineIRBuilder::buildBlockAddress(unsigned Res, const BlockAddress *BA) { #ifndef NDEBUG assert(getMRI()->getType(Res).isPointer() && "invalid res type"); #endif @@ -818,12 +751,9 @@ MachineIRBuilderBase::buildBlockAddress(unsigned Res, const BlockAddress *BA) { return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); } -void MachineIRBuilderBase::validateTruncExt(unsigned Dst, unsigned Src, - bool IsExtend) { +void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy, + bool IsExtend) { #ifndef NDEBUG - LLT SrcTy = getMRI()->getType(Src); - LLT DstTy = getMRI()->getType(Dst); - if (DstTy.isVector()) { assert(SrcTy.isVector() && "mismatched cast between vector and non-vector"); assert(SrcTy.getNumElements() == DstTy.getNumElements() && @@ -839,3 +769,236 @@ void MachineIRBuilderBase::validateTruncExt(unsigned Dst, unsigned Src, "invalid widening trunc"); #endif } + +void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy, + const LLT &Op0Ty, const LLT &Op1Ty) { +#ifndef NDEBUG + assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) && + "invalid operand type"); + assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch"); + if (ResTy.isScalar() || ResTy.isPointer()) + assert(TstTy.isScalar() && "type mismatch"); + else + assert((TstTy.isScalar() || + (TstTy.isVector() && + TstTy.getNumElements() == Op0Ty.getNumElements())) && + "type mismatch"); +#endif +} + +MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc, + ArrayRef<DstOp> DstOps, + ArrayRef<SrcOp> SrcOps, + Optional<unsigned> Flags) { + switch (Opc) { + default: + break; + case TargetOpcode::G_SELECT: { + assert(DstOps.size() == 1 && "Invalid select"); + assert(SrcOps.size() == 3 && "Invalid select"); + validateSelectOp( + DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()), + SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI())); + break; + } + case TargetOpcode::G_ADD: + case TargetOpcode::G_AND: + case TargetOpcode::G_ASHR: + case TargetOpcode::G_LSHR: + case TargetOpcode::G_MUL: + case TargetOpcode::G_OR: + case TargetOpcode::G_SHL: + case TargetOpcode::G_SUB: + case TargetOpcode::G_XOR: + case TargetOpcode::G_UDIV: + case TargetOpcode::G_SDIV: + case TargetOpcode::G_UREM: + case TargetOpcode::G_SREM: { + // All these are binary ops. + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 2 && "Invalid Srcs"); + validateBinaryOp(DstOps[0].getLLTTy(*getMRI()), + SrcOps[0].getLLTTy(*getMRI()), + SrcOps[1].getLLTTy(*getMRI())); + break; + case TargetOpcode::G_SEXT: + case TargetOpcode::G_ZEXT: + case TargetOpcode::G_ANYEXT: + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 1 && "Invalid Srcs"); + validateTruncExt(DstOps[0].getLLTTy(*getMRI()), + SrcOps[0].getLLTTy(*getMRI()), true); + break; + case TargetOpcode::G_TRUNC: + case TargetOpcode::G_FPTRUNC: + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 1 && "Invalid Srcs"); + validateTruncExt(DstOps[0].getLLTTy(*getMRI()), + SrcOps[0].getLLTTy(*getMRI()), false); + break; + } + case TargetOpcode::COPY: + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(SrcOps.size() == 1 && "Invalid Srcs"); + assert(DstOps[0].getLLTTy(*getMRI()) == LLT() || + SrcOps[0].getLLTTy(*getMRI()) == LLT() || + DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())); + break; + case TargetOpcode::G_FCMP: + case TargetOpcode::G_ICMP: { + assert(DstOps.size() == 1 && "Invalid Dst Operands"); + assert(SrcOps.size() == 3 && "Invalid Src Operands"); + // For F/ICMP, the first src operand is the predicate, followed by + // the two comparands. + assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate && + "Expecting predicate"); + assert([&]() -> bool { + CmpInst::Predicate Pred = SrcOps[0].getPredicate(); + return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred) + : CmpInst::isFPPredicate(Pred); + }() && "Invalid predicate"); + assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) && + "Type mismatch"); + assert([&]() -> bool { + LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI()); + LLT DstTy = DstOps[0].getLLTTy(*getMRI()); + if (Op0Ty.isScalar() || Op0Ty.isPointer()) + return DstTy.isScalar(); + else + return DstTy.isVector() && + DstTy.getNumElements() == Op0Ty.getNumElements(); + }() && "Type Mismatch"); + break; + } + case TargetOpcode::G_UNMERGE_VALUES: { + assert(!DstOps.empty() && "Invalid trivial sequence"); + assert(SrcOps.size() == 1 && "Invalid src for Unmerge"); + assert(std::all_of(DstOps.begin(), DstOps.end(), + [&, this](const DstOp &Op) { + return Op.getLLTTy(*getMRI()) == + DstOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in output list"); + assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() == + SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input operands do not cover output register"); + break; + } + case TargetOpcode::G_MERGE_VALUES: { + assert(!SrcOps.empty() && "invalid trivial sequence"); + assert(DstOps.size() == 1 && "Invalid Dst"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in input list"); + assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input operands do not cover output register"); + if (SrcOps.size() == 1) + return buildCast(DstOps[0], SrcOps[0]); + if (DstOps[0].getLLTTy(*getMRI()).isVector()) + return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps); + break; + } + case TargetOpcode::G_EXTRACT_VECTOR_ELT: { + assert(DstOps.size() == 1 && "Invalid Dst size"); + assert(SrcOps.size() == 2 && "Invalid Src size"); + assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type"); + assert((DstOps[0].getLLTTy(*getMRI()).isScalar() || + DstOps[0].getLLTTy(*getMRI()).isPointer()) && + "Invalid operand type"); + assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type"); + assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() == + DstOps[0].getLLTTy(*getMRI()) && + "Type mismatch"); + break; + } + case TargetOpcode::G_INSERT_VECTOR_ELT: { + assert(DstOps.size() == 1 && "Invalid dst size"); + assert(SrcOps.size() == 3 && "Invalid src size"); + assert(DstOps[0].getLLTTy(*getMRI()).isVector() && + SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type"); + assert(DstOps[0].getLLTTy(*getMRI()).getElementType() == + SrcOps[1].getLLTTy(*getMRI()) && + "Type mismatch"); + assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index"); + assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() == + SrcOps[0].getLLTTy(*getMRI()).getNumElements() && + "Type mismatch"); + break; + } + case TargetOpcode::G_BUILD_VECTOR: { + assert((!SrcOps.empty() || SrcOps.size() < 2) && + "Must have at least 2 operands"); + assert(DstOps.size() == 1 && "Invalid DstOps"); + assert(DstOps[0].getLLTTy(*getMRI()).isVector() && + "Res type must be a vector"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in input list"); + assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input scalars do not exactly cover the outpur vector register"); + break; + } + case TargetOpcode::G_BUILD_VECTOR_TRUNC: { + assert((!SrcOps.empty() || SrcOps.size() < 2) && + "Must have at least 2 operands"); + assert(DstOps.size() == 1 && "Invalid DstOps"); + assert(DstOps[0].getLLTTy(*getMRI()).isVector() && + "Res type must be a vector"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI()); + }) && + "type mismatch in input list"); + if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits()) + return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps); + break; + } + case TargetOpcode::G_CONCAT_VECTORS: { + assert(DstOps.size() == 1 && "Invalid DstOps"); + assert((!SrcOps.empty() || SrcOps.size() < 2) && + "Must have at least 2 operands"); + assert(std::all_of(SrcOps.begin(), SrcOps.end(), + [&, this](const SrcOp &Op) { + return (Op.getLLTTy(*getMRI()).isVector() && + Op.getLLTTy(*getMRI()) == + SrcOps[0].getLLTTy(*getMRI())); + }) && + "type mismatch in input list"); + assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == + DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && + "input vectors do not exactly cover the outpur vector register"); + break; + } + case TargetOpcode::G_UADDE: { + assert(DstOps.size() == 2 && "Invalid no of dst operands"); + assert(SrcOps.size() == 3 && "Invalid no of src operands"); + assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand"); + assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) && + (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) && + "Invalid operand"); + assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand"); + assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) && + "type mismatch"); + break; + } + } + + auto MIB = buildInstr(Opc); + for (const DstOp &Op : DstOps) + Op.addDefToMIB(*getMRI(), MIB); + for (const SrcOp &Op : SrcOps) + Op.addSrcToMIB(MIB); + if (Flags) + MIB->setFlags(*Flags); + return MIB; +} |