diff options
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 40 |
1 files changed, 32 insertions, 8 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index d1c5ddabb975..99406ed1496a 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -234,6 +234,11 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { // Ask the target if address-backscheduling is desirable, and if so how much. const TargetSubtargetInfo &ST = MF.getSubtarget(); + // Only use any non-zero latency for real defs/uses, in contrast to + // "fake" operands added by regalloc. + const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); + bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() && + !DefMIDesc->hasImplicitDefOfPhysReg(MO.getReg())); for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); Alias.isValid(); ++Alias) { if (!Uses.contains(*Alias)) @@ -257,11 +262,18 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { Dep = SDep(SU, SDep::Data, *Alias); RegUse = UseSU->getInstr(); } - Dep.setLatency( - SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, - UseOp)); + const MCInstrDesc *UseMIDesc = + (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); + bool ImplicitPseudoUse = + (UseMIDesc && UseOp >= ((int)UseMIDesc->getNumOperands()) && + !UseMIDesc->hasImplicitUseOfPhysReg(*Alias)); + if (!ImplicitPseudoDef && !ImplicitPseudoUse) { + Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, + RegUse, UseOp)); + ST.adjustSchedDependency(SU, UseSU, Dep); + } else + Dep.setLatency(0); - ST.adjustSchedDependency(SU, UseSU, Dep); UseSU->addPred(Dep); } } @@ -996,7 +1008,7 @@ void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores, for (auto &I : loads) for (auto *SU : I.second) NodeNums.push_back(SU->NodeNum); - llvm::sort(NodeNums.begin(), NodeNums.end()); + llvm::sort(NodeNums); // The N last elements in NodeNums will be removed, and the SU with // the lowest NodeNum of them will become the new BarrierChain to @@ -1097,10 +1109,22 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) { } } -void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { - // Cannot completely remove virtual function even in release mode. +void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const { +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + dumpNodeName(SU); + dbgs() << ": "; + SU.getInstr()->dump(); +#endif +} + +void ScheduleDAGInstrs::dump() const { #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) - SU->getInstr()->dump(); + if (EntrySU.getInstr() != nullptr) + dumpNodeAll(EntrySU); + for (const SUnit &SU : SUnits) + dumpNodeAll(SU); + if (ExitSU.getInstr() != nullptr) + dumpNodeAll(ExitSU); #endif } |
