1 files changed, 14 insertions, 3 deletions
diff --git a/lib/CodeGen/TargetSubtargetInfo.cpp b/lib/CodeGen/TargetSubtargetInfo.cpp
index f6d5bc80ddff..1a317cd865f0 100644
--- a/lib/CodeGen/TargetSubtargetInfo.cpp
+++ b/lib/CodeGen/TargetSubtargetInfo.cpp
@@ -11,11 +11,12 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/MC/MCInst.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
 #include <string>
@@ -50,6 +51,10 @@ bool TargetSubtargetInfo::enableRALocalReassignment(
   return true;
 }
 
+bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
+  return false;
+}
+
 bool TargetSubtargetInfo::enablePostRAScheduler() const {
   return getSchedModel().PostRAScheduler;
 }
@@ -93,9 +98,15 @@ std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
   // that could be changed during the compilation
   TargetSchedModel TSchedModel;
   TSchedModel.init(getSchedModel(), this, getInstrInfo());
-  if (!TSchedModel.hasInstrSchedModel())
+  unsigned Latency;
+  if (TSchedModel.hasInstrSchedModel())
+    Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
+  else if (TSchedModel.hasInstrItineraries()) {
+    auto *ItinData = TSchedModel.getInstrItineraries();
+    Latency = ItinData->getStageLatency(
+        getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
+  } else
     return std::string();
-  unsigned Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
   Optional<double> RThroughput =
       TSchedModel.computeInstrRThroughput(MCI.getOpcode());
   return createSchedInfoStr(Latency, RThroughput);