diff options
Diffstat (limited to 'lib/Target/AMDGPU/SOPInstructions.td')
| -rw-r--r-- | lib/Target/AMDGPU/SOPInstructions.td | 666 |
1 files changed, 458 insertions, 208 deletions
diff --git a/lib/Target/AMDGPU/SOPInstructions.td b/lib/Target/AMDGPU/SOPInstructions.td index ca5e981ac5c2..dfafdccc05a3 100644 --- a/lib/Target/AMDGPU/SOPInstructions.td +++ b/lib/Target/AMDGPU/SOPInstructions.td @@ -1,15 +1,15 @@ //===-- SOPInstructions.td - SOP Instruction Defintions -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// def GPRIdxModeMatchClass : AsmOperandClass { let Name = "GPRIdxMode"; let PredicateMethod = "isGPRIdxMode"; + let ParserMethod = "parseGPRIdxMode"; let RenderMethod = "addImmOperands"; } @@ -26,7 +26,6 @@ class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps, let isPseudo = 1; let isCodeGenOnly = 1; - let SubtargetPredicate = isGCN; string Mnemonic = opName; string AsmOperands = asmOps; @@ -78,10 +77,13 @@ class SOP1_Real<bits<8> op, SOP1_Pseudo ps> : let Inst{31-23} = 0x17d; //encoding; } -class SOP1_32 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < - opName, (outs SReg_32:$sdst), (ins SSrc_b32:$src0), - "$sdst, $src0", pattern ->; +class SOP1_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo < + opName, (outs SReg_32:$sdst), + !if(tied_in, (ins SSrc_b32:$src0, SReg_32:$sdst_in), + (ins SSrc_b32:$src0)), + "$sdst, $src0", pattern> { + let Constraints = !if(tied_in, "$sdst = $sdst_in", ""); +} // 32-bit input, no output. class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo < @@ -108,10 +110,13 @@ class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < >; // 32-bit input, 64-bit output. -class SOP1_64_32 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < - opName, (outs SReg_64:$sdst), (ins SSrc_b32:$src0), - "$sdst, $src0", pattern ->; +class SOP1_64_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo < + opName, (outs SReg_64:$sdst), + !if(tied_in, (ins SSrc_b32:$src0, SReg_64:$sdst_in), + (ins SSrc_b32:$src0)), + "$sdst, $src0", pattern> { + let Constraints = !if(tied_in, "$sdst = $sdst_in", ""); +} // no input, 64-bit output. class SOP1_64_0 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < @@ -120,8 +125,8 @@ class SOP1_64_0 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < } // 64-bit input, no output -class SOP1_1 <string opName, list<dag> pattern=[]> : SOP1_Pseudo < - opName, (outs), (ins SReg_64:$src0), "$src0", pattern> { +class SOP1_1 <string opName, RegisterClass rc = SReg_64, list<dag> pattern=[]> : SOP1_Pseudo < + opName, (outs), (ins rc:$src0), "$src0", pattern> { let has_sdst = 0; } @@ -147,12 +152,24 @@ let Defs = [SCC] in { [(set i64:$sdst, (not i64:$src0))] >; def S_WQM_B32 : SOP1_32 <"s_wqm_b32">; - def S_WQM_B64 : SOP1_64 <"s_wqm_b64", - [(set i1:$sdst, (int_amdgcn_wqm_vote i1:$src0))] - >; + def S_WQM_B64 : SOP1_64 <"s_wqm_b64">; } // End Defs = [SCC] +let WaveSizePredicate = isWave32 in { +def : GCNPat < + (int_amdgcn_wqm_vote i1:$src0), + (S_WQM_B32 $src0) +>; +} + +let WaveSizePredicate = isWave64 in { +def : GCNPat < + (int_amdgcn_wqm_vote i1:$src0), + (S_WQM_B64 $src0) +>; +} + def S_BREV_B32 : SOP1_32 <"s_brev_b32", [(set i32:$sdst, (bitreverse i32:$src0))] >; @@ -191,10 +208,10 @@ def S_SEXT_I32_I16 : SOP1_32 <"s_sext_i32_i16", [(set i32:$sdst, (sext_inreg i32:$src0, i16))] >; -def S_BITSET0_B32 : SOP1_32 <"s_bitset0_b32">; -def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64">; -def S_BITSET1_B32 : SOP1_32 <"s_bitset1_b32">; -def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64">; +def S_BITSET0_B32 : SOP1_32 <"s_bitset0_b32", [], 1>; +def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64", [], 1>; +def S_BITSET1_B32 : SOP1_32 <"s_bitset1_b32", [], 1>; +def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64", [], 1>; def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64", [(set i64:$sdst, (int_amdgcn_s_getpc))] >; @@ -207,7 +224,7 @@ def S_SETPC_B64 : SOP1_1 <"s_setpc_b64">; let isReturn = 1 in { // Define variant marked as return rather than branch. -def S_SETPC_B64_return : SOP1_1<"", [(AMDGPUret_flag i64:$src0)]>; +def S_SETPC_B64_return : SOP1_1<"", CCR_SGPR_64, [(AMDGPUret_flag i64:$src0)]>; } } // End isTerminator = 1, isBarrier = 1 @@ -241,8 +258,11 @@ def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">; def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">; } // End Uses = [M0] +let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in { def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">; def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">; +} // End SubtargetPredicate = isGFX6GFX7GFX8GFX9 + let Defs = [SCC] in { def S_ABS_I32 : SOP1_32 <"s_abs_i32">; } // End Defs = [SCC] @@ -255,7 +275,7 @@ def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> { } } -let SubtargetPredicate = isGFX9 in { +let SubtargetPredicate = isGFX9Plus in { let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in { def S_ANDN1_SAVEEXEC_B64 : SOP1_64<"s_andn1_saveexec_b64">; def S_ORN1_SAVEEXEC_B64 : SOP1_64<"s_orn1_saveexec_b64">; @@ -264,7 +284,28 @@ let SubtargetPredicate = isGFX9 in { } // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] def S_BITREPLICATE_B64_B32 : SOP1_64_32<"s_bitreplicate_b64_b32">; -} // End SubtargetPredicate = isGFX9 +} // End SubtargetPredicate = isGFX9Plus + +let SubtargetPredicate = isGFX10Plus in { + let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in { + def S_AND_SAVEEXEC_B32 : SOP1_32<"s_and_saveexec_b32">; + def S_OR_SAVEEXEC_B32 : SOP1_32<"s_or_saveexec_b32">; + def S_XOR_SAVEEXEC_B32 : SOP1_32<"s_xor_saveexec_b32">; + def S_ANDN2_SAVEEXEC_B32 : SOP1_32<"s_andn2_saveexec_b32">; + def S_ORN2_SAVEEXEC_B32 : SOP1_32<"s_orn2_saveexec_b32">; + def S_NAND_SAVEEXEC_B32 : SOP1_32<"s_nand_saveexec_b32">; + def S_NOR_SAVEEXEC_B32 : SOP1_32<"s_nor_saveexec_b32">; + def S_XNOR_SAVEEXEC_B32 : SOP1_32<"s_xnor_saveexec_b32">; + def S_ANDN1_SAVEEXEC_B32 : SOP1_32<"s_andn1_saveexec_b32">; + def S_ORN1_SAVEEXEC_B32 : SOP1_32<"s_orn1_saveexec_b32">; + def S_ANDN1_WREXEC_B32 : SOP1_32<"s_andn1_wrexec_b32">; + def S_ANDN2_WREXEC_B32 : SOP1_32<"s_andn2_wrexec_b32">; + } // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] + + let Uses = [M0] in { + def S_MOVRELSD_2_B32 : SOP1_32<"s_movrelsd_2_b32">; + } // End Uses = [M0] +} // End SubtargetPredicate = isGFX10Plus //===----------------------------------------------------------------------===// // SOP2 Instructions @@ -302,6 +343,8 @@ class SOP2_Real<bits<7> op, SOP_Pseudo ps> : // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; + let UseNamedOperandTable = ps.UseNamedOperandTable; + let TSFlags = ps.TSFlags; // encoding bits<7> sdst; @@ -468,22 +511,22 @@ let AddedComplexity = 1 in { let Defs = [SCC] in { // TODO: b64 versions require VOP3 change since v_lshlrev_b64 is VOP3 def S_LSHL_B32 : SOP2_32 <"s_lshl_b32", - [(set i32:$sdst, (UniformBinFrag<shl> i32:$src0, i32:$src1))] + [(set SReg_32:$sdst, (shl (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))] >; def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64", - [(set i64:$sdst, (UniformBinFrag<shl> i64:$src0, i32:$src1))] + [(set SReg_64:$sdst, (shl (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))] >; def S_LSHR_B32 : SOP2_32 <"s_lshr_b32", - [(set i32:$sdst, (UniformBinFrag<srl> i32:$src0, i32:$src1))] + [(set SReg_32:$sdst, (srl (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))] >; def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64", - [(set i64:$sdst, (UniformBinFrag<srl> i64:$src0, i32:$src1))] + [(set SReg_64:$sdst, (srl (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))] >; def S_ASHR_I32 : SOP2_32 <"s_ashr_i32", - [(set i32:$sdst, (UniformBinFrag<sra> i32:$src0, i32:$src1))] + [(set SReg_32:$sdst, (sra (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))] >; def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64", - [(set i64:$sdst, (UniformBinFrag<sra> i64:$src0, i32:$src1))] + [(set SReg_64:$sdst, (sra (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))] >; } // End Defs = [SCC] @@ -512,13 +555,14 @@ def S_CBRANCH_G_FORK : SOP2_Pseudo < "$src0, $src1" > { let has_sdst = 0; + let SubtargetPredicate = isGFX6GFX7GFX8GFX9; } let Defs = [SCC] in { def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">; } // End Defs = [SCC] -let SubtargetPredicate = isVI in { +let SubtargetPredicate = isGFX8GFX9 in { def S_RFE_RESTORE_B64 : SOP2_Pseudo < "s_rfe_restore_b64", (outs), (ins SSrc_b64:$src0, SSrc_b32:$src1), @@ -529,7 +573,7 @@ let SubtargetPredicate = isVI in { } } -let SubtargetPredicate = isGFX9 in { +let SubtargetPredicate = isGFX9Plus in { def S_PACK_LL_B32_B16 : SOP2_32<"s_pack_ll_b32_b16">; def S_PACK_LH_B32_B16 : SOP2_32<"s_pack_lh_b32_b16">; def S_PACK_HH_B32_B16 : SOP2_32<"s_pack_hh_b32_b16">; @@ -543,7 +587,7 @@ let SubtargetPredicate = isGFX9 in { def S_MUL_HI_U32 : SOP2_32<"s_mul_hi_u32">; def S_MUL_HI_I32 : SOP2_32<"s_mul_hi_i32">; -} +} // End SubtargetPredicate = isGFX9Plus //===----------------------------------------------------------------------===// // SOPK Instructions @@ -555,7 +599,6 @@ class SOPK_Pseudo <string opName, dag outs, dag ins, SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; - let SubtargetPredicate = isGCN; let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -618,6 +661,19 @@ class SOPK_32 <string opName, list<dag> pattern=[]> : SOPK_Pseudo < "$sdst, $simm16", pattern>; +class SOPK_32_BR <string opName, list<dag> pattern=[]> : SOPK_Pseudo < + opName, + (outs), + (ins sopp_brtarget:$simm16, SReg_32:$sdst), + "$sdst, $simm16", + pattern> { + let Defs = [EXEC]; + let Uses = [EXEC]; + let isBranch = 1; + let isTerminator = 1; + let SchedRW = [WriteBranch]; +} + class SOPK_SCC <string opName, string base_op, bit isSignExt> : SOPK_Pseudo < opName, (outs), @@ -684,9 +740,10 @@ let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0", def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">; } +let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in def S_CBRANCH_I_FORK : SOPK_Pseudo < "s_cbranch_i_fork", - (outs), (ins SReg_64:$sdst, s16imm:$simm16), + (outs), (ins SReg_64:$sdst, sopp_brtarget:$simm16), "$sdst, $simm16" >; @@ -720,15 +777,46 @@ def S_SETREG_IMM32_B32 : SOPK_Pseudo < } // End hasSideEffects = 1 -let SubtargetPredicate = isGFX9 in { +class SOPK_WAITCNT<string opName, list<dag> pat=[]> : + SOPK_Pseudo< + opName, + (outs), + (ins SReg_32:$sdst, s16imm:$simm16), + "$sdst, $simm16", + pat> { + let hasSideEffects = 1; + let mayLoad = 1; + let mayStore = 1; + let has_sdst = 1; // First source takes place of sdst in encoding +} + +let SubtargetPredicate = isGFX9Plus in { def S_CALL_B64 : SOPK_Pseudo< "s_call_b64", (outs SReg_64:$sdst), - (ins s16imm:$simm16), + (ins sopp_brtarget:$simm16), "$sdst, $simm16"> { let isCall = 1; } -} +} // End SubtargetPredicate = isGFX9Plus + +let SubtargetPredicate = isGFX10Plus in { + def S_VERSION : SOPK_Pseudo< + "s_version", + (outs), + (ins s16imm:$simm16), + "$simm16"> { + let has_sdst = 0; + } + + def S_SUBVECTOR_LOOP_BEGIN : SOPK_32_BR<"s_subvector_loop_begin">; + def S_SUBVECTOR_LOOP_END : SOPK_32_BR<"s_subvector_loop_end">; + + def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">; + def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">; + def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">; + def S_WAITCNT_LGKMCNT : SOPK_WAITCNT<"s_waitcnt_lgkmcnt">; +} // End SubtargetPredicate = isGFX10Plus //===----------------------------------------------------------------------===// // SOPC Instructions @@ -756,7 +844,6 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, let Defs = [SCC]; let SchedRW = [WriteSALU]; let UseNamedOperandTable = 1; - let SubtargetPredicate = isGCN; } class SOPC_Base <bits<7> op, RegisterOperand rc0, RegisterOperand rc1, @@ -811,12 +898,13 @@ def S_BITCMP0_B32 : SOPC_32 <0x0c, "s_bitcmp0_b32">; def S_BITCMP1_B32 : SOPC_32 <0x0d, "s_bitcmp1_b32">; def S_BITCMP0_B64 : SOPC_64_32 <0x0e, "s_bitcmp0_b64">; def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">; +let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">; -let SubtargetPredicate = isVI in { +let SubtargetPredicate = isGFX8Plus in { def S_CMP_EQ_U64 : SOPC_CMP_64 <0x12, "s_cmp_eq_u64", COND_EQ>; def S_CMP_LG_U64 : SOPC_CMP_64 <0x13, "s_cmp_lg_u64", COND_NE>; -} +} // End SubtargetPredicate = isGFX8Plus let SubtargetPredicate = HasVGPRIndexMode in { def S_SET_GPR_IDX_ON : SOPC <0x11, @@ -834,6 +922,10 @@ def S_SET_GPR_IDX_ON : SOPC <0x11, // SOPP Instructions //===----------------------------------------------------------------------===// +class Base_SOPP <string asm> { + string AsmString = asm; +} + class SOPPe <bits<7> op> : Enc32 { bits <16> simm16; @@ -843,7 +935,7 @@ class SOPPe <bits<7> op> : Enc32 { } class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> : - InstSI <(outs), ins, asm, pattern >, SOPPe <op> { + InstSI <(outs), ins, asm, pattern >, SOPPe <op>, Base_SOPP <asm> { let mayLoad = 0; let mayStore = 0; @@ -854,92 +946,124 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> : let SchedRW = [WriteSALU]; let UseNamedOperandTable = 1; - let SubtargetPredicate = isGCN; } - def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">; +class SOPP_w_nop_e <bits<7> op> : Enc64 { + bits <16> simm16; + + let Inst{15-0} = simm16; + let Inst{22-16} = op; + let Inst{31-23} = 0x17f; // encoding + let Inst{47-32} = 0x0; + let Inst{54-48} = S_NOP.Inst{22-16}; // opcode + let Inst{63-55} = S_NOP.Inst{31-23}; // encoding +} + +class SOPP_w_nop <bits<7> op, dag ins, string asm, list<dag> pattern = []> : + InstSI <(outs), ins, asm, pattern >, SOPP_w_nop_e <op>, Base_SOPP <asm> { + + let mayLoad = 0; + let mayStore = 0; + let hasSideEffects = 0; + let SALU = 1; + let SOPP = 1; + let Size = 8; + let SchedRW = [WriteSALU]; + + let UseNamedOperandTable = 1; +} + +multiclass SOPP_With_Relaxation <bits<7> op, dag ins, string asm, list<dag> pattern = []> { + def "" : SOPP <op, ins, asm, pattern>; + def _pad_s_nop : SOPP_w_nop <op, ins, asm, pattern>; +} + let isTerminator = 1 in { -def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", - [(AMDGPUendpgm)]> { - let simm16 = 0; +def S_ENDPGM : SOPP <0x00000001, (ins EndpgmImm:$simm16), "s_endpgm$simm16"> { let isBarrier = 1; let isReturn = 1; } -let SubtargetPredicate = isVI in { def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> { + let SubtargetPredicate = isGFX8Plus; let simm16 = 0; let isBarrier = 1; let isReturn = 1; } -} -let SubtargetPredicate = isGFX9 in { +let SubtargetPredicate = isGFX9Plus in { let isBarrier = 1, isReturn = 1, simm16 = 0 in { def S_ENDPGM_ORDERED_PS_DONE : SOPP<0x01e, (ins), "s_endpgm_ordered_ps_done">; } // End isBarrier = 1, isReturn = 1, simm16 = 0 -} // End SubtargetPredicate = isGFX9 +} // End SubtargetPredicate = isGFX9Plus + +let SubtargetPredicate = isGFX10Plus in { + let isBarrier = 1, isReturn = 1, simm16 = 0 in { + def S_CODE_END : + SOPP<0x01f, (ins), "s_code_end">; + } // End isBarrier = 1, isReturn = 1, simm16 = 0 +} // End SubtargetPredicate = isGFX10Plus let isBranch = 1, SchedRW = [WriteBranch] in { -def S_BRANCH : SOPP < +let isBarrier = 1 in { +defm S_BRANCH : SOPP_With_Relaxation < 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", - [(br bb:$simm16)]> { - let isBarrier = 1; + [(br bb:$simm16)]>; } let Uses = [SCC] in { -def S_CBRANCH_SCC0 : SOPP < +defm S_CBRANCH_SCC0 : SOPP_With_Relaxation < 0x00000004, (ins sopp_brtarget:$simm16), "s_cbranch_scc0 $simm16" >; -def S_CBRANCH_SCC1 : SOPP < +defm S_CBRANCH_SCC1 : SOPP_With_Relaxation < 0x00000005, (ins sopp_brtarget:$simm16), "s_cbranch_scc1 $simm16" >; } // End Uses = [SCC] let Uses = [VCC] in { -def S_CBRANCH_VCCZ : SOPP < +defm S_CBRANCH_VCCZ : SOPP_With_Relaxation < 0x00000006, (ins sopp_brtarget:$simm16), "s_cbranch_vccz $simm16" >; -def S_CBRANCH_VCCNZ : SOPP < +defm S_CBRANCH_VCCNZ : SOPP_With_Relaxation < 0x00000007, (ins sopp_brtarget:$simm16), "s_cbranch_vccnz $simm16" >; } // End Uses = [VCC] let Uses = [EXEC] in { -def S_CBRANCH_EXECZ : SOPP < +defm S_CBRANCH_EXECZ : SOPP_With_Relaxation < 0x00000008, (ins sopp_brtarget:$simm16), "s_cbranch_execz $simm16" >; -def S_CBRANCH_EXECNZ : SOPP < +defm S_CBRANCH_EXECNZ : SOPP_With_Relaxation < 0x00000009, (ins sopp_brtarget:$simm16), "s_cbranch_execnz $simm16" >; } // End Uses = [EXEC] -def S_CBRANCH_CDBGSYS : SOPP < +defm S_CBRANCH_CDBGSYS : SOPP_With_Relaxation < 0x00000017, (ins sopp_brtarget:$simm16), "s_cbranch_cdbgsys $simm16" >; -def S_CBRANCH_CDBGSYS_AND_USER : SOPP < +defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_With_Relaxation < 0x0000001A, (ins sopp_brtarget:$simm16), "s_cbranch_cdbgsys_and_user $simm16" >; -def S_CBRANCH_CDBGSYS_OR_USER : SOPP < +defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_With_Relaxation < 0x00000019, (ins sopp_brtarget:$simm16), "s_cbranch_cdbgsys_or_user $simm16" >; -def S_CBRANCH_CDBGUSER : SOPP < +defm S_CBRANCH_CDBGUSER : SOPP_With_Relaxation < 0x00000018, (ins sopp_brtarget:$simm16), "s_cbranch_cdbguser $simm16" >; @@ -957,16 +1081,16 @@ def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier", let isConvergent = 1; } -let SubtargetPredicate = isVI in { def S_WAKEUP : SOPP <0x00000003, (ins), "s_wakeup"> { + let SubtargetPredicate = isGFX8Plus; let simm16 = 0; let mayLoad = 1; let mayStore = 1; } -} let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in -def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">; +def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16", + [(int_amdgcn_s_waitcnt UIMM16bit:$simm16)]>; def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">; def S_SETKILL : SOPP <0x0000000b, (ins i16imm:$simm16), "s_setkill $simm16">; @@ -994,7 +1118,10 @@ def S_SENDMSGHALT : SOPP <0x00000011, (ins SendMsgImm:$simm16), "s_sendmsghalt $ >; } // End Uses = [EXEC, M0] -def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">; +def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16"> { + let isTrap = 1; +} + def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> { let simm16 = 0; } @@ -1028,6 +1155,25 @@ def S_SET_GPR_IDX_MODE : SOPP<0x1d, (ins GPRIdxMode:$simm16), } } +let SubtargetPredicate = isGFX10Plus in { + def S_INST_PREFETCH : + SOPP<0x020, (ins s16imm:$simm16), "s_inst_prefetch $simm16">; + def S_CLAUSE : + SOPP<0x021, (ins s16imm:$simm16), "s_clause $simm16">; + def S_WAITCNT_IDLE : + SOPP <0x022, (ins), "s_wait_idle"> { + let simm16 = 0; + } + def S_WAITCNT_DEPCTR : + SOPP <0x023, (ins s16imm:$simm16), "s_waitcnt_depctr $simm16">; + def S_ROUND_MODE : + SOPP<0x024, (ins s16imm:$simm16), "s_round_mode $simm16">; + def S_DENORM_MODE : + SOPP<0x025, (ins s16imm:$simm16), "s_denorm_mode $simm16">; + def S_TTRACEDATA_IMM : + SOPP<0x028, (ins s16imm:$simm16), "s_ttracedata_imm $simm16">; +} // End SubtargetPredicate = isGFX10Plus + //===----------------------------------------------------------------------===// // S_GETREG_B32 Intrinsic Pattern. //===----------------------------------------------------------------------===// @@ -1041,6 +1187,11 @@ def : GCNPat < //===----------------------------------------------------------------------===// def : GCNPat < + (AMDGPUendpgm), + (S_ENDPGM (i16 0)) +>; + +def : GCNPat < (i64 (ctpop i64:$src)), (i64 (REG_SEQUENCE SReg_64, (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0, @@ -1097,162 +1248,261 @@ def : GCNPat< >; +//===----------------------------------------------------------------------===// +// Target-specific instruction encodings. +//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// SOPP Patterns +// SOP1 - GFX10. //===----------------------------------------------------------------------===// -def : GCNPat < - (int_amdgcn_s_waitcnt i32:$simm16), - (S_WAITCNT (as_i16imm $simm16)) ->; +class Select_gfx10<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX10> { + Predicate AssemblerPredicate = isGFX10Plus; + string DecoderNamespace = "GFX10"; +} + +multiclass SOP1_Real_gfx10<bits<8> op> { + def _gfx10 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>, + Select_gfx10<!cast<SOP1_Pseudo>(NAME).Mnemonic>; +} +defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x037>; +defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x038>; +defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>; +defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>; +defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>; +defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03c>; +defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03d>; +defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03e>; +defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03f>; +defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x040>; +defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x041>; +defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x042>; +defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x043>; +defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x044>; +defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x045>; +defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx10<0x046>; +defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx10<0x047>; +defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>; //===----------------------------------------------------------------------===// -// Real target instructions, move this to the appropriate subtarget TD file +// SOP1 - GFX6, GFX7. //===----------------------------------------------------------------------===// -class Select_si<string opName> : - SIMCInstr<opName, SIEncodingFamily.SI> { - list<Predicate> AssemblerPredicates = [isSICI]; - string DecoderNamespace = "SICI"; +class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> { + Predicate AssemblerPredicate = isGFX6GFX7; + string DecoderNamespace = "GFX6GFX7"; } -class SOP1_Real_si<bits<8> op, SOP1_Pseudo ps> : - SOP1_Real<op, ps>, - Select_si<ps.Mnemonic>; +multiclass SOP1_Real_gfx6_gfx7<bits<8> op> { + def _gfx6_gfx7 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>, + Select_gfx6_gfx7<!cast<SOP1_Pseudo>(NAME).Mnemonic>; +} -class SOP2_Real_si<bits<7> op, SOP2_Pseudo ps> : - SOP2_Real<op, ps>, - Select_si<ps.Mnemonic>; +multiclass SOP1_Real_gfx6_gfx7_gfx10<bits<8> op> : + SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10<op>; + +defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>; +defm S_MOV_REGRD_B32 : SOP1_Real_gfx6_gfx7<0x033>; + +defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x003>; +defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x004>; +defm S_CMOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x005>; +defm S_CMOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x006>; +defm S_NOT_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x007>; +defm S_NOT_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x008>; +defm S_WQM_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x009>; +defm S_WQM_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00a>; +defm S_BREV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00b>; +defm S_BREV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00c>; +defm S_BCNT0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00d>; +defm S_BCNT0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00e>; +defm S_BCNT1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00f>; +defm S_BCNT1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x010>; +defm S_FF0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x011>; +defm S_FF0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x012>; +defm S_FF1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x013>; +defm S_FF1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x014>; +defm S_FLBIT_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x015>; +defm S_FLBIT_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x016>; +defm S_FLBIT_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x017>; +defm S_FLBIT_I32_I64 : SOP1_Real_gfx6_gfx7_gfx10<0x018>; +defm S_SEXT_I32_I8 : SOP1_Real_gfx6_gfx7_gfx10<0x019>; +defm S_SEXT_I32_I16 : SOP1_Real_gfx6_gfx7_gfx10<0x01a>; +defm S_BITSET0_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01b>; +defm S_BITSET0_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01c>; +defm S_BITSET1_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01d>; +defm S_BITSET1_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01e>; +defm S_GETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01f>; +defm S_SETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x020>; +defm S_SWAPPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x021>; +defm S_RFE_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x022>; +defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x024>; +defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x025>; +defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x026>; +defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x027>; +defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x028>; +defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x029>; +defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02a>; +defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02b>; +defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02c>; +defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02d>; +defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02e>; +defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02f>; +defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x030>; +defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>; +defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; +defm S_MOV_FED_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x035>; -class SOPK_Real_si<bits<5> op, SOPK_Pseudo ps> : - SOPK_Real32<op, ps>, - Select_si<ps.Mnemonic>; - -def S_MOV_B32_si : SOP1_Real_si <0x03, S_MOV_B32>; -def S_MOV_B64_si : SOP1_Real_si <0x04, S_MOV_B64>; -def S_CMOV_B32_si : SOP1_Real_si <0x05, S_CMOV_B32>; -def S_CMOV_B64_si : SOP1_Real_si <0x06, S_CMOV_B64>; -def S_NOT_B32_si : SOP1_Real_si <0x07, S_NOT_B32>; -def S_NOT_B64_si : SOP1_Real_si <0x08, S_NOT_B64>; -def S_WQM_B32_si : SOP1_Real_si <0x09, S_WQM_B32>; -def S_WQM_B64_si : SOP1_Real_si <0x0a, S_WQM_B64>; -def S_BREV_B32_si : SOP1_Real_si <0x0b, S_BREV_B32>; -def S_BREV_B64_si : SOP1_Real_si <0x0c, S_BREV_B64>; -def S_BCNT0_I32_B32_si : SOP1_Real_si <0x0d, S_BCNT0_I32_B32>; -def S_BCNT0_I32_B64_si : SOP1_Real_si <0x0e, S_BCNT0_I32_B64>; -def S_BCNT1_I32_B32_si : SOP1_Real_si <0x0f, S_BCNT1_I32_B32>; -def S_BCNT1_I32_B64_si : SOP1_Real_si <0x10, S_BCNT1_I32_B64>; -def S_FF0_I32_B32_si : SOP1_Real_si <0x11, S_FF0_I32_B32>; -def S_FF0_I32_B64_si : SOP1_Real_si <0x12, S_FF0_I32_B64>; -def S_FF1_I32_B32_si : SOP1_Real_si <0x13, S_FF1_I32_B32>; -def S_FF1_I32_B64_si : SOP1_Real_si <0x14, S_FF1_I32_B64>; -def S_FLBIT_I32_B32_si : SOP1_Real_si <0x15, S_FLBIT_I32_B32>; -def S_FLBIT_I32_B64_si : SOP1_Real_si <0x16, S_FLBIT_I32_B64>; -def S_FLBIT_I32_si : SOP1_Real_si <0x17, S_FLBIT_I32>; -def S_FLBIT_I32_I64_si : SOP1_Real_si <0x18, S_FLBIT_I32_I64>; -def S_SEXT_I32_I8_si : SOP1_Real_si <0x19, S_SEXT_I32_I8>; -def S_SEXT_I32_I16_si : SOP1_Real_si <0x1a, S_SEXT_I32_I16>; -def S_BITSET0_B32_si : SOP1_Real_si <0x1b, S_BITSET0_B32>; -def S_BITSET0_B64_si : SOP1_Real_si <0x1c, S_BITSET0_B64>; -def S_BITSET1_B32_si : SOP1_Real_si <0x1d, S_BITSET1_B32>; -def S_BITSET1_B64_si : SOP1_Real_si <0x1e, S_BITSET1_B64>; -def S_GETPC_B64_si : SOP1_Real_si <0x1f, S_GETPC_B64>; -def S_SETPC_B64_si : SOP1_Real_si <0x20, S_SETPC_B64>; -def S_SWAPPC_B64_si : SOP1_Real_si <0x21, S_SWAPPC_B64>; -def S_RFE_B64_si : SOP1_Real_si <0x22, S_RFE_B64>; -def S_AND_SAVEEXEC_B64_si : SOP1_Real_si <0x24, S_AND_SAVEEXEC_B64>; -def S_OR_SAVEEXEC_B64_si : SOP1_Real_si <0x25, S_OR_SAVEEXEC_B64>; -def S_XOR_SAVEEXEC_B64_si : SOP1_Real_si <0x26, S_XOR_SAVEEXEC_B64>; -def S_ANDN2_SAVEEXEC_B64_si: SOP1_Real_si <0x27, S_ANDN2_SAVEEXEC_B64>; -def S_ORN2_SAVEEXEC_B64_si : SOP1_Real_si <0x28, S_ORN2_SAVEEXEC_B64>; -def S_NAND_SAVEEXEC_B64_si : SOP1_Real_si <0x29, S_NAND_SAVEEXEC_B64>; -def S_NOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2a, S_NOR_SAVEEXEC_B64>; -def S_XNOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2b, S_XNOR_SAVEEXEC_B64>; -def S_QUADMASK_B32_si : SOP1_Real_si <0x2c, S_QUADMASK_B32>; -def S_QUADMASK_B64_si : SOP1_Real_si <0x2d, S_QUADMASK_B64>; -def S_MOVRELS_B32_si : SOP1_Real_si <0x2e, S_MOVRELS_B32>; -def S_MOVRELS_B64_si : SOP1_Real_si <0x2f, S_MOVRELS_B64>; -def S_MOVRELD_B32_si : SOP1_Real_si <0x30, S_MOVRELD_B32>; -def S_MOVRELD_B64_si : SOP1_Real_si <0x31, S_MOVRELD_B64>; -def S_CBRANCH_JOIN_si : SOP1_Real_si <0x32, S_CBRANCH_JOIN>; -def S_MOV_REGRD_B32_si : SOP1_Real_si <0x33, S_MOV_REGRD_B32>; -def S_ABS_I32_si : SOP1_Real_si <0x34, S_ABS_I32>; -def S_MOV_FED_B32_si : SOP1_Real_si <0x35, S_MOV_FED_B32>; - -def S_ADD_U32_si : SOP2_Real_si <0x00, S_ADD_U32>; -def S_ADD_I32_si : SOP2_Real_si <0x02, S_ADD_I32>; -def S_SUB_U32_si : SOP2_Real_si <0x01, S_SUB_U32>; -def S_SUB_I32_si : SOP2_Real_si <0x03, S_SUB_I32>; -def S_ADDC_U32_si : SOP2_Real_si <0x04, S_ADDC_U32>; -def S_SUBB_U32_si : SOP2_Real_si <0x05, S_SUBB_U32>; -def S_MIN_I32_si : SOP2_Real_si <0x06, S_MIN_I32>; -def S_MIN_U32_si : SOP2_Real_si <0x07, S_MIN_U32>; -def S_MAX_I32_si : SOP2_Real_si <0x08, S_MAX_I32>; -def S_MAX_U32_si : SOP2_Real_si <0x09, S_MAX_U32>; -def S_CSELECT_B32_si : SOP2_Real_si <0x0a, S_CSELECT_B32>; -def S_CSELECT_B64_si : SOP2_Real_si <0x0b, S_CSELECT_B64>; -def S_AND_B32_si : SOP2_Real_si <0x0e, S_AND_B32>; -def S_AND_B64_si : SOP2_Real_si <0x0f, S_AND_B64>; -def S_OR_B32_si : SOP2_Real_si <0x10, S_OR_B32>; -def S_OR_B64_si : SOP2_Real_si <0x11, S_OR_B64>; -def S_XOR_B32_si : SOP2_Real_si <0x12, S_XOR_B32>; -def S_XOR_B64_si : SOP2_Real_si <0x13, S_XOR_B64>; -def S_ANDN2_B32_si : SOP2_Real_si <0x14, S_ANDN2_B32>; -def S_ANDN2_B64_si : SOP2_Real_si <0x15, S_ANDN2_B64>; -def S_ORN2_B32_si : SOP2_Real_si <0x16, S_ORN2_B32>; -def S_ORN2_B64_si : SOP2_Real_si <0x17, S_ORN2_B64>; -def S_NAND_B32_si : SOP2_Real_si <0x18, S_NAND_B32>; -def S_NAND_B64_si : SOP2_Real_si <0x19, S_NAND_B64>; -def S_NOR_B32_si : SOP2_Real_si <0x1a, S_NOR_B32>; -def S_NOR_B64_si : SOP2_Real_si <0x1b, S_NOR_B64>; -def S_XNOR_B32_si : SOP2_Real_si <0x1c, S_XNOR_B32>; -def S_XNOR_B64_si : SOP2_Real_si <0x1d, S_XNOR_B64>; -def S_LSHL_B32_si : SOP2_Real_si <0x1e, S_LSHL_B32>; -def S_LSHL_B64_si : SOP2_Real_si <0x1f, S_LSHL_B64>; -def S_LSHR_B32_si : SOP2_Real_si <0x20, S_LSHR_B32>; -def S_LSHR_B64_si : SOP2_Real_si <0x21, S_LSHR_B64>; -def S_ASHR_I32_si : SOP2_Real_si <0x22, S_ASHR_I32>; -def S_ASHR_I64_si : SOP2_Real_si <0x23, S_ASHR_I64>; -def S_BFM_B32_si : SOP2_Real_si <0x24, S_BFM_B32>; -def S_BFM_B64_si : SOP2_Real_si <0x25, S_BFM_B64>; -def S_MUL_I32_si : SOP2_Real_si <0x26, S_MUL_I32>; -def S_BFE_U32_si : SOP2_Real_si <0x27, S_BFE_U32>; -def S_BFE_I32_si : SOP2_Real_si <0x28, S_BFE_I32>; -def S_BFE_U64_si : SOP2_Real_si <0x29, S_BFE_U64>; -def S_BFE_I64_si : SOP2_Real_si <0x2a, S_BFE_I64>; -def S_CBRANCH_G_FORK_si : SOP2_Real_si <0x2b, S_CBRANCH_G_FORK>; -def S_ABSDIFF_I32_si : SOP2_Real_si <0x2c, S_ABSDIFF_I32>; - -def S_MOVK_I32_si : SOPK_Real_si <0x00, S_MOVK_I32>; -def S_CMOVK_I32_si : SOPK_Real_si <0x02, S_CMOVK_I32>; -def S_CMPK_EQ_I32_si : SOPK_Real_si <0x03, S_CMPK_EQ_I32>; -def S_CMPK_LG_I32_si : SOPK_Real_si <0x04, S_CMPK_LG_I32>; -def S_CMPK_GT_I32_si : SOPK_Real_si <0x05, S_CMPK_GT_I32>; -def S_CMPK_GE_I32_si : SOPK_Real_si <0x06, S_CMPK_GE_I32>; -def S_CMPK_LT_I32_si : SOPK_Real_si <0x07, S_CMPK_LT_I32>; -def S_CMPK_LE_I32_si : SOPK_Real_si <0x08, S_CMPK_LE_I32>; -def S_CMPK_EQ_U32_si : SOPK_Real_si <0x09, S_CMPK_EQ_U32>; -def S_CMPK_LG_U32_si : SOPK_Real_si <0x0a, S_CMPK_LG_U32>; -def S_CMPK_GT_U32_si : SOPK_Real_si <0x0b, S_CMPK_GT_U32>; -def S_CMPK_GE_U32_si : SOPK_Real_si <0x0c, S_CMPK_GE_U32>; -def S_CMPK_LT_U32_si : SOPK_Real_si <0x0d, S_CMPK_LT_U32>; -def S_CMPK_LE_U32_si : SOPK_Real_si <0x0e, S_CMPK_LE_U32>; -def S_ADDK_I32_si : SOPK_Real_si <0x0f, S_ADDK_I32>; -def S_MULK_I32_si : SOPK_Real_si <0x10, S_MULK_I32>; -def S_CBRANCH_I_FORK_si : SOPK_Real_si <0x11, S_CBRANCH_I_FORK>; -def S_GETREG_B32_si : SOPK_Real_si <0x12, S_GETREG_B32>; -def S_SETREG_B32_si : SOPK_Real_si <0x13, S_SETREG_B32>; -//def S_GETREG_REGRD_B32_si : SOPK_Real_si <0x14, S_GETREG_REGRD_B32>; // see pseudo for comments -def S_SETREG_IMM32_B32_si : SOPK_Real64<0x15, S_SETREG_IMM32_B32>, - Select_si<S_SETREG_IMM32_B32.Mnemonic>; +//===----------------------------------------------------------------------===// +// SOP2 - GFX10. +//===----------------------------------------------------------------------===// + +multiclass SOP2_Real_gfx10<bits<7> op> { + def _gfx10 : SOP2_Real<op, !cast<SOP2_Pseudo>(NAME)>, + Select_gfx10<!cast<SOP2_Pseudo>(NAME).Mnemonic>; +} + +defm S_LSHL1_ADD_U32 : SOP2_Real_gfx10<0x02e>; +defm S_LSHL2_ADD_U32 : SOP2_Real_gfx10<0x02f>; +defm S_LSHL3_ADD_U32 : SOP2_Real_gfx10<0x030>; +defm S_LSHL4_ADD_U32 : SOP2_Real_gfx10<0x031>; +defm S_PACK_LL_B32_B16 : SOP2_Real_gfx10<0x032>; +defm S_PACK_LH_B32_B16 : SOP2_Real_gfx10<0x033>; +defm S_PACK_HH_B32_B16 : SOP2_Real_gfx10<0x034>; +defm S_MUL_HI_U32 : SOP2_Real_gfx10<0x035>; +defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>; + +//===----------------------------------------------------------------------===// +// SOP2 - GFX6, GFX7. +//===----------------------------------------------------------------------===// +multiclass SOP2_Real_gfx6_gfx7<bits<7> op> { + def _gfx6_gfx7 : SOP2_Real<op, !cast<SOP_Pseudo>(NAME)>, + Select_gfx6_gfx7<!cast<SOP_Pseudo>(NAME).Mnemonic>; +} + +multiclass SOP2_Real_gfx6_gfx7_gfx10<bits<7> op> : + SOP2_Real_gfx6_gfx7<op>, SOP2_Real_gfx10<op>; + +defm S_CBRANCH_G_FORK : SOP2_Real_gfx6_gfx7<0x02b>; + +defm S_ADD_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x000>; +defm S_SUB_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x001>; +defm S_ADD_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x002>; +defm S_SUB_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x003>; +defm S_ADDC_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x004>; +defm S_SUBB_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x005>; +defm S_MIN_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x006>; +defm S_MIN_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x007>; +defm S_MAX_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x008>; +defm S_MAX_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x009>; +defm S_CSELECT_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00a>; +defm S_CSELECT_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00b>; +defm S_AND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00e>; +defm S_AND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00f>; +defm S_OR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x010>; +defm S_OR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x011>; +defm S_XOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x012>; +defm S_XOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x013>; +defm S_ANDN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x014>; +defm S_ANDN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x015>; +defm S_ORN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x016>; +defm S_ORN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x017>; +defm S_NAND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x018>; +defm S_NAND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x019>; +defm S_NOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01a>; +defm S_NOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01b>; +defm S_XNOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01c>; +defm S_XNOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01d>; +defm S_LSHL_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01e>; +defm S_LSHL_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01f>; +defm S_LSHR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x020>; +defm S_LSHR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x021>; +defm S_ASHR_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x022>; +defm S_ASHR_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x023>; +defm S_BFM_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x024>; +defm S_BFM_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x025>; +defm S_MUL_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x026>; +defm S_BFE_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x027>; +defm S_BFE_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x028>; +defm S_BFE_U64 : SOP2_Real_gfx6_gfx7_gfx10<0x029>; +defm S_BFE_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x02a>; +defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX10. +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx10<bits<5> op> { + def _gfx10 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>, + Select_gfx10<!cast<SOPK_Pseudo>(NAME).Mnemonic>; +} + +multiclass SOPK_Real64_gfx10<bits<5> op> { + def _gfx10 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>, + Select_gfx10<!cast<SOPK_Pseudo>(NAME).Mnemonic>; +} + +defm S_VERSION : SOPK_Real32_gfx10<0x001>; +defm S_CALL_B64 : SOPK_Real32_gfx10<0x016>; +defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>; +defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>; +defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>; +defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>; +defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>; +defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX6, GFX7. +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx6_gfx7<bits<5> op> { + def _gfx6_gfx7 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>, + Select_gfx6_gfx7<!cast<SOPK_Pseudo>(NAME).Mnemonic>; +} + +multiclass SOPK_Real64_gfx6_gfx7<bits<5> op> { + def _gfx6_gfx7 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>, + Select_gfx6_gfx7<!cast<SOPK_Pseudo>(NAME).Mnemonic>; +} + +multiclass SOPK_Real32_gfx6_gfx7_gfx10<bits<5> op> : + SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10<op>; + +multiclass SOPK_Real64_gfx6_gfx7_gfx10<bits<5> op> : + SOPK_Real64_gfx6_gfx7<op>, SOPK_Real64_gfx10<op>; + +defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>; + +defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x000>; +defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x002>; +defm S_CMPK_EQ_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x003>; +defm S_CMPK_LG_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x004>; +defm S_CMPK_GT_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x005>; +defm S_CMPK_GE_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x006>; +defm S_CMPK_LT_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x007>; +defm S_CMPK_LE_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x008>; +defm S_CMPK_EQ_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x009>; +defm S_CMPK_LG_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00a>; +defm S_CMPK_GT_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00b>; +defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00c>; +defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00d>; +defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00e>; +defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00f>; +defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x010>; +defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>; +defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>; +defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>; + +//===----------------------------------------------------------------------===// +// GFX8, GFX9 (VI). +//===----------------------------------------------------------------------===// class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> { - list<Predicate> AssemblerPredicates = [isVI]; - string DecoderNamespace = "VI"; + list<Predicate> AssemblerPredicates = [isGFX8GFX9]; + string DecoderNamespace = "GFX8"; } class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> : |