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path: root/lib/Target/ARC/ARCISelLowering.cpp
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Diffstat (limited to 'lib/Target/ARC/ARCISelLowering.cpp')
-rw-r--r--lib/Target/ARC/ARCISelLowering.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARC/ARCISelLowering.cpp b/lib/Target/ARC/ARCISelLowering.cpp
index 5991838a15c4..bf98af801406 100644
--- a/lib/Target/ARC/ARCISelLowering.cpp
+++ b/lib/Target/ARC/ARCISelLowering.cpp
@@ -72,7 +72,7 @@ static ARCCC::CondCode ISDCCtoARCCC(ISD::CondCode isdCC) {
ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
const ARCSubtarget &Subtarget)
- : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
+ : TargetLowering(TM), Subtarget(Subtarget) {
// Set up the register classes.
addRegisterClass(MVT::i32, &ARC::GPR32RegClass);
@@ -486,8 +486,8 @@ SDValue ARCTargetLowering::LowerCallArguments(
EVT RegVT = VA.getLocVT();
switch (RegVT.getSimpleVT().SimpleTy) {
default: {
- DEBUG(errs() << "LowerFormalArguments Unhandled argument type: "
- << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n");
+ LLVM_DEBUG(errs() << "LowerFormalArguments Unhandled argument type: "
+ << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n");
llvm_unreachable("Unhandled LowerFormalArguments type.");
}
case MVT::i32: