diff options
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 17 | 
1 files changed, 14 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index c429ac185211..fda3e815624d 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -567,10 +567,21 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,        //   MOV  NewBase, Base        //   ADDS NewBase, #imm8.        if (Base != NewBase && Offset >= 8) { +        const ARMSubtarget &Subtarget = MBB.getParent()->getTarget() +                       .getSubtarget<ARMSubtarget>();          // Need to insert a MOV to the new base first. -        BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase) -          .addReg(Base, getKillRegState(BaseKill)) -          .addImm(Pred).addReg(PredReg); +        if (isARMLowRegister(NewBase) && isARMLowRegister(Base) && +            !Subtarget.hasV6Ops()) { +          // thumbv4t doesn't have lo->lo copies, and we can't predicate tMOVSr +          if (Pred != ARMCC::AL) +            return false; +          BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVSr), NewBase) +            .addReg(Base, getKillRegState(BaseKill)); +        } else +          BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase) +            .addReg(Base, getKillRegState(BaseKill)) +            .addImm(Pred).addReg(PredReg); +          // Set up BaseKill and Base correctly to insert the ADDS/SUBS below.          Base = NewBase;          BaseKill = false;  | 
