diff options
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.h')
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 79 |
1 files changed, 38 insertions, 41 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index f8283b08d485..dbacd4d6aada 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -11,21 +11,19 @@ // //===----------------------------------------------------------------------===// -#ifndef ARMSUBTARGET_H -#define ARMSUBTARGET_H +#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H +#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H #include "ARMFrameLowering.h" #include "ARMISelLowering.h" #include "ARMInstrInfo.h" -#include "ARMJITInfo.h" #include "ARMSelectionDAGInfo.h" #include "ARMSubtarget.h" +#include "MCTargetDesc/ARMMCTargetDesc.h" #include "Thumb1FrameLowering.h" #include "Thumb1InstrInfo.h" #include "Thumb2InstrInfo.h" -#include "ARMJITInfo.h" -#include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/ADT/Triple.h" #include "llvm/IR/DataLayout.h" #include "llvm/MC/MCInstrItineraries.h" @@ -39,12 +37,13 @@ namespace llvm { class GlobalValue; class StringRef; class TargetOptions; +class ARMBaseTargetMachine; class ARMSubtarget : public ARMGenSubtargetInfo { protected: enum ARMProcFamilyEnum { Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, - CortexR5, Swift, CortexA53, CortexA57, Krait + CortexA17, CortexR5, Swift, CortexA53, CortexA57, Krait, }; enum ARMProcClassEnum { None, AClass, RClass, MClass @@ -188,7 +187,7 @@ protected: /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory /// accesses for some types. For details, see - /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). + /// ARMTargetLowering::allowsMisalignedMemoryAccesses(). bool AllowsUnalignedMem; /// RestrictIT - If true, the subtarget disallows generation of deprecated IT @@ -219,7 +218,7 @@ protected: Triple TargetTriple; /// SchedModel - Processor specific instruction costs. - const MCSchedModel *SchedModel; + MCSchedModel SchedModel; /// Selected instruction itineraries (one entry per itinerary class.) InstrItineraryData InstrItins; @@ -227,19 +226,14 @@ protected: /// Options passed via command line that could influence the target const TargetOptions &Options; - public: - enum { - ARM_ABI_UNKNOWN, - ARM_ABI_APCS, - ARM_ABI_AAPCS // ARM EABI - } TargetABI; + const ARMBaseTargetMachine &TM; +public: /// This constructor initializes the data members to match that /// of the specified triple. /// ARMSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, TargetMachine &TM, bool IsLittle, - const TargetOptions &Options); + const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle); /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. @@ -250,27 +244,30 @@ protected: /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); - /// \brief Reset the features for the ARM target. - void resetSubtargetFeatures(const MachineFunction *MF) override; - /// initializeSubtargetDependencies - Initializes using a CPU and feature string /// so that we can use initializer lists for subtarget initialization. ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); - const DataLayout *getDataLayout() const { return &DL; } - const ARMSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } - ARMJITInfo *getJITInfo() { return &JITInfo; } - const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo.get(); } - const ARMTargetLowering *getTargetLowering() const { return &TLInfo; } - const ARMFrameLowering *getFrameLowering() const { return FrameLowering.get(); } - const ARMBaseRegisterInfo *getRegisterInfo() const { + const DataLayout *getDataLayout() const override { return &DL; } + const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { + return &TSInfo; + } + const ARMBaseInstrInfo *getInstrInfo() const override { + return InstrInfo.get(); + } + const ARMTargetLowering *getTargetLowering() const override { + return &TLInfo; + } + const ARMFrameLowering *getFrameLowering() const override { + return FrameLowering.get(); + } + const ARMBaseRegisterInfo *getRegisterInfo() const override { return &InstrInfo->getRegisterInfo(); } private: const DataLayout DL; ARMSelectionDAGInfo TSInfo; - ARMJITInfo JITInfo; // Either Thumb1InstrInfo or Thumb2InstrInfo. std::unique_ptr<ARMBaseInstrInfo> InstrInfo; ARMTargetLowering TLInfo; @@ -278,7 +275,7 @@ private: std::unique_ptr<ARMFrameLowering> FrameLowering; void initializeEnvironment(); - void resetSubtargetFeatures(StringRef CPU, StringRef FS); + void initSubtargetFeatures(StringRef CPU, StringRef FS); public: void computeIssueWidth(); @@ -347,7 +344,7 @@ public: bool isTargetIOS() const { return TargetTriple.isiOS(); } bool isTargetLinux() const { return TargetTriple.isOSLinux(); } bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } - bool isTargetNetBSD() const { return TargetTriple.getOS() == Triple::NetBSD; } + bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } bool isTargetWindows() const { return TargetTriple.isOSWindows(); } bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } @@ -388,14 +385,8 @@ public: return TargetTriple.getEnvironment() == Triple::Android; } - bool isAPCS_ABI() const { - assert(TargetABI != ARM_ABI_UNKNOWN); - return TargetABI == ARM_ABI_APCS; - } - bool isAAPCS_ABI() const { - assert(TargetABI != ARM_ABI_UNKNOWN); - return TargetABI == ARM_ABI_AAPCS; - } + bool isAPCS_ABI() const; + bool isAAPCS_ABI() const; bool isThumb() const { return InThumbMode; } bool isThumb1Only() const { return InThumbMode && !HasThumb2; } @@ -405,6 +396,10 @@ public: bool isRClass() const { return ARMProcClass == RClass; } bool isAClass() const { return ARMProcClass == AClass; } + bool isV6M() const { + return isThumb1Only() && isMClass(); + } + bool isR9Reserved() const { return IsR9Reserved; } bool useMovt(const MachineFunction &MF) const; @@ -428,12 +423,14 @@ public: /// True for some subtargets at > -O0. bool enablePostMachineScheduler() const override; - // enableAtomicExpandLoadLinked - True if we need to expand our atomics. - bool enableAtomicExpandLoadLinked() const override; + // enableAtomicExpand- True if we need to expand our atomics. + bool enableAtomicExpand() const override; - /// getInstrItins - Return the instruction itineraies based on subtarget + /// getInstrItins - Return the instruction itineraries based on subtarget /// selection. - const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } + const InstrItineraryData *getInstrItineraryData() const override { + return &InstrItins; + } /// getStackAlignment - Returns the minimum alignment known to hold of the /// stack frame on entry to the function and which must be maintained by every |