diff options
Diffstat (limited to 'lib/Target/BPF/BPFInstrInfo.td')
| -rw-r--r-- | lib/Target/BPF/BPFInstrInfo.td | 174 |
1 files changed, 161 insertions, 13 deletions
diff --git a/lib/Target/BPF/BPFInstrInfo.td b/lib/Target/BPF/BPFInstrInfo.td index 126d55fc28de..aaef5fb706e0 100644 --- a/lib/Target/BPF/BPFInstrInfo.td +++ b/lib/Target/BPF/BPFInstrInfo.td @@ -28,6 +28,10 @@ def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>, SDTCisVT<3, OtherVT>]>; def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; +def SDT_BPFMEMCPY : SDTypeProfile<0, 4, [SDTCisVT<0, i64>, + SDTCisVT<1, i64>, + SDTCisVT<2, i64>, + SDTCisVT<3, i64>]>; def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, @@ -43,8 +47,13 @@ def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC, def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>; def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>; +def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, + SDNPMayStore, SDNPMayLoad]>; def BPFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">; def BPFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">; +def BPFHasALU32 : Predicate<"Subtarget->getHasAlu32()">; +def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">; def brtarget : Operand<OtherVT> { let PrintMethod = "printBrTargetOperand"; @@ -57,6 +66,8 @@ def u64imm : Operand<i64> { def i64immSExt32 : PatLeaf<(i64 imm), [{return isInt<32>(N->getSExtValue()); }]>; +def i32immSExt32 : PatLeaf<(i32 imm), + [{return isInt<32>(N->getSExtValue()); }]>; // Addressing modes. def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>; @@ -218,7 +229,7 @@ multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> { (outs GPR32:$dst), (ins GPR32:$src2, i32imm:$imm), "$dst "#OpcodeStr#" $imm", - [(set GPR32:$dst, (OpNode GPR32:$src2, i32:$imm))]>; + [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>; } let Constraints = "$dst = $src2" in { @@ -292,7 +303,7 @@ def MOV_ri_32 : ALU_RI<BPF_ALU, BPF_MOV, (outs GPR32:$dst), (ins i32imm:$imm), "$dst = $imm", - [(set GPR32:$dst, (i32 i32:$imm))]>; + [(set GPR32:$dst, (i32 i32immSExt32:$imm))]>; } def FI_ri @@ -347,9 +358,11 @@ class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode> : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>; -def STW : STOREi64<BPF_W, "u32", truncstorei32>; -def STH : STOREi64<BPF_H, "u16", truncstorei16>; -def STB : STOREi64<BPF_B, "u8", truncstorei8>; +let Predicates = [BPFNoALU32] in { + def STW : STOREi64<BPF_W, "u32", truncstorei32>; + def STH : STOREi64<BPF_H, "u16", truncstorei16>; + def STB : STOREi64<BPF_B, "u8", truncstorei8>; +} def STD : STOREi64<BPF_DW, "u64", store>; // LOAD instructions @@ -371,9 +384,13 @@ class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>; -def LDW : LOADi64<BPF_W, "u32", zextloadi32>; -def LDH : LOADi64<BPF_H, "u16", zextloadi16>; -def LDB : LOADi64<BPF_B, "u8", zextloadi8>; + +let Predicates = [BPFNoALU32] in { + def LDW : LOADi64<BPF_W, "u32", zextloadi32>; + def LDH : LOADi64<BPF_H, "u16", zextloadi16>; + def LDB : LOADi64<BPF_B, "u8", zextloadi8>; +} + def LDD : LOADi64<BPF_DW, "u64", load>; class BRANCH<BPFJumpOp Opc, string OpcodeStr, list<dag> Pattern> @@ -456,7 +473,7 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1, } // ADJCALLSTACKDOWN/UP pseudo insns -let Defs = [R11], Uses = [R11] in { +let Defs = [R11], Uses = [R11], isCodeGenOnly = 1 in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), "#ADJCALLSTACKDOWN $amt1 $amt2", [(BPFcallseq_start timm:$amt1, timm:$amt2)]>; @@ -465,7 +482,7 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), [(BPFcallseq_end timm:$amt1, timm:$amt2)]>; } -let usesCustomInserter = 1 in { +let usesCustomInserter = 1, isCodeGenOnly = 1 in { def Select : Pseudo<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2), "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", @@ -476,6 +493,36 @@ let usesCustomInserter = 1 in { "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", [(set i64:$dst, (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i64:$src, i64:$src2))]>; + def Select_64_32 : Pseudo<(outs GPR32:$dst), + (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2), + "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", + [(set i32:$dst, + (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i32:$src, i32:$src2))]>; + def Select_Ri_64_32 : Pseudo<(outs GPR32:$dst), + (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2), + "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", + [(set i32:$dst, + (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i32:$src, i32:$src2))]>; + def Select_32 : Pseudo<(outs GPR32:$dst), + (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2), + "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", + [(set i32:$dst, + (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i32:$src, i32:$src2))]>; + def Select_Ri_32 : Pseudo<(outs GPR32:$dst), + (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2), + "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", + [(set i32:$dst, + (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i32:$src, i32:$src2))]>; + def Select_32_64 : Pseudo<(outs GPR:$dst), + (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR:$src, GPR:$src2), + "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", + [(set i64:$dst, + (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i64:$src, i64:$src2))]>; + def Select_Ri_32_64 : Pseudo<(outs GPR:$dst), + (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR:$src, GPR:$src2), + "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", + [(set i64:$dst, + (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i64:$src, i64:$src2))]>; } // load 64-bit global addr into register @@ -492,9 +539,11 @@ def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>; def : Pat<(BPFcall GPR:$dst), (JALX GPR:$dst)>; // Loads -def : Pat<(extloadi8 ADDRri:$src), (i64 (LDB ADDRri:$src))>; -def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>; -def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>; +let Predicates = [BPFNoALU32] in { + def : Pat<(i64 (extloadi8 ADDRri:$src)), (i64 (LDB ADDRri:$src))>; + def : Pat<(i64 (extloadi16 ADDRri:$src)), (i64 (LDH ADDRri:$src))>; + def : Pat<(i64 (extloadi32 ADDRri:$src)), (i64 (LDW ADDRri:$src))>; +} // Atomics class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> @@ -581,3 +630,102 @@ def LD_ABS_W : LOAD_ABS<BPF_W, "u32", int_bpf_load_word>; def LD_IND_B : LOAD_IND<BPF_B, "u8", int_bpf_load_byte>; def LD_IND_H : LOAD_IND<BPF_H, "u16", int_bpf_load_half>; def LD_IND_W : LOAD_IND<BPF_W, "u32", int_bpf_load_word>; + +let isCodeGenOnly = 1 in { + def MOV_32_64 : ALU_RR<BPF_ALU, BPF_MOV, + (outs GPR:$dst), (ins GPR32:$src), + "$dst = $src", []>; +} + +def : Pat<(i64 (sext GPR32:$src)), + (SRA_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>; + +def : Pat<(i64 (zext GPR32:$src)), + (SRL_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>; + +// For i64 -> i32 truncation, use the 32-bit subregister directly. +def : Pat<(i32 (trunc GPR:$src)), + (i32 (EXTRACT_SUBREG GPR:$src, sub_32))>; + +// For i32 -> i64 anyext, we don't care about the high bits. +def : Pat<(i64 (anyext GPR32:$src)), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; + +class STORE32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> + : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, + (outs), + (ins GPR32:$src, MEMri:$addr), + "*("#OpcodeStr#" *)($addr) = $src", + Pattern> { + bits<4> src; + bits<20> addr; + + let Inst{51-48} = addr{19-16}; // base reg + let Inst{55-52} = src; + let Inst{47-32} = addr{15-0}; // offset + let BPFClass = BPF_STX; +} + +class STOREi32<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode> + : STORE32<Opc, OpcodeStr, [(OpNode i32:$src, ADDRri:$addr)]>; + +let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { + def STW32 : STOREi32<BPF_W, "u32", store>; + def STH32 : STOREi32<BPF_H, "u16", truncstorei16>; + def STB32 : STOREi32<BPF_B, "u8", truncstorei8>; +} + +class LOAD32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> + : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, + (outs GPR32:$dst), + (ins MEMri:$addr), + "$dst = *("#OpcodeStr#" *)($addr)", + Pattern> { + bits<4> dst; + bits<20> addr; + + let Inst{51-48} = dst; + let Inst{55-52} = addr{19-16}; + let Inst{47-32} = addr{15-0}; + let BPFClass = BPF_LDX; +} + +class LOADi32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> + : LOAD32<SizeOp, OpcodeStr, [(set i32:$dst, (OpNode ADDRri:$addr))]>; + +let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { + def LDW32 : LOADi32<BPF_W, "u32", load>; + def LDH32 : LOADi32<BPF_H, "u16", zextloadi16>; + def LDB32 : LOADi32<BPF_B, "u8", zextloadi8>; +} + +let Predicates = [BPFHasALU32] in { + def : Pat<(truncstorei8 GPR:$src, ADDRri:$dst), + (STB32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; + def : Pat<(truncstorei16 GPR:$src, ADDRri:$dst), + (STH32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; + def : Pat<(truncstorei32 GPR:$src, ADDRri:$dst), + (STW32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; + def : Pat<(i32 (extloadi8 ADDRri:$src)), (i32 (LDB32 ADDRri:$src))>; + def : Pat<(i32 (extloadi16 ADDRri:$src)), (i32 (LDH32 ADDRri:$src))>; + def : Pat<(i64 (zextloadi8 ADDRri:$src)), + (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; + def : Pat<(i64 (zextloadi16 ADDRri:$src)), + (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; + def : Pat<(i64 (zextloadi32 ADDRri:$src)), + (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; + def : Pat<(i64 (extloadi8 ADDRri:$src)), + (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; + def : Pat<(i64 (extloadi16 ADDRri:$src)), + (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; + def : Pat<(i64 (extloadi32 ADDRri:$src)), + (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; +} + +let usesCustomInserter = 1, isCodeGenOnly = 1 in { + def MEMCPY : Pseudo< + (outs), + (ins GPR:$dst, GPR:$src, i64imm:$len, i64imm:$align, variable_ops), + "#memcpy dst: $dst, src: $src, len: $len, align: $align", + [(BPFmemcpy GPR:$dst, GPR:$src, imm:$len, imm:$align)]>; +} |