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-rw-r--r--lib/Target/Hexagon/HexagonIICHVX.td19
1 files changed, 10 insertions, 9 deletions
diff --git a/lib/Target/Hexagon/HexagonIICHVX.td b/lib/Target/Hexagon/HexagonIICHVX.td
index a804c5a80d03..06e9c83cf306 100644
--- a/lib/Target/Hexagon/HexagonIICHVX.td
+++ b/lib/Target/Hexagon/HexagonIICHVX.td
@@ -1,9 +1,8 @@
//===--- HexagonIICHVX.td -------------------------------------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
@@ -17,12 +16,14 @@ class HVXItin {
InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
[9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>,
- // Used by Gather Pseudo Instructions which are expanded into
- // V6_vgather* and V6_vS32b_new_ai. Even though these instructions
- // use CVI_ST resource, it's not included below to avoid having more than
- // 4 InstrStages and thus changing 'MaxResTerms' to 5.
+ // Used by gather pseudo-instructions which are expanded into V6_vgather*
+ // and V6_vS32b_new_ai. Even though these instructions use CVI_LD resource,
+ // it's not included below to avoid having more than 4 InstrStages and
+ // thus changing 'MaxResTerms' to 5. Instead, both SLOT0 and SLOT1 are
+ // used, which should be sufficient.
InstrItinData <CVI_GATHER_PSEUDO,
[InstrStage<1, [SLOT0], 0>,
- InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>,
+ InstrStage<1, [SLOT1], 0>,
+ InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>];
}