diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonStoreWidening.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonStoreWidening.cpp | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/lib/Target/Hexagon/HexagonStoreWidening.cpp b/lib/Target/Hexagon/HexagonStoreWidening.cpp index 300f6de33552..991af047387e 100644 --- a/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ b/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -433,10 +433,11 @@ bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG, const MCInstrDesc &StD = TII->get(WOpc); MachineOperand &MR = FirstSt->getOperand(0); int64_t Off = FirstSt->getOperand(1).getImm(); - MachineInstr *StI = BuildMI(*MF, DL, StD) - .addReg(MR.getReg(), getKillRegState(MR.isKill())) - .addImm(Off) - .addImm(Val); + MachineInstr *StI = + BuildMI(*MF, DL, StD) + .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg()) + .addImm(Off) + .addImm(Val); StI->addMemOperand(*MF, NewM); NG.push_back(StI); } else { @@ -455,10 +456,11 @@ bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG, const MCInstrDesc &StD = TII->get(WOpc); MachineOperand &MR = FirstSt->getOperand(0); int64_t Off = FirstSt->getOperand(1).getImm(); - MachineInstr *StI = BuildMI(*MF, DL, StD) - .addReg(MR.getReg(), getKillRegState(MR.isKill())) - .addImm(Off) - .addReg(VReg, RegState::Kill); + MachineInstr *StI = + BuildMI(*MF, DL, StD) + .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg()) + .addImm(Off) + .addReg(VReg, RegState::Kill); StI->addMemOperand(*MF, NewM); NG.push_back(StI); } @@ -472,7 +474,7 @@ bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG, // from OG was (in the order in which they appeared in the basic block). // (The ordering in OG does not have to match the order in the basic block.) bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Replacing:\n"; for (auto I : OG) dbgs() << " " << *I; @@ -576,7 +578,7 @@ bool HexagonStoreWidening::processBasicBlock(MachineBasicBlock &MBB) { }; for (auto &G : SGs) { assert(G.size() > 1 && "Store group with fewer than 2 elements"); - std::sort(G.begin(), G.end(), Less); + llvm::sort(G.begin(), G.end(), Less); Changed |= processStoreGroup(G); } |