diff options
Diffstat (limited to 'lib/Target/PowerPC/PPCCallingConv.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCCallingConv.td | 50 |
1 files changed, 40 insertions, 10 deletions
diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td index 22842d516e7d..369b9ce1a711 100644 --- a/lib/Target/PowerPC/PPCCallingConv.td +++ b/lib/Target/PowerPC/PPCCallingConv.td @@ -1,9 +1,8 @@ //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -46,6 +45,7 @@ def RetCC_PPC64_AnyReg : CallingConv<[ ]>; // Return-value convention for PowerPC coldcc. +let Entry = 1 in def RetCC_PPC_Cold : CallingConv<[ // Use the same return registers as RetCC_PPC, but limited to only // one return value. The remaining return values will be saved to @@ -70,6 +70,7 @@ def RetCC_PPC_Cold : CallingConv<[ ]>; // Return-value convention for PowerPC +let Entry = 1 in def RetCC_PPC : CallingConv<[ CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, @@ -90,7 +91,7 @@ def RetCC_PPC : CallingConv<[ CCIfSubtarget<"hasSPE()", CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>, CCIfSubtarget<"hasSPE()", - CCIfType<[f64], CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>, + CCIfType<[f64], CCCustom<"CC_PPC32_SPE_RetF64">>>, // For P9, f128 are passed in vector registers. CCIfType<[f128], @@ -126,6 +127,7 @@ def CC_PPC64_AnyReg : CallingConv<[ // Simple calling convention for 64-bit ELF PowerPC fast isel. // Only handle ints and floats. All ints are promoted to i64. // Vector types and quadword ints are not handled. +let Entry = 1 in def CC_PPC64_ELF_FIS : CallingConv<[ CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>, @@ -141,6 +143,7 @@ def CC_PPC64_ELF_FIS : CallingConv<[ // All small ints are promoted to i64. Vector types, quadword ints, // and multiple register returns are "supported" to avoid compile // errors, but none are handled by the fast selector. +let Entry = 1 in def RetCC_PPC64_ELF_FIS : CallingConv<[ CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, @@ -179,6 +182,9 @@ def CC_PPC32_SVR4_Common : CallingConv<[ CCIfType<[i32], CCIfSplit<CCIfNotSubtarget<"useSoftFloat()", CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>, + CCIfType<[f64], + CCIfSubtarget<"hasSPE()", + CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>, CCIfSplit<CCIfSubtarget<"useSoftFloat()", CCIfOrigArgWasPPCF128<CCCustom< "CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>, @@ -199,7 +205,7 @@ def CC_PPC32_SVR4_Common : CallingConv<[ CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>, CCIfType<[f64], CCIfSubtarget<"hasSPE()", - CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>, + CCCustom<"CC_PPC32_SPE_CustomSplitFP64">>>, CCIfType<[f32], CCIfSubtarget<"hasSPE()", CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>, @@ -228,12 +234,14 @@ def CC_PPC32_SVR4_Common : CallingConv<[ // This calling convention puts vector arguments always on the stack. It is used // to assign vector arguments which belong to the variable portion of the // parameter list of a variable argument function. +let Entry = 1 in def CC_PPC32_SVR4_VarArg : CallingConv<[ CCDelegateTo<CC_PPC32_SVR4_Common> ]>; // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to // put vector arguments in vector registers before putting them on the stack. +let Entry = 1 in def CC_PPC32_SVR4 : CallingConv<[ // QPX vectors mirror the scalar FP convention. CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()", @@ -265,6 +273,7 @@ def CC_PPC32_SVR4 : CallingConv<[ // The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are // not passed by value. +let Entry = 1 in def CC_PPC32_SVR4_ByVal : CallingConv<[ CCIfByVal<CCPassByVal<4, 4>>, @@ -300,6 +309,13 @@ def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>; def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>; +def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, + R21, R22, R23, R24, R25, R26, R27, R28, + R29, R30, R31, F14, F15, F16, F17, F18, + F19, F20, F21, F22, F23, F24, F25, F26, + F27, F28, F29, F30, F31, CR2, CR3, CR4 + )>; + def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, F14, F15, F16, F17, F18, @@ -316,6 +332,13 @@ def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, F27, F28, F29, F30, F31, CR2, CR3, CR4 )>; +def CSR_AIX64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, + X21, X22, X23, X24, X25, X26, X27, X28, + X29, X30, X31, F14, F15, F16, F17, F18, + F19, F20, F21, F22, F23, F24, F25, F26, + F27, F28, F29, F30, F31, CR2, CR3, CR4 + )>; + // CSRs that are handled by prologue, epilogue. def CSR_SRV464_TLS_PE : CalleeSavedRegs<(add)>; @@ -343,15 +366,22 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>; // and value may be altered by inter-library calls. // Do not include r12 as it is used as a scratch register. // Do not include return registers r3, f1, v2. -def CSR_SVR32_ColdCC : CalleeSavedRegs<(add (sequence "R%u", 4, 10), - (sequence "R%u", 14, 31), - F0, (sequence "F%u", 2, 31), - (sequence "CR%u", 0, 7))>; +def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10), + (sequence "R%u", 14, 31), + (sequence "CR%u", 0, 7))>; + +def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common, + F0, (sequence "F%u", 2, 31))>; + def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC, (sequence "V%u", 0, 1), (sequence "V%u", 3, 31))>; +def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common, + (sequence "S%u", 4, 10), + (sequence "S%u", 14, 31))>; + def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10), (sequence "X%u", 14, 31), F0, (sequence "F%u", 2, 31), |