summaryrefslogtreecommitdiff
path: root/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h')
-rw-r--r--lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h b/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
index 7c98b1c8f321..bea2f8800fa6 100644
--- a/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
+++ b/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
@@ -17,6 +17,7 @@
#include "llvm/Config/config.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/Support/DataTypes.h"
+#include <memory>
namespace llvm {
class MCAsmBackend;
@@ -43,8 +44,8 @@ MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
-MCObjectWriter *createRISCVELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
- bool Is64Bit);
+std::unique_ptr<MCObjectWriter>
+createRISCVELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool Is64Bit);
}
// Defines symbolic names for RISC-V registers.
@@ -55,4 +56,7 @@ MCObjectWriter *createRISCVELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
#define GET_INSTRINFO_ENUM
#include "RISCVGenInstrInfo.inc"
+#define GET_SUBTARGETINFO_ENUM
+#include "RISCVGenSubtargetInfo.inc"
+
#endif