diff options
Diffstat (limited to 'lib/Target/RISCV/RISCVTargetMachine.cpp')
-rw-r--r-- | lib/Target/RISCV/RISCVTargetMachine.cpp | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/RISCV/RISCVTargetMachine.cpp b/lib/Target/RISCV/RISCVTargetMachine.cpp index e12168b73999..a2ebf5bf3e6b 100644 --- a/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -13,6 +13,7 @@ #include "RISCV.h" #include "RISCVTargetMachine.h" +#include "RISCVTargetObjectFile.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -59,7 +60,7 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), getEffectiveCodeModel(CM), OL), - TLOF(make_unique<TargetLoweringObjectFileELF>()), + TLOF(make_unique<RISCVELFTargetObjectFile>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } @@ -74,7 +75,10 @@ public: return getTM<RISCVTargetMachine>(); } + void addIRPasses() override; bool addInstSelector() override; + void addPreEmitPass() override; + void addPreRegAlloc() override; }; } @@ -82,8 +86,19 @@ TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { return new RISCVPassConfig(*this, PM); } +void RISCVPassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); + TargetPassConfig::addIRPasses(); +} + bool RISCVPassConfig::addInstSelector() { addPass(createRISCVISelDag(getRISCVTargetMachine())); return false; } + +void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } + +void RISCVPassConfig::addPreRegAlloc() { + addPass(createRISCVMergeBaseOffsetOptPass()); +} |