diff options
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/Sparc/Sparc.h | 2 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcISelLowering.h | 4 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcTargetMachine.cpp | 4 |
7 files changed, 17 insertions, 17 deletions
diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index c7a5a1e8e6ee..35f52f7d279b 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -190,7 +190,7 @@ public: Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15, Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23, Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31}; - + namespace { /// SparcOperand - Instances of this class represent a parsed Sparc machine @@ -459,7 +459,7 @@ public: Op.Reg.Kind = rk_CoprocPairReg; return true; } - + static std::unique_ptr<SparcOperand> MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) { unsigned offsetReg = Op->getReg(); @@ -1000,7 +1000,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegNo, RegKind = SparcOperand::rk_Special; return true; } - + if (name.equals("wim")) { RegNo = Sparc::WIM; RegKind = SparcOperand::rk_Special; @@ -1093,7 +1093,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegNo, RegKind = SparcOperand::rk_CoprocReg; return true; } - + if (name.equals("tpc")) { RegNo = Sparc::TPC; RegKind = SparcOperand::rk_Special; diff --git a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index 8e298e8316da..3e30dae1537f 100644 --- a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -350,18 +350,18 @@ DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, return MCDisassembler::Fail; // Calling the auto-generated decoder function. - + if (STI.getFeatureBits()[Sparc::FeatureV9]) { Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); } else { - Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); + Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); } if (Result != MCDisassembler::Fail) return Result; - + Result = decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); @@ -662,7 +662,7 @@ static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address, if (status != MCDisassembler::Success) return status; } - + // Decode CC MI.addOperand(MCOperand::createImm(cc)); diff --git a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp index 4981deae6af6..c1512cbdc44f 100644 --- a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp +++ b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp @@ -118,9 +118,9 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum, if (MO.isImm()) { switch (MI->getOpcode()) { default: - O << (int)MO.getImm(); + O << (int)MO.getImm(); return; - + case SP::TICCri: // Fall through case SP::TICCrr: // Fall through case SP::TRAPri: // Fall through @@ -128,7 +128,7 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum, case SP::TXCCri: // Fall through case SP::TXCCrr: // Fall through // Only seven-bit values up to 127. - O << ((int) MO.getImm() & 0x7f); + O << ((int) MO.getImm() & 0x7f); return; } } diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index 4135e4e1b61d..0cea53b359eb 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -73,7 +73,7 @@ namespace llvm { FCC_LE = 13+16, // Less or Equal FCC_ULE = 14+16, // Unordered or Less or Equal FCC_O = 15+16, // Ordered - + CPCC_A = 8+32, // Always CPCC_N = 0+32, // Never CPCC_3 = 7+32, diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index bf700d6a99d8..0cbbda787881 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -59,9 +59,9 @@ namespace llvm { public: SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI); SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - + bool useSoftFloat() const override; - + /// computeKnownBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 6750763d8ee5..47b42444b94d 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -115,7 +115,7 @@ static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) case SPCC::FCC_UE: return SPCC::FCC_LG; case SPCC::FCC_NE: return SPCC::FCC_E; case SPCC::FCC_E: return SPCC::FCC_NE; - + case SPCC::CPCC_A: return SPCC::CPCC_N; case SPCC::CPCC_N: return SPCC::CPCC_A; case SPCC::CPCC_3: LLVM_FALLTHROUGH; diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index a0d40653fd9b..07f9e7250bd9 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -100,7 +100,7 @@ SparcTargetMachine::SparcTargetMachine( SparcTargetMachine::~SparcTargetMachine() {} -const SparcSubtarget * +const SparcSubtarget * SparcTargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); Attribute FSAttr = F.getFnAttribute("target-features"); @@ -119,7 +119,7 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const { F.hasFnAttribute("use-soft-float") && F.getFnAttribute("use-soft-float").getValueAsString() == "true"; - if (softFloat) + if (softFloat) FS += FS.empty() ? "+soft-float" : ",+soft-float"; auto &I = SubtargetMap[CPU + FS]; |