diff options
Diffstat (limited to 'lib/Target/Sparc')
24 files changed, 165 insertions, 429 deletions
diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 087c037614a9..05f78a48badf 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -108,7 +108,7 @@ public: SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, const MCTargetOptions &Options) - : MCTargetAsmParser(Options, sti), Parser(parser) { + : MCTargetAsmParser(Options, sti, MII), Parser(parser) { // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); } diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp index df819ccd15db..9b1d0f5bf3c9 100644 --- a/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/lib/Target/Sparc/DelaySlotFiller.cpp @@ -19,10 +19,10 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegisterInfo.h" using namespace llvm; diff --git a/lib/Target/Sparc/LeonFeatures.td b/lib/Target/Sparc/LeonFeatures.td index d06e734b5a7b..d9efe094d078 100755 --- a/lib/Target/Sparc/LeonFeatures.td +++ b/lib/Target/Sparc/LeonFeatures.td @@ -52,20 +52,6 @@ def InsertNOPLoad: SubtargetFeature< "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" >; -def FixFSMULD : SubtargetFeature< - "fixfsmuld", - "FixFSMULD", - "true", - "LEON erratum fix: Do not use FSMULD" ->; - -def ReplaceFMULS : SubtargetFeature< - "replacefmuls", - "ReplaceFMULS", - "true", - "LEON erratum fix: Replace FMULS instruction with FMULD and relevant conversion instructions" ->; - def DetectRoundChange : SubtargetFeature< "detectroundchange", "DetectRoundChange", diff --git a/lib/Target/Sparc/LeonPasses.cpp b/lib/Target/Sparc/LeonPasses.cpp index ca6a0dc3c2a3..5ce00db365ab 100755 --- a/lib/Target/Sparc/LeonPasses.cpp +++ b/lib/Target/Sparc/LeonPasses.cpp @@ -24,39 +24,6 @@ using namespace llvm; LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID) : MachineFunctionPass(ID) {} -int LEONMachineFunctionPass::GetRegIndexForOperand(MachineInstr &MI, - int OperandIndex) { - if (MI.getNumOperands() > 0) { - if (OperandIndex == LAST_OPERAND) { - OperandIndex = MI.getNumOperands() - 1; - } - - if (MI.getNumOperands() > (unsigned)OperandIndex && - MI.getOperand(OperandIndex).isReg()) { - return (int)MI.getOperand(OperandIndex).getReg(); - } - } - - static int NotFoundIndex = -10; - // Return a different number each time to avoid any comparisons between the - // values returned. - NotFoundIndex -= 10; - return NotFoundIndex; -} - -// finds a new free FP register -// checks also the AllocatedRegisters vector -int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo &MRI) { - for (int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) { - if (!MRI.isPhysRegUsed(RegisterIndex) && - !is_contained(UsedRegisters, RegisterIndex)) { - return RegisterIndex; - } - } - - return -1; -} - //***************************************************************************** //**** InsertNOPLoad pass //***************************************************************************** @@ -93,182 +60,6 @@ bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) { return Modified; } -//***************************************************************************** -//**** FixFSMULD pass -//***************************************************************************** -// This pass fixes the incorrectly working FSMULD instruction that exists for -// some earlier versions of the LEON processor line. -// -// The pass should convert the FSMULD operands to double precision in scratch -// registers, then calculate the result with the FMULD instruction. Therefore, -// the pass should replace operations of the form: -// fsmuld %f20,%f21,%f8 -// with the sequence: -// fstod %f20,%f0 -// fstod %f21,%f2 -// fmuld %f0,%f2,%f8 -// -char FixFSMULD::ID = 0; - -FixFSMULD::FixFSMULD() : LEONMachineFunctionPass(ID) {} - -bool FixFSMULD::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &MF.getSubtarget<SparcSubtarget>(); - const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); - DebugLoc DL = DebugLoc(); - - bool Modified = false; - for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { - MachineBasicBlock &MBB = *MFI; - for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { - - MachineInstr &MI = *MBBI; - unsigned Opcode = MI.getOpcode(); - - const int UNASSIGNED_INDEX = -1; - int Reg1Index = UNASSIGNED_INDEX; - int Reg2Index = UNASSIGNED_INDEX; - int Reg3Index = UNASSIGNED_INDEX; - - if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) { - // take the registers from fsmuld %f20,%f21,%f8 - Reg1Index = MI.getOperand(0).getReg(); - Reg2Index = MI.getOperand(1).getReg(); - Reg3Index = MI.getOperand(2).getReg(); - } - - if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && - Reg3Index != UNASSIGNED_INDEX) { - clearUsedRegisterList(); - MachineBasicBlock::iterator NMBBI = std::next(MBBI); - // Whatever Reg3Index is hasn't been used yet, so we need to reserve it. - markRegisterUsed(Reg3Index); - const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo()); - markRegisterUsed(ScratchReg1Index); - const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo()); - markRegisterUsed(ScratchReg2Index); - - if (ScratchReg1Index == UNASSIGNED_INDEX || - ScratchReg2Index == UNASSIGNED_INDEX) { - errs() << "Cannot allocate free scratch registers for the FixFSMULD " - "pass." - << "\n"; - } else { - // create fstod %f20,%f0 - BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) - .addReg(ScratchReg1Index) - .addReg(Reg1Index); - - // create fstod %f21,%f2 - BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) - .addReg(ScratchReg2Index) - .addReg(Reg2Index); - - // create fmuld %f0,%f2,%f8 - BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD)) - .addReg(Reg3Index) - .addReg(ScratchReg1Index) - .addReg(ScratchReg2Index); - - MI.eraseFromParent(); - MBBI = NMBBI; - - Modified = true; - } - } - } - } - - return Modified; -} - -//***************************************************************************** -//**** ReplaceFMULS pass -//***************************************************************************** -// This pass fixes the incorrectly working FMULS instruction that exists for -// some earlier versions of the LEON processor line. -// -// This pass converts the FMULS operands to double precision in scratch -// registers, then calculates the result with the FMULD instruction. -// The pass should replace operations of the form: -// fmuls %f20,%f21,%f8 -// with the sequence: -// fstod %f20,%f0 -// fstod %f21,%f2 -// fmuld %f0,%f2,%f8 -// -char ReplaceFMULS::ID = 0; - -ReplaceFMULS::ReplaceFMULS() : LEONMachineFunctionPass(ID) {} - -bool ReplaceFMULS::runOnMachineFunction(MachineFunction &MF) { - Subtarget = &MF.getSubtarget<SparcSubtarget>(); - const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); - DebugLoc DL = DebugLoc(); - - bool Modified = false; - for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { - MachineBasicBlock &MBB = *MFI; - for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { - MachineInstr &MI = *MBBI; - unsigned Opcode = MI.getOpcode(); - - const int UNASSIGNED_INDEX = -1; - int Reg1Index = UNASSIGNED_INDEX; - int Reg2Index = UNASSIGNED_INDEX; - int Reg3Index = UNASSIGNED_INDEX; - - if (Opcode == SP::FMULS && MI.getNumOperands() == 3) { - // take the registers from fmuls %f20,%f21,%f8 - Reg1Index = MI.getOperand(0).getReg(); - Reg2Index = MI.getOperand(1).getReg(); - Reg3Index = MI.getOperand(2).getReg(); - } - - if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && - Reg3Index != UNASSIGNED_INDEX) { - clearUsedRegisterList(); - MachineBasicBlock::iterator NMBBI = std::next(MBBI); - // Whatever Reg3Index is hasn't been used yet, so we need to reserve it. - markRegisterUsed(Reg3Index); - const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo()); - markRegisterUsed(ScratchReg1Index); - const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo()); - markRegisterUsed(ScratchReg2Index); - - if (ScratchReg1Index == UNASSIGNED_INDEX || - ScratchReg2Index == UNASSIGNED_INDEX) { - errs() << "Cannot allocate free scratch registers for the " - "ReplaceFMULS pass." - << "\n"; - } else { - // create fstod %f20,%f0 - BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) - .addReg(ScratchReg1Index) - .addReg(Reg1Index); - - // create fstod %f21,%f2 - BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) - .addReg(ScratchReg2Index) - .addReg(Reg2Index); - - // create fmuld %f0,%f2,%f8 - BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD)) - .addReg(Reg3Index) - .addReg(ScratchReg1Index) - .addReg(ScratchReg2Index); - - MI.eraseFromParent(); - MBBI = NMBBI; - - Modified = true; - } - } - } - } - - return Modified; -} //***************************************************************************** diff --git a/lib/Target/Sparc/LeonPasses.h b/lib/Target/Sparc/LeonPasses.h index 99cdfc4589ef..1b3d9a7a32f9 100755 --- a/lib/Target/Sparc/LeonPasses.h +++ b/lib/Target/Sparc/LeonPasses.h @@ -57,32 +57,6 @@ public: } }; -class LLVM_LIBRARY_VISIBILITY FixFSMULD : public LEONMachineFunctionPass { -public: - static char ID; - - FixFSMULD(); - bool runOnMachineFunction(MachineFunction &MF) override; - - StringRef getPassName() const override { - return "FixFSMULD: Erratum Fix LBR31: do not select FSMULD"; - } -}; - -class LLVM_LIBRARY_VISIBILITY ReplaceFMULS : public LEONMachineFunctionPass { -public: - static char ID; - - ReplaceFMULS(); - bool runOnMachineFunction(MachineFunction &MF) override; - - StringRef getPassName() const override { - return "ReplaceFMULS: Erratum Fix LBR32: replace FMULS instruction with a " - "routine using conversions/double precision operations to replace " - "FMULS"; - } -}; - class LLVM_LIBRARY_VISIBILITY DetectRoundChange : public LEONMachineFunctionPass { public: diff --git a/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index 0a72a4438218..a38545ecf430 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -291,7 +291,8 @@ namespace { } } - MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { + std::unique_ptr<MCObjectWriter> + createObjectWriter(raw_pwrite_stream &OS) const override { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI); } diff --git a/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp b/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp index d35e45e03466..a204036a0975 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp @@ -13,6 +13,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" @@ -131,10 +132,9 @@ bool SparcELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, } } -MCObjectWriter *llvm::createSparcELFObjectWriter(raw_pwrite_stream &OS, - bool Is64Bit, - bool IsLittleEndian, - uint8_t OSABI) { - MCELFObjectTargetWriter *MOTW = new SparcELFObjectWriter(Is64Bit, OSABI); - return createELFObjectWriter(MOTW, OS, IsLittleEndian); +std::unique_ptr<MCObjectWriter> +llvm::createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, + bool IsLittleEndian, uint8_t OSABI) { + auto MOTW = llvm::make_unique<SparcELFObjectWriter>(Is64Bit, OSABI); + return createELFObjectWriter(std::move(MOTW), OS, IsLittleEndian); } diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 889e2fd19ba9..bd6596faee5d 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -69,43 +69,6 @@ createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createSparcMCSubtargetInfoImpl(TT, CPU, FS); } -// Code models. Some only make sense for 64-bit code. -// -// SunCC Reloc CodeModel Constraints -// abs32 Static Small text+data+bss linked below 2^32 bytes -// abs44 Static Medium text+data+bss linked below 2^44 bytes -// abs64 Static Large text smaller than 2^31 bytes -// pic13 PIC_ Small GOT < 2^13 bytes -// pic32 PIC_ Medium GOT < 2^32 bytes -// -// All code models require that the text segment is smaller than 2GB. - -static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - // The default 32-bit code model is abs32/pic32 and the default 32-bit - // code model for JIT is abs32. - switch (CM) { - default: break; - case CodeModel::Default: - case CodeModel::JITDefault: CM = CodeModel::Small; break; - } -} - -static void adjustCodeGenOptsV9(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - // The default 64-bit code model is abs44/pic32 and the default 64-bit - // code model for JIT is abs64. - switch (CM) { - default: break; - case CodeModel::Default: - CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; - break; - case CodeModel::JITDefault: - CM = CodeModel::Large; - break; - } -} - static MCTargetStreamer * createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { return new SparcTargetELFStreamer(S); @@ -159,12 +122,4 @@ extern "C" void LLVMInitializeSparcTargetMC() { // Register the MCInstPrinter TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter); } - - // Register the MC codegen info. - TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcTarget(), - adjustCodeGenOpts); - TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcV9Target(), - adjustCodeGenOptsV9); - TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcelTarget(), - adjustCodeGenOpts); } diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h index 4e754c132d11..563e6f4efbe6 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -16,6 +16,8 @@ #include "llvm/Support/DataTypes.h" +#include <memory> + namespace llvm { class MCAsmBackend; class MCCodeEmitter; @@ -41,8 +43,9 @@ MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options); -MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, - bool IsLIttleEndian, uint8_t OSABI); +std::unique_ptr<MCObjectWriter> +createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, + bool IsLIttleEndian, uint8_t OSABI); } // End llvm namespace // Defines symbolic names for Sparc registers. This defines a mapping from diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 91cab00b2b65..9e0a297c8812 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -24,6 +24,13 @@ def FeatureSoftMulDiv : SubtargetFeature<"soft-mul-div", "UseSoftMulDiv", "true", "Use software emulation for integer multiply and divide">; +def FeatureNoFSMULD + : SubtargetFeature<"no-fsmuld", "HasNoFSMULD", "true", + "Disable the fsmuld instruction.">; +def FeatureNoFMULS + : SubtargetFeature<"no-fmuls", "HasNoFMULS", "true", + "Disable the fmuls instruction.">; + def FeatureV9 : SubtargetFeature<"v9", "IsV9", "true", "Enable SPARC-V9 instructions">; @@ -51,9 +58,9 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", "Use the popc (population count) instruction">; def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", - "Use software emulation for floating point">; + "Use software emulation for floating point">; -//==== Features added predmoninantly for LEON subtarget support +//==== Features added predmoninantly for LEON subtarget support include "LeonFeatures.td" //===----------------------------------------------------------------------===// @@ -79,7 +86,7 @@ class Proc<string Name, list<SubtargetFeature> Features> : Processor<Name, NoItineraries, Features>; def : Proc<"generic", []>; -def : Proc<"v7", [FeatureSoftMulDiv]>; +def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>; def : Proc<"v8", []>; def : Proc<"supersparc", []>; def : Proc<"sparclite", []>; @@ -91,9 +98,18 @@ def : Proc<"tsc701", []>; def : Proc<"myriad2", [FeatureLeon, LeonCASA]>; def : Proc<"myriad2.1", [FeatureLeon, LeonCASA]>; def : Proc<"myriad2.2", [FeatureLeon, LeonCASA]>; +def : Proc<"myriad2.3", [FeatureLeon, LeonCASA]>; def : Proc<"ma2100", [FeatureLeon, LeonCASA]>; def : Proc<"ma2150", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2155", [FeatureLeon, LeonCASA]>; def : Proc<"ma2450", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2455", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2x5x", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2080", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2085", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2480", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2485", [FeatureLeon, LeonCASA]>; +def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; def : Proc<"v9", [FeatureV9]>; def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, @@ -128,8 +144,8 @@ def : Processor<"leon3", LEON3Itineraries, // LEON 3 FT (UT699). Provides features for the UT699 processor // - covers all the erratum fixes for LEON3, but does not support the CASA instruction. -def : Processor<"ut699", LEON3Itineraries, - [FeatureLeon, InsertNOPLoad, FixFSMULD, ReplaceFMULS, FixAllFDIVSQRT]>; +def : Processor<"ut699", LEON3Itineraries, + [FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>; // LEON3 FT (GR712RC). Provides features for the GR712RC processor. // - covers all the erratum fixed for LEON3 and support for the CASA instruction. diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index c07cc213c3ed..9864aa372354 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -306,8 +306,8 @@ bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const return !(MFI.hasCalls() // has calls || MRI.isPhysRegUsed(SP::L0) // Too many registers needed - || MRI.isPhysRegUsed(SP::O6) // %SP is used - || hasFP(MF)); // need %FP + || MRI.isPhysRegUsed(SP::O6) // %sp is used + || hasFP(MF)); // need %fp } void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const { diff --git a/lib/Target/Sparc/SparcFrameLowering.h b/lib/Target/Sparc/SparcFrameLowering.h index ac0e69ccde1e..6098afa68985 100644 --- a/lib/Target/Sparc/SparcFrameLowering.h +++ b/lib/Target/Sparc/SparcFrameLowering.h @@ -15,7 +15,7 @@ #define LLVM_LIB_TARGET_SPARC_SPARCFRAMELOWERING_H #include "Sparc.h" -#include "llvm/Target/TargetFrameLowering.h" +#include "llvm/CodeGen/TargetFrameLowering.h" namespace llvm { diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 6767a59a9757..d9548ff90d7f 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -264,7 +264,7 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, unsigned RetAddrOffset = 8; // Call Inst + Delay Slot // If the function returns a struct, copy the SRetReturnReg to I0 - if (MF.getFunction()->hasStructRetAttr()) { + if (MF.getFunction().hasStructRetAttr()) { SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); unsigned Reg = SFI->getSRetReturnReg(); if (!Reg) @@ -519,7 +519,7 @@ SDValue SparcTargetLowering::LowerFormalArguments_32( InVals.push_back(Load); } - if (MF.getFunction()->hasStructRetAttr()) { + if (MF.getFunction().hasStructRetAttr()) { // Copy the SRet Argument to SRetReturnReg. SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); unsigned Reg = SFI->getSRetReturnReg(); @@ -692,17 +692,17 @@ SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, - ImmutableCallSite *CS) { + ImmutableCallSite CS) { if (CS) - return CS->hasFnAttr(Attribute::ReturnsTwice); + return CS.hasFnAttr(Attribute::ReturnsTwice); const Function *CalleeFn = nullptr; if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { CalleeFn = dyn_cast<Function>(G->getGlobal()); } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) { - const Function *Fn = DAG.getMachineFunction().getFunction(); - const Module *M = Fn->getParent(); + const Function &Fn = DAG.getMachineFunction().getFunction(); + const Module *M = Fn.getParent(); const char *CalleeName = E->getSymbol(); CalleeFn = M->getFunction(CalleeName); } @@ -1057,8 +1057,8 @@ SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const CalleeFn = dyn_cast<Function>(G->getGlobal()); } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) { - const Function *Fn = DAG.getMachineFunction().getFunction(); - const Module *M = Fn->getParent(); + const Function &F = DAG.getMachineFunction().getFunction(); + const Module *M = F.getParent(); const char *CalleeName = E->getSymbol(); CalleeFn = M->getFunction(CalleeName); if (!CalleeFn && isFP128ABICall(CalleeName)) @@ -1334,7 +1334,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Set inreg flag manually for codegen generated library calls that // return float. - if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr) + if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CS) CLI.Ins[0].Flags.setInReg(); RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); @@ -1828,9 +1828,7 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FSQRT, MVT::f32, Promote); } - if (Subtarget->replaceFMULS()) { - // Promote FMULS to FMULD instructions instead as - // the former instructions generate errata on LEON processors. + if (Subtarget->hasNoFMULS()) { setOperationAction(ISD::FMUL, MVT::f32, Promote); } @@ -3134,57 +3132,53 @@ SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, DebugLoc dl = MI.getDebugLoc(); unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm(); - // To "insert" a SELECT_CC instruction, we actually have to insert the diamond - // control-flow pattern. The incoming instruction knows the destination vreg - // to set, the condition code register to branch on, the true/false values to - // select between, and a branch opcode to use. + // To "insert" a SELECT_CC instruction, we actually have to insert the + // triangle control-flow pattern. The incoming instruction knows the + // destination vreg to set, the condition code register to branch on, the + // true/false values to select between, and the condition code for the branch. + // + // We produce the following control flow: + // ThisMBB + // | \ + // | IfFalseMBB + // | / + // SinkMBB const BasicBlock *LLVM_BB = BB->getBasicBlock(); MachineFunction::iterator It = ++BB->getIterator(); - // thisMBB: - // ... - // TrueVal = ... - // [f]bCC copy1MBB - // fallthrough --> copy0MBB - MachineBasicBlock *thisMBB = BB; + MachineBasicBlock *ThisMBB = BB; MachineFunction *F = BB->getParent(); - MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - F->insert(It, copy0MBB); - F->insert(It, sinkMBB); - - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - std::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - - // Add the true and fallthrough blocks as its successors. - BB->addSuccessor(copy0MBB); - BB->addSuccessor(sinkMBB); - - BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); - - // copy0MBB: - // %FalseValue = ... - // # fallthrough to sinkMBB - BB = copy0MBB; - - // Update machine-CFG edges - BB->addSuccessor(sinkMBB); - - // sinkMBB: - // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] - // ... - BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI.getOperand(0).getReg()) - .addReg(MI.getOperand(2).getReg()) - .addMBB(copy0MBB) + MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, IfFalseMBB); + F->insert(It, SinkMBB); + + // Transfer the remainder of ThisMBB and its successor edges to SinkMBB. + SinkMBB->splice(SinkMBB->begin(), ThisMBB, + std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end()); + SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB); + + // Set the new successors for ThisMBB. + ThisMBB->addSuccessor(IfFalseMBB); + ThisMBB->addSuccessor(SinkMBB); + + BuildMI(ThisMBB, dl, TII.get(BROpcode)) + .addMBB(SinkMBB) + .addImm(CC); + + // IfFalseMBB just falls through to SinkMBB. + IfFalseMBB->addSuccessor(SinkMBB); + + // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ] + BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI), + MI.getOperand(0).getReg()) .addReg(MI.getOperand(1).getReg()) - .addMBB(thisMBB); + .addMBB(ThisMBB) + .addReg(MI.getOperand(2).getReg()) + .addMBB(IfFalseMBB); MI.eraseFromParent(); // The pseudo instruction is gone now. - return BB; + return SinkMBB; } MachineBasicBlock * diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index cc6386bccbb1..bf700d6a99d8 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -16,7 +16,7 @@ #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H #include "Sparc.h" -#include "llvm/Target/TargetLowering.h" +#include "llvm/CodeGen/TargetLowering.h" namespace llvm { class SparcSubtarget; diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index c053cc4c475b..524b5d054163 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -15,7 +15,7 @@ #define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H #include "SparcRegisterInfo.h" -#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetInstrInfo.h" #define GET_INSTRINFO_HEADER #include "SparcGenInstrInfo.inc" diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 3194ad4aeb6b..08bccbde0bd6 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -61,8 +61,8 @@ def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">; def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">; def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">; -def HasNoFmulsFix : Predicate<"!Subtarget->replaceFMULS()">; -def HasNoFsmuldFix : Predicate<"!Subtarget->fixFSMULD()">; +def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">; +def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">; // UseDeprecatedInsts - This predicate is true when the target processor is a // V8, or when it is V9 but the V8 deprecated instructions are efficient enough @@ -1236,14 +1236,12 @@ def FSUBQ : F3_3<2, 0b110100, 0b001000111, // Floating-point Multiply and Divide Instructions, p. 147 -// FMULS generates an erratum on LEON processors, so by disabling this instruction -// this will be promoted to use FMULD with doubles instead. -let Predicates = [HasNoFmulsFix] in def FMULS : F3_3<2, 0b110100, 0b001001001, (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fmuls $rs1, $rs2, $rd", [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))], - IIC_fpu_muls>; + IIC_fpu_muls>, + Requires<[HasFMULS]>; def FMULD : F3_3<2, 0b110100, 0b001001010, (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fmuld $rs1, $rs2, $rd", @@ -1255,13 +1253,13 @@ def FMULQ : F3_3<2, 0b110100, 0b001001011, [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>, Requires<[HasHardQuad]>; -let Predicates = [HasNoFsmuldFix] in def FSMULD : F3_3<2, 0b110100, 0b001101001, (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fsmuld $rs1, $rs2, $rd", [(set f64:$rd, (fmul (fpextend f32:$rs1), (fpextend f32:$rs2)))], - IIC_fpu_muld>; + IIC_fpu_muld>, + Requires<[HasFSMULD]>; def FDMULQ : F3_3<2, 0b110100, 0b001101110, (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fdmulq $rs1, $rs2, $rd", diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 37a1fdf4d770..b9647eaa3d51 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -20,10 +20,10 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/IR/Type.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Target/TargetInstrInfo.h" using namespace llvm; diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 2ac51263957e..8dd2569d10de 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -14,7 +14,7 @@ #ifndef LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H #define LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H -#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" #define GET_REGINFO_HEADER #include "SparcGenRegisterInfo.inc" diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp index daac56add87c..01545b8d20a0 100644 --- a/lib/Target/Sparc/SparcSubtarget.cpp +++ b/lib/Target/Sparc/SparcSubtarget.cpp @@ -33,17 +33,19 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, IsLeon = false; V8DeprecatedInsts = false; IsVIS = false; + IsVIS2 = false; + IsVIS3 = false; HasHardQuad = false; UsePopc = false; UseSoftFloat = false; + HasNoFSMULD = false; + HasNoFMULS = false; // Leon features HasLeonCasa = false; HasUmacSmac = false; PerformSDIVReplace = false; InsertNOPLoad = false; - FixFSMULD = false; - ReplaceFMULS = false; FixAllFDIVSQRT = false; DetectRoundChange = false; diff --git a/lib/Target/Sparc/SparcSubtarget.h b/lib/Target/Sparc/SparcSubtarget.h index d18139984b87..bcdc96e68103 100644 --- a/lib/Target/Sparc/SparcSubtarget.h +++ b/lib/Target/Sparc/SparcSubtarget.h @@ -18,9 +18,9 @@ #include "SparcISelLowering.h" #include "SparcInstrInfo.h" #include "llvm/CodeGen/SelectionDAGTargetInfo.h" +#include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DataLayout.h" -#include "llvm/Target/TargetFrameLowering.h" -#include "llvm/Target/TargetSubtargetInfo.h" #include <string> #define GET_SUBTARGETINFO_HEADER @@ -41,13 +41,13 @@ class SparcSubtarget : public SparcGenSubtargetInfo { bool HasHardQuad; bool UsePopc; bool UseSoftFloat; + bool HasNoFSMULD; + bool HasNoFMULS; // LEON features bool HasUmacSmac; bool HasLeonCasa; bool InsertNOPLoad; - bool FixFSMULD; - bool ReplaceFMULS; bool FixAllFDIVSQRT; bool DetectRoundChange; bool PerformSDIVReplace; @@ -87,14 +87,14 @@ public: bool hasHardQuad() const { return HasHardQuad; } bool usePopc() const { return UsePopc; } bool useSoftFloat() const { return UseSoftFloat; } + bool hasNoFSMULD() const { return HasNoFSMULD; } + bool hasNoFMULS() const { return HasNoFMULS; } // Leon options bool hasUmacSmac() const { return HasUmacSmac; } bool performSDIVReplace() const { return PerformSDIVReplace; } bool hasLeonCasa() const { return HasLeonCasa; } bool insertNOPLoad() const { return InsertNOPLoad; } - bool fixFSMULD() const { return FixFSMULD; } - bool replaceFMULS() const { return ReplaceFMULS; } bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; } bool detectRoundChange() const { return DetectRoundChange; } diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index c7a1ca262d2c..a0d40653fd9b 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -60,15 +60,39 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +// Code models. Some only make sense for 64-bit code. +// +// SunCC Reloc CodeModel Constraints +// abs32 Static Small text+data+bss linked below 2^32 bytes +// abs44 Static Medium text+data+bss linked below 2^44 bytes +// abs64 Static Large text smaller than 2^31 bytes +// pic13 PIC_ Small GOT < 2^13 bytes +// pic32 PIC_ Medium GOT < 2^32 bytes +// +// All code models require that the text segment is smaller than 2GB. +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM, + Reloc::Model RM, bool Is64Bit, + bool JIT) { + if (CM) + return *CM; + if (Is64Bit) { + if (JIT) + return CodeModel::Large; + return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; + } + return CodeModel::Small; +} + /// Create an ILP32 architecture model -SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, - StringRef CPU, StringRef FS, - const TargetOptions &Options, - Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL, bool is64bit) - : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), CM, OL), +SparcTargetMachine::SparcTargetMachine( + const Target &T, const Triple &TT, StringRef CPU, StringRef FS, + const TargetOptions &Options, Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) + : LLVMTargetMachine( + T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT), + OL), TLOF(make_unique<SparcELFTargetObjectFile>()), Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) { initAsmInfo(); @@ -149,14 +173,6 @@ void SparcPassConfig::addPreEmitPass(){ { addPass(new InsertNOPLoad()); } - if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD()) - { - addPass(new FixFSMULD()); - } - if (this->getSparcTargetMachine().getSubtargetImpl()->replaceFMULS()) - { - addPass(new ReplaceFMULS()); - } if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) { addPass(new DetectRoundChange()); } @@ -172,9 +188,9 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} void SparcV9TargetMachine::anchor() { } @@ -182,9 +198,9 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} void SparcelTargetMachine::anchor() {} @@ -192,6 +208,6 @@ SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index faf714cbe2c9..b0d76abeba7d 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -28,8 +28,8 @@ class SparcTargetMachine : public LLVMTargetMachine { public: SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL, bool is64bit); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT, bool is64bit); ~SparcTargetMachine() override; const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -53,8 +53,8 @@ class SparcV8TargetMachine : public SparcTargetMachine { public: SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; /// Sparc 64-bit target machine @@ -64,8 +64,8 @@ class SparcV9TargetMachine : public SparcTargetMachine { public: SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; class SparcelTargetMachine : public SparcTargetMachine { @@ -74,8 +74,8 @@ class SparcelTargetMachine : public SparcTargetMachine { public: SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; } // end namespace llvm diff --git a/lib/Target/Sparc/SparcTargetObjectFile.cpp b/lib/Target/Sparc/SparcTargetObjectFile.cpp index 2c040dce994b..d0db854f7849 100644 --- a/lib/Target/Sparc/SparcTargetObjectFile.cpp +++ b/lib/Target/Sparc/SparcTargetObjectFile.cpp @@ -11,7 +11,7 @@ #include "MCTargetDesc/SparcMCExpr.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" -#include "llvm/Target/TargetLowering.h" +#include "llvm/CodeGen/TargetLowering.h" using namespace llvm; diff --git a/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp b/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp index 66178acd52ba..d030bd9f232d 100644 --- a/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp +++ b/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp @@ -27,9 +27,9 @@ Target &llvm::getTheSparcelTarget() { extern "C" void LLVMInitializeSparcTargetInfo() { RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(getTheSparcTarget(), "sparc", - "Sparc"); - RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(getTheSparcV9Target(), - "sparcv9", "Sparc V9"); - RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(getTheSparcelTarget(), - "sparcel", "Sparc LE"); + "Sparc", "Sparc"); + RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y( + getTheSparcV9Target(), "sparcv9", "Sparc V9", "Sparc"); + RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z( + getTheSparcelTarget(), "sparcel", "Sparc LE", "Sparc"); } |