diff options
Diffstat (limited to 'lib/Target/SystemZ/SystemZInstrInfo.h')
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.h | 272 |
1 files changed, 129 insertions, 143 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.h b/lib/Target/SystemZ/SystemZInstrInfo.h index be4c8fe2add2..83009cb8d426 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/lib/Target/SystemZ/SystemZInstrInfo.h @@ -26,93 +26,94 @@ namespace llvm { class SystemZTargetMachine; namespace SystemZII { - enum { - // See comments in SystemZInstrFormats.td. - SimpleBDXLoad = (1 << 0), - SimpleBDXStore = (1 << 1), - Has20BitOffset = (1 << 2), - HasIndex = (1 << 3), - Is128Bit = (1 << 4), - AccessSizeMask = (31 << 5), - AccessSizeShift = 5, - CCValuesMask = (15 << 10), - CCValuesShift = 10, - CompareZeroCCMaskMask = (15 << 14), - CompareZeroCCMaskShift = 14, - CCMaskFirst = (1 << 18), - CCMaskLast = (1 << 19), - IsLogical = (1 << 20) - }; - static inline unsigned getAccessSize(unsigned int Flags) { - return (Flags & AccessSizeMask) >> AccessSizeShift; - } - static inline unsigned getCCValues(unsigned int Flags) { - return (Flags & CCValuesMask) >> CCValuesShift; - } - static inline unsigned getCompareZeroCCMask(unsigned int Flags) { - return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift; - } +enum { + // See comments in SystemZInstrFormats.td. + SimpleBDXLoad = (1 << 0), + SimpleBDXStore = (1 << 1), + Has20BitOffset = (1 << 2), + HasIndex = (1 << 3), + Is128Bit = (1 << 4), + AccessSizeMask = (31 << 5), + AccessSizeShift = 5, + CCValuesMask = (15 << 10), + CCValuesShift = 10, + CompareZeroCCMaskMask = (15 << 14), + CompareZeroCCMaskShift = 14, + CCMaskFirst = (1 << 18), + CCMaskLast = (1 << 19), + IsLogical = (1 << 20) +}; +static inline unsigned getAccessSize(unsigned int Flags) { + return (Flags & AccessSizeMask) >> AccessSizeShift; +} +static inline unsigned getCCValues(unsigned int Flags) { + return (Flags & CCValuesMask) >> CCValuesShift; +} +static inline unsigned getCompareZeroCCMask(unsigned int Flags) { + return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift; +} - // SystemZ MachineOperand target flags. - enum { - // Masks out the bits for the access model. - MO_SYMBOL_MODIFIER = (1 << 0), +// SystemZ MachineOperand target flags. +enum { + // Masks out the bits for the access model. + MO_SYMBOL_MODIFIER = (1 << 0), - // @GOT (aka @GOTENT) - MO_GOT = (1 << 0) - }; - // Classifies a branch. - enum BranchType { - // An instruction that branches on the current value of CC. - BranchNormal, + // @GOT (aka @GOTENT) + MO_GOT = (1 << 0) +}; +// Classifies a branch. +enum BranchType { + // An instruction that branches on the current value of CC. + BranchNormal, - // An instruction that peforms a 32-bit signed comparison and branches - // on the result. - BranchC, + // An instruction that peforms a 32-bit signed comparison and branches + // on the result. + BranchC, - // An instruction that peforms a 32-bit unsigned comparison and branches - // on the result. - BranchCL, + // An instruction that peforms a 32-bit unsigned comparison and branches + // on the result. + BranchCL, - // An instruction that peforms a 64-bit signed comparison and branches - // on the result. - BranchCG, + // An instruction that peforms a 64-bit signed comparison and branches + // on the result. + BranchCG, - // An instruction that peforms a 64-bit unsigned comparison and branches - // on the result. - BranchCLG, + // An instruction that peforms a 64-bit unsigned comparison and branches + // on the result. + BranchCLG, - // An instruction that decrements a 32-bit register and branches if - // the result is nonzero. - BranchCT, + // An instruction that decrements a 32-bit register and branches if + // the result is nonzero. + BranchCT, - // An instruction that decrements a 64-bit register and branches if - // the result is nonzero. - BranchCTG - }; - // Information about a branch instruction. - struct Branch { - // The type of the branch. - BranchType Type; + // An instruction that decrements a 64-bit register and branches if + // the result is nonzero. + BranchCTG +}; +// Information about a branch instruction. +struct Branch { + // The type of the branch. + BranchType Type; - // CCMASK_<N> is set if CC might be equal to N. - unsigned CCValid; + // CCMASK_<N> is set if CC might be equal to N. + unsigned CCValid; - // CCMASK_<N> is set if the branch should be taken when CC == N. - unsigned CCMask; + // CCMASK_<N> is set if the branch should be taken when CC == N. + unsigned CCMask; - // The target of the branch. - const MachineOperand *Target; + // The target of the branch. + const MachineOperand *Target; - Branch(BranchType type, unsigned ccValid, unsigned ccMask, - const MachineOperand *target) - : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {} - }; -} + Branch(BranchType type, unsigned ccValid, unsigned ccMask, + const MachineOperand *target) + : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {} +}; +} // end namespace SystemZII +class SystemZSubtarget; class SystemZInstrInfo : public SystemZGenInstrInfo { const SystemZRegisterInfo RI; - SystemZTargetMachine &TM; + SystemZSubtarget &STI; void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const; void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const; @@ -130,81 +131,66 @@ class SystemZInstrInfo : public SystemZGenInstrInfo { virtual void anchor(); public: - explicit SystemZInstrInfo(SystemZTargetMachine &TM); + explicit SystemZInstrInfo(SystemZSubtarget &STI); // Override TargetInstrInfo. - virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, - int &FrameIndex) const LLVM_OVERRIDE; - virtual unsigned isStoreToStackSlot(const MachineInstr *MI, - int &FrameIndex) const LLVM_OVERRIDE; - virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, - int &SrcFrameIndex) const LLVM_OVERRIDE; - virtual bool AnalyzeBranch(MachineBasicBlock &MBB, - MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl<MachineOperand> &Cond, - bool AllowModify) const LLVM_OVERRIDE; - virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE; - virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl<MachineOperand> &Cond, - DebugLoc DL) const LLVM_OVERRIDE; + unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const override; + unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const override; + bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, + int &SrcFrameIndex) const override; + bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, + bool AllowModify) const override; + unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + const SmallVectorImpl<MachineOperand> &Cond, + DebugLoc DL) const override; bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, - unsigned &SrcReg2, int &Mask, int &Value) const - LLVM_OVERRIDE; + unsigned &SrcReg2, int &Mask, int &Value) const override; bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, - const MachineRegisterInfo *MRI) const LLVM_OVERRIDE; - virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE; - virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, - unsigned ExtraPredCycles, - const BranchProbability &Probability) const - LLVM_OVERRIDE; - virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, - unsigned NumCyclesT, - unsigned ExtraPredCyclesT, - MachineBasicBlock &FMBB, - unsigned NumCyclesF, - unsigned ExtraPredCyclesF, - const BranchProbability &Probability) const - LLVM_OVERRIDE; - virtual bool - PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl<MachineOperand> &Pred) const - LLVM_OVERRIDE; - virtual void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const LLVM_OVERRIDE; - virtual void - storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const LLVM_OVERRIDE; - virtual void - loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const LLVM_OVERRIDE; - virtual MachineInstr * - convertToThreeAddress(MachineFunction::iterator &MFI, - MachineBasicBlock::iterator &MBBI, - LiveVariables *LV) const; - virtual MachineInstr * - foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, - const SmallVectorImpl<unsigned> &Ops, - int FrameIndex) const; - virtual MachineInstr * - foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, - const SmallVectorImpl<unsigned> &Ops, - MachineInstr* LoadMI) const; - virtual bool - expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE; - virtual bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const - LLVM_OVERRIDE; + const MachineRegisterInfo *MRI) const override; + bool isPredicable(MachineInstr *MI) const override; + bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, + unsigned ExtraPredCycles, + const BranchProbability &Probability) const override; + bool isProfitableToIfCvt(MachineBasicBlock &TMBB, + unsigned NumCyclesT, unsigned ExtraPredCyclesT, + MachineBasicBlock &FMBB, + unsigned NumCyclesF, unsigned ExtraPredCyclesF, + const BranchProbability &Probability) const override; + bool PredicateInstruction(MachineInstr *MI, + const SmallVectorImpl<MachineOperand> &Pred) const + override; + void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + DebugLoc DL, unsigned DestReg, unsigned SrcReg, + bool KillSrc) const override; + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, bool isKill, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, + MachineBasicBlock::iterator &MBBI, + LiveVariables *LV) const override; + MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, + const SmallVectorImpl<unsigned> &Ops, + int FrameIndex) const override; + MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, + const SmallVectorImpl<unsigned> &Ops, + MachineInstr* LoadMI) const override; + bool expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const override; + bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const + override; // Return the SystemZRegisterInfo, which this class owns. const SystemZRegisterInfo &getRegisterInfo() const { return RI; } @@ -244,7 +230,7 @@ public: // BRANCH exists, return the opcode for the latter, otherwise return 0. // MI, if nonnull, is the compare instruction. unsigned getCompareAndBranch(unsigned Opcode, - const MachineInstr *MI = 0) const; + const MachineInstr *MI = nullptr) const; // Emit code before MBBI in MI to move immediate value Value into // physical register Reg. |