diff options
Diffstat (limited to 'llvm/lib/Target/AVR/AVRInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/AVR/AVRInstrInfo.td | 70 |
1 files changed, 37 insertions, 33 deletions
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td index acf991dcfbb1..f03c254382b4 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -107,7 +107,9 @@ def imm_com8 : Operand<i8> { def ioaddr_XFORM : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()) - 0x20, SDLoc(N), MVT::i8); + uint8_t offset = Subtarget->getIORegisterOffset(); + return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()) - offset, + SDLoc(N), MVT::i8); }]>; def iobitpos8_XFORM : SDNodeXForm<imm, @@ -124,20 +126,23 @@ def iobitposn8_XFORM : SDNodeXForm<imm, def ioaddr8 : PatLeaf<(imm), [{ - uint64_t val = N->getZExtValue(); - return val >= 0x20 && val < 0x60; + uint8_t offset = Subtarget->getIORegisterOffset(); + uint64_t val = N->getZExtValue() - offset; + return val < 0x40; }], ioaddr_XFORM>; def lowioaddr8 : PatLeaf<(imm), [{ - uint64_t val = N->getZExtValue(); - return val >= 0x20 && val < 0x40; + uint8_t offset = Subtarget->getIORegisterOffset(); + uint64_t val = N->getZExtValue() - offset; + return val < 0x20; }], ioaddr_XFORM>; def ioaddr16 : PatLeaf<(imm), [{ - uint64_t val = N->getZExtValue(); - return val >= 0x20 && val < 0x5f; + uint8_t offset = Subtarget->getIORegisterOffset(); + uint64_t val = N->getZExtValue() - offset; + return val < 0x3f; }], ioaddr_XFORM>; def iobitpos8 : PatLeaf<(imm), @@ -188,6 +193,7 @@ def brtarget_13 : Operand<OtherVT> def call_target : Operand<iPTR> { let EncoderMethod = "encodeCallTarget"; + let DecoderMethod = "decodeCallTarget"; } // A 16-bit address (which can lead to an R_AVR_16 relocation). @@ -260,58 +266,58 @@ def LDDSTDPtrReg : Operand<i16> //===----------------------------------------------------------------------===// def HasSRAM : Predicate<"Subtarget->hasSRAM()">, - AssemblerPredicate<"FeatureSRAM">; + AssemblerPredicate<(all_of FeatureSRAM)>; def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">, - AssemblerPredicate<"FeatureJMPCALL">; + AssemblerPredicate<(all_of FeatureJMPCALL)>; def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">, - AssemblerPredicate<"FeatureIJMPCALL">; + AssemblerPredicate<(all_of FeatureIJMPCALL)>; def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">, - AssemblerPredicate<"FeatureEIJMPCALL">; + AssemblerPredicate<(all_of FeatureEIJMPCALL)>; def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">, - AssemblerPredicate<"FeatureADDSUBIW">; + AssemblerPredicate<(all_of FeatureADDSUBIW)>; def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">, - AssemblerPredicate<"FeatureSmallStack">; + AssemblerPredicate<(all_of FeatureSmallStack)>; def HasMOVW : Predicate<"Subtarget->hasMOVW()">, - AssemblerPredicate<"FeatureMOVW">; + AssemblerPredicate<(all_of FeatureMOVW)>; def HasLPM : Predicate<"Subtarget->hasLPM()">, - AssemblerPredicate<"FeatureLPM">; + AssemblerPredicate<(all_of FeatureLPM)>; def HasLPMX : Predicate<"Subtarget->hasLPMX()">, - AssemblerPredicate<"FeatureLPMX">; + AssemblerPredicate<(all_of FeatureLPMX)>; def HasELPM : Predicate<"Subtarget->hasELPM()">, - AssemblerPredicate<"FeatureELPM">; + AssemblerPredicate<(all_of FeatureELPM)>; def HasELPMX : Predicate<"Subtarget->hasELPMX()">, - AssemblerPredicate<"FeatureELPMX">; + AssemblerPredicate<(all_of FeatureELPMX)>; def HasSPM : Predicate<"Subtarget->hasSPM()">, - AssemblerPredicate<"FeatureSPM">; + AssemblerPredicate<(all_of FeatureSPM)>; def HasSPMX : Predicate<"Subtarget->hasSPMX()">, - AssemblerPredicate<"FeatureSPMX">; + AssemblerPredicate<(all_of FeatureSPMX)>; def HasDES : Predicate<"Subtarget->hasDES()">, - AssemblerPredicate<"FeatureDES">; + AssemblerPredicate<(all_of FeatureDES)>; def SupportsRMW : Predicate<"Subtarget->supportsRMW()">, - AssemblerPredicate<"FeatureRMW">; + AssemblerPredicate<(all_of FeatureRMW)>; def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">, - AssemblerPredicate<"FeatureMultiplication">; + AssemblerPredicate<(all_of FeatureMultiplication)>; def HasBREAK : Predicate<"Subtarget->hasBREAK()">, - AssemblerPredicate<"FeatureBREAK">; + AssemblerPredicate<(all_of FeatureBREAK)>; def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">, - AssemblerPredicate<"FeatureTinyEncoding">; + AssemblerPredicate<(all_of FeatureTinyEncoding)>; // AVR specific condition code. These correspond to AVR_*_COND in @@ -555,7 +561,7 @@ Defs = [R1, R0, SREG] in def MULSRdRr : FMUL2RdRr<0, (outs), - (ins GPR8:$lhs, GPR8:$rhs), + (ins LD8:$lhs, LD8:$rhs), "muls\t$lhs, $rhs", []>, Requires<[SupportsMultiplication]>; @@ -563,28 +569,28 @@ Defs = [R1, R0, SREG] in def MULSURdRr : FMUL2RdRr<1, (outs), - (ins GPR8:$lhs, GPR8:$rhs), + (ins LD8lo:$lhs, LD8lo:$rhs), "mulsu\t$lhs, $rhs", []>, Requires<[SupportsMultiplication]>; def FMUL : FFMULRdRr<0b01, (outs), - (ins GPR8:$lhs, GPR8:$rhs), + (ins LD8lo:$lhs, LD8lo:$rhs), "fmul\t$lhs, $rhs", []>, Requires<[SupportsMultiplication]>; def FMULS : FFMULRdRr<0b10, (outs), - (ins GPR8:$lhs, GPR8:$rhs), + (ins LD8lo:$lhs, LD8lo:$rhs), "fmuls\t$lhs, $rhs", []>, Requires<[SupportsMultiplication]>; def FMULSU : FFMULRdRr<0b11, (outs), - (ins GPR8:$lhs, GPR8:$rhs), + (ins LD8lo:$lhs, LD8lo:$rhs), "fmulsu\t$lhs, $rhs", []>, Requires<[SupportsMultiplication]>; @@ -840,7 +846,7 @@ let isCall = 1 in //===----------------------------------------------------------------------===// let isTerminator = 1, isReturn = 1, -isBarrier = 1 in +isBarrier = 1 in { def RET : F16<0b1001010100001000, (outs), @@ -2042,8 +2048,6 @@ def : Pat<(add i16:$src1, imm:$src2), (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>; def : Pat<(addc i16:$src1, imm:$src2), (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>; -def : Pat<(adde i16:$src1, imm:$src2), - (SBCIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>; def : Pat<(add i8:$src1, imm:$src2), (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>; |