diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 165 |
1 files changed, 142 insertions, 23 deletions
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index f8dc0547baad..7514d0e67744 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -10,13 +10,13 @@ // //===----------------------------------------------------------------------===// -#include "MCTargetDesc/HexagonMCTargetDesc.h" -#include "HexagonDepArch.h" +#include "HexagonArch.h" #include "HexagonTargetStreamer.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "MCTargetDesc/HexagonMCAsmInfo.h" #include "MCTargetDesc/HexagonMCELFStreamer.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" #include "TargetInfo/HexagonTargetInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" @@ -37,8 +37,10 @@ #include "llvm/Support/raw_ostream.h" #include <cassert> #include <cstdint> +#include <mutex> #include <new> #include <string> +#include <unordered_map> using namespace llvm; @@ -72,6 +74,10 @@ cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"), cl::init(false)); cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"), cl::init(false)); +cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"), + cl::init(false)); +cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"), + cl::init(false)); cl::opt<Hexagon::ArchEnum> EnableHVX("mhvx", @@ -81,6 +87,7 @@ cl::opt<Hexagon::ArchEnum> clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), + clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"), // Sentinel for no value specified. clEnumValN(Hexagon::ArchEnum::Generic, "", "")), // Sentinel for flag not present. @@ -107,14 +114,22 @@ static StringRef HexagonGetArchVariant() { return "hexagonv65"; if (MV66) return "hexagonv66"; + if (MV67) + return "hexagonv67"; + if (MV67T) + return "hexagonv67t"; return ""; } StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) { StringRef ArchV = HexagonGetArchVariant(); if (!ArchV.empty() && !CPU.empty()) { - if (ArchV != CPU) - report_fatal_error("conflicting architectures specified."); + // Tiny cores have a "t" suffix that is discarded when creating a secondary + // non-tiny subtarget. See: addArchSubtarget + std::pair<StringRef,StringRef> ArchP = ArchV.split('t'); + std::pair<StringRef,StringRef> CPUP = CPU.split('t'); + if (!ArchP.first.equals(CPUP.first)) + report_fatal_error("conflicting architectures specified."); return CPU; } if (ArchV.empty()) { @@ -127,6 +142,56 @@ StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) { unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; } +unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) { + enum { + CVI_NONE = 0, + CVI_XLANE = 1 << 0, + CVI_SHIFT = 1 << 1, + CVI_MPY0 = 1 << 2, + CVI_MPY1 = 1 << 3, + CVI_ZW = 1 << 4 + }; + + if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL || + ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM) + return (*Lanes = 4, CVI_XLANE); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 && + ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF) + return (*Lanes = 2, CVI_XLANE | CVI_MPY0); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01) + return (*Lanes = 2, CVI_MPY0); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF) + return (*Lanes = 2, CVI_XLANE); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE && + ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT && + ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 && + ItinUnits & HexagonItinerariesV62FU::CVI_MPY1) + return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE && + ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT) + return (*Lanes = 1, CVI_XLANE | CVI_SHIFT); + else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 && + ItinUnits & HexagonItinerariesV62FU::CVI_MPY1) + return (*Lanes = 1, CVI_MPY0 | CVI_MPY1); + else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW) + return (*Lanes = 1, CVI_ZW); + else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE) + return (*Lanes = 1, CVI_XLANE); + else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT) + return (*Lanes = 1, CVI_SHIFT); + + return (*Lanes = 0, CVI_NONE); +} + + +namespace llvm { +namespace HexagonFUnits { +bool isSlot0Only(unsigned units) { + return HexagonItinerariesV62FU::SLOT0 == units; +} +} // namespace HexagonFUnits +} // namespace llvm + namespace { class HexagonTargetAsmStreamer : public HexagonTargetStreamer { @@ -186,7 +251,7 @@ public: } - void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, + void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize) override { HexagonMCELFStreamer &HexagonELFStreamer = @@ -195,7 +260,7 @@ public: AccessSize); } - void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, + void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize) override { HexagonMCELFStreamer &HexagonELFStreamer = @@ -225,9 +290,8 @@ static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). - MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(nullptr, - MRI.getDwarfRegNum(Hexagon::R30, true), 0); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( + nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0); MAI->addInitialFrameState(Inst); return MAI; @@ -296,40 +360,51 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { case Hexagon::ArchEnum::V66: Result.push_back("+hvxv66"); break; + case Hexagon::ArchEnum::V67: + Result.push_back("+hvxv67"); + break; case Hexagon::ArchEnum::Generic:{ Result.push_back(StringSwitch<StringRef>(CPU) .Case("hexagonv60", "+hvxv60") .Case("hexagonv62", "+hvxv62") .Case("hexagonv65", "+hvxv65") - .Case("hexagonv66", "+hvxv66")); + .Case("hexagonv66", "+hvxv66") + .Case("hexagonv67", "+hvxv67") + .Case("hexagonv67t", "+hvxv67")); break; } case Hexagon::ArchEnum::NoArch: - // Sentinal if -mhvx isn't specified + // Sentinel if -mhvx isn't specified break; } return join(Result.begin(), Result.end(), ","); } } -static bool isCPUValid(std::string CPU) -{ - std::vector<std::string> table { - "generic", "hexagonv5", "hexagonv55", "hexagonv60", - "hexagonv62", "hexagonv65", "hexagonv66", - }; - - return std::find(table.begin(), table.end(), CPU) != table.end(); +static bool isCPUValid(const std::string &CPU) { + return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend(); } namespace { std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU, StringRef FS) { std::pair<std::string, std::string> Result; - Result.first = Hexagon_MC::selectHexagonCPU(CPU); + Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU)); Result.second = selectHexagonFS(Result.first, FS); return Result; } +std::mutex ArchSubtargetMutex; +std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>> + ArchSubtarget; +} // namespace + +MCSubtargetInfo const * +Hexagon_MC::getArchSubtarget(MCSubtargetInfo const *STI) { + std::lock_guard<std::mutex> Lock(ArchSubtargetMutex); + auto Existing = ArchSubtarget.find(std::string(STI->getCPU())); + if (Existing == ArchSubtarget.end()) + return nullptr; + return Existing->second.get(); } FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { @@ -338,7 +413,8 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { // turns on hvxvNN, corresponding to the existing ArchVNN. FeatureBitset FB = S; unsigned CpuArch = ArchV5; - for (unsigned F : {ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) { + for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, + ArchV5}) { if (!FB.test(F)) continue; CpuArch = F; @@ -353,7 +429,7 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { } bool HasHvxVer = false; for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, - ExtensionHVXV66}) { + ExtensionHVXV66, ExtensionHVXV67}) { if (!FB.test(F)) continue; HasHvxVer = true; @@ -366,6 +442,9 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { // HasHvxVer is false, and UseHvx is true. switch (CpuArch) { + case ArchV67: + FB.set(ExtensionHVXV67); + LLVM_FALLTHROUGH; case ArchV66: FB.set(ExtensionHVXV66); LLVM_FALLTHROUGH; @@ -389,22 +468,52 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPUName = Features.first; StringRef ArchFS = Features.second; + MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); + if (X != nullptr && (CPUName == "hexagonv67t")) + addArchSubtarget(X, ArchFS); + + if (CPU.equals("help")) + exit(0); + if (!isCPUValid(CPUName.str())) { errs() << "error: invalid CPU \"" << CPUName.str().c_str() << "\" specified\n"; return nullptr; } - MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); if (HexagonDisableDuplex) { llvm::FeatureBitset Features = X->getFeatureBits(); X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex)); } X->setFeatureBits(completeHVXFeatures(X->getFeatureBits())); + + // The Z-buffer instructions are grandfathered in for current + // architectures but omitted for new ones. Future instruction + // sets may introduce new/conflicting z-buffer instructions. + const bool ZRegOnDefault = + (CPUName == "hexagonv67") || (CPUName == "hexagonv66"); + if (ZRegOnDefault) { + llvm::FeatureBitset Features = X->getFeatureBits(); + X->setFeatureBits(Features.set(Hexagon::ExtensionZReg)); + } + return X; } +void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI, + StringRef FS) { + assert(STI != nullptr); + if (STI->getCPU().contains("t")) { + auto ArchSTI = createHexagonMCSubtargetInfo( + STI->getTargetTriple(), + STI->getCPU().substr(0, STI->getCPU().size() - 1), FS); + std::lock_guard<std::mutex> Lock(ArchSubtargetMutex); + ArchSubtarget[std::string(STI->getCPU())] = + std::unique_ptr<MCSubtargetInfo const>(ArchSTI); + } +} + unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { static std::map<StringRef,unsigned> ElfFlags = { {"hexagonv5", ELF::EF_HEXAGON_MACH_V5}, @@ -413,6 +522,8 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { {"hexagonv62", ELF::EF_HEXAGON_MACH_V62}, {"hexagonv65", ELF::EF_HEXAGON_MACH_V65}, {"hexagonv66", ELF::EF_HEXAGON_MACH_V66}, + {"hexagonv67", ELF::EF_HEXAGON_MACH_V67}, + {"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T}, }; auto F = ElfFlags.find(STI.getCPU()); @@ -420,6 +531,10 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { return F->second; } +llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() { + return makeArrayRef(VectRegRev); +} + namespace { class HexagonMCInstrAnalysis : public MCInstrAnalysis { public: @@ -437,6 +552,10 @@ public: bool evaluateBranch(MCInst const &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override { + if (!(isCall(Inst) || isUnconditionalBranch(Inst) || + isConditionalBranch(Inst))) + return false; + //assert(!HexagonMCInstrInfo::isBundle(Inst)); if(!HexagonMCInstrInfo::isExtendable(*Info, Inst)) return false; |