diff options
Diffstat (limited to 'llvm/lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 43 |
1 files changed, 36 insertions, 7 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index cc15949b0d57..306289d56e4b 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -83,6 +83,10 @@ let usesCustomInserter = 1 in { def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; + def ATOMIC_LOAD_MIN_I64 : Atomic2Ops<atomic_load_min_64, GPR64>; + def ATOMIC_LOAD_MAX_I64 : Atomic2Ops<atomic_load_max_64, GPR64>; + def ATOMIC_LOAD_UMIN_I64 : Atomic2Ops<atomic_load_umin_64, GPR64>; + def ATOMIC_LOAD_UMAX_I64 : Atomic2Ops<atomic_load_umax_64, GPR64>; } def ATOMIC_LOAD_ADD_I64_POSTRA : Atomic2OpsPostRA<GPR64>; @@ -96,6 +100,11 @@ def ATOMIC_SWAP_I64_POSTRA : Atomic2OpsPostRA<GPR64>; def ATOMIC_CMP_SWAP_I64_POSTRA : AtomicCmpSwapPostRA<GPR64>; +def ATOMIC_LOAD_MIN_I64_POSTRA : Atomic2OpsPostRA<GPR64>; +def ATOMIC_LOAD_MAX_I64_POSTRA : Atomic2OpsPostRA<GPR64>; +def ATOMIC_LOAD_UMIN_I64_POSTRA : Atomic2OpsPostRA<GPR64>; +def ATOMIC_LOAD_UMAX_I64_POSTRA : Atomic2OpsPostRA<GPR64>; + /// Pseudo instructions for loading and storing accumulator registers. let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { def LOAD_ACC128 : Load<"", ACC128>; @@ -395,11 +404,11 @@ let AdditionalPredicates = [NotInMicroMips] in { } let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in { - def DEXT64_32 : InstSE<(outs GPR64Opnd:$rt), - (ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, - uimm5_plus1:$size), - "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">, - EXT_FM<3>, ISA_MIPS64R2; + def DEXT64_32 + : InstSE<(outs GPR64Opnd:$rt), + (ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, uimm5_plus1:$size), + "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">, + EXT_FM<3>, ISA_MIPS64R2; } let isCodeGenOnly = 1, rs = 0, shamt = 0 in { @@ -586,6 +595,24 @@ def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>, ASE_CNMIPS; } +// Cavium Octeon+ cnMIPS instructions +let DecoderNamespace = "CnMipsP", + // FIXME: The lack of HasStdEnc is probably a bug + EncodingPredicates = []<Predicate> in { + +class Saa<string opstr>: + InstSE<(outs), (ins GPR64Opnd:$rt, GPR64Opnd:$rs), + !strconcat(opstr, "\t$rt, (${rs})"), [], NoItinerary, FrmR, opstr>; + +def SAA : Saa<"saa">, SAA_FM<0x18>, ASE_CNMIPSP; +def SAAD : Saa<"saad">, SAA_FM<0x19>, ASE_CNMIPSP; + +def SaaAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), + "saa\t$rt, $addr">, ASE_CNMIPSP; +def SaadAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), + "saad\t$rt, $addr">, ASE_CNMIPSP; +} + } /// Move between CPU and coprocessor registers @@ -1027,8 +1054,10 @@ let AdditionalPredicates = [NotInMicroMips] in { (DMTGC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>, ISA_MIPS64R5, ASE_VIRT; } -def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; -def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; +def : MipsInstAlias<"dmfc2 $rt, $rd", + (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; +def : MipsInstAlias<"dmtc2 $rt, $rd", + (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS; def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS; |