diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrQPX.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrQPX.td | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrQPX.td b/llvm/lib/Target/PowerPC/PPCInstrQPX.td index d67041d46d9f..2265af2815cb 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrQPX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrQPX.td @@ -1,9 +1,9 @@ //===- PPCInstrQPX.td - The PowerPC QPX Extension --*- tablegen -*-===// -// +// // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// +// //===----------------------------------------------------------------------===// // // This file describes the QPX extension to the PowerPC instruction set. @@ -101,7 +101,7 @@ let FastIselShouldIgnore = 1 in // FastIsel should ignore all u12 instrs. //===----------------------------------------------------------------------===// // Instruction Definitions. -def HasQPX : Predicate<"PPCSubTarget->hasQPX()">; +def HasQPX : Predicate<"Subtarget->hasQPX()">; let Predicates = [HasQPX] in { let DecoderNamespace = "QPX" in { let hasSideEffects = 0 in { // QPX instructions don't have side effects. @@ -167,48 +167,48 @@ let Uses = [RM] in { // Multiply-add instructions def QVFMADD : AForm_1<4, 29, - (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC), + (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB), "qvfmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC, v4f64:$FRB))]>; let isCodeGenOnly = 1 in def QVFMADDS : QPXA1_Int<0, 29, "qvfmadds", int_ppc_qpx_qvfmadds>; def QVFMADDSs : AForm_1<0, 29, - (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC), + (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB), "qvfmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB))]>; def QVFNMADD : AForm_1<4, 31, - (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC), + (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB), "qvfnmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC, v4f64:$FRB)))]>; let isCodeGenOnly = 1 in def QVFNMADDS : QPXA1_Int<0, 31, "qvfnmadds", int_ppc_qpx_qvfnmadds>; def QVFNMADDSs : AForm_1<0, 31, - (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC), + (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB), "qvfnmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB)))]>; def QVFMSUB : AForm_1<4, 28, - (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC), + (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB), "qvfmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC, (fneg v4f64:$FRB)))]>; let isCodeGenOnly = 1 in def QVFMSUBS : QPXA1_Int<0, 28, "qvfmsubs", int_ppc_qpx_qvfmsubs>; def QVFMSUBSs : AForm_1<0, 28, - (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC), + (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB), "qvfmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, (fneg v4f32:$FRB)))]>; def QVFNMSUB : AForm_1<4, 30, - (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC), + (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB), "qvfnmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC, (fneg v4f64:$FRB))))]>; let isCodeGenOnly = 1 in def QVFNMSUBS : QPXA1_Int<0, 30, "qvfnmsubs", int_ppc_qpx_qvfnmsubs>; def QVFNMSUBSs : AForm_1<0, 30, - (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC), + (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB), "qvfnmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC, (fneg v4f32:$FRB))))]>; @@ -899,13 +899,13 @@ def : Pat<(int_ppc_qpx_qvfmul v4f64:$A, v4f64:$B), // Additional QVFNMSUB patterns: -a*c + b == -(a*c - b) def : Pat<(fma (fneg v4f64:$A), v4f64:$C, v4f64:$B), - (QVFNMSUB $A, $B, $C)>; + (QVFNMSUB $A, $C, $B)>; def : Pat<(fma v4f64:$A, (fneg v4f64:$C), v4f64:$B), - (QVFNMSUB $A, $B, $C)>; + (QVFNMSUB $A, $C, $B)>; def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B), - (QVFNMSUBSs $A, $B, $C)>; + (QVFNMSUBSs $A, $C, $B)>; def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B), - (QVFNMSUBSs $A, $B, $C)>; + (QVFNMSUBSs $A, $C, $B)>; def : Pat<(int_ppc_qpx_qvfmadd v4f64:$A, v4f64:$B, v4f64:$C), (QVFMADD $A, $B, $C)>; @@ -1210,4 +1210,3 @@ def : Pat<(fmaxnum v4f32:$FRA, v4f32:$FRB), (QVFTSTNANbs $FRB, $FRB), (i32 7)), $FRB, $FRA)>; } - |