diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCV.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 142 |
1 files changed, 126 insertions, 16 deletions
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 82afa13aece3..f0583f691936 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -16,21 +16,21 @@ def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true", "'M' (Integer Multiplication and Division)">; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, - AssemblerPredicate<"FeatureStdExtM", + AssemblerPredicate<(all_of FeatureStdExtM), "'M' (Integer Multiplication and Division)">; def FeatureStdExtA : SubtargetFeature<"a", "HasStdExtA", "true", "'A' (Atomic Instructions)">; def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, - AssemblerPredicate<"FeatureStdExtA", + AssemblerPredicate<(all_of FeatureStdExtA), "'A' (Atomic Instructions)">; def FeatureStdExtF : SubtargetFeature<"f", "HasStdExtF", "true", "'F' (Single-Precision Floating-Point)">; def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, - AssemblerPredicate<"FeatureStdExtF", + AssemblerPredicate<(all_of FeatureStdExtF), "'F' (Single-Precision Floating-Point)">; def FeatureStdExtD @@ -38,30 +38,130 @@ def FeatureStdExtD "'D' (Double-Precision Floating-Point)", [FeatureStdExtF]>; def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, - AssemblerPredicate<"FeatureStdExtD", + AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; def FeatureStdExtC : SubtargetFeature<"c", "HasStdExtC", "true", "'C' (Compressed Instructions)">; def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, - AssemblerPredicate<"FeatureStdExtC", + AssemblerPredicate<(all_of FeatureStdExtC), "'C' (Compressed Instructions)">; -def FeatureRVCHints - : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", - "Enable RVC Hint Instructions.">; +def FeatureExtZbb + : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true", + "'Zbb' (Base 'B' Instructions)">; +def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, + AssemblerPredicate<(all_of FeatureExtZbb), + "'Zbb' (Base 'B' Instructions)">; + +def FeatureExtZbc + : SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true", + "'Zbc' (Carry-Less 'B' Instructions)">; +def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, + AssemblerPredicate<(all_of FeatureExtZbc), + "'Zbc' (Carry-Less 'B' Instructions)">; + +def FeatureExtZbe + : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", + "'Zbe' (Extract-Deposit 'B' Instructions)">; +def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, + AssemblerPredicate<(all_of FeatureExtZbe), + "'Zbe' (Extract-Deposit 'B' Instructions)">; + +def FeatureExtZbf + : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", + "'Zbf' (Bit-Field 'B' Instructions)">; +def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, + AssemblerPredicate<(all_of FeatureExtZbf), + "'Zbf' (Bit-Field 'B' Instructions)">; + +def FeatureExtZbm + : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", + "'Zbm' (Matrix 'B' Instructions)">; +def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, + AssemblerPredicate<(all_of FeatureExtZbm), + "'Zbm' (Matrix 'B' Instructions)">; + +def FeatureExtZbp + : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", + "'Zbp' (Permutation 'B' Instructions)">; +def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, + AssemblerPredicate<(all_of FeatureExtZbp), + "'Zbp' (Permutation 'B' Instructions)">; + +def FeatureExtZbr + : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", + "'Zbr' (Polynomial Reduction 'B' Instructions)">; +def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, + AssemblerPredicate<(all_of FeatureExtZbr), + "'Zbr' (Polynomial Reduction 'B' Instructions)">; + +def FeatureExtZbs + : SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true", + "'Zbs' (Single-Bit 'B' Instructions)">; +def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, + AssemblerPredicate<(all_of FeatureExtZbs), + "'Zbs' (Single-Bit 'B' Instructions)">; + +def FeatureExtZbt + : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", + "'Zbt' (Ternary 'B' Instructions)">; +def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, + AssemblerPredicate<(all_of FeatureExtZbt), + "'Zbt' (Ternary 'B' Instructions)">; + +// Some instructions belong to both the basic and the permutation +// subextensions. They should be enabled if either has been specified. +def HasStdExtZbbOrZbp + : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, + AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp)>; + +def FeatureExtZbproposedc + : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true", + "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; +def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">, + AssemblerPredicate<(all_of FeatureExtZbproposedc), + "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; + +def FeatureStdExtB + : SubtargetFeature<"experimental-b", "HasStdExtB", "true", + "'B' (Bit Manipulation Instructions)", + [FeatureExtZbb, + FeatureExtZbc, + FeatureExtZbe, + FeatureExtZbf, + FeatureExtZbm, + FeatureExtZbp, + FeatureExtZbr, + FeatureExtZbs, + FeatureExtZbt]>; +def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, + AssemblerPredicate<(all_of FeatureStdExtB), + "'B' (Bit Manipulation Instructions)">; + +def FeatureNoRVCHints + : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", + "Disable RVC Hint Instructions.">; def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, - AssemblerPredicate<"FeatureRVCHints", - "RVC Hint Instructions">; + AssemblerPredicate<(all_of(not FeatureNoRVCHints)), + "RVC Hint Instructions">; + +def FeatureStdExtV + : SubtargetFeature<"experimental-v", "HasStdExtV", "true", + "'V' (Vector Instructions)", + [FeatureStdExtF]>; +def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, + AssemblerPredicate<(all_of FeatureStdExtV), + "'V' (Vector Instructions)">; def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, - AssemblerPredicate<"Feature64Bit", + AssemblerPredicate<(all_of Feature64Bit), "RV64I Base Instruction Set">; def IsRV32 : Predicate<"!Subtarget->is64Bit()">, - AssemblerPredicate<"!Feature64Bit", + AssemblerPredicate<(all_of (not Feature64Bit)), "RV32I Base Instruction Set">; def RV64 : HwMode<"+64bit">; @@ -71,7 +171,7 @@ def FeatureRV32E : SubtargetFeature<"e", "IsRV32E", "true", "Implements RV32E (provides 16 rather than 32 GPRs)">; def IsRV32E : Predicate<"Subtarget->isRV32E()">, - AssemblerPredicate<"FeatureRV32E">; + AssemblerPredicate<(all_of FeatureRV32E)>; def FeatureRelax : SubtargetFeature<"relax", "EnableLinkerRelax", "true", @@ -82,6 +182,9 @@ foreach i = {1-31} in SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", "true", "Reserve X"#i>; +def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", + "true", "Enable save/restore.">; + //===----------------------------------------------------------------------===// // Named operands for CSR instructions. //===----------------------------------------------------------------------===// @@ -92,19 +195,26 @@ include "RISCVSystemOperands.td" // Registers, calling conventions, instruction descriptions. //===----------------------------------------------------------------------===// +include "RISCVSchedule.td" include "RISCVRegisterInfo.td" include "RISCVCallingConv.td" include "RISCVInstrInfo.td" include "RISCVRegisterBanks.td" +include "RISCVSchedRocket32.td" +include "RISCVSchedRocket64.td" //===----------------------------------------------------------------------===// // RISC-V processors supported. //===----------------------------------------------------------------------===// -def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>; +def : ProcessorModel<"generic-rv32", NoSchedModel, []>; + +def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; + +def : ProcessorModel<"rocket-rv32", Rocket32Model, []>; + +def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit]>; -def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit, - FeatureRVCHints]>; //===----------------------------------------------------------------------===// // Define the RISC-V target. |