diff options
Diffstat (limited to 'llvm/lib/Target/Sparc')
28 files changed, 163 insertions, 153 deletions
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 2d3137f38821..16e159621672 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -68,6 +68,8 @@ class SparcAsmParser : public MCTargetAsmParser { uint64_t &ErrorInfo, bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool ParseDirective(AsmToken DirectiveID) override; @@ -600,7 +602,7 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } for (const MCInst &I : Instructions) { - Out.EmitInstruction(I, getSTI()); + Out.emitInstruction(I, getSTI()); } return false; } @@ -630,20 +632,29 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool SparcAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) + return Error(StartLoc, "invalid register name"); + return false; +} + +OperandMatchResultTy SparcAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { const AsmToken &Tok = Parser.getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); RegNo = 0; if (getLexer().getKind() != AsmToken::Percent) - return false; + return MatchOperand_Success; Parser.Lex(); unsigned regKind = SparcOperand::rk_None; if (matchRegisterName(Tok, RegNo, regKind)) { Parser.Lex(); - return false; + return MatchOperand_Success; } - return Error(StartLoc, "invalid register name"); + getLexer().UnLex(Tok); + return MatchOperand_NoMatch; } static void applyMnemonicAliases(StringRef &Mnemonic, diff --git a/llvm/lib/Target/Sparc/LeonFeatures.td b/llvm/lib/Target/Sparc/LeonFeatures.td index e0ea4e9c7645..75273eff1868 100755 --- a/llvm/lib/Target/Sparc/LeonFeatures.td +++ b/llvm/lib/Target/Sparc/LeonFeatures.td @@ -16,9 +16,9 @@ //support to casa instruction; for leon3 subtarget only def UMACSMACSupport : SubtargetFeature< - "hasumacsmac", - "HasUmacSmac", - "true", + "hasumacsmac", + "HasUmacSmac", + "true", "Enable UMAC and SMAC for LEON3 and LEON4 processors" >; @@ -30,9 +30,9 @@ def UMACSMACSupport : SubtargetFeature< //support to casa instruction; for leon3 subtarget only def LeonCASA : SubtargetFeature< - "hasleoncasa", - "HasLeonCasa", - "true", + "hasleoncasa", + "HasLeonCasa", + "true", "Enable CASA instruction for LEON3 and LEON4 processors" >; @@ -40,7 +40,7 @@ def InsertNOPLoad: SubtargetFeature< "insertnopload", "InsertNOPLoad", "true", - "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" + "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" >; def DetectRoundChange : SubtargetFeature< @@ -55,7 +55,7 @@ def FixAllFDIVSQRT : SubtargetFeature< "fixallfdivsqrt", "FixAllFDIVSQRT", "true", - "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store" + "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store" >; def LeonCycleCounter diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index 2e8fa0dbaf4c..83c44e0682ce 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -15,6 +15,7 @@ #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCValue.h" +#include "llvm/Support/EndianStream.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -270,8 +271,8 @@ namespace { llvm_unreachable("fixupNeedsRelaxation() unimplemented"); return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override { + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override { // FIXME. llvm_unreachable("relaxInstruction() unimplemented"); } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp index 8a673de69911..f6728a070736 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp @@ -46,7 +46,8 @@ void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const void SparcInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) { - if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) + if (!printAliasInstr(MI, Address, STI, O) && + !printSparcAliasInstr(MI, STI, O)) printInstruction(MI, Address, STI, O); printAnnotation(O, Annot); } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h index cb85fe98ed42..11587f165ef2 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h @@ -33,10 +33,10 @@ public: // Autogenerated by tblgen. void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, + bool printAliasInstr(const MCInst *MI, uint64_t Address, + const MCSubtargetInfo &STI, raw_ostream &O); + void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 1a2a040990ae..c5cc2ea34bb7 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -42,8 +42,6 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) { SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; - - UseIntegratedAssembler = true; } const MCExpr* diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 7eb27f55baac..fb2bcdc6c91b 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -37,7 +37,7 @@ static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, const MCTargetOptions &Options) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); return MAI; } @@ -47,7 +47,7 @@ static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, const MCTargetOptions &Options) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 2047); MAI->addInitialFrameState(Inst); return MAI; } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h index e5699bb1c133..f360946b9a79 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -27,10 +27,6 @@ class MCRegisterInfo; class MCSubtargetInfo; class MCTargetOptions; class Target; -class Triple; -class StringRef; -class raw_pwrite_stream; -class raw_ostream; MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h index 967c463f5281..aabc4f149829 100644 --- a/llvm/lib/Target/Sparc/Sparc.h +++ b/llvm/lib/Target/Sparc/Sparc.h @@ -21,7 +21,6 @@ namespace llvm { class FunctionPass; class SparcTargetMachine; - class formatted_raw_ostream; class AsmPrinter; class MCInst; class MachineInstr; diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index ca6147edc46b..da95602309a1 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -150,7 +150,7 @@ def : Processor<"ut699", LEON3Itineraries, [FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>; // LEON3 FT (GR712RC). Provides features for the GR712RC processor. -// - covers all the erratum fixed for LEON3 and support for the CASA instruction. +// - covers all the erratum fixed for LEON3 and support for the CASA instruction. def : Processor<"gr712rc", LEON3Itineraries, [FeatureLeon, LeonCASA]>; @@ -158,9 +158,9 @@ def : Processor<"gr712rc", LEON3Itineraries, def : Processor<"leon4", LEON4Itineraries, [FeatureLeon, UMACSMACSupport, LeonCASA]>; -// LEON 4 FT (GR740) +// LEON 4 FT (GR740) // TO DO: Place-holder: Processor specific features will be added *very* soon here. -def : Processor<"gr740", LEON4Itineraries, +def : Processor<"gr740", LEON4Itineraries, [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter, FeaturePWRPSR]>; diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index f0caf3bc284f..069e43c6f544 100644 --- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -52,8 +52,8 @@ namespace { void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = nullptr); - void EmitFunctionBodyStart() override; - void EmitInstruction(const MachineInstr *MI) override; + void emitFunctionBodyStart() override; + void emitInstruction(const MachineInstr *MI) override; static const char *getRegisterName(unsigned RegNo) { return SparcInstPrinter::getRegisterName(RegNo); @@ -108,7 +108,7 @@ static void EmitCall(MCStreamer &OutStreamer, MCInst CallInst; CallInst.setOpcode(SP::CALL); CallInst.addOperand(Callee); - OutStreamer.EmitInstruction(CallInst, STI); + OutStreamer.emitInstruction(CallInst, STI); } static void EmitSETHI(MCStreamer &OutStreamer, @@ -119,7 +119,7 @@ static void EmitSETHI(MCStreamer &OutStreamer, SETHIInst.setOpcode(SP::SETHIi); SETHIInst.addOperand(RD); SETHIInst.addOperand(Imm); - OutStreamer.EmitInstruction(SETHIInst, STI); + OutStreamer.emitInstruction(SETHIInst, STI); } static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, @@ -131,7 +131,7 @@ static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, Inst.addOperand(RD); Inst.addOperand(RS1); Inst.addOperand(Src2); - OutStreamer.EmitInstruction(Inst, STI); + OutStreamer.emitInstruction(Inst, STI); } static void EmitOR(MCStreamer &OutStreamer, @@ -233,15 +233,15 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO> // add <MO>, %o7, <MO> - OutStreamer->EmitLabel(StartLabel); + OutStreamer->emitLabel(StartLabel); MCOperand Callee = createPCXCallOP(EndLabel, OutContext); EmitCall(*OutStreamer, Callee, STI); - OutStreamer->EmitLabel(SethiLabel); + OutStreamer->emitLabel(SethiLabel); MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22, GOTLabel, StartLabel, SethiLabel, OutContext); EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI); - OutStreamer->EmitLabel(EndLabel); + OutStreamer->emitLabel(EndLabel); MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10, GOTLabel, StartLabel, EndLabel, OutContext); @@ -249,8 +249,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI); } -void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) -{ +void SparcAsmPrinter::emitInstruction(const MachineInstr *MI) { switch (MI->getOpcode()) { default: break; @@ -270,7 +269,7 @@ void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) } while ((++I != E) && I->isInsideBundle()); // Delay slot check. } -void SparcAsmPrinter::EmitFunctionBodyStart() { +void SparcAsmPrinter::emitFunctionBodyStart() { if (!MF->getSubtarget<SparcSubtarget>().is64Bit()) return; diff --git a/llvm/lib/Target/Sparc/SparcCallingConv.td b/llvm/lib/Target/Sparc/SparcCallingConv.td index 4be432211f1d..db540d6f0c42 100644 --- a/llvm/lib/Target/Sparc/SparcCallingConv.td +++ b/llvm/lib/Target/Sparc/SparcCallingConv.td @@ -67,7 +67,7 @@ def RetCC_Sparc32 : CallingConv<[ // bits of an integer register while the float goes in a floating point // register. // -// The difference is encoded in LLVM IR using the inreg atttribute on function +// The difference is encoded in LLVM IR using the inreg attribute on function // arguments: // // C: void f(float, float); diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp index 0f74f2bb344c..8d8424641cd9 100644 --- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -104,7 +104,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF, // rather than reporting an error, as would be sensible. This is // poor, but fixing that bogosity is going to be a large project. // For now, just see if it's lied, and report an error here. - if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment()) + if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign()) report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required " "stack re-alignment, but LLVM couldn't handle it " "(probably because it has a dynamic alloca)."); @@ -146,9 +146,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF, // Finally, ensure that the size is sufficiently aligned for the // data on the stack. - if (MFI.getMaxAlignment() > 0) { - NumBytes = alignTo(NumBytes, MFI.getMaxAlignment()); - } + NumBytes = alignTo(NumBytes, MFI.getMaxAlign()); // Update stack size with corrected value. MFI.setStackSize(NumBytes); @@ -189,9 +187,10 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF, regUnbiased = SP::O6; // andn %regUnbiased, MaxAlign-1, %regUnbiased - int MaxAlign = MFI.getMaxAlignment(); + Align MaxAlign = MFI.getMaxAlign(); BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased) - .addReg(regUnbiased).addImm(MaxAlign - 1); + .addReg(regUnbiased) + .addImm(MaxAlign.value() - 1U); if (Bias) { // add %g1, -BIAS, %o6 @@ -258,9 +257,9 @@ bool SparcFrameLowering::hasFP(const MachineFunction &MF) const { MFI.isFrameAddressTaken(); } - -int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { +int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, + int FI, + Register &FrameReg) const { const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); const MachineFrameInfo &MFI = MF.getFrameInfo(); const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.h b/llvm/lib/Target/Sparc/SparcFrameLowering.h index 8e6001da05db..3ec9dc8b85dd 100644 --- a/llvm/lib/Target/Sparc/SparcFrameLowering.h +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.h @@ -39,7 +39,7 @@ public: RegScavenger *RS = nullptr) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; /// targetHandlesStackFrameRounding - Returns true if the target is /// responsible for rounding up the stack frame (probably at emitPrologue diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index d853d0608519..116352e08382 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -59,23 +59,21 @@ static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 }; // Try to get first reg. - if (unsigned Reg = State.AllocateReg(RegList)) { + if (Register Reg = State.AllocateReg(RegList)) { State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); } else { // Assign whole thing in stack. - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(8,4), - LocVT, LocInfo)); + State.addLoc(CCValAssign::getCustomMem( + ValNo, ValVT, State.AllocateStack(8, Align(4)), LocVT, LocInfo)); return true; } // Try to get second reg. - if (unsigned Reg = State.AllocateReg(RegList)) + if (Register Reg = State.AllocateReg(RegList)) State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); else - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(4,4), - LocVT, LocInfo)); + State.addLoc(CCValAssign::getCustomMem( + ValNo, ValVT, State.AllocateStack(4, Align(4)), LocVT, LocInfo)); return true; } @@ -88,13 +86,13 @@ static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, }; // Try to get first reg. - if (unsigned Reg = State.AllocateReg(RegList)) + if (Register Reg = State.AllocateReg(RegList)) State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); else return false; // Try to get second reg. - if (unsigned Reg = State.AllocateReg(RegList)) + if (Register Reg = State.AllocateReg(RegList)) State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); else return false; @@ -112,7 +110,7 @@ static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. unsigned size = (LocVT == MVT::f128) ? 16 : 8; - unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; + Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8); unsigned Offset = State.AllocateStack(size, alignment); unsigned Reg = 0; @@ -152,7 +150,7 @@ static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); - unsigned Offset = State.AllocateStack(4, 4); + unsigned Offset = State.AllocateStack(4, Align(4)); if (LocVT == MVT::f32 && Offset < 16*8) { // Promote floats to %f0-%f31. @@ -266,7 +264,7 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, // If the function returns a struct, copy the SRetReturnReg to I0 if (MF.getFunction().hasStructRetAttr()) { SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); - unsigned Reg = SFI->getSRetReturnReg(); + Register Reg = SFI->getSRetReturnReg(); if (!Reg) llvm_unreachable("sret virtual register not created in the entry block"); auto PtrVT = getPointerTy(DAG.getDataLayout()); @@ -431,7 +429,7 @@ SDValue SparcTargetLowering::LowerFormalArguments_32( SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo()); } else { - unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), + Register loReg = MF.addLiveIn(NextVA.getLocReg(), &SP::IntRegsRegClass); LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); } @@ -522,7 +520,7 @@ SDValue SparcTargetLowering::LowerFormalArguments_32( if (MF.getFunction().hasStructRetAttr()) { // Copy the SRet Argument to SRetReturnReg. SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); - unsigned Reg = SFI->getSRetReturnReg(); + Register Reg = SFI->getSRetReturnReg(); if (!Reg) { Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); SFI->setSRetReturnReg(Reg); @@ -597,7 +595,7 @@ SDValue SparcTargetLowering::LowerFormalArguments_64( // All integer register arguments are promoted by the caller to i64. // Create a virtual register for the promoted live-in value. - unsigned VReg = MF.addLiveIn(VA.getLocReg(), + Register VReg = MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); @@ -668,7 +666,7 @@ SDValue SparcTargetLowering::LowerFormalArguments_64( // of how many arguments were actually passed. SmallVector<SDValue, 8> OutChains; for (; ArgOffset < 6*8; ArgOffset += 8) { - unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); + Register VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); int FI = MF.getFrameInfo().CreateFixedObject(8, ArgOffset + ArgArea, true); auto PtrVT = getPointerTy(MF.getDataLayout()); @@ -692,9 +690,9 @@ SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, - ImmutableCallSite CS) { - if (CS) - return CS.hasFnAttr(Attribute::ReturnsTwice); + const CallBase *Call) { + if (Call) + return Call->hasFnAttr(Attribute::ReturnsTwice); const Function *CalleeFn = nullptr; if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { @@ -753,14 +751,14 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SDValue Arg = OutVals[i]; unsigned Size = Flags.getByValSize(); - unsigned Align = Flags.getByValAlign(); + Align Alignment = Flags.getNonZeroByValAlign(); if (Size > 0U) { - int FI = MFI.CreateStackObject(Size, Align, false); + int FI = MFI.CreateStackObject(Size, Alignment, false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32); - Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, + Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment, false, // isVolatile, (Size <= 32), // AlwaysInline if size <= 32, false, // isTailCall @@ -931,12 +929,12 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // stuck together. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - unsigned Reg = toCallerWindow(RegsToPass[i].first); + Register Reg = toCallerWindow(RegsToPass[i].first); Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } - bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); + bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB); // If the callee is a GlobalAddress node (quite common, every direct call is) // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. @@ -1018,7 +1016,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // this table could be generated automatically from RegInfo. Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const { - Register Reg = StringSwitch<unsigned>(RegName) + Register Reg = StringSwitch<Register>(RegName) .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3) .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7) .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3) @@ -1060,7 +1058,7 @@ static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, CCValAssign NewVA; // Determine the offset into the argument array. - unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; + Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; unsigned Offset = argSize * (VA.getLocReg() - firstReg); assert(Offset < 16*8 && "Offset out of range, bad register enum?"); @@ -1127,7 +1125,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Collect the set of registers to pass to the function and their values. // This will be emitted as a sequence of CopyToReg nodes glued to the call // instruction. - SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; + SmallVector<std::pair<Register, SDValue>, 8> RegsToPass; // Collect chains from all the memory opeations that copy arguments to the // stack. They must follow the stack pointer adjustment above and precede the @@ -1243,7 +1241,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. // Likewise ExternalSymbol -> TargetExternalSymbol. SDValue Callee = CLI.Callee; - bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); + bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB); unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0; if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF); @@ -1292,7 +1290,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Set inreg flag manually for codegen generated library calls that // return float. - if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CS) + if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB) CLI.Ins[0].Flags.setInReg(); RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); @@ -1467,6 +1465,7 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, // Turn FP extload into load/fpextend for (MVT VT : MVT::fp_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); } @@ -1476,6 +1475,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); // Turn FP truncstore into trunc + store. + setTruncStoreAction(MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f16, Expand); setTruncStoreAction(MVT::f64, MVT::f32, Expand); setTruncStoreAction(MVT::f128, MVT::f32, Expand); setTruncStoreAction(MVT::f128, MVT::f64, Expand); @@ -1517,6 +1518,12 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); + // Lower f16 conversion operations into library calls + setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); + setOperationAction(ISD::BITCAST, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::i32, Expand); @@ -1906,10 +1913,8 @@ SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, GA->getOffset(), TF); if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) - return DAG.getTargetConstantPool(CP->getConstVal(), - CP->getValueType(0), - CP->getAlignment(), - CP->getOffset(), TF); + return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0), + CP->getAlign(), CP->getOffset(), TF); if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) return DAG.getTargetBlockAddress(BA->getBlockAddress(), @@ -2131,7 +2136,7 @@ SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, if (ArgTy->isFP128Ty()) { // Create a stack object and pass the pointer to the library function. - int FI = MFI.CreateStackObject(16, 8, false); + int FI = MFI.CreateStackObject(16, Align(8), false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(), /* Alignment = */ 8); @@ -2162,7 +2167,7 @@ SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG, if (RetTy->isFP128Ty()) { // Create a Stack Object to receive the return value of type f128. ArgListEntry Entry; - int RetFI = MFI.CreateStackObject(16, 8, false); + int RetFI = MFI.CreateStackObject(16, Align(8), false); RetPtr = DAG.getFrameIndex(RetFI, PtrVT); Entry.Node = RetPtr; Entry.Ty = PointerType::getUnqual(RetTy); @@ -2239,54 +2244,54 @@ SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, switch(SPCC) { default: { - SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UL : { SDValue Mask = DAG.getConstant(1, DL, Result.getValueType()); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); - SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_ULE: { - SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(2, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UG : { - SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(1, DL, Result.getValueType()); SPCC = SPCC::ICC_G; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UGE: { - SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(1, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_U : { - SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(3, DL, Result.getValueType()); SPCC = SPCC::ICC_E; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_O : { - SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(3, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_LG : { SDValue Mask = DAG.getConstant(3, DL, Result.getValueType()); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); - SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UE : { SDValue Mask = DAG.getConstant(3, DL, Result.getValueType()); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); - SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); + SDValue RHS = DAG.getConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_E; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } @@ -2544,15 +2549,16 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) { SDValue Chain = Op.getOperand(0); // Legalize the chain. SDValue Size = Op.getOperand(1); // Legalize the size. - unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); - unsigned StackAlign = Subtarget->getFrameLowering()->getStackAlignment(); + MaybeAlign Alignment = + cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue(); + Align StackAlign = Subtarget->getFrameLowering()->getStackAlign(); EVT VT = Size->getValueType(0); SDLoc dl(Op); // TODO: implement over-aligned alloca. (Note: also implies // supporting support for overaligned function frames + dynamic // allocations, at all, which currently isn't supported) - if (Align > StackAlign) { + if (Alignment && *Alignment > StackAlign) { const MachineFunction &MF = DAG.getMachineFunction(); report_fatal_error("Function \"" + Twine(MF.getName()) + "\": " "over-aligned dynamic alloca not supported."); diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h index 2838ca4bdc66..c6d0011b88a5 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.h +++ b/llvm/lib/Target/Sparc/SparcISelLowering.h @@ -103,14 +103,14 @@ namespace llvm { /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. - unsigned + Register getExceptionPointerRegister(const Constant *PersonalityFn) const override { return SP::I0; } /// If a physical register, this returns the register that receives the /// exception typeid on entry to a landing pad. - unsigned + Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override { return SP::I1; } diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td index d4d056ea0af6..4a0e8c856f27 100644 --- a/llvm/lib/Target/Sparc/SparcInstrAliases.td +++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td @@ -281,7 +281,7 @@ defm : int_cond_alias<"pos", 0b1110>; defm : int_cond_alias<"neg", 0b0110>; defm : int_cond_alias<"vc", 0b1111>; defm : int_cond_alias<"vs", 0b0111>; -let EmitPriority = 0 in +let EmitPriority = 0 in { defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual defm : int_cond_alias<"nz", 0b1001>; // same as ne @@ -306,7 +306,7 @@ defm : fp_cond_alias<"uge", 0b1100>; defm : fp_cond_alias<"le", 0b1101>; defm : fp_cond_alias<"ule", 0b1110>; defm : fp_cond_alias<"o", 0b1111>; -let EmitPriority = 0 in +let EmitPriority = 0 in { defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual defm : fp_cond_alias<"nz", 0b0001>; // same as ne diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td index fbf08b49d60c..2d8f063f7ed1 100644 --- a/llvm/lib/Target/Sparc/SparcInstrFormats.td +++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td @@ -24,7 +24,7 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern, let DecoderNamespace = "Sparc"; field bits<32> SoftFail = 0; - + let Itinerary = itin; } diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 31185aa508af..dc3a41c63098 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -393,7 +393,7 @@ void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void SparcInstrInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FI, + Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; @@ -403,7 +403,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const MachineFrameInfo &MFI = MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, - MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); + MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); // On the order of operands here: think "[FrameIdx + 0] = SrcReg". if (RC == &SP::I64RegsRegClass) @@ -432,7 +432,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void SparcInstrInfo:: loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, int FI, + Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; @@ -442,7 +442,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const MachineFrameInfo &MFI = MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, - MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); + MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); if (RC == &SP::I64RegsRegClass) BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) @@ -468,11 +468,10 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, llvm_unreachable("Can't load this register from stack slot"); } -unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const -{ +Register SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); - unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); - if (GlobalBaseReg != 0) + Register GlobalBaseReg = SparcFI->getGlobalBaseReg(); + if (GlobalBaseReg) return GlobalBaseReg; // Insert the set of GlobalBaseReg into the first MBB of the function diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index f0b3dde6dec3..b25de8e5a690 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -86,17 +86,17 @@ public: void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - unsigned getGlobalBaseReg(MachineFunction *MF) const; + Register getGlobalBaseReg(MachineFunction *MF) const; // Lower pseudo instructions after register allocation. bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index f26f4a1c1a84..8b01313c7911 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -27,12 +27,12 @@ def Is32Bit : Predicate<"!Subtarget->is64Bit()">; def Is64Bit : Predicate<"Subtarget->is64Bit()">; def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">, - AssemblerPredicate<"FeatureSoftMulDiv">; + AssemblerPredicate<(all_of FeatureSoftMulDiv)>; // HasV9 - This predicate is true when the target processor supports V9 // instructions. Note that the machine may be running in 32-bit mode. def HasV9 : Predicate<"Subtarget->isV9()">, - AssemblerPredicate<"FeatureV9">; + AssemblerPredicate<(all_of FeatureV9)>; // HasNoV9 - This predicate is true when the target doesn't have V9 // instructions. Use of this is just a hack for the isel not having proper @@ -41,11 +41,11 @@ def HasNoV9 : Predicate<"!Subtarget->isV9()">; // HasVIS - This is true when the target processor has VIS extensions. def HasVIS : Predicate<"Subtarget->isVIS()">, - AssemblerPredicate<"FeatureVIS">; + AssemblerPredicate<(all_of FeatureVIS)>; def HasVIS2 : Predicate<"Subtarget->isVIS2()">, - AssemblerPredicate<"FeatureVIS2">; + AssemblerPredicate<(all_of FeatureVIS2)>; def HasVIS3 : Predicate<"Subtarget->isVIS3()">, - AssemblerPredicate<"FeatureVIS3">; + AssemblerPredicate<(all_of FeatureVIS3)>; // HasHardQuad - This is true when the target processor supports quad floating // point instructions. @@ -58,7 +58,7 @@ def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">; // HasPWRPSR - This is true when the target processor supports partial // writes to the PSR register that only affects the ET field. def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">, - AssemblerPredicate<"FeaturePWRPSR">; + AssemblerPredicate<(all_of FeaturePWRPSR)>; // HasUMAC_SMAC - This is true when the target processor supports the // UMAC and SMAC instructions @@ -529,7 +529,7 @@ let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in { "ld [$addr], %csr", []>; } } - + let DecoderMethod = "DecodeLoadFP" in let Defs = [FSR] in { let rd = 0 in { @@ -571,12 +571,12 @@ let DecoderMethod = "DecodeStoreQFP" in defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>, Requires<[HasV9, HasHardQuad]>; -let DecoderMethod = "DecodeStoreCP" in - defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; - -let DecoderMethod = "DecodeStoreCPPair" in +let DecoderMethod = "DecodeStoreCP" in + defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; + +let DecoderMethod = "DecodeStoreCPPair" in defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>; - + let DecoderMethod = "DecodeStoreCP", rd = 0 in { let Defs = [CPSR] in { def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins), @@ -897,7 +897,7 @@ def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond), [(SPbrfcc bb:$imm22, imm:$cond)]>; def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), "cb$cond,a $imm22", []>; - + // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction let Uses = [O6], @@ -1080,7 +1080,7 @@ let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>; -// Section B.31 - Unimplmented Instruction +// Section B.31 - Unimplemented Instruction let rd = 0 in def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22), "unimp $imm22", []>; @@ -1186,7 +1186,7 @@ def FABSS : F3_3u<2, 0b110100, 0b000001001, // Floating-point Square Root Instructions, p.145 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction // this will be promoted to use FSQRTD with doubles instead. -let Predicates = [HasNoFdivSqrtFix] in +let Predicates = [HasNoFdivSqrtFix] in def FSQRTS : F3_3u<2, 0b110100, 0b000101001, (outs FPRegs:$rd), (ins FPRegs:$rs2), "fsqrts $rs2, $rd", @@ -1515,8 +1515,8 @@ let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13), "membar $simm13", []>; -// The CAS instruction, unlike other instructions, only comes in a -// form which requires an ASI be provided. The ASI value hardcoded +// The CAS instruction, unlike other instructions, only comes in a +// form which requires an ASI be provided. The ASI value hardcoded // here is ASI_PRIMARY, the default unprivileged ASI for SparcV9. let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in def CASrr: F3_1_asi<3, 0b111100, @@ -1536,18 +1536,18 @@ let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in "casa [$rs1] 10, $rs2, $rd", [(set i32:$rd, (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; - + // CASA supported on some LEON3 and all LEON4 processors. Same pattern as // CASrr, above, but with a different ASI. This version is supported for -// inline assembly lowering only. +// inline assembly lowering only. let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in def CASArr: F3_1_asi<3, 0b111100, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, IntRegs:$swap, i8imm:$asi), "casa [$rs1] $asi, $rs2, $rd", []>; - + // TODO: Add DAG sequence to lower these instructions. Currently, only provided -// as inline assembler-supported instructions. +// as inline assembler-supported instructions. let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { def SMACrr : F3_1<2, 0b111111, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), @@ -1558,12 +1558,12 @@ let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), "smac $rs1, $simm13, $rd", [], IIC_smac_umac>; - + def UMACrr : F3_1<2, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), "umac $rs1, $rs2, $rd", [], IIC_smac_umac>; - + def UMACri : F3_2<2, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), "umac $rs1, $simm13, $rd", diff --git a/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h b/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h index fe5705878693..d557c8ea22e2 100644 --- a/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h +++ b/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h @@ -19,14 +19,14 @@ namespace llvm { class SparcMachineFunctionInfo : public MachineFunctionInfo { virtual void anchor(); private: - unsigned GlobalBaseReg; + Register GlobalBaseReg; /// VarArgsFrameOffset - Frame offset to start of varargs area. int VarArgsFrameOffset; /// SRetReturnReg - Holds the virtual register into which the sret /// argument is passed. - unsigned SRetReturnReg; + Register SRetReturnReg; /// IsLeafProc - True if the function is a leaf procedure. bool IsLeafProc; @@ -38,14 +38,14 @@ namespace llvm { : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0), IsLeafProc(false) {} - unsigned getGlobalBaseReg() const { return GlobalBaseReg; } - void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } + Register getGlobalBaseReg() const { return GlobalBaseReg; } + void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; } int getVarArgsFrameOffset() const { return VarArgsFrameOffset; } void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; } - unsigned getSRetReturnReg() const { return SRetReturnReg; } - void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } + Register getSRetReturnReg() const { return SRetReturnReg; } + void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; } void setLeafProc(bool rhs) { IsLeafProc = rhs; } bool isLeafProc() const { return IsLeafProc; } diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index 19a90e98db7e..990dbe23e7ac 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -173,7 +173,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); const SparcFrameLowering *TFI = getFrameLowering(MF); - unsigned FrameReg; + Register FrameReg; int Offset; Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.td b/llvm/lib/Target/Sparc/SparcRegisterInfo.td index 98959d512955..8225bc21e8fe 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td @@ -359,14 +359,14 @@ let isAllocatable = 0 in { // Ancillary state registers def ASRRegs : RegisterClass<"SP", [i32], 32, (add Y, (sequence "ASR%u", 1, 31))>; - + // This register class should not be used to hold i64 values. def CoprocRegs : RegisterClass<"SP", [i32], 32, (add (sequence "C%u", 0, 31))>; // Should be in the same order as CoprocRegs. def CoprocPair : RegisterClass<"SP", [v2i32], 64, - (add C0_C1, C2_C3, C4_C5, C6_C7, + (add C0_C1, C2_C3, C4_C5, C6_C7, C8_C9, C10_C11, C12_C13, C14_C15, C16_C17, C18_C19, C20_C21, C22_C23, C24_C25, C26_C27, C28_C29, C30_C31)>; diff --git a/llvm/lib/Target/Sparc/SparcSchedule.td b/llvm/lib/Target/Sparc/SparcSchedule.td index 31e43c9bd95d..0f05372b7050 100755 --- a/llvm/lib/Target/Sparc/SparcSchedule.td +++ b/llvm/lib/Target/Sparc/SparcSchedule.td @@ -1,4 +1,4 @@ -//===-- SparcSchedule.td - Describe the Sparc Itineries ----*- tablegen -*-===// +//===-- SparcSchedule.td - Describe the Sparc Itineraries ----*- tablegen -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp index 075a002a358d..dbc6cf8e5b86 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -50,7 +50,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, HasLeonCycleCounter = false; // Determine default and user specified characteristics - std::string CPUName = CPU; + std::string CPUName = std::string(CPU); if (CPUName.empty()) CPUName = (Is64Bit) ? "v9" : "v8"; diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 76f387842f73..d48d94e2faf1 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -99,7 +99,8 @@ SparcTargetMachine::SparcTargetMachine( CM, getEffectiveRelocModel(RM), is64bit, JIT), OL), TLOF(std::make_unique<SparcELFTargetObjectFile>()), - Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) { + Subtarget(TT, std::string(CPU), std::string(FS), *this, is64bit), + is64Bit(is64bit) { initAsmInfo(); } diff --git a/llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp b/llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp index e6ad4d2d67aa..c03510fa090d 100644 --- a/llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp @@ -11,13 +11,13 @@ #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/TargetLowering.h" +#include "llvm/Target/TargetMachine.h" using namespace llvm; void SparcELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { TargetLoweringObjectFileELF::Initialize(Ctx, TM); - InitializeELF(TM.Options.UseInitArray); } const MCExpr *SparcELFTargetObjectFile::getTTypeGlobalReference( |