diff options
Diffstat (limited to 'source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp')
| -rw-r--r-- | source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp | 164 |
1 files changed, 144 insertions, 20 deletions
diff --git a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp index 99856a3684cb..47b98ca85b78 100644 --- a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -494,9 +494,13 @@ EmulateInstructionMIPS::GetOpcodeForInstruction (const char *op_name) //---------------------------------------------------------------------- // Prologue/Epilogue instructions //---------------------------------------------------------------------- - { "ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu, "ADDIU rt,rs,immediate" }, - { "SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt,offset(rs)" }, - { "LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt,offset(base)" }, + { "ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu, "ADDIU rt, rs, immediate" }, + { "SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt, offset(rs)" }, + { "LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt, offset(base)" }, + { "SUBU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "SUBU rd, rs, rt" }, + { "ADDU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "ADDU rd, rs, rt" }, + { "LUI", &EmulateInstructionMIPS::Emulate_LUI, "LUI rt, immediate" }, + //---------------------------------------------------------------------- // MicroMIPS Prologue/Epilogue instructions //---------------------------------------------------------------------- @@ -904,36 +908,57 @@ EmulateInstructionMIPS::nonvolatile_reg_p (uint32_t regnum) bool EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn) { + // ADDIU rt, rs, immediate + // GPR[rt] <- GPR[rs] + sign_extend(immediate) + + uint8_t dst, src; bool success = false; const uint32_t imm16 = insn.getOperand(2).getImm(); - uint32_t imm = SignedBits(imm16, 15, 0); - uint64_t result; - uint32_t src, dst; + int64_t imm = SignedBits(imm16, 15, 0); dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - /* Check if this is addiu sp,<src>,imm16 */ - if (dst == dwarf_sp_mips) + // If immediate value is greater then 2^16 - 1 then clang generate + // LUI, ADDIU, SUBU instructions in prolog. + // Example + // lui $1, 0x2 + // addiu $1, $1, -0x5920 + // subu $sp, $sp, $1 + // In this case, ADDIU dst and src will be same and not equal to sp + if (dst == src) { + Context context; + /* read <src> register */ - uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success); + const int64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success); if (!success) return false; - result = src_opd_val + imm; + /* Check if this is daddiu sp, sp, imm16 */ + if (dst == dwarf_sp_mips) + { + uint64_t result = src_opd_val + imm; + RegisterInfo reg_info_sp; - Context context; - RegisterInfo reg_info_sp; - if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) - context.SetRegisterPlusOffset (reg_info_sp, imm); + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, imm); - /* We are allocating bytes on stack */ - context.type = eContextAdjustStackPointer; + /* We are allocating bytes on stack */ + context.type = eContextAdjustStackPointer; - WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); + return true; + } + + imm += src_opd_val; + context.SetImmediateSigned (imm); + context.type = eContextImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + dst, imm)) + return false; } - + return true; } @@ -968,7 +993,7 @@ EmulateInstructionMIPS::Emulate_SW (llvm::MCInst& insn) WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); /* We look for sp based non-volatile register stores */ - if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) + if (nonvolatile_reg_p (src)) { RegisterInfo reg_info_src; @@ -1027,7 +1052,7 @@ EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) bad_vaddr_context.type = eContextInvalid; WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); - if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) + if (nonvolatile_reg_p (src)) { RegisterValue data_src; RegisterInfo reg_info_src; @@ -1049,6 +1074,105 @@ EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) } bool +EmulateInstructionMIPS::Emulate_SUBU_ADDU (llvm::MCInst& insn) +{ + // SUBU sp, <src>, <rt> + // ADDU sp, <src>, <rt> + // ADDU dst, sp, <rt> + + bool success = false; + uint64_t result; + uint8_t src, dst, rt; + const char *op_name = m_insn_info->getName (insn.getOpcode ()); + + dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + + /* Check if sp is destination register */ + if (dst == dwarf_sp_mips) + { + rt = m_reg_info->getEncodingValue (insn.getOperand(2).getReg()); + + /* read <src> register */ + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success); + if (!success) + return false; + + /* read <rt > register */ + uint64_t rt_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); + if (!success) + return false; + + if (!strcasecmp (op_name, "SUBU")) + result = src_opd_val - rt_opd_val; + else + result = src_opd_val + rt_opd_val; + + Context context; + RegisterInfo reg_info_sp; + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, rt_opd_val); + + /* We are allocating bytes on stack */ + context.type = eContextAdjustStackPointer; + + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); + + return true; + } + else if (src == dwarf_sp_mips) + { + rt = m_reg_info->getEncodingValue (insn.getOperand(2).getReg()); + + /* read <src> register */ + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success); + if (!success) + return false; + + /* read <rt> register */ + uint64_t rt_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); + if (!success) + return false; + + Context context; + + if (!strcasecmp (op_name, "SUBU")) + result = src_opd_val - rt_opd_val; + else + result = src_opd_val + rt_opd_val; + + context.SetImmediateSigned (result); + context.type = eContextImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + dst, result)) + return false; + } + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_LUI (llvm::MCInst& insn) +{ + // LUI rt, immediate + // GPR[rt] <- sign_extend(immediate << 16) + + const uint32_t imm32 = insn.getOperand(1).getImm() << 16; + int64_t imm = SignedBits(imm32, 31, 0); + uint8_t rt; + Context context; + + rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + context.SetImmediateSigned (imm); + context.type = eContextImmediate; + + if (WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + rt, imm)) + return true; + + return false; +} + +bool EmulateInstructionMIPS::Emulate_ADDIUSP (llvm::MCInst& insn) { bool success = false; |