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Diffstat (limited to 'source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp')
-rw-r--r--source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp130
1 files changed, 46 insertions, 84 deletions
diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
index 5af12ad141aa..9d178dd97ddf 100644
--- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -14,12 +14,12 @@
#include "lldb/Core/Address.h"
#include "lldb/Core/Opcode.h"
#include "lldb/Core/PluginManager.h"
-#include "lldb/Core/RegisterValue.h"
#include "lldb/Host/PosixApi.h"
#include "lldb/Symbol/UnwindPlan.h"
#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/ConstString.h"
#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/RegisterValue.h"
#include "lldb/Utility/Stream.h"
#include "llvm-c/Disassembler.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -207,10 +207,8 @@ EmulateInstructionMIPS64::CreateInstance(const ArchSpec &arch,
}
bool EmulateInstructionMIPS64::SetTargetTriple(const ArchSpec &arch) {
- if (arch.GetTriple().getArch() == llvm::Triple::mips64 ||
- arch.GetTriple().getArch() == llvm::Triple::mips64el)
- return true;
- return false;
+ return arch.GetTriple().getArch() == llvm::Triple::mips64 ||
+ arch.GetTriple().getArch() == llvm::Triple::mips64el;
}
const char *EmulateInstructionMIPS64::GetRegisterName(unsigned reg_num,
@@ -1099,13 +1097,24 @@ bool EmulateInstructionMIPS64::Emulate_DADDiu(llvm::MCInst &insn) {
Context context;
/* read <src> register */
- const int64_t src_opd_val = ReadRegisterUnsigned(
+ const uint64_t src_opd_val = ReadRegisterUnsigned(
eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success);
if (!success)
return false;
/* Check if this is daddiu sp, sp, imm16 */
if (dst == dwarf_sp_mips64) {
+ /*
+ * From the MIPS IV spec:
+ *
+ * The term “unsigned” in the instruction name is a misnomer; this
+ * operation is 64-bit modulo arithmetic that does not trap on overflow.
+ * It is appropriate for arithmetic which is not signed, such as address
+ * arithmetic, or integer arithmetic environments that ignore overflow,
+ * such as “C” language arithmetic.
+ *
+ * Assume 2's complement and rely on unsigned overflow here.
+ */
uint64_t result = src_opd_val + imm;
RegisterInfo reg_info_sp;
@@ -1229,10 +1238,7 @@ bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) {
Context context;
context.type = eContextRegisterLoad;
- if (!WriteRegister(context, &reg_info_src, data_src))
- return false;
-
- return true;
+ return WriteRegister(context, &reg_info_src, data_src);
}
return false;
@@ -1251,11 +1257,8 @@ bool EmulateInstructionMIPS64::Emulate_LUI(llvm::MCInst &insn) {
context.SetImmediateSigned(imm);
context.type = eContextImmediate;
- if (WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_zero_mips64 + rt,
- imm))
- return true;
-
- return false;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF,
+ dwarf_zero_mips64 + rt, imm);
}
bool EmulateInstructionMIPS64::Emulate_DSUBU_DADDU(llvm::MCInst &insn) {
@@ -1383,11 +1386,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
/*
@@ -1622,11 +1622,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BC(llvm::MCInst &insn) {
@@ -1648,11 +1645,8 @@ bool EmulateInstructionMIPS64::Emulate_BC(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
static int IsAdd64bitOverflow(int64_t a, int64_t b) {
@@ -1736,11 +1730,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(current_inst_size + offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
/*
@@ -1803,11 +1794,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(current_inst_size + offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_J(llvm::MCInst &insn) {
@@ -1830,10 +1818,8 @@ bool EmulateInstructionMIPS64::Emulate_J(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64, pc))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ pc);
}
bool EmulateInstructionMIPS64::Emulate_JAL(llvm::MCInst &insn) {
@@ -1962,11 +1948,8 @@ bool EmulateInstructionMIPS64::Emulate_JIC(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_JR(llvm::MCInst &insn) {
@@ -1987,11 +1970,8 @@ bool EmulateInstructionMIPS64::Emulate_JR(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- rs_val))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ rs_val);
}
/*
@@ -2041,11 +2021,8 @@ bool EmulateInstructionMIPS64::Emulate_FP_branch(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BC1EQZ(llvm::MCInst &insn) {
@@ -2080,11 +2057,8 @@ bool EmulateInstructionMIPS64::Emulate_BC1EQZ(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BC1NEZ(llvm::MCInst &insn) {
@@ -2119,11 +2093,8 @@ bool EmulateInstructionMIPS64::Emulate_BC1NEZ(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
/*
@@ -2182,11 +2153,8 @@ bool EmulateInstructionMIPS64::Emulate_3D_branch(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BNZB(llvm::MCInst &insn) {
@@ -2277,11 +2245,8 @@ bool EmulateInstructionMIPS64::Emulate_MSA_Branch_DF(llvm::MCInst &insn,
Context context;
context.type = eContextRelativeBranchImmediate;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BNZV(llvm::MCInst &insn) {
@@ -2323,11 +2288,8 @@ bool EmulateInstructionMIPS64::Emulate_MSA_Branch_V(llvm::MCInst &insn,
Context context;
context.type = eContextRelativeBranchImmediate;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_LDST_Imm(llvm::MCInst &insn) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-22 10:27:46 +0000