diff options
Diffstat (limited to 'source/Plugins/Instruction')
8 files changed, 2870 insertions, 1169 deletions
diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp index 95ae549e0e4b..d646d4d4754a 100644 --- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp +++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp @@ -290,9 +290,8 @@ EmulateInstructionARM::GetRegisterInfo (lldb::RegisterKind reg_kind, uint32_t re uint32_t EmulateInstructionARM::GetFramePointerRegisterNumber () const { - if (m_arch.GetTriple().getEnvironment() == llvm::Triple::Android) + if (m_arch.GetTriple().isAndroid()) return LLDB_INVALID_REGNUM; // Don't use frame pointer on android - bool is_apple = false; if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple) is_apple = true; @@ -301,6 +300,8 @@ EmulateInstructionARM::GetFramePointerRegisterNumber () const case llvm::Triple::Darwin: case llvm::Triple::MacOSX: case llvm::Triple::IOS: + case llvm::Triple::TvOS: + case llvm::Triple::WatchOS: is_apple = true; break; default: @@ -387,9 +388,8 @@ EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding enc } #endif - bool conditional = false; bool success = false; - if (ConditionPassed(opcode, &conditional)) + if (ConditionPassed(opcode)) { const uint32_t addr_byte_size = GetAddressByteSize(); const addr_t sp = ReadCoreReg (SP_REG, &success); @@ -442,10 +442,7 @@ EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding enc uint32_t i; EmulateInstruction::Context context; - if (conditional) - context.type = EmulateInstruction::eContextRegisterStore; - else - context.type = EmulateInstruction::eContextPushRegisterOnStack; + context.type = EmulateInstruction::eContextPushRegisterOnStack; RegisterInfo reg_info; RegisterInfo sp_reg; GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg); @@ -511,8 +508,7 @@ EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding enco bool success = false; - bool conditional = false; - if (ConditionPassed(opcode, &conditional)) + if (ConditionPassed(opcode)) { const uint32_t addr_byte_size = GetAddressByteSize(); const addr_t sp = ReadCoreReg (SP_REG, &success); @@ -574,10 +570,7 @@ EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding enco uint32_t i, data; EmulateInstruction::Context context; - if (conditional) - context.type = EmulateInstruction::eContextRegisterLoad; - else - context.type = EmulateInstruction::eContextPopRegisterOffStack; + context.type = EmulateInstruction::eContextPopRegisterOffStack; RegisterInfo sp_reg; GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg); @@ -586,7 +579,7 @@ EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding enco { if (BitIsSet (registers, i)) { - context.SetRegisterPlusOffset (sp_reg, addr - sp); + context.SetAddress(addr); data = MemARead(context, addr, 4, 0, &success); if (!success) return false; @@ -900,12 +893,12 @@ EmulateInstructionARM::EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding break; case eEncodingA1: - // d = UInt(Rd); setflags = (S == 1); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C); + // d = UInt(Rd); setflags = (S == '1'); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C); Rd = Bits32 (opcode, 15, 12); setflags = BitIsSet (opcode, 20); imm32 = ARMExpandImm_C (opcode, APSR_C, carry); - // if Rd == 1111 && S == 1 then SEE SUBS PC, LR and related instructions; + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; if ((Rd == 15) && setflags) return EmulateSUBSPcLrEtc (opcode, encoding); @@ -1971,9 +1964,8 @@ EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding } #endif - bool conditional = false; bool success = false; - if (ConditionPassed(opcode, &conditional)) + if (ConditionPassed(opcode)) { const uint32_t addr_byte_size = GetAddressByteSize(); const addr_t sp = ReadCoreReg (SP_REG, &success); @@ -2018,10 +2010,7 @@ EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding addr = sp; EmulateInstruction::Context context; - if (conditional) - context.type = EmulateInstruction::eContextRegisterStore; - else - context.type = EmulateInstruction::eContextPushRegisterOnStack; + context.type = EmulateInstruction::eContextPushRegisterOnStack; RegisterInfo sp_reg; RegisterInfo dwarf_reg; @@ -2082,8 +2071,7 @@ EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding en #endif bool success = false; - bool conditional = false; - if (ConditionPassed(opcode, &conditional)) + if (ConditionPassed(opcode)) { const uint32_t addr_byte_size = GetAddressByteSize(); const addr_t sp = ReadCoreReg (SP_REG, &success); @@ -2125,10 +2113,8 @@ EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding en uint32_t i; EmulateInstruction::Context context; - if (conditional) - context.type = EmulateInstruction::eContextRegisterStore; - else - context.type = EmulateInstruction::eContextPushRegisterOnStack; + context.type = EmulateInstruction::eContextPushRegisterOnStack; + RegisterInfo dwarf_reg; RegisterInfo sp_reg; GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg); @@ -2178,8 +2164,7 @@ EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding enc #endif bool success = false; - bool conditional = false; - if (ConditionPassed(opcode, &conditional)) + if (ConditionPassed(opcode)) { const uint32_t addr_byte_size = GetAddressByteSize(); const addr_t sp = ReadCoreReg (SP_REG, &success); @@ -2222,17 +2207,15 @@ EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding enc uint64_t data; // uint64_t to accommodate 64-bit registers. EmulateInstruction::Context context; - if (conditional) - context.type = EmulateInstruction::eContextRegisterLoad; - else - context.type = EmulateInstruction::eContextPopRegisterOffStack; + context.type = EmulateInstruction::eContextPopRegisterOffStack; + RegisterInfo dwarf_reg; RegisterInfo sp_reg; GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg); for (i=0; i<regs; ++i) { GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg); - context.SetRegisterPlusOffset (sp_reg, addr - sp); + context.SetAddress(addr); data = MemARead(context, addr, reg_byte_size, 0, &success); if (!success) return false; @@ -3462,8 +3445,7 @@ EmulateInstructionARM::EmulateLDM (const uint32_t opcode, const ARMEncoding enco #endif bool success = false; - bool conditional = false; - if (ConditionPassed(opcode, &conditional)) + if (ConditionPassed(opcode)) { uint32_t n; uint32_t registers = 0; @@ -3536,10 +3518,8 @@ EmulateInstructionARM::EmulateLDM (const uint32_t opcode, const ARMEncoding enco context.SetRegisterPlusOffset (dwarf_reg, offset); if (wback && (n == 13)) // Pop Instruction { - if (conditional) - context.type = EmulateInstruction::eContextRegisterLoad; - else - context.type = EmulateInstruction::eContextPopRegisterOffStack; + context.type = EmulateInstruction::eContextPopRegisterOffStack; + context.SetAddress(base_address + offset); } // R[i] = MemA [address, 4]; address = address + 4; @@ -4459,7 +4439,7 @@ EmulateInstructionARM::EmulateSTMDB (const uint32_t opcode, const ARMEncoding en break; case eEncodingA1: - // if W == '1' && Rn == '1101 && BitCount(register_list) >= 2 then SEE PUSH; + // if W == '1' && Rn == '1101' && BitCount(register_list) >= 2 then SEE PUSH; if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2) { // See Push @@ -4801,7 +4781,11 @@ EmulateInstructionARM::EmulateSTRThumb (const uint32_t opcode, const ARMEncoding address = base_address; EmulateInstruction::Context context; - context.type = eContextRegisterStore; + if (n == 13) + context.type = eContextPushRegisterOnStack; + else + context.type = eContextRegisterStore; + RegisterInfo base_reg; GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg); @@ -4829,8 +4813,12 @@ EmulateInstructionARM::EmulateSTRThumb (const uint32_t opcode, const ARMEncoding // if wback then R[n] = offset_addr; if (wback) { - context.type = eContextRegisterLoad; + if (n == 13) + context.type = eContextAdjustStackPointer; + else + context.type = eContextAdjustBaseRegister; context.SetAddress (offset_addr); + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) return false; } @@ -9579,7 +9567,7 @@ EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding if ConditionPassed() then EncodingSpecificOperations(); shifted = Shift(R[m], shift_t, shift_n, APSR.C); - (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), 1); + (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), '1'); if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else @@ -9604,7 +9592,7 @@ EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding switch (encoding) { case eEncodingT1: - // d = UInt(Rd); m = UInt(Rm); setflags = (S == 1); + // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1'); d = Bits32 (opcode, 11, 8); m = Bits32 (opcode, 3, 0); setflags = BitIsSet (opcode, 20); @@ -9622,12 +9610,12 @@ EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding break; case eEncodingA1: - // d = UInt(Rd); m = UInt(Rm); setflags = (S == 1); + // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1'); d = Bits32 (opcode, 15, 12); m = Bits32 (opcode, 3, 0); setflags = BitIsSet (opcode, 20); - // if Rd == 1111 && S == 1 then SEE SUBS PC, LR and related instructions; + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; if (d == 15 && setflags) EmulateSUBSPcLrEtc (opcode, encoding); @@ -9648,7 +9636,7 @@ EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding if (!success) return false; - // (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), 1); + // (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), '1'); uint32_t sp_val = ReadCoreReg (SP_REG, &success); if (!success) return false; @@ -9679,7 +9667,7 @@ EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncod EncodingSpecificOperations(); shift_n = UInt(R[s]<7:0>); shifted = Shift(R[m], shift_t, shift_n, APSR.C); - (result, carry, overflow) = AddWithCarry(R[n], shifted, 0); + (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); R[d] = result; if setflags then APSR.N = result<31>; @@ -9708,7 +9696,7 @@ EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncod m = Bits32 (opcode, 3, 0); s = Bits32 (opcode, 11, 8); - // setflags = (S == 1); shift_t = DecodeRegShift(type); + // setflags = (S == '1'); shift_t = DecodeRegShift(type); setflags = BitIsSet (opcode, 20); shift_t = DecodeRegShift (Bits32 (opcode, 6, 5)); @@ -9737,7 +9725,7 @@ EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncod if (!success) return false; - // (result, carry, overflow) = AddWithCarry(R[n], shifted, 0); + // (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); uint32_t Rn = ReadCoreReg (n, &success); if (!success) return false; @@ -9776,7 +9764,7 @@ EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding e if ConditionPassed() then EncodingSpecificOperations(); shifted = Shift(R[m], shift_t, shift_n, APSR.C); - (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), 1); + (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1'); if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else @@ -9839,14 +9827,14 @@ EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding e break; case eEncodingA1: - // if Rn == 1101 then SEE SUB (SP minus register); - // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == 1); + // if Rn == '1101' then SEE SUB (SP minus register); + // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1'); d = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); setflags = BitIsSet (opcode, 20); - // if Rd == 1111 && S == 1 then SEE SUBS PC, LR and related instructions; + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; if ((d == 15) && setflags) EmulateSUBSPcLrEtc (opcode, encoding); @@ -9868,7 +9856,7 @@ EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding e if (!success) return false; - // (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), 1); + // (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1'); uint32_t Rn = ReadCoreReg (n, &success); if (!success) return false; @@ -9929,7 +9917,7 @@ EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding en switch (encoding) { case eEncodingT1: - // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:00, 32); + // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); d = Bits32 (opcode, 11, 8); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -10037,13 +10025,13 @@ EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncodi switch (encoding) { case eEncodingA1: - // if P == 0 && W == 1 then SEE STRBT; + // if P == '0' && W == '1' then SEE STRBT; // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 11, 0); - // index = (P == 1); add = (U == 1); wback = (P == 0) || (W == 1); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); @@ -10135,14 +10123,14 @@ EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncodin switch (encoding) { case eEncodingA1: - // if P == 0 && W == 1 then SEE STRT; - // if Rn == 1101 && P == 1 && U == 0 && W == 1 && imm12 == 000000000100 then SEE PUSH; + // if P == '0' && W == '1' then SEE STRT; + // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm12 == '000000000100' then SEE PUSH; // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 11, 0); - // index = (P == 1); add = (U == 1); wback = (P == 0) || (W == 1); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); @@ -10247,15 +10235,15 @@ EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEnc switch (encoding) { case eEncodingT1: - //if P == 0 && W == 0 then SEE Related encodings; - //if Rn == 1111 then SEE LDRD (literal); - //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:00, 32); + //if P == '0' && W == '0' then SEE 'Related encodings'; + //if Rn == '1111' then SEE LDRD (literal); + //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); t = Bits32 (opcode, 15, 12); t2 = Bits32 (opcode, 11, 8); n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0) << 2; - //index = (P == 1); add = (U == 1); wback = (W == 1); + //index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsSet (opcode, 21); @@ -10271,8 +10259,8 @@ EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEnc break; case eEncodingA1: - //if Rn == 1111 then SEE LDRD (literal); - //if Rt<0> == 1 then UNPREDICTABLE; + //if Rn == '1111' then SEE LDRD (literal); + //if Rt<0> == '1' then UNPREDICTABLE; //t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); t = Bits32 (opcode, 15, 12); if (BitIsSet (t, 0)) @@ -10281,12 +10269,12 @@ EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEnc n = Bits32 (opcode, 19, 16); imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0); - //index = (P == 1); add = (U == 1); wback = (P == 0) || (W == 1); + //index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); - //if P == 0 && W == 1 then UNPREDICTABLE; + //if P == '0' && W == '1' then UNPREDICTABLE; if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21)) return false; @@ -10327,8 +10315,11 @@ EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEnc GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg); EmulateInstruction::Context context; - context.type = eContextRegisterLoad; - context.SetRegisterPlusOffset (base_reg, address - Rn); + if (n == 13) + context.type = eContextPopRegisterOffStack; + else + context.type = eContextRegisterLoad; + context.SetAddress(address); const uint32_t addr_byte_size = GetAddressByteSize(); uint32_t data = MemARead (context, address, addr_byte_size, 0, &success); @@ -10339,8 +10330,7 @@ EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEnc return false; //R[t2] = MemA[address+4,4]; - - context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn); + context.SetAddress(address + 4); data = MemARead (context, address + 4, addr_byte_size, 0, &success); if (!success) return false; @@ -10392,7 +10382,7 @@ EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEnco switch (encoding) { case eEncodingA1: - // if Rt<0> == 1 then UNPREDICTABLE; + // if Rt<0> == '1' then UNPREDICTABLE; // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); if (BitIsSet (t, 0)) @@ -10401,12 +10391,12 @@ EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEnco n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == 1); add = (U == 1); wback = (P == 0) || (W == 1); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); - // if P == 0 && W == 1 then UNPREDICTABLE; + // if P == '0' && W == '1' then UNPREDICTABLE; if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21)) return false; @@ -10454,8 +10444,11 @@ EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEnco address = Rn; EmulateInstruction::Context context; - context.type = eContextRegisterLoad; - context.SetRegisterPlusIndirectOffset (base_reg, offset_reg); + if (n == 13) + context.type = eContextPopRegisterOffStack; + else + context.type = eContextRegisterLoad; + context.SetAddress(address); // R[t] = MemA[address,4]; const uint32_t addr_byte_size = GetAddressByteSize(); @@ -10519,14 +10512,14 @@ EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding switch (encoding) { case eEncodingT1: - // if P == 0 && W == 0 then SEE Related encodings; - // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:00, 32); + // if P == '0' && W == '0' then SEE 'Related encodings'; + // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); t = Bits32 (opcode, 15, 12); t2 = Bits32 (opcode, 11, 8); n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0) << 2; - // index = (P == 1); add = (U == 1); wback = (W == 1); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsSet (opcode, 21); @@ -10542,7 +10535,7 @@ EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding break; case eEncodingA1: - // if Rt<0> == 1 then UNPREDICTABLE; + // if Rt<0> == '1' then UNPREDICTABLE; // t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); t = Bits32 (opcode, 15, 12); if (BitIsSet (t, 0)) @@ -10552,12 +10545,12 @@ EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding n = Bits32 (opcode, 19, 16); imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0); - // index = (P == 1); add = (U == 1); wback = (P == 0) || (W == 1); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); - // if P == 0 && W == 1 then UNPREDICTABLE; + // if P == '0' && W == '1' then UNPREDICTABLE; if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21)) return false; @@ -10605,7 +10598,10 @@ EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding return false; EmulateInstruction::Context context; - context.type = eContextRegisterStore; + if (n == 13) + context.type = eContextPushRegisterOnStack; + else + context.type = eContextRegisterStore; context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); const uint32_t addr_byte_size = GetAddressByteSize(); @@ -10627,9 +10623,12 @@ EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding //if wback then R[n] = offset_addr; if (wback) { - context.type = eContextAdjustBaseRegister; + if (n == 13) + context.type = eContextAdjustStackPointer; + else + context.type = eContextAdjustBaseRegister; context.SetAddress (offset_addr); - + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) return false; } @@ -10667,7 +10666,7 @@ EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding switch (encoding) { case eEncodingA1: - // if Rt<0> == 1 then UNPREDICTABLE; + // if Rt<0> == '1' then UNPREDICTABLE; // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); if (BitIsSet (t, 0)) @@ -10677,12 +10676,12 @@ EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == 1); add = (U == 1); wback = (P == 0) || (W == 1); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); - // if P == 0 && W == 1 then UNPREDICTABLE; + // if P == '0' && W == '1' then UNPREDICTABLE; if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21)) return false; @@ -10737,7 +10736,11 @@ EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding return false; EmulateInstruction::Context context; - context.type = eContextRegisterStore; + if (t == 13) + context.type = eContextPushRegisterOnStack; + else + context.type = eContextRegisterStore; + GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg); context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg); @@ -10808,25 +10811,25 @@ EmulateInstructionARM::EmulateVLDM (const uint32_t opcode, const ARMEncoding enc { case eEncodingT1: case eEncodingA1: - // if P == 0 && U == 0 && W == 0 then SEE Related encodings; - // if P == 0 && U == 1 && W == 1 && Rn == 1101 then SEE VPOP; - // if P == 1 && W == 0 then SEE VLDR; - // if P == U && W == 1 then UNDEFINED; + // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings'; + // if P == '0' && U == '1' && W == '1' && Rn == '1101' then SEE VPOP; + // if P == '1' && W == '0' then SEE VLDR; + // if P == U && W == '1' then UNDEFINED; if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21)) return false; // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) - // single_regs = FALSE; add = (U == 1); wback = (W == 1); + // single_regs = FALSE; add = (U == '1'); wback = (W == '1'); single_regs = false; add = BitIsSet (opcode, 23); wback = BitIsSet (opcode, 21); - // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:00, 32); + // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0) << 2; - // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see FLDMX. + // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see 'FLDMX'. regs = Bits32 (opcode, 7, 0) / 2; // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE; @@ -10841,22 +10844,22 @@ EmulateInstructionARM::EmulateVLDM (const uint32_t opcode, const ARMEncoding enc case eEncodingT2: case eEncodingA2: - // if P == 0 && U == 0 && W == 0 then SEE Related encodings; - // if P == 0 && U == 1 && W == 1 && Rn == 1101 then SEE VPOP; - // if P == 1 && W == 0 then SEE VLDR; - // if P == U && W == 1 then UNDEFINED; + // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings'; + // if P == '0' && U == '1' && W == '1' && Rn == '1101' then SEE VPOP; + // if P == '1' && W == '0' then SEE VLDR; + // if P == U && W == '1' then UNDEFINED; if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21)) return false; // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) - // single_regs = TRUE; add = (U == 1); wback = (W == 1); d = UInt(Vd:D); n = UInt(Rn); + // single_regs = TRUE; add = (U == '1'); wback = (W == '1'); d = UInt(Vd:D); n = UInt(Rn); single_regs = true; add = BitIsSet (opcode, 23); wback = BitIsSet (opcode, 21); d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22); n = Bits32 (opcode, 19, 16); - // imm32 = ZeroExtend(imm8:00, 32); regs = UInt(imm8); + // imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8); imm32 = Bits32 (opcode, 7, 0) << 2; regs = Bits32 (opcode, 7, 0); @@ -11000,25 +11003,25 @@ EmulateInstructionARM::EmulateVSTM (const uint32_t opcode, const ARMEncoding enc { case eEncodingT1: case eEncodingA1: - // if P == 0 && U == 0 && W == 0 then SEE Related encodings; - // if P == 1 && U == 0 && W == 1 && Rn == 1101 then SEE VPUSH; - // if P == 1 && W == 0 then SEE VSTR; - // if P == U && W == 1 then UNDEFINED; + // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings'; + // if P == '1' && U == '0' && W == '1' && Rn == '1101' then SEE VPUSH; + // if P == '1' && W == '0' then SEE VSTR; + // if P == U && W == '1' then UNDEFINED; if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21)) return false; // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) - // single_regs = FALSE; add = (U == 1); wback = (W == 1); + // single_regs = FALSE; add = (U == '1'); wback = (W == '1'); single_regs = false; add = BitIsSet (opcode, 23); wback = BitIsSet (opcode, 21); - // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:00, 32); + // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0) << 2; - // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see FSTMX. + // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see 'FSTMX'. regs = Bits32 (opcode, 7, 0) / 2; // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE; @@ -11033,22 +11036,22 @@ EmulateInstructionARM::EmulateVSTM (const uint32_t opcode, const ARMEncoding enc case eEncodingT2: case eEncodingA2: - // if P == 0 && U == 0 && W == 0 then SEE Related encodings; - // if P == 1 && U == 0 && W == 1 && Rn == 1101 then SEE VPUSH; - // if P == 1 && W == 0 then SEE VSTR; - // if P == U && W == 1 then UNDEFINED; + // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings'; + // if P == '1' && U == '0' && W == '1' && Rn == '1101' then SEE VPUSH; + // if P == '1' && W == '0' then SEE VSTR; + // if P == U && W == '1' then UNDEFINED; if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21)) return false; // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) - // single_regs = TRUE; add = (U == 1); wback = (W == 1); d = UInt(Vd:D); n = UInt(Rn); + // single_regs = TRUE; add = (U == '1'); wback = (W == '1'); d = UInt(Vd:D); n = UInt(Rn); single_regs = true; add = BitIsSet (opcode, 23); wback = BitIsSet (opcode, 21); d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22); n = Bits32 (opcode, 19, 16); - // imm32 = ZeroExtend(imm8:00, 32); regs = UInt(imm8); + // imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8); imm32 = Bits32 (opcode, 7, 0) << 2; regs = Bits32 (opcode, 7, 0); @@ -11193,7 +11196,7 @@ EmulateInstructionARM::EmulateVLDR (const uint32_t opcode, ARMEncoding encoding) { case eEncodingT1: case eEncodingA1: - // single_reg = FALSE; add = (U == 1); imm32 = ZeroExtend(imm8:00, 32); + // single_reg = FALSE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00', 32); single_reg = false; add = BitIsSet (opcode, 23); imm32 = Bits32 (opcode, 7, 0) << 2; @@ -11206,7 +11209,7 @@ EmulateInstructionARM::EmulateVLDR (const uint32_t opcode, ARMEncoding encoding) case eEncodingT2: case eEncodingA2: - // single_reg = TRUE; add = (U == 1); imm32 = ZeroExtend(imm8:00, 32); + // single_reg = TRUE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00', 32); single_reg = true; add = BitIsSet (opcode, 23); imm32 = Bits32 (opcode, 7, 0) << 2; @@ -11322,7 +11325,7 @@ EmulateInstructionARM::EmulateVSTR (const uint32_t opcode, ARMEncoding encoding) { case eEncodingT1: case eEncodingA1: - // single_reg = FALSE; add = (U == 1); imm32 = ZeroExtend(imm8:00, 32); + // single_reg = FALSE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00', 32); single_reg = false; add = BitIsSet (opcode, 23); imm32 = Bits32 (opcode, 7, 0) << 2; @@ -11339,7 +11342,7 @@ EmulateInstructionARM::EmulateVSTR (const uint32_t opcode, ARMEncoding encoding) case eEncodingT2: case eEncodingA2: - // single_reg = TRUE; add = (U == 1); imm32 = ZeroExtend(imm8:00, 32); + // single_reg = TRUE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00', 32); single_reg = true; add = BitIsSet (opcode, 23); imm32 = Bits32 (opcode, 7, 0) << 2; @@ -11461,16 +11464,16 @@ EmulateInstructionARM::EmulateVLD1Multiple (const uint32_t opcode, ARMEncoding e case eEncodingA1: { // case type of - // when 0111 - // regs = 1; if align<1> == 1 then UNDEFINED; - // when 1010 - // regs = 2; if align == 11 then UNDEFINED; - // when 0110 - // regs = 3; if align<1> == 1 then UNDEFINED; - // when 0010 + // when '0111' + // regs = 1; if align<1> == '1' then UNDEFINED; + // when '1010' + // regs = 2; if align == '11' then UNDEFINED; + // when '0110' + // regs = 3; if align<1> == '1' then UNDEFINED; + // when '0010' // regs = 4; // otherwise - // SEE Related encodings; + // SEE 'Related encodings'; uint32_t type = Bits32 (opcode, 11, 8); uint32_t align = Bits32 (opcode, 5, 4); if (type == 7) // '0111' @@ -11499,7 +11502,7 @@ EmulateInstructionARM::EmulateVLD1Multiple (const uint32_t opcode, ARMEncoding e else return false; - // alignment = if align == 00 then 1 else 4 << UInt(align); + // alignment = if align == '00' then 1 else 4 << UInt(align); if (align == 0) alignment = 1; else @@ -11624,13 +11627,13 @@ EmulateInstructionARM::EmulateVLD1Single (const uint32_t opcode, const ARMEncodi { uint32_t size = Bits32 (opcode, 11, 10); uint32_t index_align = Bits32 (opcode, 7, 4); - // if size == 11 then SEE VLD1 (single element to all lanes); + // if size == '11' then SEE VLD1 (single element to all lanes); if (size == 3) return EmulateVLD1SingleAll (opcode, encoding); // case size of if (size == 0) // when '00' { - // if index_align<0> != 0 then UNDEFINED; + // if index_align<0> != '0' then UNDEFINED; if (BitIsClear (index_align, 0)) return false; @@ -11640,9 +11643,9 @@ EmulateInstructionARM::EmulateVLD1Single (const uint32_t opcode, const ARMEncodi index = Bits32 (index_align, 3, 1); alignment = 1; } - else if (size == 1) // when 01 + else if (size == 1) // when '01' { - // if index_align<1> != 0 then UNDEFINED; + // if index_align<1> != '0' then UNDEFINED; if (BitIsClear (index_align, 1)) return false; @@ -11651,19 +11654,19 @@ EmulateInstructionARM::EmulateVLD1Single (const uint32_t opcode, const ARMEncodi esize = 16; index = Bits32 (index_align, 3, 2); - // alignment = if index_align<0> == 0 then 1 else 2; + // alignment = if index_align<0> == '0' then 1 else 2; if (BitIsClear (index_align, 0)) alignment = 1; else alignment = 2; } - else if (size == 2) // when 10 + else if (size == 2) // when '10' { - // if index_align<2> != 0 then UNDEFINED; + // if index_align<2> != '0' then UNDEFINED; if (BitIsClear (index_align, 2)) return false; - // if index_align<1:0> != 00 && index_align<1:0> != 11 then UNDEFINED; + // if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED; if ((Bits32 (index_align, 1, 0) != 0) && (Bits32 (index_align, 1, 0) != 3)) return false; @@ -11672,7 +11675,7 @@ EmulateInstructionARM::EmulateVLD1Single (const uint32_t opcode, const ARMEncodi esize = 32; index = Bit32 (index_align, 3); - // alignment = if index_align<1:0> == 00 then 1 else 4; + // alignment = if index_align<1:0> == '00' then 1 else 4; if (Bits32 (index_align, 1, 0) == 0) alignment = 1; else @@ -11806,35 +11809,35 @@ EmulateInstructionARM::EmulateVST1Multiple (const uint32_t opcode, ARMEncoding e uint32_t align = Bits32 (opcode, 5, 4); // case type of - if (type == 7) // when 0111 + if (type == 7) // when '0111' { - // regs = 1; if align<1> == 1 then UNDEFINED; + // regs = 1; if align<1> == '1' then UNDEFINED; regs = 1; if (BitIsSet (align, 1)) return false; } - else if (type == 10) // when 1010 + else if (type == 10) // when '1010' { - // regs = 2; if align == 11 then UNDEFINED; + // regs = 2; if align == '11' then UNDEFINED; regs = 2; if (align == 3) return false; } - else if (type == 6) // when 0110 + else if (type == 6) // when '0110' { - // regs = 3; if align<1> == 1 then UNDEFINED; + // regs = 3; if align<1> == '1' then UNDEFINED; regs = 3; if (BitIsSet (align, 1)) return false; } - else if (type == 2) // when 0010 + else if (type == 2) // when '0010' // regs = 4; regs = 4; else // otherwise - // SEE Related encodings; + // SEE 'Related encodings'; return false; - // alignment = if align == 00 then 1 else 4 << UInt(align); + // alignment = if align == '00' then 1 else 4 << UInt(align); if (align == 0) alignment = 1; else @@ -11964,14 +11967,14 @@ EmulateInstructionARM::EmulateVST1Single (const uint32_t opcode, ARMEncoding enc uint32_t size = Bits32 (opcode, 11, 10); uint32_t index_align = Bits32 (opcode, 7, 4); - // if size == 11 then UNDEFINED; + // if size == '11' then UNDEFINED; if (size == 3) return false; // case size of - if (size == 0) // when 00 + if (size == 0) // when '00' { - // if index_align<0> != 0 then UNDEFINED; + // if index_align<0> != '0' then UNDEFINED; if (BitIsClear (index_align, 0)) return false; // ebytes = 1; esize = 8; index = UInt(index_align<3:1>); alignment = 1; @@ -11980,9 +11983,9 @@ EmulateInstructionARM::EmulateVST1Single (const uint32_t opcode, ARMEncoding enc index = Bits32 (index_align, 3, 1); alignment = 1; } - else if (size == 1) // when 01 + else if (size == 1) // when '01' { - // if index_align<1> != 0 then UNDEFINED; + // if index_align<1> != '0' then UNDEFINED; if (BitIsClear (index_align, 1)) return false; @@ -11991,19 +11994,19 @@ EmulateInstructionARM::EmulateVST1Single (const uint32_t opcode, ARMEncoding enc esize = 16; index = Bits32 (index_align, 3, 2); - // alignment = if index_align<0> == 0 then 1 else 2; + // alignment = if index_align<0> == '0' then 1 else 2; if (BitIsClear (index_align, 0)) alignment = 1; else alignment = 2; } - else if (size == 2) // when 10 + else if (size == 2) // when '10' { - // if index_align<2> != 0 then UNDEFINED; + // if index_align<2> != '0' then UNDEFINED; if (BitIsClear (index_align, 2)) return false; - // if index_align<1:0> != 00 && index_align<1:0> != 11 then UNDEFINED; + // if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED; if ((Bits32 (index_align, 1, 0) != 0) && (Bits32 (index_align, 1, 0) != 3)) return false; @@ -12012,7 +12015,7 @@ EmulateInstructionARM::EmulateVST1Single (const uint32_t opcode, ARMEncoding enc esize = 32; index = Bit32 (index_align, 3); - // alignment = if index_align<1:0> == 00 then 1 else 4; + // alignment = if index_align<1:0> == '00' then 1 else 4; if (Bits32 (index_align, 1, 0) == 0) alignment = 1; else @@ -12125,12 +12128,12 @@ EmulateInstructionARM::EmulateVLD1SingleAll (const uint32_t opcode, const ARMEnc case eEncodingT1: case eEncodingA1: { - //if size == 11 || (size == 00 && a == 1) then UNDEFINED; + //if size == '11' || (size == '00' && a == '1') then UNDEFINED; uint32_t size = Bits32 (opcode, 7, 6); if ((size == 3) || ((size == 0) && BitIsSet (opcode, 4))) return false; - //ebytes = 1 << UInt(size); elements = 8 DIV ebytes; regs = if T == 0 then 1 else 2; + //ebytes = 1 << UInt(size); elements = 8 DIV ebytes; regs = if T == '0' then 1 else 2; ebytes = 1 << size; elements = 8 / ebytes; if (BitIsClear (opcode, 5)) @@ -12138,7 +12141,7 @@ EmulateInstructionARM::EmulateVLD1SingleAll (const uint32_t opcode, const ARMEnc else regs = 2; - //alignment = if a == 0 then 1 else ebytes; + //alignment = if a == '0' then 1 else ebytes; if (BitIsClear (opcode, 4)) alignment = 1; else @@ -12235,19 +12238,19 @@ EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncod UNPREDICTABLE; operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32; case opcode of - when 0000 result = R[n] AND operand2; // AND - when 0001 result = R[n] EOR operand2; // EOR - when 0010 (result, -, -) = AddWithCarry(R[n], NOT(operand2), 1); // SUB - when 0011 (result, -, -) = AddWithCarry(NOT(R[n]), operand2, 1); // RSB - when 0100 (result, -, -) = AddWithCarry(R[n], operand2, 0); // ADD - when 0101 (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC - when 0110 (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC - when 0111 (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC - when 1100 result = R[n] OR operand2; // ORR - when 1101 result = operand2; // MOV - when 1110 result = R[n] AND NOT(operand2); // BIC - when 1111 result = NOT(operand2); // MVN - CPSRWriteByInstr(SPSR[], 1111, TRUE); + when '0000' result = R[n] AND operand2; // AND + when '0001' result = R[n] EOR operand2; // EOR + when '0010' (result, -, -) = AddWithCarry(R[n], NOT(operand2), '1'); // SUB + when '0011' (result, -, -) = AddWithCarry(NOT(R[n]), operand2, '1'); // RSB + when '0100' (result, -, -) = AddWithCarry(R[n], operand2, '0'); // ADD + when '0101' (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC + when '0110' (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC + when '0111' (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC + when '1100' result = R[n] OR operand2; // ORR + when '1101' result = operand2; // MOV + when '1110' result = R[n] AND NOT(operand2); // BIC + when '1111' result = NOT(operand2); // MVN + CPSRWriteByInstr(SPSR[], '1111', TRUE); BranchWritePC(result); #endif @@ -12267,7 +12270,7 @@ EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncod { case eEncodingT1: // if CurrentInstrSet() == InstrSet_ThumbEE then UNPREDICTABLE - // n = 14; imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = 0010; // = SUB + // n = 14; imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = '0010'; // = SUB n = 14; imm32 = Bits32 (opcode, 7, 0); register_form = false; @@ -12329,62 +12332,62 @@ EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncod // case opcode of switch (code) { - case 0: // when 0000 + case 0: // when '0000' // result = R[n] AND operand2; // AND result.result = Rn & operand2; break; - case 1: // when 0001 + case 1: // when '0001' // result = R[n] EOR operand2; // EOR result.result = Rn ^ operand2; break; - case 2: // when 0010 - // (result, -, -) = AddWithCarry(R[n], NOT(operand2), 1); // SUB + case 2: // when '0010' + // (result, -, -) = AddWithCarry(R[n], NOT(operand2), '1'); // SUB result = AddWithCarry (Rn, ~(operand2), 1); break; - case 3: // when 0011 - // (result, -, -) = AddWithCarry(NOT(R[n]), operand2, 1); // RSB + case 3: // when '0011' + // (result, -, -) = AddWithCarry(NOT(R[n]), operand2, '1'); // RSB result = AddWithCarry (~(Rn), operand2, 1); break; - case 4: // when 0100 - // (result, -, -) = AddWithCarry(R[n], operand2, 0); // ADD + case 4: // when '0100' + // (result, -, -) = AddWithCarry(R[n], operand2, '0'); // ADD result = AddWithCarry (Rn, operand2, 0); break; - case 5: // when 0101 + case 5: // when '0101' // (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC result = AddWithCarry (Rn, operand2, APSR_C); break; - case 6: // when 0110 + case 6: // when '0110' // (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC result = AddWithCarry (Rn, ~(operand2), APSR_C); break; - case 7: // when 0111 + case 7: // when '0111' // (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC result = AddWithCarry (~(Rn), operand2, APSR_C); break; - case 10: // when 1100 + case 10: // when '1100' // result = R[n] OR operand2; // ORR result.result = Rn | operand2; break; - case 11: // when 1101 + case 11: // when '1101' // result = operand2; // MOV result.result = operand2; break; - case 12: // when 1110 + case 12: // when '1110' // result = R[n] AND NOT(operand2); // BIC result.result = Rn & ~(operand2); break; - case 15: // when 1111 + case 15: // when '1111' // result = NOT(operand2); // MVN result.result = ~(operand2); break; @@ -12392,7 +12395,7 @@ EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncod default: return false; } - // CPSRWriteByInstr(SPSR[], 1111, TRUE); + // CPSRWriteByInstr(SPSR[], '1111', TRUE); // For now, in emulation mode, we don't have access to the SPSR, so we will use the CPSR instead, and hope for // the best. @@ -13076,7 +13079,7 @@ EmulateInstructionARM::ArchVersion () } bool -EmulateInstructionARM::ConditionPassed (const uint32_t opcode, bool *is_conditional) +EmulateInstructionARM::ConditionPassed (const uint32_t opcode) { // If we are ignoring conditions, then always return true. // this allows us to iterate over disassembly code and still @@ -13084,12 +13087,8 @@ EmulateInstructionARM::ConditionPassed (const uint32_t opcode, bool *is_conditio // bits set in the CPSR register... if (m_ignore_conditions) return true; - - if (is_conditional) - *is_conditional = true; const uint32_t cond = CurrentCond (opcode); - if (cond == UINT32_MAX) return false; @@ -13149,8 +13148,6 @@ EmulateInstructionARM::ConditionPassed (const uint32_t opcode, bool *is_conditio case 7: // Always execute (cond == 0b1110, or the special 0b1111 which gives // opcodes different meanings, but always means execution happens. - if (is_conditional) - *is_conditional = false; return true; } @@ -13643,6 +13640,13 @@ EmulateInstructionARM::EvaluateInstruction (uint32_t evaluate_options) } bool +EmulateInstructionARM::IsInstructionConditional() +{ + const uint32_t cond = CurrentCond (m_opcode.GetOpcode32()); + return cond != 0xe && cond != 0xf && cond != UINT32_MAX; +} + +bool EmulateInstructionARM::TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data) { if (!test_data) diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.h b/source/Plugins/Instruction/ARM/EmulateInstructionARM.h index d107ca6bc702..893f43f19977 100644 --- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.h +++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.h @@ -94,20 +94,20 @@ public: return false; } - virtual lldb_private::ConstString - GetPluginName() + lldb_private::ConstString + GetPluginName() override { return GetPluginNameStatic(); } - virtual uint32_t - GetPluginVersion() + uint32_t + GetPluginVersion() override { return 1; } bool - SetTargetTriple (const ArchSpec &arch); + SetTargetTriple (const ArchSpec &arch) override; enum Mode { @@ -148,8 +148,8 @@ public: // { // } - virtual bool - SupportsEmulatingInstructionsOfType (InstructionType inst_type) + bool + SupportsEmulatingInstructionsOfType (InstructionType inst_type) override { return SupportsEmulatingInstructionsOfTypeStatic (inst_type); } @@ -157,32 +157,32 @@ public: virtual bool SetArchitecture (const ArchSpec &arch); - virtual bool - ReadInstruction (); + bool + ReadInstruction () override; - virtual bool - SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target); + bool + SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target) override; - virtual bool - EvaluateInstruction (uint32_t evaluate_options); - - virtual bool - TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data); + bool + EvaluateInstruction (uint32_t evaluate_options) override; - virtual bool - GetRegisterInfo (lldb::RegisterKind reg_kind, uint32_t reg_num, RegisterInfo ®_info); - + bool + IsInstructionConditional() override; - virtual bool - CreateFunctionEntryUnwind (UnwindPlan &unwind_plan); + bool + TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data) override; + + bool + GetRegisterInfo (lldb::RegisterKind reg_kind, uint32_t reg_num, RegisterInfo ®_info) override; + + bool + CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) override; uint32_t ArchVersion(); bool - ConditionPassed (const uint32_t opcode, - bool *is_conditional = NULL); // Filled in with true if the opcode is a conditional opcode - // Filled in with false if the opcode is always executed + ConditionPassed (const uint32_t opcode); uint32_t CurrentCond (const uint32_t opcode); diff --git a/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp b/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp index 992df1fba59e..372ccf9b05f4 100644 --- a/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp +++ b/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp @@ -231,58 +231,72 @@ EmulateInstructionARM64::GetOpcodeForInstruction (const uint32_t opcode) //---------------------------------------------------------------------- // push register(s) - { 0xff000000, 0xd1000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}" }, - { 0xff000000, 0xf1000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}" }, - { 0xff000000, 0x91000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}" }, - { 0xff000000, 0xb1000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}" }, - - { 0xff000000, 0x51000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}" }, - { 0xff000000, 0x71000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}" }, - { 0xff000000, 0x11000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}" }, - { 0xff000000, 0x31000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}" }, - - { 0xffc00000, 0x29000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0xa9000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0x2d000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0x6d000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0xad000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]" }, - - { 0xffc00000, 0x29800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xa9800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x2d800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x6d800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xad800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, - - { 0xffc00000, 0x28800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xa8800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x2c800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x6c800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xac800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, - - { 0xffc00000, 0x29400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0xa9400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0x2d400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0x6d400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]" }, - { 0xffc00000, 0xad400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]" }, - - { 0xffc00000, 0x29c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xa9c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x2dc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x6dc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xadc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, - - { 0xffc00000, 0x28c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xa8c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x2cc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0x6cc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, - { 0xffc00000, 0xacc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, - - { 0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB, "B <label>" }, - { 0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond, "B.<cond> <label>" }, - { 0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, "CBZ <Wt>, <label>" }, - { 0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, "CBNZ <Wt>, <label>" }, - { 0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, "TBZ <R><t>, #<imm>, <label>" }, - { 0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, "TBNZ <R><t>, #<imm>, <label>" }, + { 0xff000000, 0xd1000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}" }, + { 0xff000000, 0xf1000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}" }, + { 0xff000000, 0x91000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}" }, + { 0xff000000, 0xb1000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}" }, + + { 0xff000000, 0x51000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}" }, + { 0xff000000, 0x71000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}" }, + { 0xff000000, 0x11000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}" }, + { 0xff000000, 0x31000000, No_VFP, &EmulateInstructionARM64::EmulateADDSUBImm, "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}" }, + + { 0xffc00000, 0x29000000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0xa9000000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0x2d000000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0x6d000000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0xad000000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]" }, + + { 0xffc00000, 0x29800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xa9800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x2d800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "STP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x6d800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xad800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, + + { 0xffc00000, 0x28800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xa8800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x2c800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "STP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x6c800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xac800000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, + + { 0xffc00000, 0x29400000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0xa9400000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0x2d400000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0x6d400000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]" }, + { 0xffc00000, 0xad400000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]" }, + + { 0xffc00000, 0x29c00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xa9c00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x2dc00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x6dc00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xadc00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, + + { 0xffc00000, 0x28c00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xa8c00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x2cc00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0x6cc00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, + { 0xffc00000, 0xacc00000, No_VFP, &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, + + { 0xffe00c00, 0xb8000400, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, "STR <Wt>, [<Xn|SP>], #<simm>" }, + { 0xffe00c00, 0xf8000400, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, "STR <Xt>, [<Xn|SP>], #<simm>" }, + { 0xffe00c00, 0xb8000c00, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, "STR <Wt>, [<Xn|SP>, #<simm>]!" }, + { 0xffe00c00, 0xf8000c00, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, "STR <Xt>, [<Xn|SP>, #<simm>]!" }, + { 0xffc00000, 0xb9000000, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, "STR <Wt>, [<Xn|SP>{, #<pimm>}]" }, + { 0xffc00000, 0xf9000000, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, "STR <Xt>, [<Xn|SP>{, #<pimm>}]" }, + + { 0xffe00c00, 0xb8400400, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, "LDR <Wt>, [<Xn|SP>], #<simm>" }, + { 0xffe00c00, 0xf8400400, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, "LDR <Xt>, [<Xn|SP>], #<simm>" }, + { 0xffe00c00, 0xb8400c00, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, "LDR <Wt>, [<Xn|SP>, #<simm>]!" }, + { 0xffe00c00, 0xf8400c00, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, "LDR <Xt>, [<Xn|SP>, #<simm>]!" }, + { 0xffc00000, 0xb9400000, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, "LDR <Wt>, [<Xn|SP>{, #<pimm>}]" }, + { 0xffc00000, 0xf9400000, No_VFP, &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, "LDR <Xt>, [<Xn|SP>{, #<pimm>}]" }, + + { 0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB, "B <label>" }, + { 0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond, "B.<cond> <label>" }, + { 0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, "CBZ <Wt>, <label>" }, + { 0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, "CBNZ <Wt>, <label>" }, + { 0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, "TBZ <R><t>, #<imm>, <label>" }, + { 0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, "TBNZ <R><t>, #<imm>, <label>" }, }; static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes); @@ -391,7 +405,7 @@ EmulateInstructionARM64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber () const { - if (m_arch.GetTriple().getEnvironment() == llvm::Triple::Android) + if (m_arch.GetTriple().isAndroid()) return LLDB_INVALID_REGNUM; // Don't use frame pointer on android return arm64_dwarf::sp; @@ -462,7 +476,7 @@ EmulateInstructionARM64::BranchTo (const Context &context, uint32_t N, addr_t ta } bool -EmulateInstructionARM64::ConditionHolds (const uint32_t cond, bool *is_conditional) +EmulateInstructionARM64::ConditionHolds (const uint32_t cond) { // If we are ignoring conditions, then always return true. // this allows us to iterate over disassembly code and still @@ -470,10 +484,7 @@ EmulateInstructionARM64::ConditionHolds (const uint32_t cond, bool *is_condition // bits set in the CPSR register... if (m_ignore_conditions) return true; - - if (is_conditional) - *is_conditional = true; - + bool result = false; switch (UnsignedBits(cond, 3, 1)) { @@ -499,19 +510,18 @@ EmulateInstructionARM64::ConditionHolds (const uint32_t cond, bool *is_condition result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0); break; case 7: - result = true; - if (is_conditional) - *is_conditional = false; - break; + // Always execute (cond == 0b1110, or the special 0b1111 which gives + // opcodes different meanings, but always means execution happens. + return true; } - if (cond & 1 && cond != 15) + if (cond & 1) result = !result; return result; } bool -EmulateInstructionARM64::Emulate_addsub_imm (const uint32_t opcode) +EmulateInstructionARM64::EmulateADDSUBImm (const uint32_t opcode) { // integer d = UInt(Rd); // integer n = UInt(Rn); @@ -628,26 +638,8 @@ EmulateInstructionARM64::Emulate_addsub_imm (const uint32_t opcode) return false; } -bool -EmulateInstructionARM64::Emulate_ldstpair_off (const uint32_t opcode) -{ - return Emulate_ldstpair (opcode, AddrMode_OFF); -} - -bool -EmulateInstructionARM64::Emulate_ldstpair_pre (const uint32_t opcode) -{ - return Emulate_ldstpair (opcode, AddrMode_PRE); -} - -bool -EmulateInstructionARM64::Emulate_ldstpair_post (const uint32_t opcode) -{ - return Emulate_ldstpair (opcode, AddrMode_POST); -} - -bool -EmulateInstructionARM64::Emulate_ldstpair (const uint32_t opcode, AddrMode a_mode) +template <EmulateInstructionARM64::AddrMode a_mode> bool +EmulateInstructionARM64::EmulateLDPSTP (const uint32_t opcode) { uint32_t opc = Bits32(opcode, 31, 30); uint32_t V = Bit32(opcode, 26); @@ -776,10 +768,6 @@ EmulateInstructionARM64::Emulate_ldstpair (const uint32_t opcode, AddrMode a_mod Context context_t; Context context_t2; - context_t.type = eContextRegisterPlusOffset; - context_t2.type = eContextRegisterPlusOffset; - context_t.SetRegisterToRegisterPlusOffset (reg_info_Rt, reg_info_base, 0); - context_t2.SetRegisterToRegisterPlusOffset (reg_info_Rt2, reg_info_base, size); uint8_t buffer [RegisterValue::kMaxRegisterByteSize]; Error error; @@ -792,6 +780,13 @@ EmulateInstructionARM64::Emulate_ldstpair (const uint32_t opcode, AddrMode a_mod context_t.type = eContextPushRegisterOnStack; context_t2.type = eContextPushRegisterOnStack; } + else + { + context_t.type = eContextRegisterStore; + context_t2.type = eContextRegisterStore; + } + context_t.SetRegisterToRegisterPlusOffset (reg_info_Rt, reg_info_base, 0); + context_t2.SetRegisterToRegisterPlusOffset (reg_info_Rt2, reg_info_base, size); if (!ReadRegister (®_info_Rt, data_Rt)) return false; @@ -820,6 +815,13 @@ EmulateInstructionARM64::Emulate_ldstpair (const uint32_t opcode, AddrMode a_mod context_t.type = eContextPopRegisterOffStack; context_t2.type = eContextPopRegisterOffStack; } + else + { + context_t.type = eContextRegisterLoad; + context_t2.type = eContextRegisterLoad; + } + context_t.SetAddress(address); + context_t2.SetAddress(address + size); if (rt_unknown) memset (buffer, 'U', reg_info_Rt.byte_size); @@ -874,6 +876,132 @@ EmulateInstructionARM64::Emulate_ldstpair (const uint32_t opcode, AddrMode a_mod return true; } +template <EmulateInstructionARM64::AddrMode a_mode> bool +EmulateInstructionARM64::EmulateLDRSTRImm (const uint32_t opcode) +{ + uint32_t size = Bits32(opcode, 31, 30); + uint32_t opc = Bits32(opcode, 23, 22); + uint32_t n = Bits32(opcode, 9, 5); + uint32_t t = Bits32(opcode, 4, 0); + + bool wback; + bool postindex; + uint64_t offset; + + switch (a_mode) + { + case AddrMode_POST: + wback = true; + postindex = true; + offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); + break; + case AddrMode_PRE: + wback = true; + postindex = false; + offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); + break; + case AddrMode_OFF: + wback = false; + postindex = false; + offset = LSL(Bits32(opcode, 21, 10), size); + break; + } + + MemOp memop; + + if (Bit32(opc, 1) == 0) + { + memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE; + } + else + { + memop = MemOp_LOAD; + if (size == 2 && Bit32(opc, 0) == 1) + return false; + } + + Error error; + bool success = false; + uint64_t address; + uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; + RegisterValue data_Rt; + + if (n == 31) + address = ReadRegisterUnsigned (eRegisterKindDWARF, arm64_dwarf::sp, 0, &success); + else + address = ReadRegisterUnsigned (eRegisterKindDWARF, arm64_dwarf::x0 + n, 0, &success); + + if (!success) + return false; + + if (!postindex) + address += offset; + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, arm64_dwarf::x0 + n, reg_info_base)) + return false; + + RegisterInfo reg_info_Rt; + if (!GetRegisterInfo (eRegisterKindDWARF, arm64_dwarf::x0 + t, reg_info_Rt)) + return false; + + Context context; + switch (memop) + { + case MemOp_STORE: + if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is based off of the sp or fp register + context.type = eContextPushRegisterOnStack; + else + context.type = eContextRegisterStore; + context.SetRegisterToRegisterPlusOffset (reg_info_Rt, reg_info_base, postindex ? 0 : offset); + + if (!ReadRegister (®_info_Rt, data_Rt)) + return false; + + if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, eByteOrderLittle, error) == 0) + return false; + + if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size)) + return false; + break; + + case MemOp_LOAD: + if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is based off of the sp or fp register + context.type = eContextPopRegisterOffStack; + else + context.type = eContextRegisterLoad; + context.SetAddress(address); + + if (!ReadMemory (context, address, buffer, reg_info_Rt.byte_size)) + return false; + + if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, eByteOrderLittle, error) == 0) + return false; + + if (!WriteRegister (context, ®_info_Rt, data_Rt)) + return false; + + default: + return false; + } + + if (wback) + { + if (postindex) + address += offset; + + if (n == 31) + context.type = eContextAdjustStackPointer; + else + context.type = eContextAdjustBaseRegister; + context.SetImmediateSigned (offset); + + if (!WriteRegisterUnsigned (context, ®_info_base, address)) + return false; + } + return true; +} + bool EmulateInstructionARM64::EmulateB (const uint32_t opcode) { diff --git a/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.h b/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.h index b74eddeaaf63..d9333c2824d2 100644 --- a/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.h +++ b/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.h @@ -1,4 +1,4 @@ -//===-- EmulateInstructionARM64.h ------------------------------------*- C++ -*-===// +//===-- EmulateInstructionARM64.h -------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -10,6 +10,10 @@ #ifndef EmulateInstructionARM64_h_ #define EmulateInstructionARM64_h_ +// C Includes +// C++ Includes +// Other libraries and framework includes +// Project includes #include "lldb/Core/EmulateInstruction.h" #include "lldb/Core/Error.h" #include "lldb/Interpreter/OptionValue.h" @@ -18,6 +22,14 @@ class EmulateInstructionARM64 : public lldb_private::EmulateInstruction { public: + EmulateInstructionARM64 (const lldb_private::ArchSpec &arch) : + EmulateInstruction (arch), + m_opcode_pstate (), + m_emulated_pstate (), + m_ignore_conditions (false) + { + } + static void Initialize (); @@ -50,61 +62,46 @@ public: return false; } - virtual lldb_private::ConstString - GetPluginName(); - - virtual lldb_private::ConstString - GetShortPluginName() - { - return GetPluginNameStatic(); - } + lldb_private::ConstString + GetPluginName() override; - virtual uint32_t - GetPluginVersion() + uint32_t + GetPluginVersion() override { return 1; } bool - SetTargetTriple (const lldb_private::ArchSpec &arch); + SetTargetTriple(const lldb_private::ArchSpec &arch) override; - EmulateInstructionARM64 (const lldb_private::ArchSpec &arch) : - EmulateInstruction (arch), - m_opcode_pstate (), - m_emulated_pstate (), - m_ignore_conditions (false) - { - } - - virtual bool - SupportsEmulatingInstructionsOfType (lldb_private::InstructionType inst_type) + bool + SupportsEmulatingInstructionsOfType(lldb_private::InstructionType inst_type) override { return SupportsEmulatingInstructionsOfTypeStatic (inst_type); } - virtual bool - ReadInstruction (); + bool + ReadInstruction() override; - virtual bool - EvaluateInstruction (uint32_t evaluate_options); + bool + EvaluateInstruction(uint32_t evaluate_options) override; - virtual bool - TestEmulation (lldb_private::Stream *out_stream, - lldb_private::ArchSpec &arch, - lldb_private::OptionValueDictionary *test_data) + bool + TestEmulation(lldb_private::Stream *out_stream, + lldb_private::ArchSpec &arch, + lldb_private::OptionValueDictionary *test_data) override { return false; } - virtual bool - GetRegisterInfo (lldb::RegisterKind reg_kind, - uint32_t reg_num, - lldb_private::RegisterInfo ®_info); + bool + GetRegisterInfo(lldb::RegisterKind reg_kind, + uint32_t reg_num, + lldb_private::RegisterInfo ®_info) override; - virtual bool - CreateFunctionEntryUnwind (lldb_private::UnwindPlan &unwind_plan); + bool + CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override; - typedef enum { AddrMode_OFF, @@ -141,7 +138,6 @@ public: BitwiseOp_NOT, BitwiseOp_RBIT } BitwiseOp; - typedef enum { @@ -252,7 +248,6 @@ public: } ProcState; protected: - typedef struct { uint32_t mask; @@ -272,25 +267,19 @@ protected: BranchTo (const Context &context, uint32_t N, lldb::addr_t target); bool - ConditionHolds (const uint32_t cond, bool *is_conditional = nullptr); + ConditionHolds (const uint32_t cond); bool UsingAArch32 (); bool - Emulate_addsub_imm (const uint32_t opcode); - - bool - Emulate_ldstpair_off (const uint32_t opcode); + EmulateADDSUBImm (const uint32_t opcode); - bool - Emulate_ldstpair_pre (const uint32_t opcode); - - bool - Emulate_ldstpair_post (const uint32_t opcode); + template <AddrMode a_mode> bool + EmulateLDPSTP (const uint32_t opcode); - bool - Emulate_ldstpair (const uint32_t opcode, AddrMode a_mode); + template <AddrMode a_mode> bool + EmulateLDRSTRImm (const uint32_t opcode); bool EmulateB (const uint32_t opcode); @@ -309,4 +298,4 @@ protected: bool m_ignore_conditions; }; -#endif // EmulateInstructionARM64_h_ +#endif // EmulateInstructionARM64_h_ diff --git a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp index 66866c73a5cb..d6485f686e2c 100644 --- a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -29,6 +29,7 @@ #include "lldb/Core/DataExtractor.h" #include "lldb/Core/Stream.h" #include "lldb/Symbol/UnwindPlan.h" +#include "lldb/Target/Target.h" #include "llvm/ADT/STLExtras.h" @@ -132,10 +133,6 @@ EmulateInstructionMIPS::EmulateInstructionMIPS (const lldb_private::ArchSpec &ar features += "+dsp,"; if (arch_flags & ArchSpec::eMIPSAse_dspr2) features += "+dspr2,"; - if (arch_flags & ArchSpec::eMIPSAse_mips16) - features += "+mips16,"; - if (arch_flags & ArchSpec::eMIPSAse_micromips) - features += "+micromips,"; m_reg_info.reset (target->createMCRegInfo (triple.getTriple())); assert (m_reg_info.get()); @@ -152,6 +149,21 @@ EmulateInstructionMIPS::EmulateInstructionMIPS (const lldb_private::ArchSpec &ar m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context)); assert (m_disasm.get()); + + /* Create alternate disassembler for microMIPS */ + if (arch_flags & ArchSpec::eMIPSAse_mips16) + features += "+mips16,"; + else if (arch_flags & ArchSpec::eMIPSAse_micromips) + features += "+micromips,"; + + m_alt_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features)); + assert (m_alt_subtype_info.get()); + + m_alt_disasm.reset (target->createMCDisassembler (*m_alt_subtype_info, *m_context)); + assert (m_alt_disasm.get()); + + m_next_inst_size = 0; + m_use_alt_disaasm = false; } void @@ -221,41 +233,76 @@ EmulateInstructionMIPS::GetRegisterName (unsigned reg_num, bool alternate_name) { switch (reg_num) { - case gcc_dwarf_sp_mips: return "r29"; - case gcc_dwarf_r30_mips: return "r30"; - case gcc_dwarf_ra_mips: return "r31"; - case gcc_dwarf_f0_mips: return "f0"; - case gcc_dwarf_f1_mips: return "f1"; - case gcc_dwarf_f2_mips: return "f2"; - case gcc_dwarf_f3_mips: return "f3"; - case gcc_dwarf_f4_mips: return "f4"; - case gcc_dwarf_f5_mips: return "f5"; - case gcc_dwarf_f6_mips: return "f6"; - case gcc_dwarf_f7_mips: return "f7"; - case gcc_dwarf_f8_mips: return "f8"; - case gcc_dwarf_f9_mips: return "f9"; - case gcc_dwarf_f10_mips: return "f10"; - case gcc_dwarf_f11_mips: return "f11"; - case gcc_dwarf_f12_mips: return "f12"; - case gcc_dwarf_f13_mips: return "f13"; - case gcc_dwarf_f14_mips: return "f14"; - case gcc_dwarf_f15_mips: return "f15"; - case gcc_dwarf_f16_mips: return "f16"; - case gcc_dwarf_f17_mips: return "f17"; - case gcc_dwarf_f18_mips: return "f18"; - case gcc_dwarf_f19_mips: return "f19"; - case gcc_dwarf_f20_mips: return "f20"; - case gcc_dwarf_f21_mips: return "f21"; - case gcc_dwarf_f22_mips: return "f22"; - case gcc_dwarf_f23_mips: return "f23"; - case gcc_dwarf_f24_mips: return "f24"; - case gcc_dwarf_f25_mips: return "f25"; - case gcc_dwarf_f26_mips: return "f26"; - case gcc_dwarf_f27_mips: return "f27"; - case gcc_dwarf_f28_mips: return "f28"; - case gcc_dwarf_f29_mips: return "f29"; - case gcc_dwarf_f30_mips: return "f30"; - case gcc_dwarf_f31_mips: return "f31"; + case dwarf_sp_mips: return "r29"; + case dwarf_r30_mips: return "r30"; + case dwarf_ra_mips: return "r31"; + case dwarf_f0_mips: return "f0"; + case dwarf_f1_mips: return "f1"; + case dwarf_f2_mips: return "f2"; + case dwarf_f3_mips: return "f3"; + case dwarf_f4_mips: return "f4"; + case dwarf_f5_mips: return "f5"; + case dwarf_f6_mips: return "f6"; + case dwarf_f7_mips: return "f7"; + case dwarf_f8_mips: return "f8"; + case dwarf_f9_mips: return "f9"; + case dwarf_f10_mips: return "f10"; + case dwarf_f11_mips: return "f11"; + case dwarf_f12_mips: return "f12"; + case dwarf_f13_mips: return "f13"; + case dwarf_f14_mips: return "f14"; + case dwarf_f15_mips: return "f15"; + case dwarf_f16_mips: return "f16"; + case dwarf_f17_mips: return "f17"; + case dwarf_f18_mips: return "f18"; + case dwarf_f19_mips: return "f19"; + case dwarf_f20_mips: return "f20"; + case dwarf_f21_mips: return "f21"; + case dwarf_f22_mips: return "f22"; + case dwarf_f23_mips: return "f23"; + case dwarf_f24_mips: return "f24"; + case dwarf_f25_mips: return "f25"; + case dwarf_f26_mips: return "f26"; + case dwarf_f27_mips: return "f27"; + case dwarf_f28_mips: return "f28"; + case dwarf_f29_mips: return "f29"; + case dwarf_f30_mips: return "f30"; + case dwarf_f31_mips: return "f31"; + case dwarf_w0_mips: return "w0"; + case dwarf_w1_mips: return "w1"; + case dwarf_w2_mips: return "w2"; + case dwarf_w3_mips: return "w3"; + case dwarf_w4_mips: return "w4"; + case dwarf_w5_mips: return "w5"; + case dwarf_w6_mips: return "w6"; + case dwarf_w7_mips: return "w7"; + case dwarf_w8_mips: return "w8"; + case dwarf_w9_mips: return "w9"; + case dwarf_w10_mips: return "w10"; + case dwarf_w11_mips: return "w11"; + case dwarf_w12_mips: return "w12"; + case dwarf_w13_mips: return "w13"; + case dwarf_w14_mips: return "w14"; + case dwarf_w15_mips: return "w15"; + case dwarf_w16_mips: return "w16"; + case dwarf_w17_mips: return "w17"; + case dwarf_w18_mips: return "w18"; + case dwarf_w19_mips: return "w19"; + case dwarf_w20_mips: return "w20"; + case dwarf_w21_mips: return "w21"; + case dwarf_w22_mips: return "w22"; + case dwarf_w23_mips: return "w23"; + case dwarf_w24_mips: return "w24"; + case dwarf_w25_mips: return "w25"; + case dwarf_w26_mips: return "w26"; + case dwarf_w27_mips: return "w27"; + case dwarf_w28_mips: return "w28"; + case dwarf_w29_mips: return "w29"; + case dwarf_w30_mips: return "w30"; + case dwarf_w31_mips: return "w31"; + case dwarf_mir_mips: return "mir"; + case dwarf_mcsr_mips: return "mcsr"; + case dwarf_config5_mips: return "config5"; default: break; } @@ -264,78 +311,113 @@ EmulateInstructionMIPS::GetRegisterName (unsigned reg_num, bool alternate_name) switch (reg_num) { - case gcc_dwarf_zero_mips: return "r0"; - case gcc_dwarf_r1_mips: return "r1"; - case gcc_dwarf_r2_mips: return "r2"; - case gcc_dwarf_r3_mips: return "r3"; - case gcc_dwarf_r4_mips: return "r4"; - case gcc_dwarf_r5_mips: return "r5"; - case gcc_dwarf_r6_mips: return "r6"; - case gcc_dwarf_r7_mips: return "r7"; - case gcc_dwarf_r8_mips: return "r8"; - case gcc_dwarf_r9_mips: return "r9"; - case gcc_dwarf_r10_mips: return "r10"; - case gcc_dwarf_r11_mips: return "r11"; - case gcc_dwarf_r12_mips: return "r12"; - case gcc_dwarf_r13_mips: return "r13"; - case gcc_dwarf_r14_mips: return "r14"; - case gcc_dwarf_r15_mips: return "r15"; - case gcc_dwarf_r16_mips: return "r16"; - case gcc_dwarf_r17_mips: return "r17"; - case gcc_dwarf_r18_mips: return "r18"; - case gcc_dwarf_r19_mips: return "r19"; - case gcc_dwarf_r20_mips: return "r20"; - case gcc_dwarf_r21_mips: return "r21"; - case gcc_dwarf_r22_mips: return "r22"; - case gcc_dwarf_r23_mips: return "r23"; - case gcc_dwarf_r24_mips: return "r24"; - case gcc_dwarf_r25_mips: return "r25"; - case gcc_dwarf_r26_mips: return "r26"; - case gcc_dwarf_r27_mips: return "r27"; - case gcc_dwarf_gp_mips: return "gp"; - case gcc_dwarf_sp_mips: return "sp"; - case gcc_dwarf_r30_mips: return "fp"; - case gcc_dwarf_ra_mips: return "ra"; - case gcc_dwarf_sr_mips: return "sr"; - case gcc_dwarf_lo_mips: return "lo"; - case gcc_dwarf_hi_mips: return "hi"; - case gcc_dwarf_bad_mips: return "bad"; - case gcc_dwarf_cause_mips: return "cause"; - case gcc_dwarf_pc_mips: return "pc"; - case gcc_dwarf_f0_mips: return "f0"; - case gcc_dwarf_f1_mips: return "f1"; - case gcc_dwarf_f2_mips: return "f2"; - case gcc_dwarf_f3_mips: return "f3"; - case gcc_dwarf_f4_mips: return "f4"; - case gcc_dwarf_f5_mips: return "f5"; - case gcc_dwarf_f6_mips: return "f6"; - case gcc_dwarf_f7_mips: return "f7"; - case gcc_dwarf_f8_mips: return "f8"; - case gcc_dwarf_f9_mips: return "f9"; - case gcc_dwarf_f10_mips: return "f10"; - case gcc_dwarf_f11_mips: return "f11"; - case gcc_dwarf_f12_mips: return "f12"; - case gcc_dwarf_f13_mips: return "f13"; - case gcc_dwarf_f14_mips: return "f14"; - case gcc_dwarf_f15_mips: return "f15"; - case gcc_dwarf_f16_mips: return "f16"; - case gcc_dwarf_f17_mips: return "f17"; - case gcc_dwarf_f18_mips: return "f18"; - case gcc_dwarf_f19_mips: return "f19"; - case gcc_dwarf_f20_mips: return "f20"; - case gcc_dwarf_f21_mips: return "f21"; - case gcc_dwarf_f22_mips: return "f22"; - case gcc_dwarf_f23_mips: return "f23"; - case gcc_dwarf_f24_mips: return "f24"; - case gcc_dwarf_f25_mips: return "f25"; - case gcc_dwarf_f26_mips: return "f26"; - case gcc_dwarf_f27_mips: return "f27"; - case gcc_dwarf_f28_mips: return "f28"; - case gcc_dwarf_f29_mips: return "f29"; - case gcc_dwarf_f30_mips: return "f30"; - case gcc_dwarf_f31_mips: return "f31"; - case gcc_dwarf_fcsr_mips: return "fcsr"; - case gcc_dwarf_fir_mips: return "fir"; + case dwarf_zero_mips: return "r0"; + case dwarf_r1_mips: return "r1"; + case dwarf_r2_mips: return "r2"; + case dwarf_r3_mips: return "r3"; + case dwarf_r4_mips: return "r4"; + case dwarf_r5_mips: return "r5"; + case dwarf_r6_mips: return "r6"; + case dwarf_r7_mips: return "r7"; + case dwarf_r8_mips: return "r8"; + case dwarf_r9_mips: return "r9"; + case dwarf_r10_mips: return "r10"; + case dwarf_r11_mips: return "r11"; + case dwarf_r12_mips: return "r12"; + case dwarf_r13_mips: return "r13"; + case dwarf_r14_mips: return "r14"; + case dwarf_r15_mips: return "r15"; + case dwarf_r16_mips: return "r16"; + case dwarf_r17_mips: return "r17"; + case dwarf_r18_mips: return "r18"; + case dwarf_r19_mips: return "r19"; + case dwarf_r20_mips: return "r20"; + case dwarf_r21_mips: return "r21"; + case dwarf_r22_mips: return "r22"; + case dwarf_r23_mips: return "r23"; + case dwarf_r24_mips: return "r24"; + case dwarf_r25_mips: return "r25"; + case dwarf_r26_mips: return "r26"; + case dwarf_r27_mips: return "r27"; + case dwarf_gp_mips: return "gp"; + case dwarf_sp_mips: return "sp"; + case dwarf_r30_mips: return "fp"; + case dwarf_ra_mips: return "ra"; + case dwarf_sr_mips: return "sr"; + case dwarf_lo_mips: return "lo"; + case dwarf_hi_mips: return "hi"; + case dwarf_bad_mips: return "bad"; + case dwarf_cause_mips: return "cause"; + case dwarf_pc_mips: return "pc"; + case dwarf_f0_mips: return "f0"; + case dwarf_f1_mips: return "f1"; + case dwarf_f2_mips: return "f2"; + case dwarf_f3_mips: return "f3"; + case dwarf_f4_mips: return "f4"; + case dwarf_f5_mips: return "f5"; + case dwarf_f6_mips: return "f6"; + case dwarf_f7_mips: return "f7"; + case dwarf_f8_mips: return "f8"; + case dwarf_f9_mips: return "f9"; + case dwarf_f10_mips: return "f10"; + case dwarf_f11_mips: return "f11"; + case dwarf_f12_mips: return "f12"; + case dwarf_f13_mips: return "f13"; + case dwarf_f14_mips: return "f14"; + case dwarf_f15_mips: return "f15"; + case dwarf_f16_mips: return "f16"; + case dwarf_f17_mips: return "f17"; + case dwarf_f18_mips: return "f18"; + case dwarf_f19_mips: return "f19"; + case dwarf_f20_mips: return "f20"; + case dwarf_f21_mips: return "f21"; + case dwarf_f22_mips: return "f22"; + case dwarf_f23_mips: return "f23"; + case dwarf_f24_mips: return "f24"; + case dwarf_f25_mips: return "f25"; + case dwarf_f26_mips: return "f26"; + case dwarf_f27_mips: return "f27"; + case dwarf_f28_mips: return "f28"; + case dwarf_f29_mips: return "f29"; + case dwarf_f30_mips: return "f30"; + case dwarf_f31_mips: return "f31"; + case dwarf_fcsr_mips: return "fcsr"; + case dwarf_fir_mips: return "fir"; + case dwarf_w0_mips: return "w0"; + case dwarf_w1_mips: return "w1"; + case dwarf_w2_mips: return "w2"; + case dwarf_w3_mips: return "w3"; + case dwarf_w4_mips: return "w4"; + case dwarf_w5_mips: return "w5"; + case dwarf_w6_mips: return "w6"; + case dwarf_w7_mips: return "w7"; + case dwarf_w8_mips: return "w8"; + case dwarf_w9_mips: return "w9"; + case dwarf_w10_mips: return "w10"; + case dwarf_w11_mips: return "w11"; + case dwarf_w12_mips: return "w12"; + case dwarf_w13_mips: return "w13"; + case dwarf_w14_mips: return "w14"; + case dwarf_w15_mips: return "w15"; + case dwarf_w16_mips: return "w16"; + case dwarf_w17_mips: return "w17"; + case dwarf_w18_mips: return "w18"; + case dwarf_w19_mips: return "w19"; + case dwarf_w20_mips: return "w20"; + case dwarf_w21_mips: return "w21"; + case dwarf_w22_mips: return "w22"; + case dwarf_w23_mips: return "w23"; + case dwarf_w24_mips: return "w24"; + case dwarf_w25_mips: return "w25"; + case dwarf_w26_mips: return "w26"; + case dwarf_w27_mips: return "w27"; + case dwarf_w28_mips: return "w28"; + case dwarf_w29_mips: return "w29"; + case dwarf_w30_mips: return "w30"; + case dwarf_w31_mips: return "w31"; + case dwarf_mcsr_mips: return "mcsr"; + case dwarf_mir_mips: return "mir"; + case dwarf_config5_mips: return "config5"; } return nullptr; } @@ -347,11 +429,11 @@ EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num { switch (reg_num) { - case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_pc_mips; break; - case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sp_mips; break; - case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_r30_mips; break; - case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_ra_mips; break; - case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sr_mips; break; + case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc_mips; break; + case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp_mips; break; + case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_r30_mips; break; + case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = dwarf_ra_mips; break; + case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sr_mips; break; default: return false; } @@ -362,18 +444,24 @@ EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num ::memset (®_info, 0, sizeof(RegisterInfo)); ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds)); - if (reg_num == gcc_dwarf_sr_mips || reg_num == gcc_dwarf_fcsr_mips || reg_num == gcc_dwarf_fir_mips) + if (reg_num == dwarf_sr_mips || reg_num == dwarf_fcsr_mips || reg_num == dwarf_fir_mips || reg_num == dwarf_mcsr_mips || reg_num == dwarf_mir_mips || reg_num == dwarf_config5_mips) { reg_info.byte_size = 4; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } - else if ((int)reg_num >= gcc_dwarf_zero_mips && (int)reg_num <= gcc_dwarf_f31_mips) + else if ((int)reg_num >= dwarf_zero_mips && (int)reg_num <= dwarf_f31_mips) { reg_info.byte_size = 4; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } + else if ((int)reg_num >= dwarf_w0_mips && (int)reg_num <= dwarf_w31_mips) + { + reg_info.byte_size = 16; + reg_info.format = eFormatVectorOfUInt8; + reg_info.encoding = eEncodingVector; + } else { return false; @@ -385,11 +473,11 @@ EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num switch (reg_num) { - case gcc_dwarf_r30_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; - case gcc_dwarf_ra_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; - case gcc_dwarf_sp_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; - case gcc_dwarf_pc_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; - case gcc_dwarf_sr_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; + case dwarf_r30_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; + case dwarf_ra_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; + case dwarf_sp_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; + case dwarf_pc_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; + case dwarf_sr_mips: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; default: break; } return true; @@ -409,6 +497,96 @@ EmulateInstructionMIPS::GetOpcodeForInstruction (const char *op_name) { "ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu, "ADDIU rt,rs,immediate" }, { "SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt,offset(rs)" }, { "LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt,offset(base)" }, + //---------------------------------------------------------------------- + // MicroMIPS Prologue/Epilogue instructions + //---------------------------------------------------------------------- + { "ADDIUSP_MM", &EmulateInstructionMIPS::Emulate_ADDIUSP, "ADDIU immediate" }, + { "ADDIUS5_MM", &EmulateInstructionMIPS::Emulate_ADDIUS5, "ADDIUS5 rd,immediate" }, + { "SWSP_MM", &EmulateInstructionMIPS::Emulate_SWSP, "SWSP rt,offset(sp)" }, + { "SWM16_MM", &EmulateInstructionMIPS::Emulate_SWM16_32, "SWM16 reglist,offset(sp)" }, + { "SWM32_MM", &EmulateInstructionMIPS::Emulate_SWM16_32, "SWM32 reglist,offset(base)" }, + { "SWP_MM", &EmulateInstructionMIPS::Emulate_SWM16_32, "SWP rs1,offset(base)" }, + { "LWSP_MM", &EmulateInstructionMIPS::Emulate_LWSP, "LWSP rt,offset(sp)" }, + { "LWM16_MM", &EmulateInstructionMIPS::Emulate_LWM16_32, "LWM16 reglist,offset(sp)" }, + { "LWM32_MM", &EmulateInstructionMIPS::Emulate_LWM16_32, "LWM32 reglist,offset(base)" }, + { "LWP_MM", &EmulateInstructionMIPS::Emulate_LWM16_32, "LWP rd,offset(base)" }, + { "JRADDIUSP", &EmulateInstructionMIPS::Emulate_JRADDIUSP, "JRADDIUSP immediate" }, + //---------------------------------------------------------------------- + + // Load/Store instructions + //---------------------------------------------------------------------- + /* Following list of emulated instructions are required by implementation of hardware watchpoint + for MIPS in lldb. As we just need the address accessed by instructions, we have generalised + all these instructions in 2 functions depending on their addressing modes */ + + { "LB", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LB rt, offset(base)" }, + { "LBE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBE rt, offset(base)" }, + { "LBU", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBU rt, offset(base)" }, + { "LBUE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBUE rt, offset(base)" }, + { "LDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDC1 ft, offset(base)" }, + { "LD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LD rt, offset(base)" }, + { "LDL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDL rt, offset(base)" }, + { "LDR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDR rt, offset(base)" }, + { "LLD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLD rt, offset(base)" }, + { "LDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LDC2 rt, offset(base)" }, + { "LDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LDXC1 fd, index (base)" }, + { "LH", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LH rt, offset(base)" }, + { "LHE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHE rt, offset(base)" }, + { "LHU", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHU rt, offset(base)" }, + { "LHUE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHUE rt, offset(base)" }, + { "LL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LL rt, offset(base)" }, + { "LLE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLE rt, offset(base)" }, + { "LUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LUXC1 fd, index (base)" }, + { "LW", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LW rt, offset(base)" }, + { "LWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWC1 ft, offset(base)" }, + { "LWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWC2 rt, offset(base)" }, + { "LWE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWE rt, offset(base)" }, + { "LWL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWL rt, offset(base)" }, + { "LWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWLE rt, offset(base)" }, + { "LWR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWR rt, offset(base)" }, + { "LWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWRE rt, offset(base)" }, + { "LWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "LWXC1 fd, index (base)" }, + { "LLX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLX rt, offset(base)" }, + { "LLXE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLXE rt, offset(base)" }, + { "LLDX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LLDX rt, offset(base)" }, + + { "SB", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SB rt, offset(base)" }, + { "SBE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SBE rt, offset(base)" }, + { "SC", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SC rt, offset(base)" }, + { "SCE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCE rt, offset(base)" }, + { "SCD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCD rt, offset(base)" }, + { "SD", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SD rt, offset(base)" }, + { "SDL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDL rt, offset(base)" }, + { "SDR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDR rt, offset(base)" }, + { "SDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDC1 ft, offset(base)" }, + { "SDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SDC2 rt, offset(base)" }, + { "SDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "SDXC1 fs, index(base)" }, + { "SH", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SH rt, offset(base)" }, + { "SHE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SHE rt, offset(base)" }, + { "SUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "SUXC1 fs, index (base)" }, + { "SWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWC1 ft, offset(base)" }, + { "SWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWC2 rt, offset(base)" }, + { "SWE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWE rt, offset(base)" }, + { "SWL", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWL rt, offset(base)" }, + { "SWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWLE rt, offset(base)" }, + { "SWR", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWR rt, offset(base)" }, + { "SWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWRE rt, offset(base)" }, + { "SWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg, "SWXC1 fs, index (base)" }, + { "SCX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCX rt, offset(base)" }, + { "SCXE", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCXE rt, offset(base)" }, + { "SCDX", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SCDX rt, offset(base)" }, + + //---------------------------------------------------------------------- + // MicroMIPS Load/Store instructions + //---------------------------------------------------------------------- + { "LBU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LBU16 rt, decoded_offset(base)" }, + { "LHU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LHU16 rt, left_shifted_offset(base)" }, + { "LW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LW16 rt, left_shifted_offset(base)" }, + { "LWGP_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "LWGP rt, left_shifted_offset(gp)" }, + { "SH16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SH16 rt, left_shifted_offset(base)" }, + { "SW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SW16 rt, left_shifted_offset(base)" }, + { "SW_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SWSP rt, left_shifted_offset(base)" }, + { "SB16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm, "SB16 rt, offset(base)" }, //---------------------------------------------------------------------- // Branch instructions @@ -471,6 +649,34 @@ EmulateInstructionMIPS::GetOpcodeForInstruction (const char *op_name) { "BC1ANY2T", &EmulateInstructionMIPS::Emulate_BC1ANY2T, "BC1ANY2T cc, offset" }, { "BC1ANY4F", &EmulateInstructionMIPS::Emulate_BC1ANY4F, "BC1ANY4F cc, offset" }, { "BC1ANY4T", &EmulateInstructionMIPS::Emulate_BC1ANY4T, "BC1ANY4T cc, offset" }, + { "BNZ_B", &EmulateInstructionMIPS::Emulate_BNZB, "BNZ.b wt,s16" }, + { "BNZ_H", &EmulateInstructionMIPS::Emulate_BNZH, "BNZ.h wt,s16" }, + { "BNZ_W", &EmulateInstructionMIPS::Emulate_BNZW, "BNZ.w wt,s16" }, + { "BNZ_D", &EmulateInstructionMIPS::Emulate_BNZD, "BNZ.d wt,s16" }, + { "BZ_B", &EmulateInstructionMIPS::Emulate_BZB, "BZ.b wt,s16" }, + { "BZ_H", &EmulateInstructionMIPS::Emulate_BZH, "BZ.h wt,s16" }, + { "BZ_W", &EmulateInstructionMIPS::Emulate_BZW, "BZ.w wt,s16" }, + { "BZ_D", &EmulateInstructionMIPS::Emulate_BZD, "BZ.d wt,s16" }, + { "BNZ_V", &EmulateInstructionMIPS::Emulate_BNZV, "BNZ.V wt,s16" }, + { "BZ_V", &EmulateInstructionMIPS::Emulate_BZV, "BZ.V wt,s16" }, + + //---------------------------------------------------------------------- + // MicroMIPS Branch instructions + //---------------------------------------------------------------------- + { "B16_MM", &EmulateInstructionMIPS::Emulate_B16_MM, "B16 offset" }, + { "BEQZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BEQZ16 rs, offset" }, + { "BNEZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BNEZ16 rs, offset" }, + { "BEQZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BEQZC rs, offset" }, + { "BNEZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BNEZC rs, offset" }, + { "BGEZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BGEZALS rs, offset" }, + { "BLTZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM, "BLTZALS rs, offset" }, + { "JALR16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALR16 rs" }, + { "JALRS16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALRS16 rs" }, + { "JR16_MM", &EmulateInstructionMIPS::Emulate_JR, "JR16 rs rs" }, + { "JRC16_MM", &EmulateInstructionMIPS::Emulate_JR, "JRC16 rs rs" }, + { "JALS_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALS target" }, + { "JALX_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALX target" }, + { "JALRS_MM", &EmulateInstructionMIPS::Emulate_JALRS, "JALRS rt, rs" }, }; static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes); @@ -484,6 +690,76 @@ EmulateInstructionMIPS::GetOpcodeForInstruction (const char *op_name) return NULL; } +uint32_t +EmulateInstructionMIPS::GetSizeOfInstruction (lldb_private::DataExtractor& data, uint64_t inst_addr) +{ + uint64_t next_inst_size = 0; + llvm::MCInst mc_insn; + llvm::MCDisassembler::DecodeStatus decode_status; + llvm::ArrayRef<uint8_t> raw_insn (data.GetDataStart(), data.GetByteSize()); + + if (m_use_alt_disaasm) + decode_status = m_alt_disasm->getInstruction (mc_insn, next_inst_size, raw_insn, inst_addr, llvm::nulls(), llvm::nulls()); + else + decode_status = m_disasm->getInstruction (mc_insn, next_inst_size, raw_insn, inst_addr, llvm::nulls(), llvm::nulls()); + + if (decode_status != llvm::MCDisassembler::Success) + return false; + + return m_insn_info->get(mc_insn.getOpcode()).getSize(); +} + +bool +EmulateInstructionMIPS::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target) +{ + m_use_alt_disaasm = false; + + if (EmulateInstruction::SetInstruction (insn_opcode, inst_addr, target)) + { + if (inst_addr.GetAddressClass() == eAddressClassCodeAlternateISA) + { + Error error; + lldb::addr_t load_addr = LLDB_INVALID_ADDRESS; + + /* + * The address belongs to microMIPS function. To find the size of + * next instruction use microMIPS disassembler. + */ + m_use_alt_disaasm = true; + + uint32_t current_inst_size = insn_opcode.GetByteSize(); + uint8_t buf[sizeof(uint32_t)]; + uint64_t next_inst_addr = (m_addr & (~1ull)) + current_inst_size; + Address next_addr (next_inst_addr); + + const size_t bytes_read = target->ReadMemory (next_addr, /* Address of next instruction */ + true, /* prefer_file_cache */ + buf, + sizeof(uint32_t), + error, + &load_addr); + + if (bytes_read == 0) + return true; + + DataExtractor data (buf, sizeof(uint32_t), GetByteOrder(), GetAddressByteSize()); + m_next_inst_size = GetSizeOfInstruction (data, next_inst_addr); + return true; + } + else + { + /* + * If the address class is not eAddressClassCodeAlternateISA then + * the function is not microMIPS. In this case instruction size is + * always 4 bytes. + */ + m_next_inst_size = 4; + return true; + } + } + return false; +} + bool EmulateInstructionMIPS::ReadInstruction () { @@ -514,7 +790,11 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) { llvm::MCDisassembler::DecodeStatus decode_status; llvm::ArrayRef<uint8_t> raw_insn (data.GetDataStart(), data.GetByteSize()); - decode_status = m_disasm->getInstruction (mc_insn, insn_size, raw_insn, m_addr, llvm::nulls(), llvm::nulls()); + if (m_use_alt_disaasm) + decode_status = m_alt_disasm->getInstruction (mc_insn, insn_size, raw_insn, m_addr, llvm::nulls(), llvm::nulls()); + else + decode_status = m_disasm->getInstruction (mc_insn, insn_size, raw_insn, m_addr, llvm::nulls(), llvm::nulls()); + if (decode_status != llvm::MCDisassembler::Success) return false; } @@ -542,7 +822,7 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; } @@ -554,7 +834,7 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -563,7 +843,7 @@ EmulateInstructionMIPS::EvaluateInstruction (uint32_t evaluate_options) { new_pc += 4; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, new_pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, new_pc)) return false; } } @@ -581,10 +861,10 @@ EmulateInstructionMIPS::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) const bool can_replace = false; // Our previous Call Frame Address is the stack pointer - row->GetCFAValue().SetIsRegisterPlusOffset(gcc_dwarf_sp_mips, 0); + row->GetCFAValue().SetIsRegisterPlusOffset(dwarf_sp_mips, 0); // Our previous PC is in the RA - row->SetRegisterLocationToRegister(gcc_dwarf_pc_mips, gcc_dwarf_ra_mips, can_replace); + row->SetRegisterLocationToRegister(dwarf_pc_mips, dwarf_ra_mips, can_replace); unwind_plan.AppendRow (row); @@ -592,6 +872,7 @@ EmulateInstructionMIPS::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) unwind_plan.SetSourceName ("EmulateInstructionMIPS"); unwind_plan.SetSourcedFromCompiler (eLazyBoolNo); unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes); + unwind_plan.SetReturnAddressRegister (dwarf_ra_mips); return true; } @@ -601,18 +882,18 @@ EmulateInstructionMIPS::nonvolatile_reg_p (uint32_t regnum) { switch (regnum) { - case gcc_dwarf_r16_mips: - case gcc_dwarf_r17_mips: - case gcc_dwarf_r18_mips: - case gcc_dwarf_r19_mips: - case gcc_dwarf_r20_mips: - case gcc_dwarf_r21_mips: - case gcc_dwarf_r22_mips: - case gcc_dwarf_r23_mips: - case gcc_dwarf_gp_mips: - case gcc_dwarf_sp_mips: - case gcc_dwarf_r30_mips: - case gcc_dwarf_ra_mips: + case dwarf_r16_mips: + case dwarf_r17_mips: + case dwarf_r18_mips: + case dwarf_r19_mips: + case dwarf_r20_mips: + case dwarf_r21_mips: + case dwarf_r22_mips: + case dwarf_r23_mips: + case dwarf_gp_mips: + case dwarf_sp_mips: + case dwarf_r30_mips: + case dwarf_ra_mips: return true; default: return false; @@ -633,10 +914,10 @@ EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn) src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); /* Check if this is addiu sp,<src>,imm16 */ - if (dst == gcc_dwarf_sp_mips) + if (dst == dwarf_sp_mips) { /* read <src> register */ - uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + src, 0, &success); + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success); if (!success) return false; @@ -644,13 +925,13 @@ EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn) Context context; RegisterInfo reg_info_sp; - if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips, reg_info_sp)) + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) context.SetRegisterPlusOffset (reg_info_sp, imm); /* We are allocating bytes on stack */ context.type = eContextAdjustStackPointer; - WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips, result); + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); } return true; @@ -663,30 +944,206 @@ EmulateInstructionMIPS::Emulate_SW (llvm::MCInst& insn) uint32_t imm16 = insn.getOperand(2).getImm(); uint32_t imm = SignedBits(imm16, 15, 0); uint32_t src, base; + int32_t address; + Context bad_vaddr_context; + + RegisterInfo reg_info_base; src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address = (int32_t)ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + /* We look for sp based non-volatile register stores */ - if (base == gcc_dwarf_sp_mips && nonvolatile_reg_p (src)) + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) + { + + RegisterInfo reg_info_src; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) + return false; + + Context context; + RegisterValue data_src; + context.type = eContextPushRegisterOnStack; + context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0); + + uint8_t buffer [RegisterValue::kMaxRegisterByteSize]; + Error error; + + if (!ReadRegister (®_info_base, data_src)) + return false; + + if (data_src.GetAsMemoryData (®_info_src, buffer, reg_info_src.byte_size, eByteOrderLittle, error) == 0) + return false; + + if (!WriteMemory (context, address, buffer, reg_info_src.byte_size)) + return false; + + return true; + } + + return false; +} + +bool +EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) +{ + bool success =false; + uint32_t src, base; + int32_t imm, address; + Context bad_vaddr_context; + + src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + imm = insn.getOperand(2).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address = (int32_t)ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) { - uint32_t address; - RegisterInfo reg_info_base; + RegisterValue data_src; RegisterInfo reg_info_src; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips + base, reg_info_base) - || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) return false; - /* read SP */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + base, 0, &success); + Context context; + context.type = eContextPopRegisterOffStack; + context.SetAddress (address); + + if (!WriteRegister (context, ®_info_src, data_src)) + return false; + + return true; + } + + return false; +} + +bool +EmulateInstructionMIPS::Emulate_ADDIUSP (llvm::MCInst& insn) +{ + bool success = false; + const uint32_t imm9 = insn.getOperand(0).getImm(); + uint64_t result; + + // This instruction operates implicitly on stack pointer, so read <sp> register. + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_sp_mips, 0, &success); + if (!success) + return false; + + result = src_opd_val + imm9; + + Context context; + RegisterInfo reg_info_sp; + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, imm9); + + // We are adjusting the stack. + context.type = eContextAdjustStackPointer; + + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); + return true; +} + +bool +EmulateInstructionMIPS::Emulate_ADDIUS5 (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + const uint32_t imm4 = insn.getOperand(2).getImm(); + uint64_t result; + + // The source and destination register is same for this instruction. + base = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + + // We are looking for stack adjustment only + if (base == dwarf_sp_mips) + { + // Read stack pointer register + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); if (!success) return false; - /* destination address */ - address = address + imm; + result = src_opd_val + imm4; Context context; + RegisterInfo reg_info_sp; + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, imm4); + + // We are adjusting the stack. + context.type = eContextAdjustStackPointer; + + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result); + } + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_SWSP (llvm::MCInst& insn) +{ + bool success = false; + uint32_t imm5 = insn.getOperand(2).getImm(); + uint32_t src, base; + Context bad_vaddr_context; + uint32_t address; + + src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + + RegisterInfo reg_info_base; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + // read base register + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + // destination address + address = address + imm5; + + // We use bad_vaddr_context to store base address which is used by H/W watchpoint + // Set the bad_vaddr register with base address used in the instruction + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + // We look for sp based non-volatile register stores. + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) + { + RegisterInfo reg_info_src; + Context context; RegisterValue data_src; context.type = eContextPushRegisterOnStack; context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0); @@ -709,24 +1166,118 @@ EmulateInstructionMIPS::Emulate_SW (llvm::MCInst& insn) return false; } +/* Emulate SWM16,SWM32 and SWP instruction. + + SWM16 always has stack pointer as a base register (but it is still available in MCInst as an operand). + SWM32 and SWP can have base register other than stack pointer. +*/ bool -EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) +EmulateInstructionMIPS::Emulate_SWM16_32 (llvm::MCInst& insn) { + bool success = false; uint32_t src, base; + uint32_t num_operands = insn.getNumOperands(); // No of operands vary based on no of regs to store. - src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); - base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + // Base register is second last operand of the instruction. + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + + // We are looking for sp based stores so if base is not a stack pointer then don't proceed. + if (base != dwarf_sp_mips) + return false; + + // offset is always the last operand. + uint32_t offset = insn.getOperand(num_operands-1).getImm(); + + RegisterInfo reg_info_base; + RegisterInfo reg_info_src; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + // read SP + uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + // Resulting base addrss + base_address = base_address + offset; + + // Total no of registers to be stored are num_operands-2. + for (uint32_t i = 0; i < num_operands - 2; i++) + { + // Get the register number to be stored. + src = m_reg_info->getEncodingValue (insn.getOperand(i).getReg()); + + /* + Record only non-volatile stores. + This check is required for SWP instruction because source operand could be any register. + SWM16 and SWM32 instruction always has saved registers as source operands. + */ + if (!nonvolatile_reg_p (src)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) + return false; + + Context context; + RegisterValue data_src; + context.type = eContextPushRegisterOnStack; + context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0); + + uint8_t buffer [RegisterValue::kMaxRegisterByteSize]; + Error error; + + if (!ReadRegister (®_info_base, data_src)) + return false; + + if (data_src.GetAsMemoryData (®_info_src, buffer, reg_info_src.byte_size, eByteOrderLittle, error) == 0) + return false; + + if (!WriteMemory (context, base_address, buffer, reg_info_src.byte_size)) + return false; + + // Stack address for next register + base_address = base_address + reg_info_src.byte_size; + } + return true; +} + +bool +EmulateInstructionMIPS::Emulate_LWSP (llvm::MCInst& insn) +{ + bool success = false; + uint32_t src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + uint32_t base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + uint32_t imm5 = insn.getOperand(2).getImm(); + Context bad_vaddr_context; + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; - if (base == gcc_dwarf_sp_mips && nonvolatile_reg_p (src)) + // read base register + uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + base_address = base_address + imm5; + + // We use bad_vaddr_context to store base address which is used by H/W watchpoint + // Set the bad_vaddr register with base address used in the instruction + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, base_address); + + if (base == dwarf_sp_mips && nonvolatile_reg_p (src)) { RegisterValue data_src; RegisterInfo reg_info_src; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src)) return false; Context context; - context.type = eContextRegisterLoad; + context.type = eContextPopRegisterOffStack; + context.SetAddress (base_address); if (!WriteRegister (context, ®_info_src, data_src)) return false; @@ -737,6 +1288,105 @@ EmulateInstructionMIPS::Emulate_LW (llvm::MCInst& insn) return false; } +/* Emulate LWM16, LWM32 and LWP instructions. + + LWM16 always has stack pointer as a base register (but it is still available in MCInst as an operand). + LWM32 and LWP can have base register other than stack pointer. +*/ +bool +EmulateInstructionMIPS::Emulate_LWM16_32 (llvm::MCInst& insn) +{ + bool success = false; + uint32_t dst, base; + uint32_t num_operands = insn.getNumOperands(); // No of operands vary based on no of regs to store. + uint32_t imm = insn.getOperand(num_operands-1).getImm(); // imm is the last operand in the instruction. + + // Base register is second last operand of the instruction. + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + + // We are looking for sp based loads so if base is not a stack pointer then don't proceed. + if (base != dwarf_sp_mips) + return false; + + uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + base_address = base_address + imm; + + RegisterValue data_dst; + RegisterInfo reg_info_dst; + + // Total no of registers to be re-stored are num_operands-2. + for (uint32_t i = 0; i < num_operands - 2; i++) + { + // Get the register number to be re-stored. + dst = m_reg_info->getEncodingValue (insn.getOperand(i).getReg()); + + /* + Record only non-volatile loads. + This check is required for LWP instruction because destination operand could be any register. + LWM16 and LWM32 instruction always has saved registers as destination operands. + */ + if (!nonvolatile_reg_p (dst)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + dst, reg_info_dst)) + return false; + + Context context; + context.type = eContextPopRegisterOffStack; + context.SetAddress (base_address + (i*4)); + + if (!WriteRegister (context, ®_info_dst, data_dst)) + return false; + } + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_JRADDIUSP (llvm::MCInst& insn) +{ + bool success = false; + int32_t imm5 = insn.getOperand(0).getImm(); + + /* JRADDIUSP immediate + * PC <- RA + * SP <- SP + zero_extend(Immediate << 2) + */ + + // This instruction operates implicitly on stack pointer, so read <sp> register. + int32_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_sp_mips, 0, &success); + if (!success) + return false; + + int32_t ra_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_ra_mips, 0, &success); + if (!success) + return false; + + int32_t result = src_opd_val + imm5; + + Context context; + + // Update the PC + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, ra_val)) + return false; + + RegisterInfo reg_info_sp; + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp)) + context.SetRegisterPlusOffset (reg_info_sp, imm5); + + // We are adjusting stack + context.type = eContextAdjustStackPointer; + + // update SP + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, result)) + return false; + + return true; +} + bool EmulateInstructionMIPS::Emulate_BEQ (llvm::MCInst& insn) { @@ -754,15 +1404,15 @@ EmulateInstructionMIPS::Emulate_BEQ (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -774,13 +1424,270 @@ EmulateInstructionMIPS::Emulate_BEQ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; } bool +EmulateInstructionMIPS::Emulate_B16_MM (llvm::MCInst& insn) +{ + bool success = false; + int32_t offset, pc, target; + uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize(); + + offset = insn.getOperand(0).getImm(); + + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + // unconditional branch + target = pc + offset; + + Context context; + context.type = eContextRelativeBranchImmediate; + context.SetImmediate (current_inst_size + offset); + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + return true; +} + +/* + BEQZC, BNEZC are 32 bit compact instructions without a delay slot. + BEQZ16, BNEZ16 are 16 bit instructions with delay slot. + BGEZALS, BLTZALS are 16 bit instructions with short (2-byte) delay slot. +*/ +bool +EmulateInstructionMIPS::Emulate_Branch_MM (llvm::MCInst& insn) +{ + bool success = false; + int32_t target = 0; + uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize(); + const char *op_name = m_insn_info->getName (insn.getOpcode ()); + bool update_ra = false; + uint32_t ra_offset = 0; + + /* + * BEQZ16 rs, offset + * condition <- (GPR[rs] = 0) + * if condition then + * PC = PC + sign_ext (offset || 0) + * + * BNEZ16 rs, offset + * condition <- (GPR[rs] != 0) + * if condition then + * PC = PC + sign_ext (offset || 0) + * + * BEQZC rs, offset (compact instruction: No delay slot) + * condition <- (GPR[rs] == 0) + * if condition then + * PC = PC + 4 + sign_ext (offset || 0) + */ + + uint32_t rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int32_t offset = insn.getOperand(1).getImm(); + + int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + int32_t rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); + if (!success) + return false; + + if (!strcasecmp (op_name, "BEQZ16_MM")) + { + if (rs_val == 0) + target = pc + offset; + else + target = pc + current_inst_size + m_next_inst_size; // Skip delay slot instruction. + } + else if (!strcasecmp (op_name, "BNEZ16_MM")) + { + if (rs_val != 0) + target = pc + offset; + else + target = pc + current_inst_size + m_next_inst_size; // Skip delay slot instruction. + } + else if (!strcasecmp (op_name, "BEQZC_MM")) + { + if (rs_val == 0) + target = pc + 4 + offset; + else + target = pc + 4; // 32 bit instruction and does not have delay slot instruction. + } + else if (!strcasecmp (op_name, "BNEZC_MM")) + { + if (rs_val != 0) + target = pc + 4 + offset; + else + target = pc + 4; // 32 bit instruction and does not have delay slot instruction. + } + else if (!strcasecmp (op_name, "BGEZALS_MM")) + { + if (rs_val >= 0) + target = pc + offset; + else + target = pc + 6; // 32 bit instruction with short (2-byte) delay slot + + update_ra = true; + ra_offset = 6; + } + else if (!strcasecmp (op_name, "BLTZALS_MM")) + { + if (rs_val >= 0) + target = pc + offset; + else + target = pc + 6; // 32 bit instruction with short (2-byte) delay slot + + update_ra = true; + ra_offset = 6; + } + + Context context; + context.type = eContextRelativeBranchImmediate; + context.SetImmediate (current_inst_size + offset); + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + if (update_ra) + { + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + ra_offset)) + return false; + } + return true; +} + +/* Emulate micromips jump instructions. + JALR16,JALRS16 +*/ +bool +EmulateInstructionMIPS::Emulate_JALRx16_MM (llvm::MCInst& insn) +{ + bool success = false; + uint32_t ra_offset = 0; + const char *op_name = m_insn_info->getName (insn.getOpcode ()); + + uint32_t rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + + uint32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + uint32_t rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); + if (!success) + return false; + + if (!strcasecmp (op_name, "JALR16_MM")) + ra_offset = 6; // 2-byte instruction with 4-byte delay slot. + else if (!strcasecmp (op_name, "JALRS16_MM")) + ra_offset = 4; // 2-byte instruction with 2-byte delay slot. + + Context context; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) + return false; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + ra_offset)) + return false; + + return true; +} + +/* Emulate JALS and JALX instructions. + JALS 32 bit instruction with short (2-byte) delay slot. + JALX 32 bit instruction with 4-byte delay slot. +*/ +bool +EmulateInstructionMIPS::Emulate_JALx (llvm::MCInst& insn) +{ + bool success = false; + uint32_t offset=0, target=0, pc=0, ra_offset=0; + const char *op_name = m_insn_info->getName (insn.getOpcode ()); + + /* + * JALS target + * RA = PC + 6 + * offset = sign_ext (offset << 1) + * PC = PC[31-27] | offset + * JALX target + * RA = PC + 8 + * offset = sign_ext (offset << 2) + * PC = PC[31-28] | offset + */ + offset = insn.getOperand(0).getImm(); + + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + // These are PC-region branches and not PC-relative. + if (!strcasecmp (op_name, "JALS_MM")) + { + // target address is in the “current” 128 MB-aligned region + target = (pc & 0xF8000000UL) | offset; + ra_offset = 6; + } + else if (!strcasecmp (op_name, "JALX_MM")) + { + // target address is in the “current” 256 MB-aligned region + target = (pc & 0xF0000000UL) | offset; + ra_offset = 8; + } + + Context context; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + ra_offset)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_JALRS (llvm::MCInst& insn) +{ + bool success = false; + uint32_t rs=0, rt=0; + int32_t pc=0, rs_val=0; + + /* + JALRS rt, rs + GPR[rt] <- PC + 6 + PC <- GPR[rs] + */ + + rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + rs = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); + if (!success) + return false; + + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + Context context; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) + return false; + + // This is 4-byte instruction with 2-byte delay slot. + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + rt, pc + 6)) + return false; + + return true; +} + +bool EmulateInstructionMIPS::Emulate_BNE (llvm::MCInst& insn) { bool success = false; @@ -797,15 +1704,15 @@ EmulateInstructionMIPS::Emulate_BNE (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -817,7 +1724,7 @@ EmulateInstructionMIPS::Emulate_BNE (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -840,15 +1747,15 @@ EmulateInstructionMIPS::Emulate_BEQL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -860,7 +1767,7 @@ EmulateInstructionMIPS::Emulate_BEQL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -883,15 +1790,15 @@ EmulateInstructionMIPS::Emulate_BNEL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -903,7 +1810,7 @@ EmulateInstructionMIPS::Emulate_BNEL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -926,11 +1833,11 @@ EmulateInstructionMIPS::Emulate_BGEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -942,7 +1849,7 @@ EmulateInstructionMIPS::Emulate_BGEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -965,11 +1872,11 @@ EmulateInstructionMIPS::Emulate_BLTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -981,7 +1888,7 @@ EmulateInstructionMIPS::Emulate_BLTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1004,11 +1911,11 @@ EmulateInstructionMIPS::Emulate_BGTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1020,7 +1927,7 @@ EmulateInstructionMIPS::Emulate_BGTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1043,11 +1950,11 @@ EmulateInstructionMIPS::Emulate_BLEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1059,7 +1966,7 @@ EmulateInstructionMIPS::Emulate_BLEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1082,11 +1989,11 @@ EmulateInstructionMIPS::Emulate_BGTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1098,7 +2005,7 @@ EmulateInstructionMIPS::Emulate_BGTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1121,11 +2028,11 @@ EmulateInstructionMIPS::Emulate_BLEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1137,7 +2044,7 @@ EmulateInstructionMIPS::Emulate_BLEZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1160,11 +2067,11 @@ EmulateInstructionMIPS::Emulate_BLTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1176,7 +2083,7 @@ EmulateInstructionMIPS::Emulate_BLTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1199,11 +2106,11 @@ EmulateInstructionMIPS::Emulate_BGEZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1215,10 +2122,10 @@ EmulateInstructionMIPS::Emulate_BGEZALL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1238,7 +2145,7 @@ EmulateInstructionMIPS::Emulate_BAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -1246,10 +2153,10 @@ EmulateInstructionMIPS::Emulate_BAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1269,7 +2176,7 @@ EmulateInstructionMIPS::Emulate_BALC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -1277,10 +2184,10 @@ EmulateInstructionMIPS::Emulate_BALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1305,11 +2212,11 @@ EmulateInstructionMIPS::Emulate_BGEZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1320,10 +2227,10 @@ EmulateInstructionMIPS::Emulate_BGEZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1348,11 +2255,11 @@ EmulateInstructionMIPS::Emulate_BLTZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1363,10 +2270,10 @@ EmulateInstructionMIPS::Emulate_BLTZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1391,11 +2298,11 @@ EmulateInstructionMIPS::Emulate_BLTZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1406,10 +2313,10 @@ EmulateInstructionMIPS::Emulate_BLTZALL (llvm::MCInst& insn) else target = pc + 8; /* skip delay slot */ - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -1435,11 +2342,11 @@ EmulateInstructionMIPS::Emulate_BLEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1450,10 +2357,10 @@ EmulateInstructionMIPS::Emulate_BLEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1478,11 +2385,11 @@ EmulateInstructionMIPS::Emulate_BGEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1493,10 +2400,10 @@ EmulateInstructionMIPS::Emulate_BGEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1521,11 +2428,11 @@ EmulateInstructionMIPS::Emulate_BLTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1536,10 +2443,10 @@ EmulateInstructionMIPS::Emulate_BLTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1564,11 +2471,11 @@ EmulateInstructionMIPS::Emulate_BGTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1579,10 +2486,10 @@ EmulateInstructionMIPS::Emulate_BGTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1606,11 +2513,11 @@ EmulateInstructionMIPS::Emulate_BEQZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1621,10 +2528,10 @@ EmulateInstructionMIPS::Emulate_BEQZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1648,11 +2555,11 @@ EmulateInstructionMIPS::Emulate_BNEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1663,10 +2570,10 @@ EmulateInstructionMIPS::Emulate_BNEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -1689,11 +2596,11 @@ EmulateInstructionMIPS::Emulate_BGEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -1704,7 +2611,7 @@ EmulateInstructionMIPS::Emulate_BGEZ (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1723,7 +2630,7 @@ EmulateInstructionMIPS::Emulate_BC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -1731,7 +2638,7 @@ EmulateInstructionMIPS::Emulate_BC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1754,15 +2661,15 @@ EmulateInstructionMIPS::Emulate_BEQC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1774,7 +2681,7 @@ EmulateInstructionMIPS::Emulate_BEQC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1797,15 +2704,15 @@ EmulateInstructionMIPS::Emulate_BNEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1817,7 +2724,7 @@ EmulateInstructionMIPS::Emulate_BNEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1841,15 +2748,15 @@ EmulateInstructionMIPS::Emulate_BLTC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1861,7 +2768,7 @@ EmulateInstructionMIPS::Emulate_BLTC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1885,15 +2792,15 @@ EmulateInstructionMIPS::Emulate_BGEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1905,7 +2812,7 @@ EmulateInstructionMIPS::Emulate_BGEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1929,15 +2836,15 @@ EmulateInstructionMIPS::Emulate_BLTUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1949,7 +2856,7 @@ EmulateInstructionMIPS::Emulate_BLTUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -1973,15 +2880,15 @@ EmulateInstructionMIPS::Emulate_BGEUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -1993,7 +2900,7 @@ EmulateInstructionMIPS::Emulate_BGEUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2016,11 +2923,11 @@ EmulateInstructionMIPS::Emulate_BLTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2032,7 +2939,7 @@ EmulateInstructionMIPS::Emulate_BLTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2055,11 +2962,11 @@ EmulateInstructionMIPS::Emulate_BLEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2071,7 +2978,7 @@ EmulateInstructionMIPS::Emulate_BLEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2094,11 +3001,11 @@ EmulateInstructionMIPS::Emulate_BGEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2110,7 +3017,7 @@ EmulateInstructionMIPS::Emulate_BGEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2133,11 +3040,11 @@ EmulateInstructionMIPS::Emulate_BGTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2149,7 +3056,7 @@ EmulateInstructionMIPS::Emulate_BGTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2172,11 +3079,11 @@ EmulateInstructionMIPS::Emulate_BEQZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2188,7 +3095,7 @@ EmulateInstructionMIPS::Emulate_BEQZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2211,11 +3118,11 @@ EmulateInstructionMIPS::Emulate_BNEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; @@ -2227,7 +3134,7 @@ EmulateInstructionMIPS::Emulate_BNEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2258,15 +3165,15 @@ EmulateInstructionMIPS::Emulate_BOVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2278,7 +3185,7 @@ EmulateInstructionMIPS::Emulate_BOVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2302,15 +3209,15 @@ EmulateInstructionMIPS::Emulate_BNVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2322,7 +3229,7 @@ EmulateInstructionMIPS::Emulate_BNVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2341,7 +3248,7 @@ EmulateInstructionMIPS::Emulate_J (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -2350,7 +3257,7 @@ EmulateInstructionMIPS::Emulate_J (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, pc)) return false; return true; @@ -2369,7 +3276,7 @@ EmulateInstructionMIPS::Emulate_JAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; @@ -2378,10 +3285,10 @@ EmulateInstructionMIPS::Emulate_JAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 8)) return false; return true; @@ -2402,20 +3309,20 @@ EmulateInstructionMIPS::Emulate_JALR (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips + rt, pc + 8)) return false; return true; @@ -2437,11 +3344,11 @@ EmulateInstructionMIPS::Emulate_JIALC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2449,10 +3356,10 @@ EmulateInstructionMIPS::Emulate_JIALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips, pc + 4)) return false; return true; @@ -2473,7 +3380,7 @@ EmulateInstructionMIPS::Emulate_JIC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rt, 0, &success); + rt_val = (int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rt, 0, &success); if (!success) return false; @@ -2481,7 +3388,7 @@ EmulateInstructionMIPS::Emulate_JIC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2500,13 +3407,13 @@ EmulateInstructionMIPS::Emulate_JR (llvm::MCInst& insn) */ rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, rs_val)) return false; return true; @@ -2529,11 +3436,11 @@ EmulateInstructionMIPS::Emulate_BC1F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2547,7 +3454,7 @@ EmulateInstructionMIPS::Emulate_BC1F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2570,11 +3477,11 @@ EmulateInstructionMIPS::Emulate_BC1T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2588,7 +3495,7 @@ EmulateInstructionMIPS::Emulate_BC1T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2611,11 +3518,11 @@ EmulateInstructionMIPS::Emulate_BC1FL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2629,7 +3536,7 @@ EmulateInstructionMIPS::Emulate_BC1FL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2652,11 +3559,11 @@ EmulateInstructionMIPS::Emulate_BC1TL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2670,7 +3577,7 @@ EmulateInstructionMIPS::Emulate_BC1TL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2694,11 +3601,11 @@ EmulateInstructionMIPS::Emulate_BC1EQZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + ft, 0, &success); if (!success) return false; @@ -2709,7 +3616,7 @@ EmulateInstructionMIPS::Emulate_BC1EQZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2733,11 +3640,11 @@ EmulateInstructionMIPS::Emulate_BC1NEZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + ft, 0, &success); if (!success) return false; @@ -2748,7 +3655,7 @@ EmulateInstructionMIPS::Emulate_BC1NEZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2772,11 +3679,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY2F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2791,7 +3698,7 @@ EmulateInstructionMIPS::Emulate_BC1ANY2F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2815,11 +3722,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY2T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2834,7 +3741,7 @@ EmulateInstructionMIPS::Emulate_BC1ANY2T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2860,11 +3767,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY4F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2879,7 +3786,7 @@ EmulateInstructionMIPS::Emulate_BC1ANY4F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; @@ -2905,11 +3812,11 @@ EmulateInstructionMIPS::Emulate_BC1ANY4T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); if (!success) return false; @@ -2924,8 +3831,234 @@ EmulateInstructionMIPS::Emulate_BC1ANY4T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_BNZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, true); +} + +bool +EmulateInstructionMIPS::Emulate_BNZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, true); +} + +bool +EmulateInstructionMIPS::Emulate_BNZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, true); +} + +bool +EmulateInstructionMIPS::Emulate_BNZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, true); +} + +bool +EmulateInstructionMIPS::Emulate_BZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, false); +} + +bool +EmulateInstructionMIPS::Emulate_BZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, false); +} + +bool +EmulateInstructionMIPS::Emulate_BZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, false); +} + +bool +EmulateInstructionMIPS::Emulate_BZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, false); +} + +bool +EmulateInstructionMIPS::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz) +{ + bool success = false, branch_hit = true; + int32_t target = 0; + RegisterValue reg_value; + uint8_t * ptr = NULL; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int32_t offset = insn.getOperand(1).getImm(); + + int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips + wt, reg_value)) + ptr = (uint8_t *)reg_value.GetBytes(); + else + return false; + + for(int i = 0; i < 16 / element_byte_size; i++) + { + switch(element_byte_size) + { + case 1: + if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) ) + branch_hit = false; + break; + case 2: + if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 4: + if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 8: + if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + } + if(!branch_hit) + break; + ptr = ptr + element_byte_size; + } + + if(branch_hit) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) return false; return true; } + +bool +EmulateInstructionMIPS::Emulate_BNZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, true); +} + +bool +EmulateInstructionMIPS::Emulate_BZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, false); +} + +bool +EmulateInstructionMIPS::Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz) +{ + bool success = false; + int32_t target = 0; + llvm::APInt wr_val = llvm::APInt::getNullValue(128); + llvm::APInt fail_value = llvm::APInt::getMaxValue(128); + llvm::APInt zero_value = llvm::APInt::getNullValue(128); + RegisterValue reg_value; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int32_t offset = insn.getOperand(1).getImm(); + + int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips + wt, reg_value)) + wr_val = reg_value.GetAsUInt128(fail_value); + else + return false; + + if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz)) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_LDST_Imm (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + int32_t imm, address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + imm = insn.getOperand(num_operands-1).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address =(int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} + +bool +EmulateInstructionMIPS::Emulate_LDST_Reg (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base, index; + int32_t address, index_address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + index = m_reg_info->getEncodingValue (insn.getOperand(num_operands-1).getReg()); + + RegisterInfo reg_info_base, reg_info_index; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + index, reg_info_index)) + return false; + + /* read base register */ + address =(int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* read index register */ + index_address =(int32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + index, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + index_address; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} diff --git a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h index 25d8fc8891d5..e1340f983278 100644 --- a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h +++ b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h @@ -60,53 +60,52 @@ public: return false; } - virtual lldb_private::ConstString - GetPluginName(); + lldb_private::ConstString + GetPluginName() override; - virtual lldb_private::ConstString - GetShortPluginName() - { - return GetPluginNameStatic(); - } - - virtual uint32_t - GetPluginVersion() + uint32_t + GetPluginVersion() override { return 1; } bool - SetTargetTriple (const lldb_private::ArchSpec &arch); + SetTargetTriple (const lldb_private::ArchSpec &arch) override; EmulateInstructionMIPS (const lldb_private::ArchSpec &arch); - virtual bool - SupportsEmulatingInstructionsOfType (lldb_private::InstructionType inst_type) + bool + SupportsEmulatingInstructionsOfType (lldb_private::InstructionType inst_type) override { return SupportsEmulatingInstructionsOfTypeStatic (inst_type); } - virtual bool - ReadInstruction (); - - virtual bool - EvaluateInstruction (uint32_t evaluate_options); + bool + ReadInstruction () override; - virtual bool + bool + EvaluateInstruction (uint32_t evaluate_options) override; + + bool + SetInstruction (const lldb_private::Opcode &insn_opcode, + const lldb_private::Address &inst_addr, + lldb_private::Target *target) override; + + bool TestEmulation (lldb_private::Stream *out_stream, lldb_private::ArchSpec &arch, - lldb_private::OptionValueDictionary *test_data) + lldb_private::OptionValueDictionary *test_data) override { return false; } - virtual bool + bool GetRegisterInfo (lldb::RegisterKind reg_kind, uint32_t reg_num, - lldb_private::RegisterInfo ®_info); + lldb_private::RegisterInfo ®_info) override; - virtual bool - CreateFunctionEntryUnwind (lldb_private::UnwindPlan &unwind_plan); + bool + CreateFunctionEntryUnwind (lldb_private::UnwindPlan &unwind_plan) override; protected: @@ -121,6 +120,9 @@ protected: static MipsOpcode* GetOpcodeForInstruction (const char *op_name); + uint32_t + GetSizeOfInstruction (lldb_private::DataExtractor& data, uint64_t inst_addr); + bool Emulate_ADDiu (llvm::MCInst& insn); @@ -131,6 +133,33 @@ protected: Emulate_LW (llvm::MCInst& insn); bool + Emulate_ADDIUSP (llvm::MCInst& insn); + + bool + Emulate_ADDIUS5 (llvm::MCInst& insn); + + bool + Emulate_SWSP (llvm::MCInst& insn); + + bool + Emulate_SWM16_32 (llvm::MCInst& insn); + + bool + Emulate_LWSP (llvm::MCInst& insn); + + bool + Emulate_LWM16_32 (llvm::MCInst& insn); + + bool + Emulate_JRADDIUSP (llvm::MCInst& insn); + + bool + Emulate_LDST_Imm (llvm::MCInst& insn); + + bool + Emulate_LDST_Reg (llvm::MCInst& insn); + + bool Emulate_BEQ (llvm::MCInst& insn); bool @@ -296,6 +325,57 @@ protected: Emulate_BC1ANY4T (llvm::MCInst& insn); bool + Emulate_BNZB (llvm::MCInst& insn); + + bool + Emulate_BNZH (llvm::MCInst& insn); + + bool + Emulate_BNZW (llvm::MCInst& insn); + + bool + Emulate_BNZD (llvm::MCInst& insn); + + bool + Emulate_BZB (llvm::MCInst& insn); + + bool + Emulate_BZH (llvm::MCInst& insn); + + bool + Emulate_BZW (llvm::MCInst& insn); + + bool + Emulate_BZD (llvm::MCInst& insn); + + bool + Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz); + + bool + Emulate_BNZV (llvm::MCInst& insn); + + bool + Emulate_BZV (llvm::MCInst& insn); + + bool + Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz); + + bool + Emulate_B16_MM (llvm::MCInst& insn); + + bool + Emulate_Branch_MM (llvm::MCInst& insn); + + bool + Emulate_JALRx16_MM (llvm::MCInst& insn); + + bool + Emulate_JALx (llvm::MCInst& insn); + + bool + Emulate_JALRS (llvm::MCInst& insn); + + bool nonvolatile_reg_p (uint32_t regnum); const char * @@ -303,11 +383,15 @@ protected: private: std::unique_ptr<llvm::MCDisassembler> m_disasm; + std::unique_ptr<llvm::MCDisassembler> m_alt_disasm; std::unique_ptr<llvm::MCSubtargetInfo> m_subtype_info; + std::unique_ptr<llvm::MCSubtargetInfo> m_alt_subtype_info; std::unique_ptr<llvm::MCRegisterInfo> m_reg_info; std::unique_ptr<llvm::MCAsmInfo> m_asm_info; std::unique_ptr<llvm::MCContext> m_context; std::unique_ptr<llvm::MCInstrInfo> m_insn_info; + uint32_t m_next_inst_size; + bool m_use_alt_disaasm; }; #endif // EmulateInstructionMIPS_h_ diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp index a574e7d348e1..28eba093f317 100644 --- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -221,41 +221,76 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name { switch (reg_num) { - case gcc_dwarf_sp_mips64: return "r29"; - case gcc_dwarf_r30_mips64: return "r30"; - case gcc_dwarf_ra_mips64: return "r31"; - case gcc_dwarf_f0_mips64: return "f0"; - case gcc_dwarf_f1_mips64: return "f1"; - case gcc_dwarf_f2_mips64: return "f2"; - case gcc_dwarf_f3_mips64: return "f3"; - case gcc_dwarf_f4_mips64: return "f4"; - case gcc_dwarf_f5_mips64: return "f5"; - case gcc_dwarf_f6_mips64: return "f6"; - case gcc_dwarf_f7_mips64: return "f7"; - case gcc_dwarf_f8_mips64: return "f8"; - case gcc_dwarf_f9_mips64: return "f9"; - case gcc_dwarf_f10_mips64: return "f10"; - case gcc_dwarf_f11_mips64: return "f11"; - case gcc_dwarf_f12_mips64: return "f12"; - case gcc_dwarf_f13_mips64: return "f13"; - case gcc_dwarf_f14_mips64: return "f14"; - case gcc_dwarf_f15_mips64: return "f15"; - case gcc_dwarf_f16_mips64: return "f16"; - case gcc_dwarf_f17_mips64: return "f17"; - case gcc_dwarf_f18_mips64: return "f18"; - case gcc_dwarf_f19_mips64: return "f19"; - case gcc_dwarf_f20_mips64: return "f20"; - case gcc_dwarf_f21_mips64: return "f21"; - case gcc_dwarf_f22_mips64: return "f22"; - case gcc_dwarf_f23_mips64: return "f23"; - case gcc_dwarf_f24_mips64: return "f24"; - case gcc_dwarf_f25_mips64: return "f25"; - case gcc_dwarf_f26_mips64: return "f26"; - case gcc_dwarf_f27_mips64: return "f27"; - case gcc_dwarf_f28_mips64: return "f28"; - case gcc_dwarf_f29_mips64: return "f29"; - case gcc_dwarf_f30_mips64: return "f30"; - case gcc_dwarf_f31_mips64: return "f31"; + case dwarf_sp_mips64: return "r29"; + case dwarf_r30_mips64: return "r30"; + case dwarf_ra_mips64: return "r31"; + case dwarf_f0_mips64: return "f0"; + case dwarf_f1_mips64: return "f1"; + case dwarf_f2_mips64: return "f2"; + case dwarf_f3_mips64: return "f3"; + case dwarf_f4_mips64: return "f4"; + case dwarf_f5_mips64: return "f5"; + case dwarf_f6_mips64: return "f6"; + case dwarf_f7_mips64: return "f7"; + case dwarf_f8_mips64: return "f8"; + case dwarf_f9_mips64: return "f9"; + case dwarf_f10_mips64: return "f10"; + case dwarf_f11_mips64: return "f11"; + case dwarf_f12_mips64: return "f12"; + case dwarf_f13_mips64: return "f13"; + case dwarf_f14_mips64: return "f14"; + case dwarf_f15_mips64: return "f15"; + case dwarf_f16_mips64: return "f16"; + case dwarf_f17_mips64: return "f17"; + case dwarf_f18_mips64: return "f18"; + case dwarf_f19_mips64: return "f19"; + case dwarf_f20_mips64: return "f20"; + case dwarf_f21_mips64: return "f21"; + case dwarf_f22_mips64: return "f22"; + case dwarf_f23_mips64: return "f23"; + case dwarf_f24_mips64: return "f24"; + case dwarf_f25_mips64: return "f25"; + case dwarf_f26_mips64: return "f26"; + case dwarf_f27_mips64: return "f27"; + case dwarf_f28_mips64: return "f28"; + case dwarf_f29_mips64: return "f29"; + case dwarf_f30_mips64: return "f30"; + case dwarf_f31_mips64: return "f31"; + case dwarf_w0_mips64: return "w0"; + case dwarf_w1_mips64: return "w1"; + case dwarf_w2_mips64: return "w2"; + case dwarf_w3_mips64: return "w3"; + case dwarf_w4_mips64: return "w4"; + case dwarf_w5_mips64: return "w5"; + case dwarf_w6_mips64: return "w6"; + case dwarf_w7_mips64: return "w7"; + case dwarf_w8_mips64: return "w8"; + case dwarf_w9_mips64: return "w9"; + case dwarf_w10_mips64: return "w10"; + case dwarf_w11_mips64: return "w11"; + case dwarf_w12_mips64: return "w12"; + case dwarf_w13_mips64: return "w13"; + case dwarf_w14_mips64: return "w14"; + case dwarf_w15_mips64: return "w15"; + case dwarf_w16_mips64: return "w16"; + case dwarf_w17_mips64: return "w17"; + case dwarf_w18_mips64: return "w18"; + case dwarf_w19_mips64: return "w19"; + case dwarf_w20_mips64: return "w20"; + case dwarf_w21_mips64: return "w21"; + case dwarf_w22_mips64: return "w22"; + case dwarf_w23_mips64: return "w23"; + case dwarf_w24_mips64: return "w24"; + case dwarf_w25_mips64: return "w25"; + case dwarf_w26_mips64: return "w26"; + case dwarf_w27_mips64: return "w27"; + case dwarf_w28_mips64: return "w28"; + case dwarf_w29_mips64: return "w29"; + case dwarf_w30_mips64: return "w30"; + case dwarf_w31_mips64: return "w31"; + case dwarf_mir_mips64: return "mir"; + case dwarf_mcsr_mips64: return "mcsr"; + case dwarf_config5_mips64: return "config5"; default: break; } @@ -264,78 +299,113 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name switch (reg_num) { - case gcc_dwarf_zero_mips64: return "r0"; - case gcc_dwarf_r1_mips64: return "r1"; - case gcc_dwarf_r2_mips64: return "r2"; - case gcc_dwarf_r3_mips64: return "r3"; - case gcc_dwarf_r4_mips64: return "r4"; - case gcc_dwarf_r5_mips64: return "r5"; - case gcc_dwarf_r6_mips64: return "r6"; - case gcc_dwarf_r7_mips64: return "r7"; - case gcc_dwarf_r8_mips64: return "r8"; - case gcc_dwarf_r9_mips64: return "r9"; - case gcc_dwarf_r10_mips64: return "r10"; - case gcc_dwarf_r11_mips64: return "r11"; - case gcc_dwarf_r12_mips64: return "r12"; - case gcc_dwarf_r13_mips64: return "r13"; - case gcc_dwarf_r14_mips64: return "r14"; - case gcc_dwarf_r15_mips64: return "r15"; - case gcc_dwarf_r16_mips64: return "r16"; - case gcc_dwarf_r17_mips64: return "r17"; - case gcc_dwarf_r18_mips64: return "r18"; - case gcc_dwarf_r19_mips64: return "r19"; - case gcc_dwarf_r20_mips64: return "r20"; - case gcc_dwarf_r21_mips64: return "r21"; - case gcc_dwarf_r22_mips64: return "r22"; - case gcc_dwarf_r23_mips64: return "r23"; - case gcc_dwarf_r24_mips64: return "r24"; - case gcc_dwarf_r25_mips64: return "r25"; - case gcc_dwarf_r26_mips64: return "r26"; - case gcc_dwarf_r27_mips64: return "r27"; - case gcc_dwarf_gp_mips64: return "gp"; - case gcc_dwarf_sp_mips64: return "sp"; - case gcc_dwarf_r30_mips64: return "fp"; - case gcc_dwarf_ra_mips64: return "ra"; - case gcc_dwarf_sr_mips64: return "sr"; - case gcc_dwarf_lo_mips64: return "lo"; - case gcc_dwarf_hi_mips64: return "hi"; - case gcc_dwarf_bad_mips64: return "bad"; - case gcc_dwarf_cause_mips64: return "cause"; - case gcc_dwarf_pc_mips64: return "pc"; - case gcc_dwarf_f0_mips64: return "f0"; - case gcc_dwarf_f1_mips64: return "f1"; - case gcc_dwarf_f2_mips64: return "f2"; - case gcc_dwarf_f3_mips64: return "f3"; - case gcc_dwarf_f4_mips64: return "f4"; - case gcc_dwarf_f5_mips64: return "f5"; - case gcc_dwarf_f6_mips64: return "f6"; - case gcc_dwarf_f7_mips64: return "f7"; - case gcc_dwarf_f8_mips64: return "f8"; - case gcc_dwarf_f9_mips64: return "f9"; - case gcc_dwarf_f10_mips64: return "f10"; - case gcc_dwarf_f11_mips64: return "f11"; - case gcc_dwarf_f12_mips64: return "f12"; - case gcc_dwarf_f13_mips64: return "f13"; - case gcc_dwarf_f14_mips64: return "f14"; - case gcc_dwarf_f15_mips64: return "f15"; - case gcc_dwarf_f16_mips64: return "f16"; - case gcc_dwarf_f17_mips64: return "f17"; - case gcc_dwarf_f18_mips64: return "f18"; - case gcc_dwarf_f19_mips64: return "f19"; - case gcc_dwarf_f20_mips64: return "f20"; - case gcc_dwarf_f21_mips64: return "f21"; - case gcc_dwarf_f22_mips64: return "f22"; - case gcc_dwarf_f23_mips64: return "f23"; - case gcc_dwarf_f24_mips64: return "f24"; - case gcc_dwarf_f25_mips64: return "f25"; - case gcc_dwarf_f26_mips64: return "f26"; - case gcc_dwarf_f27_mips64: return "f27"; - case gcc_dwarf_f28_mips64: return "f28"; - case gcc_dwarf_f29_mips64: return "f29"; - case gcc_dwarf_f30_mips64: return "f30"; - case gcc_dwarf_f31_mips64: return "f31"; - case gcc_dwarf_fcsr_mips64: return "fcsr"; - case gcc_dwarf_fir_mips64: return "fir"; + case dwarf_zero_mips64: return "r0"; + case dwarf_r1_mips64: return "r1"; + case dwarf_r2_mips64: return "r2"; + case dwarf_r3_mips64: return "r3"; + case dwarf_r4_mips64: return "r4"; + case dwarf_r5_mips64: return "r5"; + case dwarf_r6_mips64: return "r6"; + case dwarf_r7_mips64: return "r7"; + case dwarf_r8_mips64: return "r8"; + case dwarf_r9_mips64: return "r9"; + case dwarf_r10_mips64: return "r10"; + case dwarf_r11_mips64: return "r11"; + case dwarf_r12_mips64: return "r12"; + case dwarf_r13_mips64: return "r13"; + case dwarf_r14_mips64: return "r14"; + case dwarf_r15_mips64: return "r15"; + case dwarf_r16_mips64: return "r16"; + case dwarf_r17_mips64: return "r17"; + case dwarf_r18_mips64: return "r18"; + case dwarf_r19_mips64: return "r19"; + case dwarf_r20_mips64: return "r20"; + case dwarf_r21_mips64: return "r21"; + case dwarf_r22_mips64: return "r22"; + case dwarf_r23_mips64: return "r23"; + case dwarf_r24_mips64: return "r24"; + case dwarf_r25_mips64: return "r25"; + case dwarf_r26_mips64: return "r26"; + case dwarf_r27_mips64: return "r27"; + case dwarf_gp_mips64: return "gp"; + case dwarf_sp_mips64: return "sp"; + case dwarf_r30_mips64: return "fp"; + case dwarf_ra_mips64: return "ra"; + case dwarf_sr_mips64: return "sr"; + case dwarf_lo_mips64: return "lo"; + case dwarf_hi_mips64: return "hi"; + case dwarf_bad_mips64: return "bad"; + case dwarf_cause_mips64: return "cause"; + case dwarf_pc_mips64: return "pc"; + case dwarf_f0_mips64: return "f0"; + case dwarf_f1_mips64: return "f1"; + case dwarf_f2_mips64: return "f2"; + case dwarf_f3_mips64: return "f3"; + case dwarf_f4_mips64: return "f4"; + case dwarf_f5_mips64: return "f5"; + case dwarf_f6_mips64: return "f6"; + case dwarf_f7_mips64: return "f7"; + case dwarf_f8_mips64: return "f8"; + case dwarf_f9_mips64: return "f9"; + case dwarf_f10_mips64: return "f10"; + case dwarf_f11_mips64: return "f11"; + case dwarf_f12_mips64: return "f12"; + case dwarf_f13_mips64: return "f13"; + case dwarf_f14_mips64: return "f14"; + case dwarf_f15_mips64: return "f15"; + case dwarf_f16_mips64: return "f16"; + case dwarf_f17_mips64: return "f17"; + case dwarf_f18_mips64: return "f18"; + case dwarf_f19_mips64: return "f19"; + case dwarf_f20_mips64: return "f20"; + case dwarf_f21_mips64: return "f21"; + case dwarf_f22_mips64: return "f22"; + case dwarf_f23_mips64: return "f23"; + case dwarf_f24_mips64: return "f24"; + case dwarf_f25_mips64: return "f25"; + case dwarf_f26_mips64: return "f26"; + case dwarf_f27_mips64: return "f27"; + case dwarf_f28_mips64: return "f28"; + case dwarf_f29_mips64: return "f29"; + case dwarf_f30_mips64: return "f30"; + case dwarf_f31_mips64: return "f31"; + case dwarf_fcsr_mips64: return "fcsr"; + case dwarf_fir_mips64: return "fir"; + case dwarf_w0_mips64: return "w0"; + case dwarf_w1_mips64: return "w1"; + case dwarf_w2_mips64: return "w2"; + case dwarf_w3_mips64: return "w3"; + case dwarf_w4_mips64: return "w4"; + case dwarf_w5_mips64: return "w5"; + case dwarf_w6_mips64: return "w6"; + case dwarf_w7_mips64: return "w7"; + case dwarf_w8_mips64: return "w8"; + case dwarf_w9_mips64: return "w9"; + case dwarf_w10_mips64: return "w10"; + case dwarf_w11_mips64: return "w11"; + case dwarf_w12_mips64: return "w12"; + case dwarf_w13_mips64: return "w13"; + case dwarf_w14_mips64: return "w14"; + case dwarf_w15_mips64: return "w15"; + case dwarf_w16_mips64: return "w16"; + case dwarf_w17_mips64: return "w17"; + case dwarf_w18_mips64: return "w18"; + case dwarf_w19_mips64: return "w19"; + case dwarf_w20_mips64: return "w20"; + case dwarf_w21_mips64: return "w21"; + case dwarf_w22_mips64: return "w22"; + case dwarf_w23_mips64: return "w23"; + case dwarf_w24_mips64: return "w24"; + case dwarf_w25_mips64: return "w25"; + case dwarf_w26_mips64: return "w26"; + case dwarf_w27_mips64: return "w27"; + case dwarf_w28_mips64: return "w28"; + case dwarf_w29_mips64: return "w29"; + case dwarf_w30_mips64: return "w30"; + case dwarf_w31_mips64: return "w31"; + case dwarf_mcsr_mips64: return "mcsr"; + case dwarf_mir_mips64: return "mir"; + case dwarf_config5_mips64: return "config5"; } return nullptr; } @@ -347,11 +417,11 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n { switch (reg_num) { - case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_pc_mips64; break; - case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sp_mips64; break; - case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_r30_mips64; break; - case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_ra_mips64; break; - case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sr_mips64; break; + case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc_mips64; break; + case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp_mips64; break; + case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_r30_mips64; break; + case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = dwarf_ra_mips64; break; + case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sr_mips64; break; default: return false; } @@ -362,18 +432,24 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n ::memset (®_info, 0, sizeof(RegisterInfo)); ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds)); - if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64) + if (reg_num == dwarf_sr_mips64 || reg_num == dwarf_fcsr_mips64 || reg_num == dwarf_fir_mips64 || reg_num == dwarf_mcsr_mips64 || reg_num == dwarf_mir_mips64 || reg_num == dwarf_config5_mips64) { reg_info.byte_size = 4; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } - else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_f31_mips64) + else if ((int)reg_num >= dwarf_zero_mips64 && (int)reg_num <= dwarf_f31_mips64) { reg_info.byte_size = 8; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } + else if ((int)reg_num >= dwarf_w0_mips64 && (int)reg_num <= dwarf_w31_mips64) + { + reg_info.byte_size = 16; + reg_info.format = eFormatVectorOfUInt8; + reg_info.encoding = eEncodingVector; + } else { return false; @@ -385,11 +461,11 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n switch (reg_num) { - case gcc_dwarf_r30_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; - case gcc_dwarf_ra_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; - case gcc_dwarf_sp_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; - case gcc_dwarf_pc_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; - case gcc_dwarf_sr_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; + case dwarf_r30_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; + case dwarf_ra_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; + case dwarf_sp_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; + case dwarf_pc_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; + case dwarf_sr_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; default: break; } return true; @@ -410,8 +486,65 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name) { "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" }, { "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" }, - { "SW", &EmulateInstructionMIPS64::Emulate_SW, "SW rt,offset(rs)" }, - { "LW", &EmulateInstructionMIPS64::Emulate_LW, "LW rt,offset(rs)" }, + + + + //---------------------------------------------------------------------- + // Load/Store instructions + //---------------------------------------------------------------------- + /* Following list of emulated instructions are required by implementation of hardware watchpoint + for MIPS in lldb. As we just need the address accessed by instructions, we have generalised + all these instructions in 2 functions depending on their addressing modes */ + + { "LB", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LB rt, offset(base)" }, + { "LBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBE rt, offset(base)" }, + { "LBU", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBU rt, offset(base)" }, + { "LBUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBUE rt, offset(base)" }, + { "LDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDC1 ft, offset(base)" }, + { "LDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDL rt, offset(base)" }, + { "LDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDR rt, offset(base)" }, + { "LLD", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LLD rt, offset(base)" }, + { "LDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDC2 rt, offset(base)" }, + { "LDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LDXC1 fd, index (base)" }, + { "LH", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LH rt, offset(base)" }, + { "LHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHE rt, offset(base)" }, + { "LHU", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHU rt, offset(base)" }, + { "LHUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHUE rt, offset(base)" }, + { "LL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LL rt, offset(base)" }, + { "LLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LLE rt, offset(base)" }, + { "LUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LUXC1 fd, index (base)" }, + { "LW", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LW rt, offset(rs)" }, + { "LWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWC1 ft, offset(base)" }, + { "LWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWC2 rt, offset(base)" }, + { "LWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWE rt, offset(base)" }, + { "LWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWL rt, offset(base)" }, + { "LWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWLE rt, offset(base)" }, + { "LWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWR rt, offset(base)" }, + { "LWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWRE rt, offset(base)" }, + { "LWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LWXC1 fd, index (base)" }, + + { "SB", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SB rt, offset(base)" }, + { "SBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SBE rt, offset(base)" }, + { "SC", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SC rt, offset(base)" }, + { "SCE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SCE rt, offset(base)" }, + { "SCD", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SCD rt, offset(base)" }, + { "SDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDL rt, offset(base)" }, + { "SDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDR rt, offset(base)" }, + { "SDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDC1 ft, offset(base)" }, + { "SDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDC2 rt, offset(base)" }, + { "SDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SDXC1 fs, index (base)" }, + { "SH", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SH rt, offset(base)" }, + { "SHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SHE rt, offset(base)" }, + { "SUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SUXC1 fs, index (base)" }, + { "SW", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SW rt, offset(rs)" }, + { "SWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWC1 ft, offset(base)" }, + { "SWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWC2 rt, offset(base)" }, + { "SWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWE rt, offset(base)" }, + { "SWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWL rt, offset(base)" }, + { "SWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWLE rt, offset(base)" }, + { "SWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWR rt, offset(base)" }, + { "SWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWRE rt, offset(base)" }, + { "SWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SWXC1 fs, index (base)" }, //---------------------------------------------------------------------- // Branch instructions @@ -474,6 +607,16 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name) { "BC1ANY2T", &EmulateInstructionMIPS64::Emulate_BC1ANY2T, "BC1ANY2T cc, offset" }, { "BC1ANY4F", &EmulateInstructionMIPS64::Emulate_BC1ANY4F, "BC1ANY4F cc, offset" }, { "BC1ANY4T", &EmulateInstructionMIPS64::Emulate_BC1ANY4T, "BC1ANY4T cc, offset" }, + { "BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16" }, + { "BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16" }, + { "BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16" }, + { "BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16" }, + { "BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16" }, + { "BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16" }, + { "BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16" }, + { "BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16" }, + { "BNZ_V", &EmulateInstructionMIPS64::Emulate_BNZV, "BNZ.V wt,s16" }, + { "BZ_V", &EmulateInstructionMIPS64::Emulate_BZV, "BZ.V wt,s16" }, }; static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes); @@ -545,7 +688,7 @@ EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; } @@ -557,7 +700,7 @@ EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -566,7 +709,7 @@ EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options) { new_pc += 4; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, new_pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, new_pc)) return false; } } @@ -584,10 +727,10 @@ EmulateInstructionMIPS64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) const bool can_replace = false; // Our previous Call Frame Address is the stack pointer - row->GetCFAValue().SetIsRegisterPlusOffset(gcc_dwarf_sp_mips64, 0); + row->GetCFAValue().SetIsRegisterPlusOffset(dwarf_sp_mips64, 0); // Our previous PC is in the RA - row->SetRegisterLocationToRegister(gcc_dwarf_pc_mips64, gcc_dwarf_ra_mips64, can_replace); + row->SetRegisterLocationToRegister(dwarf_pc_mips64, dwarf_ra_mips64, can_replace); unwind_plan.AppendRow (row); @@ -595,6 +738,7 @@ EmulateInstructionMIPS64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) unwind_plan.SetSourceName ("EmulateInstructionMIPS64"); unwind_plan.SetSourcedFromCompiler (eLazyBoolNo); unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes); + unwind_plan.SetReturnAddressRegister (dwarf_ra_mips64); return true; } @@ -604,18 +748,18 @@ EmulateInstructionMIPS64::nonvolatile_reg_p (uint64_t regnum) { switch (regnum) { - case gcc_dwarf_r16_mips64: - case gcc_dwarf_r17_mips64: - case gcc_dwarf_r18_mips64: - case gcc_dwarf_r19_mips64: - case gcc_dwarf_r20_mips64: - case gcc_dwarf_r21_mips64: - case gcc_dwarf_r22_mips64: - case gcc_dwarf_r23_mips64: - case gcc_dwarf_gp_mips64: - case gcc_dwarf_sp_mips64: - case gcc_dwarf_r30_mips64: - case gcc_dwarf_ra_mips64: + case dwarf_r16_mips64: + case dwarf_r17_mips64: + case dwarf_r18_mips64: + case dwarf_r19_mips64: + case dwarf_r20_mips64: + case dwarf_r21_mips64: + case dwarf_r22_mips64: + case dwarf_r23_mips64: + case dwarf_gp_mips64: + case dwarf_sp_mips64: + case dwarf_r30_mips64: + case dwarf_ra_mips64: return true; default: return false; @@ -636,10 +780,10 @@ EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn) src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); /* Check if this is daddiu sp,<src>,imm16 */ - if (dst == gcc_dwarf_sp_mips64) + if (dst == dwarf_sp_mips64) { /* read <src> register */ - uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, 0, &success); + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success); if (!success) return false; @@ -647,79 +791,19 @@ EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn) Context context; RegisterInfo reg_info_sp; - if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips64, reg_info_sp)) + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp)) context.SetRegisterPlusOffset (reg_info_sp, imm); /* We are allocating bytes on stack */ context.type = eContextAdjustStackPointer; - WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips64, result); + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips64, result); } return true; } bool -EmulateInstructionMIPS64::Emulate_SW (llvm::MCInst& insn) -{ - bool success = false; - uint32_t base; - int64_t imm, address; - Context bad_vaddr_context; - - base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - imm = insn.getOperand(2).getImm(); - - RegisterInfo reg_info_base; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)) - return false; - - /* read base register */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); - if (!success) - return false; - - /* destination address */ - address = address + imm; - - /* Set the bad_vaddr register with base address used in the instruction */ - bad_vaddr_context.type = eContextInvalid; - WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); - - return true; -} - -bool -EmulateInstructionMIPS64::Emulate_LW (llvm::MCInst& insn) -{ - bool success = false; - uint32_t base; - int64_t imm, address; - Context bad_vaddr_context; - - base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - imm = insn.getOperand(2).getImm(); - - RegisterInfo reg_info_base; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)) - return false; - - /* read base register */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); - if (!success) - return false; - - /* destination address */ - address = address + imm; - - /* Set the bad_vaddr register with base address used in the instruction */ - bad_vaddr_context.type = eContextInvalid; - WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); - - return true; -} - -bool EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) { uint64_t address; @@ -734,12 +818,12 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base) - || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + base, reg_info_base) + || !GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + src, reg_info_src)) return false; /* read SP */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + base, 0, &success); if (!success) return false; @@ -747,7 +831,7 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) address = address + imm; /* We look for sp based non-volatile register stores */ - if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src)) + if (base == dwarf_sp_mips64 && nonvolatile_reg_p (src)) { Context context; RegisterValue data_src; @@ -769,7 +853,7 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) /* Set the bad_vaddr register with base address used in the instruction */ bad_vaddr_context.type = eContextInvalid; - WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64, address); return true; } @@ -777,17 +861,38 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) bool EmulateInstructionMIPS64::Emulate_LD (llvm::MCInst& insn) { + bool success =false; uint32_t src, base; + int64_t imm, address; + Context bad_vaddr_context; src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + imm = insn.getOperand(2).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + base, reg_info_base)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + base, 0, &success); + if (!success) + return false; - if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src)) + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64, address); + + + if (base == dwarf_sp_mips64 && nonvolatile_reg_p (src)) { RegisterValue data_src; RegisterInfo reg_info_src; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + src, reg_info_src)) return false; Context context; @@ -821,15 +926,15 @@ EmulateInstructionMIPS64::Emulate_BEQ (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -841,7 +946,7 @@ EmulateInstructionMIPS64::Emulate_BEQ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -864,15 +969,15 @@ EmulateInstructionMIPS64::Emulate_BNE (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -884,7 +989,7 @@ EmulateInstructionMIPS64::Emulate_BNE (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -907,15 +1012,15 @@ EmulateInstructionMIPS64::Emulate_BEQL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -927,7 +1032,7 @@ EmulateInstructionMIPS64::Emulate_BEQL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -950,15 +1055,15 @@ EmulateInstructionMIPS64::Emulate_BNEL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -970,7 +1075,7 @@ EmulateInstructionMIPS64::Emulate_BNEL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -993,11 +1098,11 @@ EmulateInstructionMIPS64::Emulate_BGEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1009,7 +1114,7 @@ EmulateInstructionMIPS64::Emulate_BGEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1032,11 +1137,11 @@ EmulateInstructionMIPS64::Emulate_BLTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1048,7 +1153,7 @@ EmulateInstructionMIPS64::Emulate_BLTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1071,11 +1176,11 @@ EmulateInstructionMIPS64::Emulate_BGTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1087,7 +1192,7 @@ EmulateInstructionMIPS64::Emulate_BGTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1110,11 +1215,11 @@ EmulateInstructionMIPS64::Emulate_BLEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1126,7 +1231,7 @@ EmulateInstructionMIPS64::Emulate_BLEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1149,11 +1254,11 @@ EmulateInstructionMIPS64::Emulate_BGTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1165,7 +1270,7 @@ EmulateInstructionMIPS64::Emulate_BGTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1188,11 +1293,11 @@ EmulateInstructionMIPS64::Emulate_BLEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1204,7 +1309,7 @@ EmulateInstructionMIPS64::Emulate_BLEZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1227,11 +1332,11 @@ EmulateInstructionMIPS64::Emulate_BLTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1243,7 +1348,7 @@ EmulateInstructionMIPS64::Emulate_BLTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1266,11 +1371,11 @@ EmulateInstructionMIPS64::Emulate_BGEZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1282,10 +1387,10 @@ EmulateInstructionMIPS64::Emulate_BGEZALL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1305,7 +1410,7 @@ EmulateInstructionMIPS64::Emulate_BAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -1313,10 +1418,10 @@ EmulateInstructionMIPS64::Emulate_BAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1336,7 +1441,7 @@ EmulateInstructionMIPS64::Emulate_BALC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -1344,10 +1449,10 @@ EmulateInstructionMIPS64::Emulate_BALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1372,11 +1477,11 @@ EmulateInstructionMIPS64::Emulate_BGEZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1387,10 +1492,10 @@ EmulateInstructionMIPS64::Emulate_BGEZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1415,11 +1520,11 @@ EmulateInstructionMIPS64::Emulate_BLTZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1430,10 +1535,10 @@ EmulateInstructionMIPS64::Emulate_BLTZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1458,11 +1563,11 @@ EmulateInstructionMIPS64::Emulate_BLTZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1473,10 +1578,10 @@ EmulateInstructionMIPS64::Emulate_BLTZALL (llvm::MCInst& insn) else target = pc + 8; /* skip delay slot */ - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1502,11 +1607,11 @@ EmulateInstructionMIPS64::Emulate_BLEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1517,10 +1622,10 @@ EmulateInstructionMIPS64::Emulate_BLEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1545,11 +1650,11 @@ EmulateInstructionMIPS64::Emulate_BGEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1560,10 +1665,10 @@ EmulateInstructionMIPS64::Emulate_BGEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1588,11 +1693,11 @@ EmulateInstructionMIPS64::Emulate_BLTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1603,10 +1708,10 @@ EmulateInstructionMIPS64::Emulate_BLTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1631,11 +1736,11 @@ EmulateInstructionMIPS64::Emulate_BGTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1646,10 +1751,10 @@ EmulateInstructionMIPS64::Emulate_BGTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1673,11 +1778,11 @@ EmulateInstructionMIPS64::Emulate_BEQZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1688,10 +1793,10 @@ EmulateInstructionMIPS64::Emulate_BEQZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1715,11 +1820,11 @@ EmulateInstructionMIPS64::Emulate_BNEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1730,10 +1835,10 @@ EmulateInstructionMIPS64::Emulate_BNEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1756,11 +1861,11 @@ EmulateInstructionMIPS64::Emulate_BGEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1771,7 +1876,7 @@ EmulateInstructionMIPS64::Emulate_BGEZ (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1790,7 +1895,7 @@ EmulateInstructionMIPS64::Emulate_BC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -1798,7 +1903,7 @@ EmulateInstructionMIPS64::Emulate_BC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1821,15 +1926,15 @@ EmulateInstructionMIPS64::Emulate_BEQC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1841,7 +1946,7 @@ EmulateInstructionMIPS64::Emulate_BEQC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1864,15 +1969,15 @@ EmulateInstructionMIPS64::Emulate_BNEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1884,7 +1989,7 @@ EmulateInstructionMIPS64::Emulate_BNEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1908,15 +2013,15 @@ EmulateInstructionMIPS64::Emulate_BLTC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1928,7 +2033,7 @@ EmulateInstructionMIPS64::Emulate_BLTC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1952,15 +2057,15 @@ EmulateInstructionMIPS64::Emulate_BGEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1972,7 +2077,7 @@ EmulateInstructionMIPS64::Emulate_BGEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1996,15 +2101,15 @@ EmulateInstructionMIPS64::Emulate_BLTUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2016,7 +2121,7 @@ EmulateInstructionMIPS64::Emulate_BLTUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2040,15 +2145,15 @@ EmulateInstructionMIPS64::Emulate_BGEUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2060,7 +2165,7 @@ EmulateInstructionMIPS64::Emulate_BGEUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2083,11 +2188,11 @@ EmulateInstructionMIPS64::Emulate_BLTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2099,7 +2204,7 @@ EmulateInstructionMIPS64::Emulate_BLTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2122,11 +2227,11 @@ EmulateInstructionMIPS64::Emulate_BLEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2138,7 +2243,7 @@ EmulateInstructionMIPS64::Emulate_BLEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2161,11 +2266,11 @@ EmulateInstructionMIPS64::Emulate_BGEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2177,7 +2282,7 @@ EmulateInstructionMIPS64::Emulate_BGEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2200,11 +2305,11 @@ EmulateInstructionMIPS64::Emulate_BGTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2216,7 +2321,7 @@ EmulateInstructionMIPS64::Emulate_BGTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2239,11 +2344,11 @@ EmulateInstructionMIPS64::Emulate_BEQZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2255,7 +2360,7 @@ EmulateInstructionMIPS64::Emulate_BEQZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2278,11 +2383,11 @@ EmulateInstructionMIPS64::Emulate_BNEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2294,7 +2399,7 @@ EmulateInstructionMIPS64::Emulate_BNEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2325,15 +2430,15 @@ EmulateInstructionMIPS64::Emulate_BOVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2345,7 +2450,7 @@ EmulateInstructionMIPS64::Emulate_BOVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2369,15 +2474,15 @@ EmulateInstructionMIPS64::Emulate_BNVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2389,7 +2494,7 @@ EmulateInstructionMIPS64::Emulate_BNVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2408,7 +2513,7 @@ EmulateInstructionMIPS64::Emulate_J (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -2417,7 +2522,7 @@ EmulateInstructionMIPS64::Emulate_J (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, pc)) return false; return true; @@ -2436,7 +2541,7 @@ EmulateInstructionMIPS64::Emulate_JAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -2445,10 +2550,10 @@ EmulateInstructionMIPS64::Emulate_JAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -2469,20 +2574,20 @@ EmulateInstructionMIPS64::Emulate_JALR (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, rs_val)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips64 + rt, pc + 8)) return false; return true; @@ -2504,11 +2609,11 @@ EmulateInstructionMIPS64::Emulate_JIALC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2516,10 +2621,10 @@ EmulateInstructionMIPS64::Emulate_JIALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -2540,7 +2645,7 @@ EmulateInstructionMIPS64::Emulate_JIC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2548,7 +2653,7 @@ EmulateInstructionMIPS64::Emulate_JIC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2567,13 +2672,13 @@ EmulateInstructionMIPS64::Emulate_JR (llvm::MCInst& insn) */ rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, rs_val)) return false; return true; @@ -2596,11 +2701,11 @@ EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2614,7 +2719,7 @@ EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2637,11 +2742,11 @@ EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2655,7 +2760,7 @@ EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2678,11 +2783,11 @@ EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2696,7 +2801,7 @@ EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2719,11 +2824,11 @@ EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2737,7 +2842,7 @@ EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2761,11 +2866,11 @@ EmulateInstructionMIPS64::Emulate_BC1EQZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + ft, 0, &success); if (!success) return false; @@ -2776,7 +2881,7 @@ EmulateInstructionMIPS64::Emulate_BC1EQZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2800,11 +2905,11 @@ EmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + ft, 0, &success); if (!success) return false; @@ -2815,7 +2920,7 @@ EmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2839,11 +2944,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2858,7 +2963,7 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2882,11 +2987,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2901,7 +3006,7 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2927,11 +3032,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2946,7 +3051,7 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2972,11 +3077,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2991,8 +3096,234 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; } + +bool +EmulateInstructionMIPS64::Emulate_BNZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BNZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BNZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BNZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, false); +} + +bool +EmulateInstructionMIPS64::Emulate_BZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, false); +} + +bool +EmulateInstructionMIPS64::Emulate_BZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, false); +} + +bool +EmulateInstructionMIPS64::Emulate_BZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, false); +} + +bool +EmulateInstructionMIPS64::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz) +{ + bool success = false, branch_hit = true; + int64_t target = 0; + RegisterValue reg_value; + uint8_t * ptr = NULL; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int64_t offset = insn.getOperand(1).getImm(); + + int64_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips64 + wt, reg_value)) + ptr = (uint8_t *)reg_value.GetBytes(); + else + return false; + + for(int i = 0; i < 16 / element_byte_size; i++) + { + switch(element_byte_size) + { + case 1: + if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) ) + branch_hit = false; + break; + case 2: + if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 4: + if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 8: + if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + } + if(!branch_hit) + break; + ptr = ptr + element_byte_size; + } + + if(branch_hit) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS64::Emulate_BNZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, false); +} + +bool +EmulateInstructionMIPS64::Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz) +{ + bool success = false; + int64_t target = 0; + llvm::APInt wr_val = llvm::APInt::getNullValue(128); + llvm::APInt fail_value = llvm::APInt::getMaxValue(128); + llvm::APInt zero_value = llvm::APInt::getNullValue(128); + RegisterValue reg_value; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int64_t offset = insn.getOperand(1).getImm(); + + int64_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips64 + wt, reg_value)) + wr_val = reg_value.GetAsUInt128(fail_value); + else + return false; + + if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz)) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS64::Emulate_LDST_Imm (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + int64_t imm, address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + imm = insn.getOperand(num_operands-1).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} + +bool +EmulateInstructionMIPS64::Emulate_LDST_Reg (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base, index; + int64_t address, index_address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + index = m_reg_info->getEncodingValue (insn.getOperand(num_operands-1).getReg()); + + RegisterInfo reg_info_base, reg_info_index; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + index, reg_info_index)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* read index register */ + index_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + index, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + index_address; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h index faefd329a8e4..e0b20792ae1f 100644 --- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h +++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h @@ -1,4 +1,4 @@ -//===-- EmulateInstructionMIPS64.h ------------------------------------*- C++ -*-===// +//===-- EmulateInstructionMIPS64.h ------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -10,6 +10,14 @@ #ifndef EmulateInstructionMIPS64_h_ #define EmulateInstructionMIPS64_h_ +// C Includes +// C++ Includes +// Other libraries and framework includes +// Project includes +#include "lldb/Core/EmulateInstruction.h" +#include "lldb/Core/Error.h" +#include "lldb/Interpreter/OptionValue.h" + namespace llvm { class MCDisassembler; @@ -19,15 +27,13 @@ namespace llvm class MCContext; class MCInstrInfo; class MCInst; -} - -#include "lldb/Core/EmulateInstruction.h" -#include "lldb/Core/Error.h" -#include "lldb/Interpreter/OptionValue.h" +} // namespace llvm class EmulateInstructionMIPS64 : public lldb_private::EmulateInstruction { public: + EmulateInstructionMIPS64(const lldb_private::ArchSpec &arch); + static void Initialize (); @@ -60,57 +66,47 @@ public: return false; } - virtual lldb_private::ConstString - GetPluginName(); - - virtual lldb_private::ConstString - GetShortPluginName() - { - return GetPluginNameStatic(); - } + lldb_private::ConstString + GetPluginName() override; - virtual uint32_t - GetPluginVersion() + uint32_t + GetPluginVersion() override { return 1; } bool - SetTargetTriple (const lldb_private::ArchSpec &arch); + SetTargetTriple(const lldb_private::ArchSpec &arch) override; - EmulateInstructionMIPS64 (const lldb_private::ArchSpec &arch); - - virtual bool - SupportsEmulatingInstructionsOfType (lldb_private::InstructionType inst_type) + bool + SupportsEmulatingInstructionsOfType(lldb_private::InstructionType inst_type) override { return SupportsEmulatingInstructionsOfTypeStatic (inst_type); } - virtual bool - ReadInstruction (); + bool + ReadInstruction() override; - virtual bool - EvaluateInstruction (uint32_t evaluate_options); + bool + EvaluateInstruction(uint32_t evaluate_options) override; - virtual bool - TestEmulation (lldb_private::Stream *out_stream, - lldb_private::ArchSpec &arch, - lldb_private::OptionValueDictionary *test_data) + bool + TestEmulation(lldb_private::Stream *out_stream, + lldb_private::ArchSpec &arch, + lldb_private::OptionValueDictionary *test_data) override { return false; } - virtual bool - GetRegisterInfo (lldb::RegisterKind reg_kind, - uint32_t reg_num, - lldb_private::RegisterInfo ®_info); - - virtual bool - CreateFunctionEntryUnwind (lldb_private::UnwindPlan &unwind_plan); + bool + GetRegisterInfo(lldb::RegisterKind reg_kind, + uint32_t reg_num, + lldb_private::RegisterInfo ®_info) override; + bool + CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override; protected: - typedef struct { const char *op_name; @@ -128,13 +124,13 @@ protected: Emulate_SD (llvm::MCInst& insn); bool - Emulate_SW (llvm::MCInst& insn); + Emulate_LD (llvm::MCInst& insn); bool - Emulate_LW (llvm::MCInst& insn); + Emulate_LDST_Imm (llvm::MCInst& insn); bool - Emulate_LD (llvm::MCInst& insn); + Emulate_LDST_Reg (llvm::MCInst& insn); bool Emulate_BEQ (llvm::MCInst& insn); @@ -302,6 +298,42 @@ protected: Emulate_BC1ANY4T (llvm::MCInst& insn); bool + Emulate_BNZB (llvm::MCInst& insn); + + bool + Emulate_BNZH (llvm::MCInst& insn); + + bool + Emulate_BNZW (llvm::MCInst& insn); + + bool + Emulate_BNZD (llvm::MCInst& insn); + + bool + Emulate_BZB (llvm::MCInst& insn); + + bool + Emulate_BZH (llvm::MCInst& insn); + + bool + Emulate_BZW (llvm::MCInst& insn); + + bool + Emulate_BZD (llvm::MCInst& insn); + + bool + Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz); + + bool + Emulate_BNZV (llvm::MCInst& insn); + + bool + Emulate_BZV (llvm::MCInst& insn); + + bool + Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz); + + bool nonvolatile_reg_p (uint64_t regnum); const char * @@ -316,4 +348,4 @@ private: std::unique_ptr<llvm::MCInstrInfo> m_insn_info; }; -#endif // EmulateInstructionMIPS64_h_ +#endif // EmulateInstructionMIPS64_h_ |