diff options
Diffstat (limited to 'src/arm/exynos4412.dtsi')
-rw-r--r-- | src/arm/exynos4412.dtsi | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/arm/exynos4412.dtsi b/src/arm/exynos4412.dtsi new file mode 100644 index 000000000000..0f6ec93bb1d8 --- /dev/null +++ b/src/arm/exynos4412.dtsi @@ -0,0 +1,69 @@ +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4412", "samsung,exynos4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@A00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + }; + + cpu@A01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + + cpu@A02 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA02>; + }; + + cpu@A03 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA03>; + }; + }; + + combiner: interrupt-controller@10440000 { + samsung,combiner-nr = <20>; + }; + + pmu { + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + }; + + gic: interrupt-controller@10490000 { + cpu-offset = <0x4000>; + }; + + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4412-pmu", "syscon"; + }; +}; |