diff options
Diffstat (limited to 'test/CodeGen/AArch64/misched-fusion-aes.ll')
| -rw-r--r-- | test/CodeGen/AArch64/misched-fusion-aes.ll | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/misched-fusion-aes.ll b/test/CodeGen/AArch64/misched-fusion-aes.ll index f29dfb3a9802..4c682e594e66 100644 --- a/test/CodeGen/AArch64/misched-fusion-aes.ll +++ b/test/CodeGen/AArch64/misched-fusion-aes.ll @@ -1,4 +1,5 @@ ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKA57 +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKA72 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKM1 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k) @@ -87,6 +88,22 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, ; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VG]] ; CHECKA57: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} ; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VH]] +; CHECKA72: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VA]] +; CHECKA72: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VB]] +; CHECKA72: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VC]] +; CHECKA72: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VD]] +; CHECKA72: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VE]] +; CHECKA72: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VF]] +; CHECKA72: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VG]] +; CHECKA72: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VH]] ; CHECKM1: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1: aesmc {{v[0-7].16b}}, [[VA]] ; CHECKM1: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} @@ -187,6 +204,22 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, ; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VG]] ; CHECKA57: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} ; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VH]] +; CHECKA72: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VA]] +; CHECKA72: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VB]] +; CHECKA72: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VC]] +; CHECKA72: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VD]] +; CHECKA72: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VE]] +; CHECKA72: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VF]] +; CHECKA72: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VG]] +; CHECKA72: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VH]] ; CHECKM1: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1: aesimc {{v[0-7].16b}}, [[VA]] ; CHECKM1: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} |