diff options
Diffstat (limited to 'test/CodeGen/AMDGPU/scheduler-subrange-crash.ll')
| -rw-r--r-- | test/CodeGen/AMDGPU/scheduler-subrange-crash.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll b/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll index 47e32724d9ca..5edc2c5c9b71 100644 --- a/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll +++ b/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll @@ -15,16 +15,16 @@ target triple = "amdgcn--" define amdgpu_gs void @main(i32 inreg %arg) #0 { main_body: - %tmp = call float @llvm.SI.load.const(<16 x i8> undef, i32 20) - %tmp1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 24) - %tmp2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 48) + %tmp = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 20) + %tmp1 = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 24) + %tmp2 = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 48) %array_vector3 = insertelement <4 x float> zeroinitializer, float %tmp2, i32 3 %array_vector5 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp, i32 1 %array_vector6 = insertelement <4 x float> %array_vector5, float undef, i32 2 %array_vector9 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp1, i32 1 %array_vector10 = insertelement <4 x float> %array_vector9, float 0.000000e+00, i32 2 %array_vector11 = insertelement <4 x float> %array_vector10, float undef, i32 3 - %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> undef, i32 undef, i32 4864, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) + %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> undef, i32 undef, i32 4864, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) call void @llvm.amdgcn.tbuffer.store.i32(i32 %tmp3, <4 x i32> undef, i32 0, i32 0, i32 %arg, i32 36, i32 4, i32 4, i1 1, i1 1) %bc = bitcast <4 x float> %array_vector3 to <4 x i32> %tmp4 = extractelement <4 x i32> %bc, i32 undef @@ -45,8 +45,8 @@ main_body: ret void } -declare float @llvm.SI.load.const(<16 x i8>, i32) #1 -declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #2 +declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1 +declare i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2 declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #3 attributes #0 = { nounwind "target-cpu"="tonga" } |