aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen/ARM/emutls.ll
diff options
context:
space:
mode:
Diffstat (limited to 'test/CodeGen/ARM/emutls.ll')
-rw-r--r--test/CodeGen/ARM/emutls.ll74
1 files changed, 44 insertions, 30 deletions
diff --git a/test/CodeGen/ARM/emutls.ll b/test/CodeGen/ARM/emutls.ll
index 7ba50dd249bb..e66d93ebcb89 100644
--- a/test/CodeGen/ARM/emutls.ll
+++ b/test/CodeGen/ARM/emutls.ll
@@ -11,8 +11,9 @@ define i32 @my_get_xyz() {
; ARM32-LABEL: my_get_xyz:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl my_emutls_get_address(PLT)
+; ARM32-NEXT: bl my_emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
+; ARM32: .long my_emutls_v_xyz(GOT_PREL)
entry:
%call = call i8* @my_emutls_get_address(i8* bitcast (i8** @my_emutls_v_xyz to i8*))
@@ -33,8 +34,9 @@ define i32 @f1() {
; ARM32-LABEL: f1:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
+; ARM32: .long __emutls_v.i1(GOT_PREL)
entry:
%tmp1 = load i32, i32* @i1
@@ -45,8 +47,9 @@ define i32* @f2() {
; ARM32-LABEL: f2:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
+; ARM32: .long __emutls_v.i1(GOT_PREL)
entry:
ret i32* @i1
@@ -56,8 +59,9 @@ define i32 @f3() nounwind {
; ARM32-LABEL: f3:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
+; ARM32: .long __emutls_v.i2(GOT_PREL)
entry:
%tmp1 = load i32, i32* @i2
@@ -68,8 +72,9 @@ define i32* @f4() {
; ARM32-LABEL: f4:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
+; ARM32: .long __emutls_v.i2(GOT_PREL)
entry:
ret i32* @i2
@@ -78,9 +83,10 @@ entry:
define i32 @f5() nounwind {
; ARM32-LABEL: f5:
; ARM32: ldr r0,
-; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32: add r0, pc, r0
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
+; ARM32: .long __emutls_v.i3-
entry:
%tmp1 = load i32, i32* @i3
@@ -90,9 +96,10 @@ entry:
define i32* @f6() {
; ARM32-LABEL: f6:
; ARM32: ldr r0,
-; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32: add r0, pc, r0
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
+; ARM32: .long __emutls_v.i3-
entry:
ret i32* @i3
@@ -101,9 +108,10 @@ entry:
define i32 @f7() {
; ARM32-LABEL: f7:
; ARM32: ldr r0,
-; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32: add r0, pc, r0
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
+; ARM32: .long __emutls_v.i4-(.LPC
entry:
%tmp1 = load i32, i32* @i4
@@ -113,9 +121,10 @@ entry:
define i32* @f8() {
; ARM32-LABEL: f8:
; ARM32: ldr r0,
-; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32: add r0, pc, r0
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
+; ARM32: .long __emutls_v.i4-(.LPC
entry:
ret i32* @i4
@@ -124,8 +133,8 @@ entry:
define i32 @f9() {
; ARM32-LABEL: f9:
; ARM32: ldr r0,
-; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32: add r0, pc, r0
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
entry:
@@ -136,8 +145,8 @@ entry:
define i32* @f10() {
; ARM32-LABEL: f10:
; ARM32: ldr r0,
-; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32: add r0, pc, r0
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
entry:
@@ -148,7 +157,7 @@ define i16 @f11() {
; ARM32-LABEL: f11:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrh r0, [r0]
entry:
@@ -160,7 +169,7 @@ define i32 @f12() {
; ARM32-LABEL: f12:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrsh r0, [r0]
entry:
@@ -173,7 +182,7 @@ define i8 @f13() {
; ARM32-LABEL: f13:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrb r0, [r0]
; ARM32-NEXT: pop
@@ -186,7 +195,7 @@ define i32 @f14() {
; ARM32-LABEL: f14:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrsb r0, [r0]
; ARM32-NEXT: pop
@@ -198,46 +207,50 @@ entry:
;;;;;;;;;;;;;; 32-bit __emutls_v. and __emutls_t.
-; ARM32 .section .data.rel.local,
+; ARM32: .data{{$}}
+; ARM32: .globl __emutls_v.i1
; ARM32-LABEL: __emutls_v.i1:
; ARM32-NEXT: .long 4
; ARM32-NEXT: .long 4
; ARM32-NEXT: .long 0
; ARM32-NEXT: .long __emutls_t.i1
-; ARM32 .section .rodata,
+; ARM32: .section .rodata,
; ARM32-LABEL: __emutls_t.i1:
; ARM32-NEXT: .long 15
; ARM32-NOT: __emutls_v.i2
-; ARM32 .section .data.rel.local,
+; ARM32: .data{{$}}
+; ARM32-NOT: .globl
; ARM32-LABEL: __emutls_v.i3:
; ARM32-NEXT: .long 4
; ARM32-NEXT: .long 4
; ARM32-NEXT: .long 0
; ARM32-NEXT: .long __emutls_t.i3
-; ARM32 .section .rodata,
+; ARM32: .section .rodata,
; ARM32-LABEL: __emutls_t.i3:
; ARM32-NEXT: .long 15
-; ARM32 .section .data.rel.local,
+; ARM32: .data{{$}}
+; ARM32: .globl __emutls_v.i4
; ARM32-LABEL: __emutls_v.i4:
; ARM32-NEXT: .long 4
; ARM32-NEXT: .long 4
; ARM32-NEXT: .long 0
; ARM32-NEXT: .long __emutls_t.i4
-; ARM32 .section .rodata,
+; ARM32: .section .rodata,
; ARM32-LABEL: __emutls_t.i4:
; ARM32-NEXT: .long 15
; ARM32-NOT: __emutls_v.i5:
-; ARM32 .hidden __emutls_v.i5
+; ARM32: .hidden __emutls_v.i5
; ARM32-NOT: __emutls_v.i5:
-; ARM32 .section .data.rel.local,
+; ARM32: .data{{$}}
+; ARM32: .globl __emutls_v.s1
; ARM32-LABEL: __emutls_v.s1:
; ARM32-NEXT: .long 2
; ARM32-NEXT: .long 2
@@ -248,7 +261,8 @@ entry:
; ARM32-LABEL: __emutls_t.s1:
; ARM32-NEXT: .short 15
-; ARM32 .section .data.rel.local,
+; ARM32: .data{{$}}
+; ARM32: .globl __emutls_v.b1
; ARM32-LABEL: __emutls_v.b1:
; ARM32-NEXT: .long 1
; ARM32-NEXT: .long 1
generated by cgit v1.3 (git 2.53.0) at 2026-03-10 12:18:11 +0000