diff options
Diffstat (limited to 'test/CodeGen/ARM')
497 files changed, 16350 insertions, 5606 deletions
diff --git a/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll b/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll index f8bd886aa9e1..b719f9f4d235 100644 --- a/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll +++ b/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll @@ -11,9 +11,9 @@ bb169.i: ; preds = %entry ret void cond_true11: ; preds = %entry - %tmp.i32 = load %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2] - %tmp3.i35 = getelementptr %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; <i8*> [#uses=2] - %tmp.i36 = getelementptr %struct.layer_data* %tmp.i32, i32 0, i32 2 ; <i8**> [#uses=1] + %tmp.i32 = load %struct.layer_data*, %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2] + %tmp3.i35 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; <i8*> [#uses=2] + %tmp.i36 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 2 ; <i8**> [#uses=1] store i8* %tmp3.i35, i8** %tmp.i36 store i8* %tmp3.i35, i8** null ret void diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index e7c0129a7752..4ba81e01ad31 100644 --- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -1,5 +1,9 @@ ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck --check-prefix=DOMAIN %s +; The execution domain checking code would translate vmovs to vorr whether or not +; we had NEON instructions. Verify we don't if we're not compiled with NEON. +; DOMAIN-NOT: vorr @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] @@ -15,15 +19,15 @@ entry: br label %cond_next489 cond_next489: ; preds = %cond_false, %bb471 - %j.7.in = load i8* null ; <i8> [#uses=1] - %i.8.in = load i8* null ; <i8> [#uses=1] + %j.7.in = load i8, i8* null ; <i8> [#uses=1] + %i.8.in = load i8, i8* null ; <i8> [#uses=1] %i.8 = zext i8 %i.8.in to i32 ; <i32> [#uses=4] %j.7 = zext i8 %j.7.in to i32 ; <i32> [#uses=4] - %tmp495 = getelementptr [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=2] - %tmp496 = load i32* %tmp495 ; <i32> [#uses=2] - %tmp502 = load i32* null ; <i32> [#uses=1] - %tmp542 = getelementptr [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] - %tmp543 = load i32* %tmp542 ; <i32> [#uses=1] + %tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=2] + %tmp496 = load i32, i32* %tmp495 ; <i32> [#uses=2] + %tmp502 = load i32, i32* null ; <i32> [#uses=1] + %tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] + %tmp543 = load i32, i32* %tmp542 ; <i32> [#uses=1] %tmp548 = ashr i32 0, 0 ; <i32> [#uses=3] %tmp561 = sub i32 0, %tmp496 ; <i32> [#uses=3] %abscond563 = icmp sgt i32 %tmp561, -1 ; <i1> [#uses=1] @@ -35,10 +39,10 @@ cond_next489: ; preds = %cond_false, %bb471 br i1 %tmp579, label %bb712, label %cond_next589 cond_next589: ; preds = %cond_next489 - %tmp605 = getelementptr [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] - %tmp606 = load i32* %tmp605 ; <i32> [#uses=1] - %tmp612 = load i32* null ; <i32> [#uses=1] - %tmp629 = load i32* null ; <i32> [#uses=1] + %tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] + %tmp606 = load i32, i32* %tmp605 ; <i32> [#uses=1] + %tmp612 = load i32, i32* null ; <i32> [#uses=1] + %tmp629 = load i32, i32* null ; <i32> [#uses=1] %tmp629a = sitofp i32 %tmp629 to double ; <double> [#uses=1] %tmp631 = fmul double %tmp629a, 0.000000e+00 ; <double> [#uses=1] %tmp632 = fadd double 0.000000e+00, %tmp631 ; <double> [#uses=1] @@ -85,9 +89,9 @@ bb737: ; preds = %cond_false689 cond_true740: ; preds = %bb737 %tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; <i32> [#uses=1] - %tmp780 = load i32* null ; <i32> [#uses=1] - %tmp785 = getelementptr [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] - %tmp786 = load i32* %tmp785 ; <i32> [#uses=1] + %tmp780 = load i32, i32* null ; <i32> [#uses=1] + %tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] + %tmp786 = load i32, i32* %tmp785 ; <i32> [#uses=1] %tmp781 = mul i32 %tmp780, %tmp761 ; <i32> [#uses=1] %tmp787 = mul i32 %tmp781, %tmp786 ; <i32> [#uses=1] %tmp789 = shl i32 %tmp787, 0 ; <i32> [#uses=1] @@ -96,7 +100,7 @@ cond_true740: ; preds = %bb737 cond_next791: ; preds = %cond_true740, %bb737 %ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; <i32> [#uses=1] - %tmp796 = load i32* %tmp495 ; <i32> [#uses=1] + %tmp796 = load i32, i32* %tmp495 ; <i32> [#uses=1] %tmp798 = add i32 %tmp796, %ilev.1 ; <i32> [#uses=1] %tmp812 = mul i32 0, %tmp502 ; <i32> [#uses=0] %tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; <i32> [#uses=0] diff --git a/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll b/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll index 83b26d340062..472a345a0d71 100644 --- a/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll +++ b/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll @@ -4,10 +4,10 @@ define fastcc i8* @read_sleb128(i8* %p, i32* %val) { br label %bb bb: ; preds = %bb, %0 - %p_addr.0 = getelementptr i8* %p, i32 0 ; <i8*> [#uses=1] - %tmp2 = load i8* %p_addr.0 ; <i8> [#uses=2] + %p_addr.0 = getelementptr i8, i8* %p, i32 0 ; <i8*> [#uses=1] + %tmp2 = load i8, i8* %p_addr.0 ; <i8> [#uses=2] %tmp4.rec = add i32 0, 1 ; <i32> [#uses=1] - %tmp4 = getelementptr i8* %p, i32 %tmp4.rec ; <i8*> [#uses=1] + %tmp4 = getelementptr i8, i8* %p, i32 %tmp4.rec ; <i8*> [#uses=1] %tmp56 = zext i8 %tmp2 to i32 ; <i32> [#uses=1] %tmp7 = and i32 %tmp56, 127 ; <i32> [#uses=1] %tmp9 = shl i32 %tmp7, 0 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/test/CodeGen/ARM/2007-03-13-InstrSched.ll index 4783f3707690..9c0143be06c3 100644 --- a/test/CodeGen/ARM/2007-03-13-InstrSched.ll +++ b/test/CodeGen/ARM/2007-03-13-InstrSched.ll @@ -23,30 +23,30 @@ bb74: ; preds = %bb26, %newFuncRoot %d1.1 = phi i32 [ %tmp54, %bb26 ], [ 8192, %newFuncRoot ] ; <i32> [#uses=2] %d2.1 = phi i32 [ %tmp64, %bb26 ], [ 8192, %newFuncRoot ] ; <i32> [#uses=2] %d3.1 = phi i32 [ %tmp69, %bb26 ], [ 8192, %newFuncRoot ] ; <i32> [#uses=2] - %fm.1 = load i32* %fm.1.in ; <i32> [#uses=4] + %fm.1 = load i32, i32* %fm.1.in ; <i32> [#uses=4] icmp eq i32 %fp.1.rec, %tmp8 ; <i1>:0 [#uses=1] br i1 %0, label %bb78.exitStub, label %bb26 bb26: ; preds = %bb74 - %tmp28 = getelementptr i32** %tmp1, i32 %fp.1.rec ; <i32**> [#uses=1] - %tmp30 = load i32** %tmp28 ; <i32*> [#uses=4] - %tmp33 = getelementptr i32* %tmp30, i32 %i.0196.0.ph ; <i32*> [#uses=1] - %tmp34 = load i32* %tmp33 ; <i32> [#uses=1] - %tmp38 = getelementptr i32* %tmp30, i32 %tmp36224 ; <i32*> [#uses=1] - %tmp39 = load i32* %tmp38 ; <i32> [#uses=1] + %tmp28 = getelementptr i32*, i32** %tmp1, i32 %fp.1.rec ; <i32**> [#uses=1] + %tmp30 = load i32*, i32** %tmp28 ; <i32*> [#uses=4] + %tmp33 = getelementptr i32, i32* %tmp30, i32 %i.0196.0.ph ; <i32*> [#uses=1] + %tmp34 = load i32, i32* %tmp33 ; <i32> [#uses=1] + %tmp38 = getelementptr i32, i32* %tmp30, i32 %tmp36224 ; <i32*> [#uses=1] + %tmp39 = load i32, i32* %tmp38 ; <i32> [#uses=1] %tmp42 = mul i32 %tmp34, %fm.1 ; <i32> [#uses=1] %tmp44 = add i32 %tmp42, %d0.1 ; <i32> [#uses=1] - %tmp48 = getelementptr i32* %tmp30, i32 %tmp46223 ; <i32*> [#uses=1] - %tmp49 = load i32* %tmp48 ; <i32> [#uses=1] + %tmp48 = getelementptr i32, i32* %tmp30, i32 %tmp46223 ; <i32*> [#uses=1] + %tmp49 = load i32, i32* %tmp48 ; <i32> [#uses=1] %tmp52 = mul i32 %tmp39, %fm.1 ; <i32> [#uses=1] %tmp54 = add i32 %tmp52, %d1.1 ; <i32> [#uses=1] - %tmp58 = getelementptr i32* %tmp30, i32 %tmp56222 ; <i32*> [#uses=1] - %tmp59 = load i32* %tmp58 ; <i32> [#uses=1] + %tmp58 = getelementptr i32, i32* %tmp30, i32 %tmp56222 ; <i32*> [#uses=1] + %tmp59 = load i32, i32* %tmp58 ; <i32> [#uses=1] %tmp62 = mul i32 %tmp49, %fm.1 ; <i32> [#uses=1] %tmp64 = add i32 %tmp62, %d2.1 ; <i32> [#uses=1] %tmp67 = mul i32 %tmp59, %fm.1 ; <i32> [#uses=1] %tmp69 = add i32 %tmp67, %d3.1 ; <i32> [#uses=1] %tmp71.rec = add i32 %fp.1.rec, 1 ; <i32> [#uses=2] - %tmp71 = getelementptr i32* %tmp1011, i32 %tmp71.rec ; <i32*> [#uses=1] + %tmp71 = getelementptr i32, i32* %tmp1011, i32 %tmp71.rec ; <i32*> [#uses=1] br label %bb74 } diff --git a/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll index b0953dc8b61f..7c425961958c 100644 --- a/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll +++ b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll @@ -41,7 +41,7 @@ entry: %spec.1961.adj.ins = or i64 %spec.1961.adj, 0 ; <i64> [#uses=2] %tmp10959 = lshr i64 %spec.1961.adj.ins, 32 ; <i64> [#uses=2] %tmp1920 = inttoptr i64 %tmp10959 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1] - %tmp21 = getelementptr %struct.tree_common* %tmp1920, i32 0, i32 3 ; <i8*> [#uses=1] + %tmp21 = getelementptr %struct.tree_common, %struct.tree_common* %tmp1920, i32 0, i32 3 ; <i8*> [#uses=1] %tmp2122 = bitcast i8* %tmp21 to i32* ; <i32*> [#uses=1] br i1 false, label %cond_next53, label %cond_true @@ -71,7 +71,7 @@ cond_next856: ; preds = %cond_true851 ret void bb866: ; preds = %cond_true851 - %tmp874 = load i32* %tmp2122 ; <i32> [#uses=1] + %tmp874 = load i32, i32* %tmp2122 ; <i32> [#uses=1] %tmp876877 = trunc i32 %tmp874 to i8 ; <i8> [#uses=1] icmp eq i8 %tmp876877, 1 ; <i1>:0 [#uses=1] br i1 %0, label %cond_next881, label %cond_true878 @@ -81,9 +81,9 @@ cond_true878: ; preds = %bb866 cond_next881: ; preds = %bb866 %tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier* ; <%struct.tree_identifier*> [#uses=1] - %tmp887 = getelementptr %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; <i8**> [#uses=1] - %tmp888 = load i8** %tmp887 ; <i8*> [#uses=1] - tail call void (i32, ...)* @error( i32 undef, i8* %tmp888 ) + %tmp887 = getelementptr %struct.tree_identifier, %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; <i8**> [#uses=1] + %tmp888 = load i8*, i8** %tmp887 ; <i8*> [#uses=1] + tail call void (i32, ...) @error( i32 undef, i8* %tmp888 ) ret void cond_true918: ; preds = %cond_false841 diff --git a/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll index e4635f50279d..2a0ef770f3bc 100644 --- a/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll @@ -13,7 +13,7 @@ cond_true340: ; preds = %entry ret void cond_next416: ; preds = %entry - %tmp1085 = load %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1] + %tmp1085 = load %struct.rtx_def*, %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1] br i1 false, label %bb1084, label %cond_true418 cond_true418: ; preds = %cond_next416 @@ -23,9 +23,9 @@ bb1084: ; preds = %cond_next416 br i1 false, label %cond_true1092, label %cond_next1102 cond_true1092: ; preds = %bb1084 - %tmp1094 = getelementptr %struct.rtx_def* %tmp1085, i32 0, i32 3 ; <%struct.u*> [#uses=1] + %tmp1094 = getelementptr %struct.rtx_def, %struct.rtx_def* %tmp1085, i32 0, i32 3 ; <%struct.u*> [#uses=1] %tmp10981099 = bitcast %struct.u* %tmp1094 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=2] - %tmp1101 = load %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1] + %tmp1101 = load %struct.rtx_def*, %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1] store %struct.rtx_def* %tmp1101, %struct.rtx_def** %ad_addr br label %cond_next1102 diff --git a/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll index f24def31f97a..7b74e6ce948f 100644 --- a/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll @@ -28,7 +28,7 @@ entry: br i1 false, label %bb.preheader, label %return bb.preheader: ; preds = %entry - %tbl.014.us = load i32* null ; <i32> [#uses=1] + %tbl.014.us = load i32, i32* null ; <i32> [#uses=1] br i1 false, label %cond_next.us, label %bb cond_next51.us: ; preds = %cond_next.us, %cond_true33.us.cond_true46.us_crit_edge @@ -40,8 +40,8 @@ cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us br label %cond_next51.us cond_next.us: ; preds = %bb.preheader - %tmp37.us = getelementptr %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <%struct.H_TBL**> [#uses=3] - %tmp4524.us = load %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1] + %tmp37.us = getelementptr %struct.X_Y, %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <%struct.H_TBL**> [#uses=3] + %tmp4524.us = load %struct.H_TBL*, %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1] icmp eq %struct.H_TBL* %tmp4524.us, null ; <i1>:0 [#uses=1] br i1 %0, label %cond_true33.us.cond_true46.us_crit_edge, label %cond_next51.us diff --git a/test/CodeGen/ARM/2007-04-03-PEIBug.ll b/test/CodeGen/ARM/2007-04-03-PEIBug.ll index cf5094fb3800..87863bd3ec15 100644 --- a/test/CodeGen/ARM/2007-04-03-PEIBug.ll +++ b/test/CodeGen/ARM/2007-04-03-PEIBug.ll @@ -5,7 +5,7 @@ entry: %A = alloca [1123 x i32], align 16 ; <[1123 x i32]*> [#uses=1] %B = alloca [3123 x i32], align 16 ; <[3123 x i32]*> [#uses=1] %C = alloca [12312 x i32], align 16 ; <[12312 x i32]*> [#uses=1] - %tmp = call i32 (...)* @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; <i32> [#uses=0] + %tmp = call i32 (...) @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; <i32> [#uses=0] ret i32 undef } diff --git a/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll index e001cde8351b..11f3003e05b5 100644 --- a/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll +++ b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll @@ -8,9 +8,9 @@ define internal void @_ZN1B1iEv(%struct.B* %this) { entry: - %tmp1 = getelementptr %struct.B* %this, i32 0, i32 0 ; <i32*> [#uses=1] - %tmp2 = load i32* %tmp1 ; <i32> [#uses=1] - %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str, i32 0, i32 0), i32 %tmp2 ) ; <i32> [#uses=0] + %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 ; <i32*> [#uses=1] + %tmp2 = load i32, i32* %tmp1 ; <i32> [#uses=1] + %tmp4 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str, i32 0, i32 0), i32 %tmp2 ) ; <i32> [#uses=0] ret void } @@ -18,9 +18,9 @@ declare i32 @printf(i8*, ...) define internal void @_ZN1B1jEv(%struct.B* %this) { entry: - %tmp1 = getelementptr %struct.B* %this, i32 0, i32 0 ; <i32*> [#uses=1] - %tmp2 = load i32* %tmp1 ; <i32> [#uses=1] - %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 ) ; <i32> [#uses=0] + %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 ; <i32*> [#uses=1] + %tmp2 = load i32, i32* %tmp1 ; <i32> [#uses=1] + %tmp4 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 ) ; <i32> [#uses=0] ret void } @@ -29,70 +29,70 @@ entry: %b.i29 = alloca %struct.B, align 4 ; <%struct.B*> [#uses=3] %b.i1 = alloca %struct.B, align 4 ; <%struct.B*> [#uses=3] %b.i = alloca %struct.B, align 4 ; <%struct.B*> [#uses=3] - %tmp2.i = getelementptr %struct.B* %b.i, i32 0, i32 0 ; <i32*> [#uses=1] + %tmp2.i = getelementptr %struct.B, %struct.B* %b.i, i32 0, i32 0 ; <i32*> [#uses=1] store i32 4, i32* %tmp2.i br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i cond_true.i: ; preds = %entry %b2.i = bitcast %struct.B* %b.i to i8* ; <i8*> [#uses=1] - %ctg23.i = getelementptr i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] + %ctg23.i = getelementptr i8, i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] %tmp121314.i = bitcast i8* %ctg23.i to i32 (...)*** ; <i32 (...)***> [#uses=1] - %tmp15.i = load i32 (...)*** %tmp121314.i ; <i32 (...)**> [#uses=1] + %tmp15.i = load i32 (...)**, i32 (...)*** %tmp121314.i ; <i32 (...)**> [#uses=1] %tmp151.i = bitcast i32 (...)** %tmp15.i to i8* ; <i8*> [#uses=1] - %ctg2.i = getelementptr i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; <i8*> [#uses=1] + %ctg2.i = getelementptr i8, i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; <i8*> [#uses=1] %tmp2021.i = bitcast i8* %ctg2.i to i32 (...)** ; <i32 (...)**> [#uses=1] - %tmp22.i = load i32 (...)** %tmp2021.i ; <i32 (...)*> [#uses=1] + %tmp22.i = load i32 (...)*, i32 (...)** %tmp2021.i ; <i32 (...)*> [#uses=1] %tmp2223.i = bitcast i32 (...)* %tmp22.i to void (%struct.B*)* ; <void (%struct.B*)*> [#uses=1] br label %_Z3fooiM1BFvvE.exit _Z3fooiM1BFvvE.exit: ; preds = %cond_true.i, %entry %iftmp.2.0.i = phi void (%struct.B*)* [ %tmp2223.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %entry ] ; <void (%struct.B*)*> [#uses=1] %b4.i = bitcast %struct.B* %b.i to i8* ; <i8*> [#uses=1] - %ctg25.i = getelementptr i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] + %ctg25.i = getelementptr i8, i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] %tmp3031.i = bitcast i8* %ctg25.i to %struct.B* ; <%struct.B*> [#uses=1] call void %iftmp.2.0.i( %struct.B* %tmp3031.i ) - %tmp2.i30 = getelementptr %struct.B* %b.i29, i32 0, i32 0 ; <i32*> [#uses=1] + %tmp2.i30 = getelementptr %struct.B, %struct.B* %b.i29, i32 0, i32 0 ; <i32*> [#uses=1] store i32 6, i32* %tmp2.i30 br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46 cond_true.i46: ; preds = %_Z3fooiM1BFvvE.exit %b2.i35 = bitcast %struct.B* %b.i29 to i8* ; <i8*> [#uses=1] - %ctg23.i36 = getelementptr i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] + %ctg23.i36 = getelementptr i8, i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] %tmp121314.i37 = bitcast i8* %ctg23.i36 to i32 (...)*** ; <i32 (...)***> [#uses=1] - %tmp15.i38 = load i32 (...)*** %tmp121314.i37 ; <i32 (...)**> [#uses=1] + %tmp15.i38 = load i32 (...)**, i32 (...)*** %tmp121314.i37 ; <i32 (...)**> [#uses=1] %tmp151.i41 = bitcast i32 (...)** %tmp15.i38 to i8* ; <i8*> [#uses=1] - %ctg2.i42 = getelementptr i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) ; <i8*> [#uses=1] + %ctg2.i42 = getelementptr i8, i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) ; <i8*> [#uses=1] %tmp2021.i43 = bitcast i8* %ctg2.i42 to i32 (...)** ; <i32 (...)**> [#uses=1] - %tmp22.i44 = load i32 (...)** %tmp2021.i43 ; <i32 (...)*> [#uses=1] + %tmp22.i44 = load i32 (...)*, i32 (...)** %tmp2021.i43 ; <i32 (...)*> [#uses=1] %tmp2223.i45 = bitcast i32 (...)* %tmp22.i44 to void (%struct.B*)* ; <void (%struct.B*)*> [#uses=1] br label %_Z3fooiM1BFvvE.exit56 _Z3fooiM1BFvvE.exit56: ; preds = %cond_true.i46, %_Z3fooiM1BFvvE.exit %iftmp.2.0.i49 = phi void (%struct.B*)* [ %tmp2223.i45, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit ] ; <void (%struct.B*)*> [#uses=1] %b4.i53 = bitcast %struct.B* %b.i29 to i8* ; <i8*> [#uses=1] - %ctg25.i54 = getelementptr i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] + %ctg25.i54 = getelementptr i8, i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] %tmp3031.i55 = bitcast i8* %ctg25.i54 to %struct.B* ; <%struct.B*> [#uses=1] call void %iftmp.2.0.i49( %struct.B* %tmp3031.i55 ) - %tmp2.i2 = getelementptr %struct.B* %b.i1, i32 0, i32 0 ; <i32*> [#uses=1] + %tmp2.i2 = getelementptr %struct.B, %struct.B* %b.i1, i32 0, i32 0 ; <i32*> [#uses=1] store i32 -1, i32* %tmp2.i2 br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18 cond_true.i18: ; preds = %_Z3fooiM1BFvvE.exit56 %b2.i7 = bitcast %struct.B* %b.i1 to i8* ; <i8*> [#uses=1] - %ctg23.i8 = getelementptr i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] + %ctg23.i8 = getelementptr i8, i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] %tmp121314.i9 = bitcast i8* %ctg23.i8 to i32 (...)*** ; <i32 (...)***> [#uses=1] - %tmp15.i10 = load i32 (...)*** %tmp121314.i9 ; <i32 (...)**> [#uses=1] + %tmp15.i10 = load i32 (...)**, i32 (...)*** %tmp121314.i9 ; <i32 (...)**> [#uses=1] %tmp151.i13 = bitcast i32 (...)** %tmp15.i10 to i8* ; <i8*> [#uses=1] - %ctg2.i14 = getelementptr i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; <i8*> [#uses=1] + %ctg2.i14 = getelementptr i8, i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; <i8*> [#uses=1] %tmp2021.i15 = bitcast i8* %ctg2.i14 to i32 (...)** ; <i32 (...)**> [#uses=1] - %tmp22.i16 = load i32 (...)** %tmp2021.i15 ; <i32 (...)*> [#uses=1] + %tmp22.i16 = load i32 (...)*, i32 (...)** %tmp2021.i15 ; <i32 (...)*> [#uses=1] %tmp2223.i17 = bitcast i32 (...)* %tmp22.i16 to void (%struct.B*)* ; <void (%struct.B*)*> [#uses=1] br label %_Z3fooiM1BFvvE.exit28 _Z3fooiM1BFvvE.exit28: ; preds = %cond_true.i18, %_Z3fooiM1BFvvE.exit56 %iftmp.2.0.i21 = phi void (%struct.B*)* [ %tmp2223.i17, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit56 ] ; <void (%struct.B*)*> [#uses=1] %b4.i25 = bitcast %struct.B* %b.i1 to i8* ; <i8*> [#uses=1] - %ctg25.i26 = getelementptr i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] + %ctg25.i26 = getelementptr i8, i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1] %tmp3031.i27 = bitcast i8* %ctg25.i26 to %struct.B* ; <%struct.B*> [#uses=1] call void %iftmp.2.0.i21( %struct.B* %tmp3031.i27 ) ret i32 0 diff --git a/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll b/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll index a89e937d3e10..05c2ff4f7ca2 100644 --- a/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll +++ b/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll @@ -9,15 +9,15 @@ target triple = "arm-apple-darwin8" define fastcc void @EvaluateDevelopment() { entry: - %tmp7 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 7) ; <i64> [#uses=1] - %tmp50 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 0) ; <i64> [#uses=1] - %tmp52 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 1) ; <i64> [#uses=1] + %tmp7 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 7) ; <i64> [#uses=1] + %tmp50 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 0) ; <i64> [#uses=1] + %tmp52 = load i64, i64* getelementptr (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 1) ; <i64> [#uses=1] %tmp53 = or i64 %tmp52, %tmp50 ; <i64> [#uses=1] - %tmp57.b = load i1* @rank_mask.1.b ; <i1> [#uses=1] + %tmp57.b = load i1, i1* @rank_mask.1.b ; <i1> [#uses=1] %tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0 ; <i64> [#uses=1] %tmp58 = and i64 %tmp57, %tmp7 ; <i64> [#uses=1] %tmp59 = lshr i64 %tmp58, 8 ; <i64> [#uses=1] - %tmp63 = load i64* getelementptr ([8 x i64]* @file_mask, i32 0, i32 4) ; <i64> [#uses=1] + %tmp63 = load i64, i64* getelementptr ([8 x i64], [8 x i64]* @file_mask, i32 0, i32 4) ; <i64> [#uses=1] %tmp64 = or i64 %tmp63, 0 ; <i64> [#uses=1] %tmp65 = and i64 %tmp59, %tmp53 ; <i64> [#uses=1] %tmp66 = and i64 %tmp65, %tmp64 ; <i64> [#uses=1] diff --git a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll index 25ac52e5ec77..50573b457c37 100644 --- a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll +++ b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll @@ -14,7 +14,7 @@ define fastcc void @Draw7(i32 %Option, i32* %Status) { entry: - %tmp115.b = load i1* @FirstTime.4637.b ; <i1> [#uses=1] + %tmp115.b = load i1, i1* @FirstTime.4637.b ; <i1> [#uses=1] br i1 %tmp115.b, label %cond_next239, label %cond_next.i cond_next.i: ; preds = %entry @@ -88,19 +88,19 @@ cond_next1267: ; preds = %cond_next1235 br i1 %tmp1148, label %cond_next1275, label %cond_true1272 cond_true1272: ; preds = %cond_next1267 - %tmp1273 = load %struct.TestObj** null ; <%struct.TestObj*> [#uses=2] + %tmp1273 = load %struct.TestObj*, %struct.TestObj** null ; <%struct.TestObj*> [#uses=2] %tmp2930.i = ptrtoint %struct.TestObj* %tmp1273 to i32 ; <i32> [#uses=1] %tmp42.i348 = sub i32 0, %tmp2930.i ; <i32> [#uses=1] - %tmp45.i = getelementptr %struct.TestObj* %tmp1273, i32 0, i32 0 ; <i8**> [#uses=2] - %tmp48.i = load i8** %tmp45.i ; <i8*> [#uses=1] - %tmp50.i350 = call i32 (i8*, i8*, ...)* @sprintf( i8* getelementptr ([256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; <i32> [#uses=0] + %tmp45.i = getelementptr %struct.TestObj, %struct.TestObj* %tmp1273, i32 0, i32 0 ; <i8**> [#uses=2] + %tmp48.i = load i8*, i8** %tmp45.i ; <i8*> [#uses=1] + %tmp50.i350 = call i32 (i8*, i8*, ...) @sprintf( i8* getelementptr ([256 x i8], [256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8], [48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; <i32> [#uses=0] br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i cond_true.i632.i: ; preds = %cond_true1272 ret void Ut_TraceMsg.exit648.i: ; preds = %cond_true1272 - %tmp57.i = getelementptr i8* null, i32 %tmp42.i348 ; <i8*> [#uses=0] + %tmp57.i = getelementptr i8, i8* null, i32 %tmp42.i348 ; <i8*> [#uses=0] ret void cond_next1275: ; preds = %cond_next1267 diff --git a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll index 90a3b372937e..f49c805469a0 100644 --- a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll +++ b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll @@ -17,45 +17,45 @@ entry: %retval = alloca i32, align 4 ; <i32*> [#uses=1] store i32 %i, i32* %i_addr store i32 %q, i32* %q_addr - %tmp = load i32* %i_addr ; <i32> [#uses=1] + %tmp = load i32, i32* %i_addr ; <i32> [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1] br i1 %toBool, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] br label %cond_next cond_false: ; preds = %entry - %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] br label %cond_next cond_next: ; preds = %cond_false, %cond_true - %tmp7 = load i32* %q_addr ; <i32> [#uses=1] + %tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1] br i1 %toBool10, label %cond_true11, label %cond_false15 cond_true11: ; preds = %cond_next - %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp13 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_false15: ; preds = %cond_next - %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp16 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_next18: ; preds = %cond_false15, %cond_true11 - %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp19 = call i32 (...) @bar( ) ; <i32> [#uses=0] br label %return return: ; preds = %cond_next18 - %retval20 = load i32* %retval ; <i32> [#uses=1] + %retval20 = load i32, i32* %retval ; <i32> [#uses=1] ret i32 %retval20 } diff --git a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll index 37e41ecc4b1e..421d501a2ca9 100644 --- a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll +++ b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll @@ -19,46 +19,46 @@ entry: %retval = alloca i32, align 4 ; <i32*> [#uses=1] store i32 %i, i32* %i_addr store i32 %q, i32* %q_addr - %tmp = load i32* %i_addr ; <i32> [#uses=1] + %tmp = load i32, i32* %i_addr ; <i32> [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1] br i1 %toBool, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] - %tmp7 = load i32* %q_addr ; <i32> [#uses=1] + %tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1] br i1 %toBool10, label %cond_true11, label %cond_false15 cond_false: ; preds = %entry - %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] - %tmp27 = load i32* %q_addr ; <i32> [#uses=1] + %tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp27 = load i32, i32* %q_addr ; <i32> [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1] %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1] br i1 %toBool210, label %cond_true11, label %cond_false15 cond_true11: ; preds = %cond_next - %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp13 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_false15: ; preds = %cond_next - %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp16 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_next18: ; preds = %cond_false15, %cond_true11 - %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp19 = call i32 (...) @bar( ) ; <i32> [#uses=0] br label %return return: ; preds = %cond_next18 - %retval20 = load i32* %retval ; <i32> [#uses=1] + %retval20 = load i32, i32* %retval ; <i32> [#uses=1] ret i32 %retval20 } diff --git a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll index 30ae7237395e..52cc37e24084 100644 --- a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll @@ -29,46 +29,46 @@ entry: %retval = alloca i32, align 4 ; <i32*> [#uses=1] store i32 %i, i32* %i_addr store i32 %q, i32* %q_addr - %tmp = load i32* %i_addr ; <i32> [#uses=1] + %tmp = load i32, i32* %i_addr ; <i32> [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1] br i1 %toBool, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] - %tmp7 = load i32* %q_addr ; <i32> [#uses=1] + %tmp3 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp7 = load i32, i32* %q_addr ; <i32> [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1] br i1 %toBool10, label %cond_true11, label %cond_false15 cond_false: ; preds = %entry - %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] - %tmp27 = load i32* %q_addr ; <i32> [#uses=1] + %tmp5 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp27 = load i32, i32* %q_addr ; <i32> [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1] %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1] br i1 %toBool210, label %cond_true11, label %cond_false15 cond_true11: ; preds = %cond_next - %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0] - %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp13 = call i32 (...) @foo( ) ; <i32> [#uses=0] + %tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_false15: ; preds = %cond_next - %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0] - %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + %tmp16 = call i32 (...) @bar( ) ; <i32> [#uses=0] + %tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; <i32> [#uses=0] br label %cond_next18 cond_next18: ; preds = %cond_false15, %cond_true11 - %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp19 = call i32 (...) @bar( ) ; <i32> [#uses=0] br label %return return: ; preds = %cond_next18 - %retval20 = load i32* %retval ; <i32> [#uses=1] + %retval20 = load i32, i32* %retval ; <i32> [#uses=1] ret i32 %retval20 } diff --git a/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll b/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll index 5988c65dae6c..e0b28e874b90 100644 --- a/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll +++ b/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll @@ -17,10 +17,10 @@ cond_false: ; preds = %entry bb140: ; preds = %bb140, %cond_false %indvar = phi i32 [ 0, %cond_false ], [ %indvar.next, %bb140 ] ; <i32> [#uses=2] %edge.230.0.rec = shl i32 %indvar, 1 ; <i32> [#uses=3] - %edge.230.0 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.rec ; <%struct.shape_edge_t*> [#uses=1] + %edge.230.0 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.rec ; <%struct.shape_edge_t*> [#uses=1] %edge.230.0.sum6970 = or i32 %edge.230.0.rec, 1 ; <i32> [#uses=2] - %tmp154 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.sum6970 ; <%struct.shape_edge_t*> [#uses=1] - %tmp11.i5 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0 ; <%struct.shape_edge_t**> [#uses=1] + %tmp154 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970 ; <%struct.shape_edge_t*> [#uses=1] + %tmp11.i5 = getelementptr %struct.shape_edge_t, %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0 ; <%struct.shape_edge_t**> [#uses=1] store %struct.shape_edge_t* %edge.230.0, %struct.shape_edge_t** %tmp11.i5 store %struct.shape_edge_t* %tmp154, %struct.shape_edge_t** null %tmp16254.0.rec = add i32 %edge.230.0.rec, 2 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/2007-08-15-ReuseBug.ll b/test/CodeGen/ARM/2007-08-15-ReuseBug.ll index 30b72e09a114..76b6221d0222 100644 --- a/test/CodeGen/ARM/2007-08-15-ReuseBug.ll +++ b/test/CodeGen/ARM/2007-08-15-ReuseBug.ll @@ -44,13 +44,13 @@ bb102.i: ; preds = %cond_next212.i br i1 false, label %cond_true110.i, label %cond_next123.i cond_true110.i: ; preds = %bb102.i - %tmp116.i = getelementptr i8** %argv_addr.2321.0.i, i32 2 ; <i8**> [#uses=1] - %tmp117.i = load i8** %tmp116.i ; <i8*> [#uses=1] - %tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8]* @.str44, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=0] + %tmp116.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 2 ; <i8**> [#uses=1] + %tmp117.i = load i8*, i8** %tmp116.i ; <i8*> [#uses=1] + %tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8], [2 x i8]* @.str44, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=0] ret i32 0 cond_next123.i: ; preds = %bb102.i - %tmp122.i = getelementptr i8* %tmp215.i, i32 2 ; <i8*> [#uses=0] + %tmp122.i = getelementptr i8, i8* %tmp215.i, i32 2 ; <i8*> [#uses=0] ret i32 0 bb162.i: ; preds = %cond_next212.i @@ -58,12 +58,12 @@ bb162.i: ; preds = %cond_next212.i C_addcmd.exit120.i: ; preds = %cond_next212.i %tmp3.i.i.i.i105.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1] - %tmp1.i108.i = getelementptr [100 x i8*]* @_C_cmds, i32 0, i32 0 ; <i8**> [#uses=1] + %tmp1.i108.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 0 ; <i8**> [#uses=1] store i8* %tmp3.i.i.i.i105.i, i8** %tmp1.i108.i, align 4 - %tmp.i91.i = load i32* @_C_nextcmd, align 4 ; <i32> [#uses=1] + %tmp.i91.i = load i32, i32* @_C_nextcmd, align 4 ; <i32> [#uses=1] store i32 0, i32* @_C_nextcmd, align 4 %tmp3.i.i.i.i95.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1] - %tmp1.i98.i = getelementptr [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i ; <i8**> [#uses=1] + %tmp1.i98.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i ; <i8**> [#uses=1] store i8* %tmp3.i.i.i.i95.i, i8** %tmp1.i98.i, align 4 br label %cond_next212.i @@ -77,8 +77,8 @@ cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %c %max_d.3 = phi i32 [ -1, %entry ], [ %max_d.3, %bb30.i ], [ %max_d.3, %bb21.i ], [ %max_d.3, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ] ; <i32> [#uses=7] %argv_addr.2321.0.i = phi i8** [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; <i8**> [#uses=2] %argc_addr.2358.0.i = phi i32 [ %argc, %entry ], [ %tmp205399.i, %bb30.i ], [ 0, %bb21.i ], [ 0, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ] ; <i32> [#uses=1] - %tmp214.i = getelementptr i8** %argv_addr.2321.0.i, i32 1 ; <i8**> [#uses=9] - %tmp215.i = load i8** %tmp214.i ; <i8*> [#uses=1] + %tmp214.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 1 ; <i8**> [#uses=9] + %tmp215.i = load i8*, i8** %tmp214.i ; <i8*> [#uses=1] %tmp1314.i = sext i8 0 to i32 ; <i32> [#uses=1] switch i32 %tmp1314.i, label %bb192.i [ i32 76, label %C_addcmd.exit120.i diff --git a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll index 3754db01fdd1..989410552f3f 100644 --- a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll +++ b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll @@ -10,7 +10,7 @@ define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) { entry: %opb_addr = alloca %struct.oggpack_buffer* ; <%struct.oggpack_buffer**> [#uses=1] - %tmp1 = load %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1] + %tmp1 = load %struct.oggpack_buffer*, %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1] call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind unreachable diff --git a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll index 5fbed0da5ce8..03b473a4658a 100644 --- a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll @@ -8,7 +8,7 @@ define %"struct.kc::impl_ID"* @_ZN2kc18f_typeofunpsubtermEPNS_15impl_unpsubtermEPNS_7impl_IDE(%"struct.kc::impl_Ccode_option"* %a_unpsubterm, %"struct.kc::impl_ID"* %a_operator) { entry: - %tmp8 = getelementptr %"struct.kc::impl_Ccode_option"* %a_unpsubterm, i32 0, i32 0, i32 0 ; <i32 (...)***> [#uses=0] + %tmp8 = getelementptr %"struct.kc::impl_Ccode_option", %"struct.kc::impl_Ccode_option"* %a_unpsubterm, i32 0, i32 0, i32 0 ; <i32 (...)***> [#uses=0] br i1 false, label %bb41, label %bb55 bb41: ; preds = %entry diff --git a/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll b/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll index dabe62003d9f..b0a50a49a76d 100644 --- a/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll +++ b/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll @@ -4,7 +4,7 @@ define i32 @main(i32 %argc, i8** %argv) { entry: br label %bb1 bb1: ; preds = %entry - %tmp3.i.i = load i8* null, align 1 ; <i8> [#uses=1] + %tmp3.i.i = load i8, i8* null, align 1 ; <i8> [#uses=1] %tmp4.i.i = icmp slt i8 %tmp3.i.i, 0 ; <i1> [#uses=1] br i1 %tmp4.i.i, label %bb2, label %bb3 bb2: ; preds = %bb1 diff --git a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll index 94c562bf0129..753f9e3d1331 100644 --- a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll @@ -11,9 +11,9 @@ bb74.i: ; preds = %bb88.i, %bb74.i, %entry bb88.i: ; preds = %bb74.i br i1 false, label %mandel.exit, label %bb74.i mandel.exit: ; preds = %bb88.i - %tmp2 = load volatile double* getelementptr ({ double, double }* @accum, i32 0, i32 0), align 8 ; <double> [#uses=1] + %tmp2 = load volatile double, double* getelementptr ({ double, double }, { double, double }* @accum, i32 0, i32 0), align 8 ; <double> [#uses=1] %tmp23 = fptosi double %tmp2 to i32 ; <i32> [#uses=1] - %tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; <i32> [#uses=0] + %tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll index 6b39a76d0d19..4b1aa19ef067 100644 --- a/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll @@ -46,7 +46,7 @@ bb17.i: ; preds = %cond_next119.i cond_true53.i: ; preds = %bb17.i ret { i16, %struct.rnode* }* null cond_false99.i: ; preds = %bb17.i - %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64), i64 2) to i32)) + %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i1** getelementptr (i1*, i1** null, i32 1) to i64), i64 2) to i32)) %tmp106.i = bitcast i8* %malloccall to %struct.ch_set* br i1 false, label %bb126.i, label %cond_next119.i cond_next119.i: ; preds = %cond_false99.i, %bb42 diff --git a/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll index c9a8a67ac5f9..1ededa3c3877 100644 --- a/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll @@ -24,7 +24,7 @@ define void @main(i32 %argc, i8** %argv) noreturn { entry: br i1 false, label %cond_next48, label %cond_false674 cond_next48: ; preds = %entry - %tmp61 = call %struct.FILE* @fopen( i8* null, i8* getelementptr ([2 x i8]* @.str127, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=2] + %tmp61 = call %struct.FILE* @fopen( i8* null, i8* getelementptr ([2 x i8], [2 x i8]* @.str127, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=2] br i1 false, label %bb220.i.i.i, label %bb62.preheader.i.i.i bb62.preheader.i.i.i: ; preds = %cond_next48 ret void @@ -53,11 +53,11 @@ bb177.i393.i: ; preds = %bb40.i.i bb192.i.i: ; preds = %bb177.i393.i ret void cond_false373.i.i: ; preds = %bb.i350.i - %tmp376.i.i = call i32 @strcmp( i8* null, i8* getelementptr ([9 x i8]* @.str8115, i32 0, i32 0) ) ; <i32> [#uses=0] + %tmp376.i.i = call i32 @strcmp( i8* null, i8* getelementptr ([9 x i8], [9 x i8]* @.str8115, i32 0, i32 0) ) ; <i32> [#uses=0] br i1 false, label %cond_true380.i.i, label %cond_next602.i.i cond_true380.i.i: ; preds = %cond_false373.i.i %tmp394.i418.i = add i32 %cell.0.i.i, 1 ; <i32> [#uses=1] - %tmp397.i420.i = load %struct.cellbox** null, align 4 ; <%struct.cellbox*> [#uses=1] + %tmp397.i420.i = load %struct.cellbox*, %struct.cellbox** null, align 4 ; <%struct.cellbox*> [#uses=1] br label %bb398.i.i bb398.i.i: ; preds = %bb398.i.i, %cond_true380.i.i br i1 false, label %bb414.i.i, label %bb398.i.i @@ -73,10 +73,10 @@ bb609.i.i: ; preds = %cond_next602.i.i br label %bb620.i.i bb620.i.i: ; preds = %bb620.i.i, %bb609.i.i %indvar166.i465.i = phi i32 [ %indvar.next167.i.i, %bb620.i.i ], [ 0, %bb609.i.i ] ; <i32> [#uses=1] - %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0] - %tmp648.i.i = load i32* null, align 4 ; <i32> [#uses=1] + %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0] + %tmp648.i.i = load i32, i32* null, align 4 ; <i32> [#uses=1] %tmp650.i468.i = icmp sgt i32 0, %tmp648.i.i ; <i1> [#uses=1] - %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0] + %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0] %indvar.next167.i.i = add i32 %indvar166.i465.i, 1 ; <i32> [#uses=1] br i1 %tmp650.i468.i, label %bb653.i.i.loopexit, label %bb620.i.i bb653.i.i.loopexit: ; preds = %bb620.i.i @@ -108,7 +108,7 @@ declare fastcc i32 @init_outer_loop(%struct.lame_global_flags*, double*, %struct define fastcc void @outer_loop(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) { entry: - %cod_info.182 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 1 ; <i32*> [#uses=1] + %cod_info.182 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 1 ; <i32*> [#uses=1] br label %bb bb: ; preds = %bb226, %entry %save_cod_info.1.1 = phi i32 [ undef, %entry ], [ %save_cod_info.1.1, %bb226 ] ; <i32> [#uses=2] @@ -126,7 +126,7 @@ cond_true163: ; preds = %cond_next144 bb.i53: ; preds = %cond_true163 ret void bb34.i: ; preds = %cond_true163 - %tmp37.i55 = load i32* null, align 4 ; <i32> [#uses=1] + %tmp37.i55 = load i32, i32* null, align 4 ; <i32> [#uses=1] br i1 false, label %bb65.preheader.i, label %bb78.i bb65.preheader.i: ; preds = %bb34.i br label %bb65.outer.us.i @@ -148,16 +148,16 @@ bb226.backedge.i: ; preds = %cond_next215.i, %bb151.i bb155.i: ; preds = %cond_next215.i, %bb151.i %indvar90.i = phi i32 [ %indvar.next91.i, %cond_next215.i ], [ 0, %bb151.i ] ; <i32> [#uses=2] %sfb.3.reg2mem.0.i = add i32 %indvar90.i, %tmp37.i55 ; <i32> [#uses=4] - %tmp161.i = getelementptr [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; <double*> [#uses=1] - %tmp162.i74 = load double* %tmp161.i, align 4 ; <double> [#uses=0] + %tmp161.i = getelementptr [4 x [21 x double]], [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; <double*> [#uses=1] + %tmp162.i74 = load double, double* %tmp161.i, align 4 ; <double> [#uses=0] br i1 false, label %cond_true167.i, label %cond_next215.i cond_true167.i: ; preds = %bb155.i - %tmp173.i = getelementptr %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; <i32*> [#uses=1] + %tmp173.i = getelementptr %struct.III_scalefac_t, %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; <i32*> [#uses=1] store i32 0, i32* %tmp173.i, align 4 - %tmp182.1.i = getelementptr [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; <i32*> [#uses=0] + %tmp182.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; <i32*> [#uses=0] %tmp185.i78 = add i32 %sfb.3.reg2mem.0.i, 1 ; <i32> [#uses=1] - %tmp187.1.i = getelementptr [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78 ; <i32*> [#uses=1] - %tmp188.i = load i32* %tmp187.1.i, align 4 ; <i32> [#uses=1] + %tmp187.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78 ; <i32*> [#uses=1] + %tmp188.i = load i32, i32* %tmp187.1.i, align 4 ; <i32> [#uses=1] %tmp21153.i = icmp slt i32 0, %tmp188.i ; <i1> [#uses=1] br i1 %tmp21153.i, label %bb190.preheader.i, label %cond_next215.i bb190.preheader.i: ; preds = %cond_true167.i @@ -190,9 +190,9 @@ bb231: ; preds = %bb226 define fastcc void @outer_loop2(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) { entry: - %cod_info.20128.1 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 1 ; <i32*> [#uses=1] - %cod_info.20128.2 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 2 ; <i32*> [#uses=1] - %cod_info.20128.3 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 3 ; <i32*> [#uses=1] + %cod_info.20128.1 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 1 ; <i32*> [#uses=1] + %cod_info.20128.2 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 2 ; <i32*> [#uses=1] + %cod_info.20128.3 = getelementptr %struct.gr_info, %struct.gr_info* %cod_info, i32 0, i32 20, i32 3 ; <i32*> [#uses=1] br label %bb bb: ; preds = %bb226, %entry %save_cod_info.19.1 = phi i32* [ undef, %entry ], [ %save_cod_info.19.0, %bb226 ] ; <i32*> [#uses=1] @@ -224,7 +224,7 @@ cond_next144: ; preds = %cond_next104, %bb %over.1 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1] %best_over.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1] %notdone.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1] - %tmp147 = load i32* null, align 4 ; <i32> [#uses=1] + %tmp147 = load i32, i32* null, align 4 ; <i32> [#uses=1] %tmp148 = icmp eq i32 %tmp147, 0 ; <i1> [#uses=1] %tmp153 = icmp eq i32 %over.1, 0 ; <i1> [#uses=1] %bothcond = and i1 %tmp148, %tmp153 ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll b/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll index 71aa6037a137..85ef8302a18a 100644 --- a/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll +++ b/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll @@ -21,14 +21,14 @@ entry: br i1 false, label %init_orig_buffers.exit, label %cond_true.i29 cond_true.i29: ; preds = %entry - %tmp17.i = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 20), align 8 ; <i32> [#uses=1] - %tmp20.i27 = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 16), align 8 ; <i32> [#uses=1] + %tmp17.i = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 20), align 8 ; <i32> [#uses=1] + %tmp20.i27 = load i32, i32* getelementptr (%struct.ImageParameters, %struct.ImageParameters* @images, i32 0, i32 16), align 8 ; <i32> [#uses=1] %tmp8.i.i = select i1 false, i32 1, i32 0 ; <i32> [#uses=1] br label %bb.i8.us.i bb.i8.us.i: ; preds = %get_mem2Dpel.exit.i.us.i, %cond_true.i29 %j.04.i.us.i = phi i32 [ %indvar.next39.i, %get_mem2Dpel.exit.i.us.i ], [ 0, %cond_true.i29 ] ; <i32> [#uses=2] - %tmp13.i.us.i = getelementptr i16*** null, i32 %j.04.i.us.i ; <i16***> [#uses=0] + %tmp13.i.us.i = getelementptr i16**, i16*** null, i32 %j.04.i.us.i ; <i16***> [#uses=0] %tmp15.i.i.us.i = tail call i8* @calloc( i32 0, i32 2 ) ; <i8*> [#uses=0] store i16* null, i16** null, align 4 br label %bb.i.i.us.i diff --git a/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll b/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll index aa61d86e1389..3d69e4fefbc2 100644 --- a/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll @@ -9,7 +9,7 @@ declare fastcc i32 @get_mem2Dint(i32***, i32, i32) define fastcc void @init_global_buffers() nounwind { entry: - %tmp151 = tail call fastcc i32 @get_mem2Dint( i32*** getelementptr (%struct.Decoders* @decoders, i32 0, i32 0), i32 16, i32 16 ) ; <i32> [#uses=1] + %tmp151 = tail call fastcc i32 @get_mem2Dint( i32*** getelementptr (%struct.Decoders, %struct.Decoders* @decoders, i32 0, i32 0), i32 16, i32 16 ) ; <i32> [#uses=1] %tmp158 = tail call i8* @calloc( i32 0, i32 4 ) ; <i8*> [#uses=0] br i1 false, label %cond_true166, label %bb190.preheader diff --git a/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll b/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll index e86bc1ba5ccc..cf98d7f91df0 100644 --- a/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll +++ b/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll @@ -4,6 +4,6 @@ define void @main({ i32 }*) { entry: %sret1 = alloca { i32 } ; <{ i32 }*> [#uses=1] - load { i32 }* %sret1 ; <{ i32 }>:1 [#uses=0] + load { i32 }, { i32 }* %sret1 ; <{ i32 }>:1 [#uses=0] ret void } diff --git a/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll b/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll index adb011277604..dfbbeb9968c4 100644 --- a/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll +++ b/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll @@ -8,6 +8,6 @@ define i32 @__gcov_close() nounwind { entry: - load i32* getelementptr (%struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4 ; <i32>:0 [#uses=1] + load i32, i32* getelementptr (%struct.__gcov_var, %struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4 ; <i32>:0 [#uses=1] ret i32 %0 } diff --git a/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll index 4c0c59ccfbc6..cad5440bddc9 100644 --- a/test/CodeGen/ARM/2009-02-16-SpillerBug.ll +++ b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll @@ -81,13 +81,13 @@ bb244: ; preds = %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122 br i1 %0, label %bb435, label %bb433 bb394: ; preds = %bb122 - call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 3, i8* getelementptr ([23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 3, i8* getelementptr ([23 x i8], [23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind br label %bb396 bb396: ; preds = %bb394, %bb131, %bb122, %bb122, %bb122, %bb122, %RESUME %stop_link.3 = phi %struct.rec* [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ] ; <%struct.rec*> [#uses=7] %headers_seen.1 = phi i32 [ 0, %RESUME ], [ %headers_seen.1, %bb394 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ %headers_seen.1, %bb131 ] ; <i32> [#uses=2] - %link.1 = load %struct.rec** null ; <%struct.rec*> [#uses=2] + %link.1 = load %struct.rec*, %struct.rec** null ; <%struct.rec*> [#uses=2] %1 = icmp eq %struct.rec* %link.1, %hd ; <i1> [#uses=1] br i1 %1, label %bb398, label %bb122 diff --git a/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll b/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll index a48f0033acc8..a14589fa47d8 100644 --- a/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll +++ b/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll @@ -15,6 +15,6 @@ entry: br label %return return: ; preds = %entry - %2 = load i32* %retval ; <i32> [#uses=1] + %2 = load i32, i32* %retval ; <i32> [#uses=1] ret i32 %2 } diff --git a/test/CodeGen/ARM/2009-02-27-SpillerBug.ll b/test/CodeGen/ARM/2009-02-27-SpillerBug.ll index bc5e6023409f..d9ec4d28c5d7 100644 --- a/test/CodeGen/ARM/2009-02-27-SpillerBug.ll +++ b/test/CodeGen/ARM/2009-02-27-SpillerBug.ll @@ -28,12 +28,12 @@ bb53: ; preds = %bb52 br i1 %phitmp, label %bb55, label %bb52 bb55: ; preds = %bb53 - %4 = load double* @a, align 4 ; <double> [#uses=10] + %4 = load double, double* @a, align 4 ; <double> [#uses=10] %5 = fadd double %4, 0.000000e+00 ; <double> [#uses=16] %6 = fcmp ogt double %k.4, 0.000000e+00 ; <i1> [#uses=1] %.pn404 = fmul double %4, %4 ; <double> [#uses=4] %.pn402 = fmul double %5, %5 ; <double> [#uses=5] - %.pn165.in = load double* @N ; <double> [#uses=5] + %.pn165.in = load double, double* @N ; <double> [#uses=5] %.pn198 = fmul double 0.000000e+00, %5 ; <double> [#uses=1] %.pn185 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=1] %.pn147 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=1] diff --git a/test/CodeGen/ARM/2009-03-07-SpillerBug.ll b/test/CodeGen/ARM/2009-03-07-SpillerBug.ll index 377bbd211752..567400318ee0 100644 --- a/test/CodeGen/ARM/2009-03-07-SpillerBug.ll +++ b/test/CodeGen/ARM/2009-03-07-SpillerBug.ll @@ -42,7 +42,7 @@ bb3: ; preds = %entry %17 = fdiv double %16, %0 %18 = fadd double 0.000000e+00, %17 %19 = call double @acos(double %18) nounwind readonly - %20 = load double* null, align 4 + %20 = load double, double* null, align 4 %21 = fmul double %20, 0x401921FB54442D18 %22 = call double @sin(double %19) nounwind readonly %23 = fmul double %22, 0.000000e+00 diff --git a/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll b/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll index 7bb1429872b9..a9d5480e72c9 100644 --- a/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll +++ b/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll @@ -6,7 +6,7 @@ define fastcc %struct.node_t* @_ZL6createP6node_tii3v_tS1_d(%struct.node_t* %n, i32 %lvl, i32 %dist, i64 %c.0.0, i64 %c.0.1, i64 %c.0.2, i64 %d.0.0, i64 %d.0.1, i64 %d.0.2, double %r) nounwind { entry: - %0 = getelementptr %struct.node_t* %n, i32 0, i32 1 ; <%struct.hit_t*> [#uses=1] + %0 = getelementptr %struct.node_t, %struct.node_t* %n, i32 0, i32 1 ; <%struct.hit_t*> [#uses=1] %1 = bitcast %struct.hit_t* %0 to i256* ; <i256*> [#uses=1] store i256 0, i256* %1, align 4 unreachable diff --git a/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/test/CodeGen/ARM/2009-04-06-AsmModifier.ll index e90c5b322db7..bc7dbd4f6953 100644 --- a/test/CodeGen/ARM/2009-04-06-AsmModifier.ll +++ b/test/CodeGen/ARM/2009-04-06-AsmModifier.ll @@ -8,14 +8,14 @@ entry: store i32 0, i32* %retval %res = alloca i32 ; <i32*> [#uses=0] %fh = alloca i32 ; <i32*> [#uses=1] - %1 = load i32* %fh ; <i32> [#uses=1] - %2 = load i32* %ptr ; <i32> [#uses=1] + %1 = load i32, i32* %fh ; <i32> [#uses=1] + %2 = load i32, i32* %ptr ; <i32> [#uses=1] %3 = call i32 asm "mov r0, $2; mov r1, $3; swi ${1:a}; mov $0, r0", "=r,i,r,r,~{r0},~{r1}"(i32 107, i32 %1, i32 %2) nounwind ; <i32> [#uses=1] store i32 %3, i32* %retval br label %return return: ; preds = %entry - %4 = load i32* %retval ; <i32> [#uses=1] + %4 = load i32, i32* %retval ; <i32> [#uses=1] ret i32 %4 } diff --git a/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll b/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll index ade6a10afef6..edeae9b88bce 100644 --- a/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll +++ b/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll @@ -8,11 +8,11 @@ entry: %b = alloca { double, double } ; <{ double, double }*> [#uses=1] store { i32, { double, double }* } %d_arg, { i32, { double, double }* }* %d store i32 %x_arg, i32* %x - %tmp = load i32* %x ; <i32> [#uses=1] - %tmp1 = getelementptr { i32, { double, double }* }* %d, i32 0, i32 1 ; <{ double, double }**> [#uses=1] - %.ptr = load { double, double }** %tmp1 ; <{ double, double }*> [#uses=1] - %tmp2 = getelementptr { double, double }* %.ptr, i32 %tmp ; <{ double, double }*> [#uses=1] - %tmp3 = load { double, double }* %tmp2 ; <{ double, double }> [#uses=1] + %tmp = load i32, i32* %x ; <i32> [#uses=1] + %tmp1 = getelementptr { i32, { double, double }* }, { i32, { double, double }* }* %d, i32 0, i32 1 ; <{ double, double }**> [#uses=1] + %.ptr = load { double, double }*, { double, double }** %tmp1 ; <{ double, double }*> [#uses=1] + %tmp2 = getelementptr { double, double }, { double, double }* %.ptr, i32 %tmp ; <{ double, double }*> [#uses=1] + %tmp3 = load { double, double }, { double, double }* %tmp2 ; <{ double, double }> [#uses=1] store { double, double } %tmp3, { double, double }* %b ret void } diff --git a/test/CodeGen/ARM/2009-04-08-FREM.ll b/test/CodeGen/ARM/2009-04-08-FREM.ll index 606c6b1471b4..e0f9485888d9 100644 --- a/test/CodeGen/ARM/2009-04-08-FREM.ll +++ b/test/CodeGen/ARM/2009-04-08-FREM.ll @@ -4,6 +4,6 @@ declare i32 @printf(i8*, ...) define i32 @main() { %rem_r = frem double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1] - %1 = call i32 (i8*, ...)* @printf(i8* null, double %rem_r) ; <i32> [#uses=0] + %1 = call i32 (i8*, ...) @printf(i8* null, double %rem_r) ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/2009-04-08-FloatUndef.ll b/test/CodeGen/ARM/2009-04-08-FloatUndef.ll index 9e32e05b040b..949e1072b2b6 100644 --- a/test/CodeGen/ARM/2009-04-08-FloatUndef.ll +++ b/test/CodeGen/ARM/2009-04-08-FloatUndef.ll @@ -2,7 +2,7 @@ define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) { entry: - %input2 = load <4 x float>* null, align 16 ; <<4 x float>> [#uses=2] + %input2 = load <4 x float>, <4 x float>* null, align 16 ; <<4 x float>> [#uses=2] %shuffle7 = shufflevector <4 x float> %input2, <4 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <4 x i32> <i32 2, i32 2, i32 2, i32 2> ; <<4 x float>> [#uses=1] %mul1 = fmul <4 x float> %shuffle7, zeroinitializer ; <<4 x float>> [#uses=1] %add2 = fadd <4 x float> %mul1, %input2 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll b/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll index 5b1746301f4e..f2532d798f83 100644 --- a/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll +++ b/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll @@ -4,7 +4,7 @@ define void @foo(...) nounwind { entry: %rr = alloca i32 ; <i32*> [#uses=2] - %0 = load i32* %rr ; <i32> [#uses=1] + %0 = load i32, i32* %rr ; <i32> [#uses=1] %1 = call i32 asm "nop", "=r,0"(i32 %0) nounwind ; <i32> [#uses=1] store i32 %1, i32* %rr br label %return diff --git a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll index 524b5ebddc0a..ac641f99dbf9 100644 --- a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll @@ -5,7 +5,7 @@ define i16 @fn16(i16 %arg0.0, <2 x i16> %arg1, i16 %arg2.0) nounwind { entry: store <2 x i16> %arg1, <2 x i16>* null - %0 = call i32 (i8*, ...)* @printf(i8* getelementptr ([30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind ; <i32> [#uses=0] + %0 = call i32 (i8*, ...) @printf(i8* getelementptr ([30 x i8], [30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind ; <i32> [#uses=0] ret i16 0 } diff --git a/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll index 2bc7df028534..ae005dbf4b13 100644 --- a/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll +++ b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll @@ -19,8 +19,8 @@ bb1: ; preds = %bb bb3: ; preds = %bb1, %bb %iftmp.0.0 = phi i32 [ 0, %bb1 ], [ -1, %bb ] ; <i32> [#uses=1] - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; <i32> [#uses=0] - %2 = load %struct.List** null, align 4 ; <%struct.List*> [#uses=2] + %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; <i32> [#uses=0] + %2 = load %struct.List*, %struct.List** null, align 4 ; <%struct.List*> [#uses=2] %phitmp = icmp eq %struct.List* %2, null ; <i1> [#uses=1] br i1 %phitmp, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll index 403e3f6509f3..7bbb8090c849 100644 --- a/test/CodeGen/ARM/2009-06-02-ISelCrash.ll +++ b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll @@ -57,6 +57,6 @@ Fft.exit.i: ; preds = %bb7.i.i br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer bb5.i: ; preds = %Fft.exit.i - %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; <i32> [#uses=0] + %0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([15 x i8], [15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; <i32> [#uses=0] unreachable } diff --git a/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll index 98e002302558..17beb3c25947 100644 --- a/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll +++ b/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll @@ -136,7 +136,7 @@ bb138: ; preds = %bb77 br label %bb141 bb139: ; preds = %bb141 - %scevgep441442881 = load i16* undef ; <i16> [#uses=1] + %scevgep441442881 = load i16, i16* undef ; <i16> [#uses=1] %1 = icmp ugt i16 %scevgep441442881, %0 ; <i1> [#uses=1] br i1 %1, label %bb141, label %bb142 diff --git a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll index 7e9b066984f9..4ab54c2e8faf 100644 --- a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -5,9 +5,9 @@ define void @simplify_unary_real(i8* nocapture %p) nounwind { entry: - %tmp121 = load i64* null, align 4 ; <i64> [#uses=1] - %0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1] - %tmp122 = load i64* %0, align 4 ; <i64> [#uses=1] + %tmp121 = load i64, i64* null, align 4 ; <i64> [#uses=1] + %0 = getelementptr %struct.rtx_def, %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1] + %tmp122 = load i64, i64* %0, align 4 ; <i64> [#uses=1] %1 = zext i64 undef to i192 ; <i192> [#uses=2] %2 = zext i64 %tmp121 to i192 ; <i192> [#uses=1] %3 = shl i192 %2, 64 ; <i192> [#uses=2] diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll index 812f0188f19a..e9c4b0335dc0 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -35,26 +35,26 @@ bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - %0 = load i32* undef, align 4 ; <i32> [#uses=2] + %0 = load i32, i32* undef, align 4 ; <i32> [#uses=2] %1 = add i32 %0, 1 ; <i32> [#uses=2] store i32 %1, i32* undef, align 4 - %2 = load i32* undef, align 4 ; <i32> [#uses=1] + %2 = load i32, i32* undef, align 4 ; <i32> [#uses=1] store i32 %2, i32* @nn, align 4 store i32 0, i32* @al_len, align 4 store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 - %3 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] + %3 = getelementptr i8, i8* %B, i32 %0 ; <i8*> [#uses=1] tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind %4 = sitofp i32 undef to double ; <double> [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1] - %6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] - %7 = load i32* @al_len, align 4 ; <i32> [#uses=1] - %8 = load i32* @no_mat, align 4 ; <i32> [#uses=1] - %9 = load i32* @no_mis, align 4 ; <i32> [#uses=1] + %6 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([29 x i8], [29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] + %7 = load i32, i32* @al_len, align 4 ; <i32> [#uses=1] + %8 = load i32, i32* @no_mat, align 4 ; <i32> [#uses=1] + %9 = load i32, i32* @no_mis, align 4 ; <i32> [#uses=1] %10 = sub i32 %7, %8 ; <i32> [#uses=1] %11 = sub i32 %10, %9 ; <i32> [#uses=1] - %12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] - %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] + %12 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] + %13 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll index f5fb97c0ef53..08291e62b65e 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -33,19 +33,19 @@ bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - %0 = load i32* undef, align 4 ; <i32> [#uses=3] + %0 = load i32, i32* undef, align 4 ; <i32> [#uses=3] %1 = add i32 %0, 1 ; <i32> [#uses=2] store i32 %1, i32* undef, align 4 - %2 = load i32* undef, align 4 ; <i32> [#uses=2] + %2 = load i32, i32* undef, align 4 ; <i32> [#uses=2] %3 = sub i32 %2, %0 ; <i32> [#uses=1] store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 - %4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] + %4 = getelementptr i8, i8* %B, i32 %0 ; <i8*> [#uses=1] tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind - %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] - %6 = load i32* @no_mis, align 4 ; <i32> [#uses=1] - %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] - %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] + %5 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] + %6 = load i32, i32* @no_mis, align 4 ; <i32> [#uses=1] + %7 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] + %8 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll index d7e4c90abb18..cf7325ddf895 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -28,7 +28,7 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32** @JJ, align 4 ; <i32*> [#uses=1] + %0 = load i32*, i32** @JJ, align 4 ; <i32*> [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -84,10 +84,10 @@ bb167.i: ; preds = %bb163.i bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ] ; <i32> [#uses=1] %fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] - %scevgep88.i = getelementptr i32* null, i32 %i.121.i ; <i32*> [#uses=3] - %4 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=2] - %scevgep89.i = getelementptr i32* %0, i32 %i.121.i ; <i32*> [#uses=3] - %5 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1] + %scevgep88.i = getelementptr i32, i32* null, i32 %i.121.i ; <i32*> [#uses=3] + %4 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=2] + %scevgep89.i = getelementptr i32, i32* %0, i32 %i.121.i ; <i32*> [#uses=3] + %5 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i ; <i32> [#uses=0] %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0] %6 = icmp slt i32 undef, 0 ; <i1> [#uses=3] @@ -95,8 +95,8 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; <i32> [#uses=1] %c.14.i = select i1 %6, i32 0, i32 undef ; <i32> [#uses=2] store i32 %c.14.i, i32* undef, align 4 - %7 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1] - %8 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1] + %7 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1] + %8 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1] store i32 %ci.12.i, i32* %scevgep88.i, align 4 store i32 %cj.11.i100, i32* %scevgep89.i, align 4 store i32 %4, i32* undef, align 4 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll index 77c133a80f95..203608ac1d40 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -22,7 +22,7 @@ bb6: ; preds = %bb6, %bb5 br i1 undef, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 - %0 = load i8** @name1, align 4 ; <i8*> [#uses=0] + %0 = load i8*, i8** @name1, align 4 ; <i8*> [#uses=0] br label %bb15 bb9: ; preds = %bb15 @@ -33,15 +33,15 @@ bb10: ; preds = %bb9 bb11: ; preds = %bb9 store i32 0, i32* @no_mis, align 4 - %1 = getelementptr i8* %A, i32 0 ; <i8*> [#uses=1] - %2 = getelementptr i8* %B, i32 0 ; <i8*> [#uses=1] + %1 = getelementptr i8, i8* %A, i32 0 ; <i8*> [#uses=1] + %2 = getelementptr i8, i8* %B, i32 0 ; <i8*> [#uses=1] tail call void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %3 = load i32** @II, align 4 ; <i32*> [#uses=1] - %4 = load i32* @r, align 4 ; <i32> [#uses=1] - %5 = load i32* @qr, align 4 ; <i32> [#uses=1] + %3 = load i32*, i32** @II, align 4 ; <i32*> [#uses=1] + %4 = load i32, i32* @r, align 4 ; <i32> [#uses=1] + %5 = load i32, i32* @qr, align 4 ; <i32> [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -95,12 +95,12 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2] %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] %f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; <i32> [#uses=2] - %scevgep88.i = getelementptr i32* %3, i32 undef ; <i32*> [#uses=1] + %scevgep88.i = getelementptr i32, i32* %3, i32 undef ; <i32*> [#uses=1] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0] %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=1] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] - %10 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1] + %10 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1] br i1 undef, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i @@ -110,7 +110,7 @@ bb218.i: ; preds = %bb211.i, %bb168.i br i1 undef, label %bb220.i, label %bb158.i bb220.i: ; preds = %bb218.i, %bb153.i - %11 = getelementptr i32* null, i32 %6 ; <i32*> [#uses=1] + %11 = getelementptr i32, i32* null, i32 %6 ; <i32*> [#uses=1] store i32 undef, i32* %11, align 4 br i1 undef, label %bb221.i, label %bb228.i diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll index 16f5d1dc150f..b3c91ed3fb0d 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -28,7 +28,7 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32** @XX, align 4 ; <i32*> [#uses=0] + %0 = load i32*, i32** @XX, align 4 ; <i32*> [#uses=0] br label %bb228.i bb74.i: ; preds = %bb228.i diff --git a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll index f0d79ce25c97..55039dd7f57b 100644 --- a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -30,9 +30,9 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32** @II, align 4 ; <i32*> [#uses=1] - %1 = load i32** @JJ, align 4 ; <i32*> [#uses=1] - %2 = load i32* @qr, align 4 ; <i32> [#uses=1] + %0 = load i32*, i32** @II, align 4 ; <i32*> [#uses=1] + %1 = load i32*, i32** @JJ, align 4 ; <i32*> [#uses=1] + %2 = load i32, i32* @qr, align 4 ; <i32> [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -90,15 +90,15 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2] %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] %f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; <i32> [#uses=2] - %scevgep88.i = getelementptr i32* %0, i32 undef ; <i32*> [#uses=2] - %scevgep89.i = getelementptr i32* %1, i32 undef ; <i32*> [#uses=2] + %scevgep88.i = getelementptr i32, i32* %0, i32 undef ; <i32*> [#uses=2] + %scevgep89.i = getelementptr i32, i32* %1, i32 undef ; <i32*> [#uses=2] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0] %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0] %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=2] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=2] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] - %6 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1] - %7 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1] + %6 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1] + %7 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1] store i32 %ci.12.i, i32* %scevgep88.i, align 4 store i32 %cj.11.i100, i32* %scevgep89.i, align 4 br i1 undef, label %bb211.i, label %bb218.i diff --git a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll index 454fee5c5ae1..2146dd330822 100644 --- a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll +++ b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll @@ -16,43 +16,43 @@ entry: br i1 %0, label %bb8, label %bb bb: ; preds = %entry - %1 = getelementptr %struct.VERTEX* %tree, i32 0, i32 2 ; <%struct.VERTEX**> [#uses=1] - %2 = load %struct.VERTEX** %1, align 4 ; <%struct.VERTEX*> [#uses=2] + %1 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 2 ; <%struct.VERTEX**> [#uses=1] + %2 = load %struct.VERTEX*, %struct.VERTEX** %1, align 4 ; <%struct.VERTEX*> [#uses=2] %3 = icmp eq %struct.VERTEX* %2, null ; <i1> [#uses=1] br i1 %3, label %bb7, label %bb1.i bb1.i: ; preds = %bb1.i, %bb %tree_addr.0.i = phi %struct.VERTEX* [ %5, %bb1.i ], [ %tree, %bb ] ; <%struct.VERTEX*> [#uses=3] - %4 = getelementptr %struct.VERTEX* %tree_addr.0.i, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] - %5 = load %struct.VERTEX** %4, align 4 ; <%struct.VERTEX*> [#uses=2] + %4 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree_addr.0.i, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] + %5 = load %struct.VERTEX*, %struct.VERTEX** %4, align 4 ; <%struct.VERTEX*> [#uses=2] %6 = icmp eq %struct.VERTEX* %5, null ; <i1> [#uses=1] br i1 %6, label %get_low.exit, label %bb1.i get_low.exit: ; preds = %bb1.i call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind - %7 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] - %8 = load %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] + %7 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] + %8 = load %struct.VERTEX*, %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind - %9 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] - %10 = load %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] - %11 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %12 = load %struct.edge_rec** %11, align 4 ; <%struct.edge_rec*> [#uses=1] - %13 = getelementptr %struct.EDGE_PAIR* %delright, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] - %14 = load %struct.edge_rec** %13, align 8 ; <%struct.edge_rec*> [#uses=1] - %15 = getelementptr %struct.EDGE_PAIR* %delright, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %16 = load %struct.edge_rec** %15, align 4 ; <%struct.edge_rec*> [#uses=2] + %9 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] + %10 = load %struct.edge_rec*, %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] + %11 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %12 = load %struct.edge_rec*, %struct.edge_rec** %11, align 4 ; <%struct.edge_rec*> [#uses=1] + %13 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delright, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] + %14 = load %struct.edge_rec*, %struct.edge_rec** %13, align 8 ; <%struct.edge_rec*> [#uses=1] + %15 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delright, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %16 = load %struct.edge_rec*, %struct.edge_rec** %15, align 4 ; <%struct.edge_rec*> [#uses=2] br label %bb.i bb.i: ; preds = %bb4.i, %get_low.exit %rdi_addr.0.i = phi %struct.edge_rec* [ %14, %get_low.exit ], [ %72, %bb4.i ] ; <%struct.edge_rec*> [#uses=2] %ldi_addr.1.i = phi %struct.edge_rec* [ %12, %get_low.exit ], [ %ldi_addr.0.i, %bb4.i ] ; <%struct.edge_rec*> [#uses=3] - %17 = getelementptr %struct.edge_rec* %rdi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %18 = load %struct.VERTEX** %17, align 4 ; <%struct.VERTEX*> [#uses=3] + %17 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %18 = load %struct.VERTEX*, %struct.VERTEX** %17, align 4 ; <%struct.VERTEX*> [#uses=3] %19 = ptrtoint %struct.edge_rec* %ldi_addr.1.i to i32 ; <i32> [#uses=1] - %20 = getelementptr %struct.VERTEX* %18, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %21 = load double* %20, align 4 ; <double> [#uses=3] - %22 = getelementptr %struct.VERTEX* %18, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %23 = load double* %22, align 4 ; <double> [#uses=3] + %20 = getelementptr %struct.VERTEX, %struct.VERTEX* %18, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %21 = load double, double* %20, align 4 ; <double> [#uses=3] + %22 = getelementptr %struct.VERTEX, %struct.VERTEX* %18, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %23 = load double, double* %22, align 4 ; <double> [#uses=3] br label %bb2.i bb1.i1: ; preds = %bb2.i @@ -62,8 +62,8 @@ bb1.i1: ; preds = %bb2.i %27 = and i32 %24, -64 ; <i32> [#uses=1] %28 = or i32 %26, %27 ; <i32> [#uses=1] %29 = inttoptr i32 %28 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %30 = getelementptr %struct.edge_rec* %29, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %31 = load %struct.edge_rec** %30, align 4 ; <%struct.edge_rec*> [#uses=1] + %30 = getelementptr %struct.edge_rec, %struct.edge_rec* %29, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %31 = load %struct.edge_rec*, %struct.edge_rec** %30, align 4 ; <%struct.edge_rec*> [#uses=1] %32 = ptrtoint %struct.edge_rec* %31 to i32 ; <i32> [#uses=2] %33 = add i32 %32, 16 ; <i32> [#uses=1] %34 = and i32 %33, 63 ; <i32> [#uses=1] @@ -78,18 +78,18 @@ bb2.i: ; preds = %bb1.i1, %bb.i %ldi_addr.0.i = phi %struct.edge_rec* [ %ldi_addr.1.i, %bb.i ], [ %37, %bb1.i1 ] ; <%struct.edge_rec*> [#uses=4] %.pn6.in.i = xor i32 %.pn6.in.in.i, 32 ; <i32> [#uses=1] %.pn6.i = inttoptr i32 %.pn6.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %t1.0.in.i = getelementptr %struct.edge_rec* %ldi_addr.1.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %t2.0.in.i = getelementptr %struct.edge_rec* %.pn6.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %t1.0.i = load %struct.VERTEX** %t1.0.in.i ; <%struct.VERTEX*> [#uses=2] - %t2.0.i = load %struct.VERTEX** %t2.0.in.i ; <%struct.VERTEX*> [#uses=2] - %38 = getelementptr %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %39 = load double* %38, align 4 ; <double> [#uses=3] - %40 = getelementptr %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %41 = load double* %40, align 4 ; <double> [#uses=3] - %42 = getelementptr %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %43 = load double* %42, align 4 ; <double> [#uses=1] - %44 = getelementptr %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %45 = load double* %44, align 4 ; <double> [#uses=1] + %t1.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.1.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %t2.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn6.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %t1.0.i = load %struct.VERTEX*, %struct.VERTEX** %t1.0.in.i ; <%struct.VERTEX*> [#uses=2] + %t2.0.i = load %struct.VERTEX*, %struct.VERTEX** %t2.0.in.i ; <%struct.VERTEX*> [#uses=2] + %38 = getelementptr %struct.VERTEX, %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %39 = load double, double* %38, align 4 ; <double> [#uses=3] + %40 = getelementptr %struct.VERTEX, %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %41 = load double, double* %40, align 4 ; <double> [#uses=3] + %42 = getelementptr %struct.VERTEX, %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %43 = load double, double* %42, align 4 ; <double> [#uses=1] + %44 = getelementptr %struct.VERTEX, %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %45 = load double, double* %44, align 4 ; <double> [#uses=1] %46 = fsub double %39, %21 ; <double> [#uses=1] %47 = fsub double %45, %23 ; <double> [#uses=1] %48 = fmul double %46, %47 ; <double> [#uses=1] @@ -104,12 +104,12 @@ bb3.i: ; preds = %bb2.i %54 = ptrtoint %struct.edge_rec* %rdi_addr.0.i to i32 ; <i32> [#uses=1] %55 = xor i32 %54, 32 ; <i32> [#uses=3] %56 = inttoptr i32 %55 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %57 = getelementptr %struct.edge_rec* %56, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %58 = load %struct.VERTEX** %57, align 4 ; <%struct.VERTEX*> [#uses=2] - %59 = getelementptr %struct.VERTEX* %58, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %60 = load double* %59, align 4 ; <double> [#uses=1] - %61 = getelementptr %struct.VERTEX* %58, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %62 = load double* %61, align 4 ; <double> [#uses=1] + %57 = getelementptr %struct.edge_rec, %struct.edge_rec* %56, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %58 = load %struct.VERTEX*, %struct.VERTEX** %57, align 4 ; <%struct.VERTEX*> [#uses=2] + %59 = getelementptr %struct.VERTEX, %struct.VERTEX* %58, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %60 = load double, double* %59, align 4 ; <double> [#uses=1] + %61 = getelementptr %struct.VERTEX, %struct.VERTEX* %58, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %62 = load double, double* %61, align 4 ; <double> [#uses=1] %63 = fsub double %60, %39 ; <double> [#uses=1] %64 = fsub double %23, %41 ; <double> [#uses=1] %65 = fmul double %63, %64 ; <double> [#uses=1] @@ -121,8 +121,8 @@ bb3.i: ; preds = %bb2.i br i1 %70, label %bb4.i, label %bb5.i bb4.i: ; preds = %bb3.i - %71 = getelementptr %struct.edge_rec* %56, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %72 = load %struct.edge_rec** %71, align 4 ; <%struct.edge_rec*> [#uses=1] + %71 = getelementptr %struct.edge_rec, %struct.edge_rec* %56, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %72 = load %struct.edge_rec*, %struct.edge_rec** %71, align 4 ; <%struct.edge_rec*> [#uses=1] br label %bb.i bb5.i: ; preds = %bb3.i @@ -131,110 +131,110 @@ bb5.i: ; preds = %bb3.i %75 = and i32 %55, -64 ; <i32> [#uses=1] %76 = or i32 %74, %75 ; <i32> [#uses=1] %77 = inttoptr i32 %76 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %78 = getelementptr %struct.edge_rec* %77, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %79 = load %struct.edge_rec** %78, align 4 ; <%struct.edge_rec*> [#uses=1] + %78 = getelementptr %struct.edge_rec, %struct.edge_rec* %77, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %79 = load %struct.edge_rec*, %struct.edge_rec** %78, align 4 ; <%struct.edge_rec*> [#uses=1] %80 = ptrtoint %struct.edge_rec* %79 to i32 ; <i32> [#uses=2] %81 = add i32 %80, 16 ; <i32> [#uses=1] %82 = and i32 %81, 63 ; <i32> [#uses=1] %83 = and i32 %80, -64 ; <i32> [#uses=1] %84 = or i32 %82, %83 ; <i32> [#uses=1] %85 = inttoptr i32 %84 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %86 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %87 = load %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] + %86 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %87 = load %struct.VERTEX*, %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] %88 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] - %89 = getelementptr %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] + %89 = getelementptr %struct.edge_rec, %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4 - %90 = getelementptr %struct.edge_rec* %88, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=2] + %90 = getelementptr %struct.edge_rec, %struct.edge_rec* %88, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=2] store %struct.VERTEX* %18, %struct.VERTEX** %90, align 4 %91 = ptrtoint %struct.edge_rec* %88 to i32 ; <i32> [#uses=5] %92 = add i32 %91, 16 ; <i32> [#uses=2] %93 = inttoptr i32 %92 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %94 = add i32 %91, 48 ; <i32> [#uses=1] %95 = inttoptr i32 %94 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %96 = getelementptr %struct.edge_rec* %93, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %96 = getelementptr %struct.edge_rec, %struct.edge_rec* %93, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %95, %struct.edge_rec** %96, align 4 %97 = add i32 %91, 32 ; <i32> [#uses=1] %98 = inttoptr i32 %97 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %99 = getelementptr %struct.edge_rec* %98, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %99 = getelementptr %struct.edge_rec, %struct.edge_rec* %98, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %98, %struct.edge_rec** %99, align 4 - %100 = getelementptr %struct.edge_rec* %98, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %100 = getelementptr %struct.edge_rec, %struct.edge_rec* %98, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %87, %struct.VERTEX** %100, align 4 - %101 = getelementptr %struct.edge_rec* %95, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %101 = getelementptr %struct.edge_rec, %struct.edge_rec* %95, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %93, %struct.edge_rec** %101, align 4 - %102 = load %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] + %102 = load %struct.edge_rec*, %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] %103 = ptrtoint %struct.edge_rec* %102 to i32 ; <i32> [#uses=2] %104 = add i32 %103, 16 ; <i32> [#uses=1] %105 = and i32 %104, 63 ; <i32> [#uses=1] %106 = and i32 %103, -64 ; <i32> [#uses=1] %107 = or i32 %105, %106 ; <i32> [#uses=1] %108 = inttoptr i32 %107 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %109 = getelementptr %struct.edge_rec* %85, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %110 = load %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] + %109 = getelementptr %struct.edge_rec, %struct.edge_rec* %85, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %110 = load %struct.edge_rec*, %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] %111 = ptrtoint %struct.edge_rec* %110 to i32 ; <i32> [#uses=2] %112 = add i32 %111, 16 ; <i32> [#uses=1] %113 = and i32 %112, 63 ; <i32> [#uses=1] %114 = and i32 %111, -64 ; <i32> [#uses=1] %115 = or i32 %113, %114 ; <i32> [#uses=1] %116 = inttoptr i32 %115 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %117 = getelementptr %struct.edge_rec* %116, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %118 = load %struct.edge_rec** %117, align 4 ; <%struct.edge_rec*> [#uses=1] - %119 = getelementptr %struct.edge_rec* %108, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %120 = load %struct.edge_rec** %119, align 4 ; <%struct.edge_rec*> [#uses=1] + %117 = getelementptr %struct.edge_rec, %struct.edge_rec* %116, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %118 = load %struct.edge_rec*, %struct.edge_rec** %117, align 4 ; <%struct.edge_rec*> [#uses=1] + %119 = getelementptr %struct.edge_rec, %struct.edge_rec* %108, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %120 = load %struct.edge_rec*, %struct.edge_rec** %119, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %118, %struct.edge_rec** %119, align 4 store %struct.edge_rec* %120, %struct.edge_rec** %117, align 4 - %121 = load %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] - %122 = load %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] + %121 = load %struct.edge_rec*, %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] + %122 = load %struct.edge_rec*, %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %121, %struct.edge_rec** %109, align 4 store %struct.edge_rec* %122, %struct.edge_rec** %89, align 4 %123 = xor i32 %91, 32 ; <i32> [#uses=1] %124 = inttoptr i32 %123 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %125 = getelementptr %struct.edge_rec* %124, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %126 = load %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] + %125 = getelementptr %struct.edge_rec, %struct.edge_rec* %124, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %126 = load %struct.edge_rec*, %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] %127 = ptrtoint %struct.edge_rec* %126 to i32 ; <i32> [#uses=2] %128 = add i32 %127, 16 ; <i32> [#uses=1] %129 = and i32 %128, 63 ; <i32> [#uses=1] %130 = and i32 %127, -64 ; <i32> [#uses=1] %131 = or i32 %129, %130 ; <i32> [#uses=1] %132 = inttoptr i32 %131 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %133 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %134 = load %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=1] + %133 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %134 = load %struct.edge_rec*, %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=1] %135 = ptrtoint %struct.edge_rec* %134 to i32 ; <i32> [#uses=2] %136 = add i32 %135, 16 ; <i32> [#uses=1] %137 = and i32 %136, 63 ; <i32> [#uses=1] %138 = and i32 %135, -64 ; <i32> [#uses=1] %139 = or i32 %137, %138 ; <i32> [#uses=1] %140 = inttoptr i32 %139 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %141 = getelementptr %struct.edge_rec* %140, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %142 = load %struct.edge_rec** %141, align 4 ; <%struct.edge_rec*> [#uses=1] - %143 = getelementptr %struct.edge_rec* %132, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %144 = load %struct.edge_rec** %143, align 4 ; <%struct.edge_rec*> [#uses=1] + %141 = getelementptr %struct.edge_rec, %struct.edge_rec* %140, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %142 = load %struct.edge_rec*, %struct.edge_rec** %141, align 4 ; <%struct.edge_rec*> [#uses=1] + %143 = getelementptr %struct.edge_rec, %struct.edge_rec* %132, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %144 = load %struct.edge_rec*, %struct.edge_rec** %143, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %142, %struct.edge_rec** %143, align 4 store %struct.edge_rec* %144, %struct.edge_rec** %141, align 4 - %145 = load %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] - %146 = load %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=2] + %145 = load %struct.edge_rec*, %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] + %146 = load %struct.edge_rec*, %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=2] store %struct.edge_rec* %145, %struct.edge_rec** %133, align 4 store %struct.edge_rec* %146, %struct.edge_rec** %125, align 4 %147 = and i32 %92, 63 ; <i32> [#uses=1] %148 = and i32 %91, -64 ; <i32> [#uses=1] %149 = or i32 %147, %148 ; <i32> [#uses=1] %150 = inttoptr i32 %149 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %151 = getelementptr %struct.edge_rec* %150, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %152 = load %struct.edge_rec** %151, align 4 ; <%struct.edge_rec*> [#uses=1] + %151 = getelementptr %struct.edge_rec, %struct.edge_rec* %150, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %152 = load %struct.edge_rec*, %struct.edge_rec** %151, align 4 ; <%struct.edge_rec*> [#uses=1] %153 = ptrtoint %struct.edge_rec* %152 to i32 ; <i32> [#uses=2] %154 = add i32 %153, 16 ; <i32> [#uses=1] %155 = and i32 %154, 63 ; <i32> [#uses=1] %156 = and i32 %153, -64 ; <i32> [#uses=1] %157 = or i32 %155, %156 ; <i32> [#uses=1] %158 = inttoptr i32 %157 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %159 = load %struct.VERTEX** %90, align 4 ; <%struct.VERTEX*> [#uses=1] - %160 = getelementptr %struct.edge_rec* %124, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %161 = load %struct.VERTEX** %160, align 4 ; <%struct.VERTEX*> [#uses=1] - %162 = getelementptr %struct.edge_rec* %16, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %163 = load %struct.VERTEX** %162, align 4 ; <%struct.VERTEX*> [#uses=1] + %159 = load %struct.VERTEX*, %struct.VERTEX** %90, align 4 ; <%struct.VERTEX*> [#uses=1] + %160 = getelementptr %struct.edge_rec, %struct.edge_rec* %124, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %161 = load %struct.VERTEX*, %struct.VERTEX** %160, align 4 ; <%struct.VERTEX*> [#uses=1] + %162 = getelementptr %struct.edge_rec, %struct.edge_rec* %16, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %163 = load %struct.VERTEX*, %struct.VERTEX** %162, align 4 ; <%struct.VERTEX*> [#uses=1] %164 = icmp eq %struct.VERTEX* %163, %159 ; <i1> [#uses=1] %rdo_addr.0.i = select i1 %164, %struct.edge_rec* %88, %struct.edge_rec* %16 ; <%struct.edge_rec*> [#uses=3] - %165 = getelementptr %struct.edge_rec* %10, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %166 = load %struct.VERTEX** %165, align 4 ; <%struct.VERTEX*> [#uses=1] + %165 = getelementptr %struct.edge_rec, %struct.edge_rec* %10, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %166 = load %struct.VERTEX*, %struct.VERTEX** %165, align 4 ; <%struct.VERTEX*> [#uses=1] %167 = icmp eq %struct.VERTEX* %166, %161 ; <i1> [#uses=1] %ldo_addr.0.ph.i = select i1 %167, %struct.edge_rec* %124, %struct.edge_rec* %10 ; <%struct.edge_rec*> [#uses=3] br label %bb9.i @@ -243,32 +243,32 @@ bb9.i: ; preds = %bb25.i, %bb24.i, %bb5.i %lcand.2.i = phi %struct.edge_rec* [ %146, %bb5.i ], [ %lcand.1.i, %bb24.i ], [ %739, %bb25.i ] ; <%struct.edge_rec*> [#uses=5] %rcand.2.i = phi %struct.edge_rec* [ %158, %bb5.i ], [ %666, %bb24.i ], [ %rcand.1.i, %bb25.i ] ; <%struct.edge_rec*> [#uses=5] %basel.0.i = phi %struct.edge_rec* [ %88, %bb5.i ], [ %595, %bb24.i ], [ %716, %bb25.i ] ; <%struct.edge_rec*> [#uses=2] - %168 = getelementptr %struct.edge_rec* %lcand.2.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %169 = load %struct.edge_rec** %168, align 4 ; <%struct.edge_rec*> [#uses=3] - %170 = getelementptr %struct.edge_rec* %basel.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] - %171 = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=4] + %168 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.2.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %169 = load %struct.edge_rec*, %struct.edge_rec** %168, align 4 ; <%struct.edge_rec*> [#uses=3] + %170 = getelementptr %struct.edge_rec, %struct.edge_rec* %basel.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] + %171 = load %struct.VERTEX*, %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=4] %172 = ptrtoint %struct.edge_rec* %basel.0.i to i32 ; <i32> [#uses=3] %173 = xor i32 %172, 32 ; <i32> [#uses=1] %174 = inttoptr i32 %173 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %175 = getelementptr %struct.edge_rec* %174, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] - %176 = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=3] + %175 = getelementptr %struct.edge_rec, %struct.edge_rec* %174, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] + %176 = load %struct.VERTEX*, %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=3] %177 = ptrtoint %struct.edge_rec* %169 to i32 ; <i32> [#uses=1] %178 = xor i32 %177, 32 ; <i32> [#uses=1] %179 = inttoptr i32 %178 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %180 = getelementptr %struct.edge_rec* %179, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %181 = load %struct.VERTEX** %180, align 4 ; <%struct.VERTEX*> [#uses=2] - %182 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 0 ; <double*> [#uses=2] - %183 = load double* %182, align 4 ; <double> [#uses=2] - %184 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 1 ; <double*> [#uses=2] - %185 = load double* %184, align 4 ; <double> [#uses=2] - %186 = getelementptr %struct.VERTEX* %181, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %187 = load double* %186, align 4 ; <double> [#uses=1] - %188 = getelementptr %struct.VERTEX* %181, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %189 = load double* %188, align 4 ; <double> [#uses=1] - %190 = getelementptr %struct.VERTEX* %176, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %191 = load double* %190, align 4 ; <double> [#uses=2] - %192 = getelementptr %struct.VERTEX* %176, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %193 = load double* %192, align 4 ; <double> [#uses=2] + %180 = getelementptr %struct.edge_rec, %struct.edge_rec* %179, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %181 = load %struct.VERTEX*, %struct.VERTEX** %180, align 4 ; <%struct.VERTEX*> [#uses=2] + %182 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 0 ; <double*> [#uses=2] + %183 = load double, double* %182, align 4 ; <double> [#uses=2] + %184 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 1 ; <double*> [#uses=2] + %185 = load double, double* %184, align 4 ; <double> [#uses=2] + %186 = getelementptr %struct.VERTEX, %struct.VERTEX* %181, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %187 = load double, double* %186, align 4 ; <double> [#uses=1] + %188 = getelementptr %struct.VERTEX, %struct.VERTEX* %181, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %189 = load double, double* %188, align 4 ; <double> [#uses=1] + %190 = getelementptr %struct.VERTEX, %struct.VERTEX* %176, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %191 = load double, double* %190, align 4 ; <double> [#uses=2] + %192 = getelementptr %struct.VERTEX, %struct.VERTEX* %176, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %193 = load double, double* %192, align 4 ; <double> [#uses=2] %194 = fsub double %183, %191 ; <double> [#uses=1] %195 = fsub double %189, %193 ; <double> [#uses=1] %196 = fmul double %194, %195 ; <double> [#uses=1] @@ -280,8 +280,8 @@ bb9.i: ; preds = %bb25.i, %bb24.i, %bb5.i br i1 %201, label %bb10.i, label %bb13.i bb10.i: ; preds = %bb9.i - %202 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %avail_edge.promoted25 = load %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] + %202 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %avail_edge.promoted25 = load %struct.edge_rec*, %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] br label %bb12.i bb11.i: ; preds = %bb12.i @@ -291,38 +291,38 @@ bb11.i: ; preds = %bb12.i %206 = and i32 %203, -64 ; <i32> [#uses=3] %207 = or i32 %205, %206 ; <i32> [#uses=1] %208 = inttoptr i32 %207 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %209 = getelementptr %struct.edge_rec* %208, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %210 = load %struct.edge_rec** %209, align 4 ; <%struct.edge_rec*> [#uses=1] + %209 = getelementptr %struct.edge_rec, %struct.edge_rec* %208, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %210 = load %struct.edge_rec*, %struct.edge_rec** %209, align 4 ; <%struct.edge_rec*> [#uses=1] %211 = ptrtoint %struct.edge_rec* %210 to i32 ; <i32> [#uses=2] %212 = add i32 %211, 16 ; <i32> [#uses=1] %213 = and i32 %212, 63 ; <i32> [#uses=1] %214 = and i32 %211, -64 ; <i32> [#uses=1] %215 = or i32 %213, %214 ; <i32> [#uses=1] %216 = inttoptr i32 %215 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %217 = getelementptr %struct.edge_rec* %lcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %218 = load %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] + %217 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %218 = load %struct.edge_rec*, %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] %219 = ptrtoint %struct.edge_rec* %218 to i32 ; <i32> [#uses=2] %220 = add i32 %219, 16 ; <i32> [#uses=1] %221 = and i32 %220, 63 ; <i32> [#uses=1] %222 = and i32 %219, -64 ; <i32> [#uses=1] %223 = or i32 %221, %222 ; <i32> [#uses=1] %224 = inttoptr i32 %223 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %225 = getelementptr %struct.edge_rec* %216, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %226 = load %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] + %225 = getelementptr %struct.edge_rec, %struct.edge_rec* %216, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %226 = load %struct.edge_rec*, %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] %227 = ptrtoint %struct.edge_rec* %226 to i32 ; <i32> [#uses=2] %228 = add i32 %227, 16 ; <i32> [#uses=1] %229 = and i32 %228, 63 ; <i32> [#uses=1] %230 = and i32 %227, -64 ; <i32> [#uses=1] %231 = or i32 %229, %230 ; <i32> [#uses=1] %232 = inttoptr i32 %231 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %233 = getelementptr %struct.edge_rec* %232, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %234 = load %struct.edge_rec** %233, align 4 ; <%struct.edge_rec*> [#uses=1] - %235 = getelementptr %struct.edge_rec* %224, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %236 = load %struct.edge_rec** %235, align 4 ; <%struct.edge_rec*> [#uses=1] + %233 = getelementptr %struct.edge_rec, %struct.edge_rec* %232, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %234 = load %struct.edge_rec*, %struct.edge_rec** %233, align 4 ; <%struct.edge_rec*> [#uses=1] + %235 = getelementptr %struct.edge_rec, %struct.edge_rec* %224, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %236 = load %struct.edge_rec*, %struct.edge_rec** %235, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %234, %struct.edge_rec** %235, align 4 store %struct.edge_rec* %236, %struct.edge_rec** %233, align 4 - %237 = load %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] - %238 = load %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] + %237 = load %struct.edge_rec*, %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] + %238 = load %struct.edge_rec*, %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %237, %struct.edge_rec** %225, align 4 store %struct.edge_rec* %238, %struct.edge_rec** %217, align 4 %239 = xor i32 %203, 32 ; <i32> [#uses=2] @@ -330,8 +330,8 @@ bb11.i: ; preds = %bb12.i %241 = and i32 %240, 63 ; <i32> [#uses=1] %242 = or i32 %241, %206 ; <i32> [#uses=1] %243 = inttoptr i32 %242 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %244 = getelementptr %struct.edge_rec* %243, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %245 = load %struct.edge_rec** %244, align 4 ; <%struct.edge_rec*> [#uses=1] + %244 = getelementptr %struct.edge_rec, %struct.edge_rec* %243, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %245 = load %struct.edge_rec*, %struct.edge_rec** %244, align 4 ; <%struct.edge_rec*> [#uses=1] %246 = ptrtoint %struct.edge_rec* %245 to i32 ; <i32> [#uses=2] %247 = add i32 %246, 16 ; <i32> [#uses=1] %248 = and i32 %247, 63 ; <i32> [#uses=1] @@ -339,39 +339,39 @@ bb11.i: ; preds = %bb12.i %250 = or i32 %248, %249 ; <i32> [#uses=1] %251 = inttoptr i32 %250 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %252 = inttoptr i32 %239 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %253 = getelementptr %struct.edge_rec* %252, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %254 = load %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] + %253 = getelementptr %struct.edge_rec, %struct.edge_rec* %252, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %254 = load %struct.edge_rec*, %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] %255 = ptrtoint %struct.edge_rec* %254 to i32 ; <i32> [#uses=2] %256 = add i32 %255, 16 ; <i32> [#uses=1] %257 = and i32 %256, 63 ; <i32> [#uses=1] %258 = and i32 %255, -64 ; <i32> [#uses=1] %259 = or i32 %257, %258 ; <i32> [#uses=1] %260 = inttoptr i32 %259 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %261 = getelementptr %struct.edge_rec* %251, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %262 = load %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] + %261 = getelementptr %struct.edge_rec, %struct.edge_rec* %251, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %262 = load %struct.edge_rec*, %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] %263 = ptrtoint %struct.edge_rec* %262 to i32 ; <i32> [#uses=2] %264 = add i32 %263, 16 ; <i32> [#uses=1] %265 = and i32 %264, 63 ; <i32> [#uses=1] %266 = and i32 %263, -64 ; <i32> [#uses=1] %267 = or i32 %265, %266 ; <i32> [#uses=1] %268 = inttoptr i32 %267 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %269 = getelementptr %struct.edge_rec* %268, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %270 = load %struct.edge_rec** %269, align 4 ; <%struct.edge_rec*> [#uses=1] - %271 = getelementptr %struct.edge_rec* %260, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %272 = load %struct.edge_rec** %271, align 4 ; <%struct.edge_rec*> [#uses=1] + %269 = getelementptr %struct.edge_rec, %struct.edge_rec* %268, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %270 = load %struct.edge_rec*, %struct.edge_rec** %269, align 4 ; <%struct.edge_rec*> [#uses=1] + %271 = getelementptr %struct.edge_rec, %struct.edge_rec* %260, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %272 = load %struct.edge_rec*, %struct.edge_rec** %271, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %270, %struct.edge_rec** %271, align 4 store %struct.edge_rec* %272, %struct.edge_rec** %269, align 4 - %273 = load %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] - %274 = load %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] + %273 = load %struct.edge_rec*, %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] + %274 = load %struct.edge_rec*, %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %273, %struct.edge_rec** %261, align 4 store %struct.edge_rec* %274, %struct.edge_rec** %253, align 4 %275 = inttoptr i32 %206 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %276 = getelementptr %struct.edge_rec* %275, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %276 = getelementptr %struct.edge_rec, %struct.edge_rec* %275, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** %276, align 4 - %277 = getelementptr %struct.edge_rec* %t.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %278 = load %struct.edge_rec** %277, align 4 ; <%struct.edge_rec*> [#uses=2] - %.pre.i = load double* %182, align 4 ; <double> [#uses=1] - %.pre22.i = load double* %184, align 4 ; <double> [#uses=1] + %277 = getelementptr %struct.edge_rec, %struct.edge_rec* %t.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %278 = load %struct.edge_rec*, %struct.edge_rec** %277, align 4 ; <%struct.edge_rec*> [#uses=2] + %.pre.i = load double, double* %182, align 4 ; <double> [#uses=1] + %.pre22.i = load double, double* %184, align 4 ; <double> [#uses=1] br label %bb12.i bb12.i: ; preds = %bb11.i, %bb10.i @@ -389,37 +389,37 @@ bb12.i: ; preds = %bb11.i, %bb10.i %.pn4.in.i = xor i32 %.pn4.in.in.i, 32 ; <i32> [#uses=1] %.pn5.i = inttoptr i32 %.pn5.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %.pn4.i = inttoptr i32 %.pn4.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %v1.0.in.i = getelementptr %struct.edge_rec* %.pn5.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v2.0.in.i = getelementptr %struct.edge_rec* %.pn4.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v3.0.in.i = getelementptr %struct.edge_rec* %lcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v1.0.i = load %struct.VERTEX** %v1.0.in.i ; <%struct.VERTEX*> [#uses=3] - %v2.0.i = load %struct.VERTEX** %v2.0.in.i ; <%struct.VERTEX*> [#uses=3] - %v3.0.i = load %struct.VERTEX** %v3.0.in.i ; <%struct.VERTEX*> [#uses=3] - %281 = load double* %202, align 4 ; <double> [#uses=3] - %282 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %283 = load double* %282, align 4 ; <double> [#uses=1] + %v1.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn5.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %v2.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn4.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %v3.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %v1.0.i = load %struct.VERTEX*, %struct.VERTEX** %v1.0.in.i ; <%struct.VERTEX*> [#uses=3] + %v2.0.i = load %struct.VERTEX*, %struct.VERTEX** %v2.0.in.i ; <%struct.VERTEX*> [#uses=3] + %v3.0.i = load %struct.VERTEX*, %struct.VERTEX** %v3.0.in.i ; <%struct.VERTEX*> [#uses=3] + %281 = load double, double* %202, align 4 ; <double> [#uses=3] + %282 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %283 = load double, double* %282, align 4 ; <double> [#uses=1] %284 = fsub double %283, %280 ; <double> [#uses=2] - %285 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %286 = load double* %285, align 4 ; <double> [#uses=1] + %285 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %286 = load double, double* %285, align 4 ; <double> [#uses=1] %287 = fsub double %286, %279 ; <double> [#uses=2] - %288 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %289 = load double* %288, align 4 ; <double> [#uses=1] - %290 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %291 = load double* %290, align 4 ; <double> [#uses=1] + %288 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %289 = load double, double* %288, align 4 ; <double> [#uses=1] + %290 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %291 = load double, double* %290, align 4 ; <double> [#uses=1] %292 = fsub double %291, %280 ; <double> [#uses=2] - %293 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %294 = load double* %293, align 4 ; <double> [#uses=1] + %293 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %294 = load double, double* %293, align 4 ; <double> [#uses=1] %295 = fsub double %294, %279 ; <double> [#uses=2] - %296 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %297 = load double* %296, align 4 ; <double> [#uses=1] - %298 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %299 = load double* %298, align 4 ; <double> [#uses=1] + %296 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %297 = load double, double* %296, align 4 ; <double> [#uses=1] + %298 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %299 = load double, double* %298, align 4 ; <double> [#uses=1] %300 = fsub double %299, %280 ; <double> [#uses=2] - %301 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %302 = load double* %301, align 4 ; <double> [#uses=1] + %301 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %302 = load double, double* %301, align 4 ; <double> [#uses=1] %303 = fsub double %302, %279 ; <double> [#uses=2] - %304 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %305 = load double* %304, align 4 ; <double> [#uses=1] + %304 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %305 = load double, double* %304, align 4 ; <double> [#uses=1] %306 = fsub double %289, %281 ; <double> [#uses=1] %307 = fmul double %292, %303 ; <double> [#uses=1] %308 = fmul double %295, %300 ; <double> [#uses=1] @@ -442,8 +442,8 @@ bb12.i: ; preds = %bb11.i, %bb10.i bb13.loopexit.i: ; preds = %bb12.i store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** @avail_edge - %.pre23.i = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] - %.pre24.i = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre23.i = load %struct.VERTEX*, %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre24.i = load %struct.VERTEX*, %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] br label %bb13.i bb13.i: ; preds = %bb13.loopexit.i, %bb9.i @@ -456,8 +456,8 @@ bb13.i: ; preds = %bb13.loopexit.i, %bb9.i %329 = and i32 %326, -64 ; <i32> [#uses=1] %330 = or i32 %328, %329 ; <i32> [#uses=1] %331 = inttoptr i32 %330 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %332 = getelementptr %struct.edge_rec* %331, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %333 = load %struct.edge_rec** %332, align 4 ; <%struct.edge_rec*> [#uses=1] + %332 = getelementptr %struct.edge_rec, %struct.edge_rec* %331, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %333 = load %struct.edge_rec*, %struct.edge_rec** %332, align 4 ; <%struct.edge_rec*> [#uses=1] %334 = ptrtoint %struct.edge_rec* %333 to i32 ; <i32> [#uses=2] %335 = add i32 %334, 16 ; <i32> [#uses=1] %336 = and i32 %335, 63 ; <i32> [#uses=1] @@ -465,20 +465,20 @@ bb13.i: ; preds = %bb13.loopexit.i, %bb9.i %338 = or i32 %336, %337 ; <i32> [#uses=3] %339 = xor i32 %338, 32 ; <i32> [#uses=1] %340 = inttoptr i32 %339 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %341 = getelementptr %struct.edge_rec* %340, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %342 = load %struct.VERTEX** %341, align 4 ; <%struct.VERTEX*> [#uses=2] - %343 = getelementptr %struct.VERTEX* %325, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %344 = load double* %343, align 4 ; <double> [#uses=1] - %345 = getelementptr %struct.VERTEX* %325, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %346 = load double* %345, align 4 ; <double> [#uses=1] - %347 = getelementptr %struct.VERTEX* %342, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %348 = load double* %347, align 4 ; <double> [#uses=1] - %349 = getelementptr %struct.VERTEX* %342, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %350 = load double* %349, align 4 ; <double> [#uses=1] - %351 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 0 ; <double*> [#uses=2] - %352 = load double* %351, align 4 ; <double> [#uses=3] - %353 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 1 ; <double*> [#uses=2] - %354 = load double* %353, align 4 ; <double> [#uses=3] + %341 = getelementptr %struct.edge_rec, %struct.edge_rec* %340, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %342 = load %struct.VERTEX*, %struct.VERTEX** %341, align 4 ; <%struct.VERTEX*> [#uses=2] + %343 = getelementptr %struct.VERTEX, %struct.VERTEX* %325, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %344 = load double, double* %343, align 4 ; <double> [#uses=1] + %345 = getelementptr %struct.VERTEX, %struct.VERTEX* %325, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %346 = load double, double* %345, align 4 ; <double> [#uses=1] + %347 = getelementptr %struct.VERTEX, %struct.VERTEX* %342, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %348 = load double, double* %347, align 4 ; <double> [#uses=1] + %349 = getelementptr %struct.VERTEX, %struct.VERTEX* %342, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %350 = load double, double* %349, align 4 ; <double> [#uses=1] + %351 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 0 ; <double*> [#uses=2] + %352 = load double, double* %351, align 4 ; <double> [#uses=3] + %353 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 1 ; <double*> [#uses=2] + %354 = load double, double* %353, align 4 ; <double> [#uses=3] %355 = fsub double %344, %352 ; <double> [#uses=1] %356 = fsub double %350, %354 ; <double> [#uses=1] %357 = fmul double %355, %356 ; <double> [#uses=1] @@ -490,8 +490,8 @@ bb13.i: ; preds = %bb13.loopexit.i, %bb9.i br i1 %362, label %bb14.i, label %bb17.i bb14.i: ; preds = %bb13.i - %363 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %avail_edge.promoted = load %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] + %363 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %avail_edge.promoted = load %struct.edge_rec*, %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] br label %bb16.i bb15.i: ; preds = %bb16.i @@ -501,38 +501,38 @@ bb15.i: ; preds = %bb16.i %367 = and i32 %364, -64 ; <i32> [#uses=3] %368 = or i32 %366, %367 ; <i32> [#uses=1] %369 = inttoptr i32 %368 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %370 = getelementptr %struct.edge_rec* %369, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %371 = load %struct.edge_rec** %370, align 4 ; <%struct.edge_rec*> [#uses=1] + %370 = getelementptr %struct.edge_rec, %struct.edge_rec* %369, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %371 = load %struct.edge_rec*, %struct.edge_rec** %370, align 4 ; <%struct.edge_rec*> [#uses=1] %372 = ptrtoint %struct.edge_rec* %371 to i32 ; <i32> [#uses=2] %373 = add i32 %372, 16 ; <i32> [#uses=1] %374 = and i32 %373, 63 ; <i32> [#uses=1] %375 = and i32 %372, -64 ; <i32> [#uses=1] %376 = or i32 %374, %375 ; <i32> [#uses=1] %377 = inttoptr i32 %376 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %378 = getelementptr %struct.edge_rec* %rcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %379 = load %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] + %378 = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %379 = load %struct.edge_rec*, %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] %380 = ptrtoint %struct.edge_rec* %379 to i32 ; <i32> [#uses=2] %381 = add i32 %380, 16 ; <i32> [#uses=1] %382 = and i32 %381, 63 ; <i32> [#uses=1] %383 = and i32 %380, -64 ; <i32> [#uses=1] %384 = or i32 %382, %383 ; <i32> [#uses=1] %385 = inttoptr i32 %384 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %386 = getelementptr %struct.edge_rec* %377, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %387 = load %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] + %386 = getelementptr %struct.edge_rec, %struct.edge_rec* %377, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %387 = load %struct.edge_rec*, %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] %388 = ptrtoint %struct.edge_rec* %387 to i32 ; <i32> [#uses=2] %389 = add i32 %388, 16 ; <i32> [#uses=1] %390 = and i32 %389, 63 ; <i32> [#uses=1] %391 = and i32 %388, -64 ; <i32> [#uses=1] %392 = or i32 %390, %391 ; <i32> [#uses=1] %393 = inttoptr i32 %392 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %394 = getelementptr %struct.edge_rec* %393, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %395 = load %struct.edge_rec** %394, align 4 ; <%struct.edge_rec*> [#uses=1] - %396 = getelementptr %struct.edge_rec* %385, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %397 = load %struct.edge_rec** %396, align 4 ; <%struct.edge_rec*> [#uses=1] + %394 = getelementptr %struct.edge_rec, %struct.edge_rec* %393, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %395 = load %struct.edge_rec*, %struct.edge_rec** %394, align 4 ; <%struct.edge_rec*> [#uses=1] + %396 = getelementptr %struct.edge_rec, %struct.edge_rec* %385, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %397 = load %struct.edge_rec*, %struct.edge_rec** %396, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %395, %struct.edge_rec** %396, align 4 store %struct.edge_rec* %397, %struct.edge_rec** %394, align 4 - %398 = load %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] - %399 = load %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] + %398 = load %struct.edge_rec*, %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] + %399 = load %struct.edge_rec*, %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %398, %struct.edge_rec** %386, align 4 store %struct.edge_rec* %399, %struct.edge_rec** %378, align 4 %400 = xor i32 %364, 32 ; <i32> [#uses=2] @@ -540,8 +540,8 @@ bb15.i: ; preds = %bb16.i %402 = and i32 %401, 63 ; <i32> [#uses=1] %403 = or i32 %402, %367 ; <i32> [#uses=1] %404 = inttoptr i32 %403 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %405 = getelementptr %struct.edge_rec* %404, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %406 = load %struct.edge_rec** %405, align 4 ; <%struct.edge_rec*> [#uses=1] + %405 = getelementptr %struct.edge_rec, %struct.edge_rec* %404, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %406 = load %struct.edge_rec*, %struct.edge_rec** %405, align 4 ; <%struct.edge_rec*> [#uses=1] %407 = ptrtoint %struct.edge_rec* %406 to i32 ; <i32> [#uses=2] %408 = add i32 %407, 16 ; <i32> [#uses=1] %409 = and i32 %408, 63 ; <i32> [#uses=1] @@ -549,49 +549,49 @@ bb15.i: ; preds = %bb16.i %411 = or i32 %409, %410 ; <i32> [#uses=1] %412 = inttoptr i32 %411 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %413 = inttoptr i32 %400 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %414 = getelementptr %struct.edge_rec* %413, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %415 = load %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] + %414 = getelementptr %struct.edge_rec, %struct.edge_rec* %413, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %415 = load %struct.edge_rec*, %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] %416 = ptrtoint %struct.edge_rec* %415 to i32 ; <i32> [#uses=2] %417 = add i32 %416, 16 ; <i32> [#uses=1] %418 = and i32 %417, 63 ; <i32> [#uses=1] %419 = and i32 %416, -64 ; <i32> [#uses=1] %420 = or i32 %418, %419 ; <i32> [#uses=1] %421 = inttoptr i32 %420 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %422 = getelementptr %struct.edge_rec* %412, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %423 = load %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] + %422 = getelementptr %struct.edge_rec, %struct.edge_rec* %412, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %423 = load %struct.edge_rec*, %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] %424 = ptrtoint %struct.edge_rec* %423 to i32 ; <i32> [#uses=2] %425 = add i32 %424, 16 ; <i32> [#uses=1] %426 = and i32 %425, 63 ; <i32> [#uses=1] %427 = and i32 %424, -64 ; <i32> [#uses=1] %428 = or i32 %426, %427 ; <i32> [#uses=1] %429 = inttoptr i32 %428 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %430 = getelementptr %struct.edge_rec* %429, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %431 = load %struct.edge_rec** %430, align 4 ; <%struct.edge_rec*> [#uses=1] - %432 = getelementptr %struct.edge_rec* %421, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %433 = load %struct.edge_rec** %432, align 4 ; <%struct.edge_rec*> [#uses=1] + %430 = getelementptr %struct.edge_rec, %struct.edge_rec* %429, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %431 = load %struct.edge_rec*, %struct.edge_rec** %430, align 4 ; <%struct.edge_rec*> [#uses=1] + %432 = getelementptr %struct.edge_rec, %struct.edge_rec* %421, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %433 = load %struct.edge_rec*, %struct.edge_rec** %432, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %431, %struct.edge_rec** %432, align 4 store %struct.edge_rec* %433, %struct.edge_rec** %430, align 4 - %434 = load %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] - %435 = load %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] + %434 = load %struct.edge_rec*, %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] + %435 = load %struct.edge_rec*, %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %434, %struct.edge_rec** %422, align 4 store %struct.edge_rec* %435, %struct.edge_rec** %414, align 4 %436 = inttoptr i32 %367 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %437 = getelementptr %struct.edge_rec* %436, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %437 = getelementptr %struct.edge_rec, %struct.edge_rec* %436, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %avail_edge.tmp.0, %struct.edge_rec** %437, align 4 %438 = add i32 %t.1.in.i, 16 ; <i32> [#uses=1] %439 = and i32 %438, 63 ; <i32> [#uses=1] %440 = and i32 %t.1.in.i, -64 ; <i32> [#uses=1] %441 = or i32 %439, %440 ; <i32> [#uses=1] %442 = inttoptr i32 %441 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %443 = getelementptr %struct.edge_rec* %442, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %444 = load %struct.edge_rec** %443, align 4 ; <%struct.edge_rec*> [#uses=1] + %443 = getelementptr %struct.edge_rec, %struct.edge_rec* %442, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %444 = load %struct.edge_rec*, %struct.edge_rec** %443, align 4 ; <%struct.edge_rec*> [#uses=1] %445 = ptrtoint %struct.edge_rec* %444 to i32 ; <i32> [#uses=2] %446 = add i32 %445, 16 ; <i32> [#uses=1] %447 = and i32 %446, 63 ; <i32> [#uses=1] %448 = and i32 %445, -64 ; <i32> [#uses=1] %449 = or i32 %447, %448 ; <i32> [#uses=2] - %.pre25.i = load double* %351, align 4 ; <double> [#uses=1] - %.pre26.i = load double* %353, align 4 ; <double> [#uses=1] + %.pre25.i = load double, double* %351, align 4 ; <double> [#uses=1] + %.pre26.i = load double, double* %353, align 4 ; <double> [#uses=1] br label %bb16.i bb16.i: ; preds = %bb15.i, %bb14.i @@ -609,37 +609,37 @@ bb16.i: ; preds = %bb15.i, %bb14.i %.pn.in.i = xor i32 %.pn.in.in.i, 32 ; <i32> [#uses=1] %.pn3.i = inttoptr i32 %.pn3.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %.pn.i = inttoptr i32 %.pn.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %v1.1.in.i = getelementptr %struct.edge_rec* %.pn3.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v2.1.in.i = getelementptr %struct.edge_rec* %.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v3.1.in.i = getelementptr %struct.edge_rec* %rcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v1.1.i = load %struct.VERTEX** %v1.1.in.i ; <%struct.VERTEX*> [#uses=3] - %v2.1.i = load %struct.VERTEX** %v2.1.in.i ; <%struct.VERTEX*> [#uses=3] - %v3.1.i = load %struct.VERTEX** %v3.1.in.i ; <%struct.VERTEX*> [#uses=3] - %452 = load double* %363, align 4 ; <double> [#uses=3] - %453 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %454 = load double* %453, align 4 ; <double> [#uses=1] + %v1.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn3.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %v2.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %v3.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %v1.1.i = load %struct.VERTEX*, %struct.VERTEX** %v1.1.in.i ; <%struct.VERTEX*> [#uses=3] + %v2.1.i = load %struct.VERTEX*, %struct.VERTEX** %v2.1.in.i ; <%struct.VERTEX*> [#uses=3] + %v3.1.i = load %struct.VERTEX*, %struct.VERTEX** %v3.1.in.i ; <%struct.VERTEX*> [#uses=3] + %452 = load double, double* %363, align 4 ; <double> [#uses=3] + %453 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %454 = load double, double* %453, align 4 ; <double> [#uses=1] %455 = fsub double %454, %451 ; <double> [#uses=2] - %456 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %457 = load double* %456, align 4 ; <double> [#uses=1] + %456 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %457 = load double, double* %456, align 4 ; <double> [#uses=1] %458 = fsub double %457, %450 ; <double> [#uses=2] - %459 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %460 = load double* %459, align 4 ; <double> [#uses=1] - %461 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %462 = load double* %461, align 4 ; <double> [#uses=1] + %459 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %460 = load double, double* %459, align 4 ; <double> [#uses=1] + %461 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %462 = load double, double* %461, align 4 ; <double> [#uses=1] %463 = fsub double %462, %451 ; <double> [#uses=2] - %464 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %465 = load double* %464, align 4 ; <double> [#uses=1] + %464 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %465 = load double, double* %464, align 4 ; <double> [#uses=1] %466 = fsub double %465, %450 ; <double> [#uses=2] - %467 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %468 = load double* %467, align 4 ; <double> [#uses=1] - %469 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %470 = load double* %469, align 4 ; <double> [#uses=1] + %467 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %468 = load double, double* %467, align 4 ; <double> [#uses=1] + %469 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %470 = load double, double* %469, align 4 ; <double> [#uses=1] %471 = fsub double %470, %451 ; <double> [#uses=2] - %472 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %473 = load double* %472, align 4 ; <double> [#uses=1] + %472 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %473 = load double, double* %472, align 4 ; <double> [#uses=1] %474 = fsub double %473, %450 ; <double> [#uses=2] - %475 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %476 = load double* %475, align 4 ; <double> [#uses=1] + %475 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %476 = load double, double* %475, align 4 ; <double> [#uses=1] %477 = fsub double %460, %452 ; <double> [#uses=1] %478 = fmul double %463, %474 ; <double> [#uses=1] %479 = fmul double %466, %471 ; <double> [#uses=1] @@ -662,8 +662,8 @@ bb16.i: ; preds = %bb15.i, %bb14.i bb17.loopexit.i: ; preds = %bb16.i store %struct.edge_rec* %avail_edge.tmp.0, %struct.edge_rec** @avail_edge - %.pre27.i = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] - %.pre28.i = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre27.i = load %struct.VERTEX*, %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre28.i = load %struct.VERTEX*, %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] br label %bb17.i bb17.i: ; preds = %bb17.loopexit.i, %bb13.i @@ -673,20 +673,20 @@ bb17.i: ; preds = %bb17.loopexit.i, %bb13.i %497 = ptrtoint %struct.edge_rec* %lcand.1.i to i32 ; <i32> [#uses=1] %498 = xor i32 %497, 32 ; <i32> [#uses=1] %499 = inttoptr i32 %498 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %500 = getelementptr %struct.edge_rec* %499, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %501 = load %struct.VERTEX** %500, align 4 ; <%struct.VERTEX*> [#uses=4] - %502 = getelementptr %struct.VERTEX* %496, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %503 = load double* %502, align 4 ; <double> [#uses=1] - %504 = getelementptr %struct.VERTEX* %496, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %505 = load double* %504, align 4 ; <double> [#uses=1] - %506 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %507 = load double* %506, align 4 ; <double> [#uses=2] - %508 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %509 = load double* %508, align 4 ; <double> [#uses=2] - %510 = getelementptr %struct.VERTEX* %495, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %511 = load double* %510, align 4 ; <double> [#uses=3] - %512 = getelementptr %struct.VERTEX* %495, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %513 = load double* %512, align 4 ; <double> [#uses=3] + %500 = getelementptr %struct.edge_rec, %struct.edge_rec* %499, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %501 = load %struct.VERTEX*, %struct.VERTEX** %500, align 4 ; <%struct.VERTEX*> [#uses=4] + %502 = getelementptr %struct.VERTEX, %struct.VERTEX* %496, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %503 = load double, double* %502, align 4 ; <double> [#uses=1] + %504 = getelementptr %struct.VERTEX, %struct.VERTEX* %496, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %505 = load double, double* %504, align 4 ; <double> [#uses=1] + %506 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %507 = load double, double* %506, align 4 ; <double> [#uses=2] + %508 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %509 = load double, double* %508, align 4 ; <double> [#uses=2] + %510 = getelementptr %struct.VERTEX, %struct.VERTEX* %495, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %511 = load double, double* %510, align 4 ; <double> [#uses=3] + %512 = getelementptr %struct.VERTEX, %struct.VERTEX* %495, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %513 = load double, double* %512, align 4 ; <double> [#uses=3] %514 = fsub double %503, %511 ; <double> [#uses=2] %515 = fsub double %509, %513 ; <double> [#uses=1] %516 = fmul double %514, %515 ; <double> [#uses=1] @@ -698,12 +698,12 @@ bb17.i: ; preds = %bb17.loopexit.i, %bb13.i %522 = ptrtoint %struct.edge_rec* %rcand.1.i to i32 ; <i32> [#uses=3] %523 = xor i32 %522, 32 ; <i32> [#uses=1] %524 = inttoptr i32 %523 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %525 = getelementptr %struct.edge_rec* %524, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %526 = load %struct.VERTEX** %525, align 4 ; <%struct.VERTEX*> [#uses=4] - %527 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %528 = load double* %527, align 4 ; <double> [#uses=4] - %529 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %530 = load double* %529, align 4 ; <double> [#uses=4] + %525 = getelementptr %struct.edge_rec, %struct.edge_rec* %524, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %526 = load %struct.VERTEX*, %struct.VERTEX** %525, align 4 ; <%struct.VERTEX*> [#uses=4] + %527 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %528 = load double, double* %527, align 4 ; <double> [#uses=4] + %529 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %530 = load double, double* %529, align 4 ; <double> [#uses=4] %531 = fsub double %530, %513 ; <double> [#uses=1] %532 = fmul double %514, %531 ; <double> [#uses=1] %533 = fsub double %528, %511 ; <double> [#uses=1] @@ -714,38 +714,38 @@ bb17.i: ; preds = %bb17.loopexit.i, %bb13.i br i1 %537, label %bb21.i, label %do_merge.exit bb21.i: ; preds = %bb17.i - %538 = getelementptr %struct.edge_rec* %lcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %539 = load %struct.VERTEX** %538, align 4 ; <%struct.VERTEX*> [#uses=3] - %540 = getelementptr %struct.edge_rec* %rcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %541 = load %struct.VERTEX** %540, align 4 ; <%struct.VERTEX*> [#uses=3] + %538 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %539 = load %struct.VERTEX*, %struct.VERTEX** %538, align 4 ; <%struct.VERTEX*> [#uses=3] + %540 = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %541 = load %struct.VERTEX*, %struct.VERTEX** %540, align 4 ; <%struct.VERTEX*> [#uses=3] br i1 %521, label %bb22.i, label %bb24.i bb22.i: ; preds = %bb21.i br i1 %536, label %bb23.i, label %bb25.i bb23.i: ; preds = %bb22.i - %542 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %543 = load double* %542, align 4 ; <double> [#uses=3] + %542 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %543 = load double, double* %542, align 4 ; <double> [#uses=3] %544 = fsub double %507, %528 ; <double> [#uses=2] %545 = fsub double %509, %530 ; <double> [#uses=2] - %546 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %547 = load double* %546, align 4 ; <double> [#uses=1] - %548 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %549 = load double* %548, align 4 ; <double> [#uses=1] + %546 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %547 = load double, double* %546, align 4 ; <double> [#uses=1] + %548 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %549 = load double, double* %548, align 4 ; <double> [#uses=1] %550 = fsub double %549, %528 ; <double> [#uses=2] - %551 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %552 = load double* %551, align 4 ; <double> [#uses=1] + %551 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %552 = load double, double* %551, align 4 ; <double> [#uses=1] %553 = fsub double %552, %530 ; <double> [#uses=2] - %554 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %555 = load double* %554, align 4 ; <double> [#uses=1] - %556 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %557 = load double* %556, align 4 ; <double> [#uses=1] + %554 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %555 = load double, double* %554, align 4 ; <double> [#uses=1] + %556 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %557 = load double, double* %556, align 4 ; <double> [#uses=1] %558 = fsub double %557, %528 ; <double> [#uses=2] - %559 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %560 = load double* %559, align 4 ; <double> [#uses=1] + %559 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %560 = load double, double* %559, align 4 ; <double> [#uses=1] %561 = fsub double %560, %530 ; <double> [#uses=2] - %562 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 2 ; <double*> [#uses=1] - %563 = load double* %562, align 4 ; <double> [#uses=1] + %562 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 2 ; <double*> [#uses=1] + %563 = load double, double* %562, align 4 ; <double> [#uses=1] %564 = fsub double %547, %543 ; <double> [#uses=1] %565 = fmul double %550, %561 ; <double> [#uses=1] %566 = fmul double %553, %558 ; <double> [#uses=1] @@ -772,8 +772,8 @@ bb24.i: ; preds = %bb23.i, %bb21.i %584 = and i32 %522, -64 ; <i32> [#uses=1] %585 = or i32 %583, %584 ; <i32> [#uses=1] %586 = inttoptr i32 %585 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %587 = getelementptr %struct.edge_rec* %586, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %588 = load %struct.edge_rec** %587, align 4 ; <%struct.edge_rec*> [#uses=1] + %587 = getelementptr %struct.edge_rec, %struct.edge_rec* %586, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %588 = load %struct.edge_rec*, %struct.edge_rec** %587, align 4 ; <%struct.edge_rec*> [#uses=1] %589 = ptrtoint %struct.edge_rec* %588 to i32 ; <i32> [#uses=2] %590 = add i32 %589, 16 ; <i32> [#uses=1] %591 = and i32 %590, 63 ; <i32> [#uses=1] @@ -781,76 +781,76 @@ bb24.i: ; preds = %bb23.i, %bb21.i %593 = or i32 %591, %592 ; <i32> [#uses=1] %594 = inttoptr i32 %593 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %595 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] - %596 = getelementptr %struct.edge_rec* %595, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] + %596 = getelementptr %struct.edge_rec, %struct.edge_rec* %595, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %595, %struct.edge_rec** %596, align 4 - %597 = getelementptr %struct.edge_rec* %595, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %597 = getelementptr %struct.edge_rec, %struct.edge_rec* %595, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %526, %struct.VERTEX** %597, align 4 %598 = ptrtoint %struct.edge_rec* %595 to i32 ; <i32> [#uses=5] %599 = add i32 %598, 16 ; <i32> [#uses=1] %600 = inttoptr i32 %599 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %601 = add i32 %598, 48 ; <i32> [#uses=1] %602 = inttoptr i32 %601 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %603 = getelementptr %struct.edge_rec* %600, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %603 = getelementptr %struct.edge_rec, %struct.edge_rec* %600, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %602, %struct.edge_rec** %603, align 4 %604 = add i32 %598, 32 ; <i32> [#uses=1] %605 = inttoptr i32 %604 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %606 = getelementptr %struct.edge_rec* %605, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %606 = getelementptr %struct.edge_rec, %struct.edge_rec* %605, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %605, %struct.edge_rec** %606, align 4 - %607 = getelementptr %struct.edge_rec* %605, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %607 = getelementptr %struct.edge_rec, %struct.edge_rec* %605, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %495, %struct.VERTEX** %607, align 4 - %608 = getelementptr %struct.edge_rec* %602, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %608 = getelementptr %struct.edge_rec, %struct.edge_rec* %602, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %600, %struct.edge_rec** %608, align 4 - %609 = load %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] + %609 = load %struct.edge_rec*, %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] %610 = ptrtoint %struct.edge_rec* %609 to i32 ; <i32> [#uses=2] %611 = add i32 %610, 16 ; <i32> [#uses=1] %612 = and i32 %611, 63 ; <i32> [#uses=1] %613 = and i32 %610, -64 ; <i32> [#uses=1] %614 = or i32 %612, %613 ; <i32> [#uses=1] %615 = inttoptr i32 %614 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %616 = getelementptr %struct.edge_rec* %594, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %617 = load %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] + %616 = getelementptr %struct.edge_rec, %struct.edge_rec* %594, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %617 = load %struct.edge_rec*, %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] %618 = ptrtoint %struct.edge_rec* %617 to i32 ; <i32> [#uses=2] %619 = add i32 %618, 16 ; <i32> [#uses=1] %620 = and i32 %619, 63 ; <i32> [#uses=1] %621 = and i32 %618, -64 ; <i32> [#uses=1] %622 = or i32 %620, %621 ; <i32> [#uses=1] %623 = inttoptr i32 %622 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %624 = getelementptr %struct.edge_rec* %623, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %625 = load %struct.edge_rec** %624, align 4 ; <%struct.edge_rec*> [#uses=1] - %626 = getelementptr %struct.edge_rec* %615, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %627 = load %struct.edge_rec** %626, align 4 ; <%struct.edge_rec*> [#uses=1] + %624 = getelementptr %struct.edge_rec, %struct.edge_rec* %623, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %625 = load %struct.edge_rec*, %struct.edge_rec** %624, align 4 ; <%struct.edge_rec*> [#uses=1] + %626 = getelementptr %struct.edge_rec, %struct.edge_rec* %615, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %627 = load %struct.edge_rec*, %struct.edge_rec** %626, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %625, %struct.edge_rec** %626, align 4 store %struct.edge_rec* %627, %struct.edge_rec** %624, align 4 - %628 = load %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] - %629 = load %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] + %628 = load %struct.edge_rec*, %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] + %629 = load %struct.edge_rec*, %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %628, %struct.edge_rec** %616, align 4 store %struct.edge_rec* %629, %struct.edge_rec** %596, align 4 %630 = xor i32 %598, 32 ; <i32> [#uses=2] %631 = inttoptr i32 %630 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %632 = getelementptr %struct.edge_rec* %631, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %633 = load %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] + %632 = getelementptr %struct.edge_rec, %struct.edge_rec* %631, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %633 = load %struct.edge_rec*, %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] %634 = ptrtoint %struct.edge_rec* %633 to i32 ; <i32> [#uses=2] %635 = add i32 %634, 16 ; <i32> [#uses=1] %636 = and i32 %635, 63 ; <i32> [#uses=1] %637 = and i32 %634, -64 ; <i32> [#uses=1] %638 = or i32 %636, %637 ; <i32> [#uses=1] %639 = inttoptr i32 %638 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %640 = getelementptr %struct.edge_rec* %174, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %641 = load %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] + %640 = getelementptr %struct.edge_rec, %struct.edge_rec* %174, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %641 = load %struct.edge_rec*, %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] %642 = ptrtoint %struct.edge_rec* %641 to i32 ; <i32> [#uses=2] %643 = add i32 %642, 16 ; <i32> [#uses=1] %644 = and i32 %643, 63 ; <i32> [#uses=1] %645 = and i32 %642, -64 ; <i32> [#uses=1] %646 = or i32 %644, %645 ; <i32> [#uses=1] %647 = inttoptr i32 %646 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %648 = getelementptr %struct.edge_rec* %647, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %649 = load %struct.edge_rec** %648, align 4 ; <%struct.edge_rec*> [#uses=1] - %650 = getelementptr %struct.edge_rec* %639, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %651 = load %struct.edge_rec** %650, align 4 ; <%struct.edge_rec*> [#uses=1] + %648 = getelementptr %struct.edge_rec, %struct.edge_rec* %647, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %649 = load %struct.edge_rec*, %struct.edge_rec** %648, align 4 ; <%struct.edge_rec*> [#uses=1] + %650 = getelementptr %struct.edge_rec, %struct.edge_rec* %639, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %651 = load %struct.edge_rec*, %struct.edge_rec** %650, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %649, %struct.edge_rec** %650, align 4 store %struct.edge_rec* %651, %struct.edge_rec** %648, align 4 - %652 = load %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] - %653 = load %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] + %652 = load %struct.edge_rec*, %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] + %653 = load %struct.edge_rec*, %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %652, %struct.edge_rec** %640, align 4 store %struct.edge_rec* %653, %struct.edge_rec** %632, align 4 %654 = add i32 %630, 48 ; <i32> [#uses=1] @@ -858,8 +858,8 @@ bb24.i: ; preds = %bb23.i, %bb21.i %656 = and i32 %598, -64 ; <i32> [#uses=1] %657 = or i32 %655, %656 ; <i32> [#uses=1] %658 = inttoptr i32 %657 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %659 = getelementptr %struct.edge_rec* %658, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %660 = load %struct.edge_rec** %659, align 4 ; <%struct.edge_rec*> [#uses=1] + %659 = getelementptr %struct.edge_rec, %struct.edge_rec* %658, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %660 = load %struct.edge_rec*, %struct.edge_rec** %659, align 4 ; <%struct.edge_rec*> [#uses=1] %661 = ptrtoint %struct.edge_rec* %660 to i32 ; <i32> [#uses=2] %662 = add i32 %661, 16 ; <i32> [#uses=1] %663 = and i32 %662, 63 ; <i32> [#uses=1] @@ -874,8 +874,8 @@ bb25.i: ; preds = %bb23.i, %bb22.i %669 = and i32 %172, -64 ; <i32> [#uses=1] %670 = or i32 %668, %669 ; <i32> [#uses=1] %671 = inttoptr i32 %670 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %672 = getelementptr %struct.edge_rec* %671, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %673 = load %struct.edge_rec** %672, align 4 ; <%struct.edge_rec*> [#uses=1] + %672 = getelementptr %struct.edge_rec, %struct.edge_rec* %671, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %673 = load %struct.edge_rec*, %struct.edge_rec** %672, align 4 ; <%struct.edge_rec*> [#uses=1] %674 = ptrtoint %struct.edge_rec* %673 to i32 ; <i32> [#uses=2] %675 = add i32 %674, 16 ; <i32> [#uses=1] %676 = and i32 %675, 63 ; <i32> [#uses=1] @@ -883,84 +883,84 @@ bb25.i: ; preds = %bb23.i, %bb22.i %678 = or i32 %676, %677 ; <i32> [#uses=1] %679 = inttoptr i32 %678 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %680 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] - %681 = getelementptr %struct.edge_rec* %680, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=5] + %681 = getelementptr %struct.edge_rec, %struct.edge_rec* %680, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=5] store %struct.edge_rec* %680, %struct.edge_rec** %681, align 4 - %682 = getelementptr %struct.edge_rec* %680, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %682 = getelementptr %struct.edge_rec, %struct.edge_rec* %680, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %501, %struct.VERTEX** %682, align 4 %683 = ptrtoint %struct.edge_rec* %680 to i32 ; <i32> [#uses=4] %684 = add i32 %683, 16 ; <i32> [#uses=1] %685 = inttoptr i32 %684 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %686 = add i32 %683, 48 ; <i32> [#uses=1] %687 = inttoptr i32 %686 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %688 = getelementptr %struct.edge_rec* %685, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %688 = getelementptr %struct.edge_rec, %struct.edge_rec* %685, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %687, %struct.edge_rec** %688, align 4 %689 = add i32 %683, 32 ; <i32> [#uses=1] %690 = inttoptr i32 %689 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %691 = getelementptr %struct.edge_rec* %690, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %691 = getelementptr %struct.edge_rec, %struct.edge_rec* %690, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %690, %struct.edge_rec** %691, align 4 - %692 = getelementptr %struct.edge_rec* %690, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %692 = getelementptr %struct.edge_rec, %struct.edge_rec* %690, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %496, %struct.VERTEX** %692, align 4 - %693 = getelementptr %struct.edge_rec* %687, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %693 = getelementptr %struct.edge_rec, %struct.edge_rec* %687, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %685, %struct.edge_rec** %693, align 4 - %694 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] + %694 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] %695 = ptrtoint %struct.edge_rec* %694 to i32 ; <i32> [#uses=2] %696 = add i32 %695, 16 ; <i32> [#uses=1] %697 = and i32 %696, 63 ; <i32> [#uses=1] %698 = and i32 %695, -64 ; <i32> [#uses=1] %699 = or i32 %697, %698 ; <i32> [#uses=1] %700 = inttoptr i32 %699 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %701 = getelementptr %struct.edge_rec* %499, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %702 = load %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] + %701 = getelementptr %struct.edge_rec, %struct.edge_rec* %499, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %702 = load %struct.edge_rec*, %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] %703 = ptrtoint %struct.edge_rec* %702 to i32 ; <i32> [#uses=2] %704 = add i32 %703, 16 ; <i32> [#uses=1] %705 = and i32 %704, 63 ; <i32> [#uses=1] %706 = and i32 %703, -64 ; <i32> [#uses=1] %707 = or i32 %705, %706 ; <i32> [#uses=1] %708 = inttoptr i32 %707 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %709 = getelementptr %struct.edge_rec* %708, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %710 = load %struct.edge_rec** %709, align 4 ; <%struct.edge_rec*> [#uses=1] - %711 = getelementptr %struct.edge_rec* %700, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %712 = load %struct.edge_rec** %711, align 4 ; <%struct.edge_rec*> [#uses=1] + %709 = getelementptr %struct.edge_rec, %struct.edge_rec* %708, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %710 = load %struct.edge_rec*, %struct.edge_rec** %709, align 4 ; <%struct.edge_rec*> [#uses=1] + %711 = getelementptr %struct.edge_rec, %struct.edge_rec* %700, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %712 = load %struct.edge_rec*, %struct.edge_rec** %711, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %710, %struct.edge_rec** %711, align 4 store %struct.edge_rec* %712, %struct.edge_rec** %709, align 4 - %713 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] - %714 = load %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] + %713 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] + %714 = load %struct.edge_rec*, %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %713, %struct.edge_rec** %701, align 4 store %struct.edge_rec* %714, %struct.edge_rec** %681, align 4 %715 = xor i32 %683, 32 ; <i32> [#uses=1] %716 = inttoptr i32 %715 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %717 = getelementptr %struct.edge_rec* %716, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %718 = load %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] + %717 = getelementptr %struct.edge_rec, %struct.edge_rec* %716, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %718 = load %struct.edge_rec*, %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] %719 = ptrtoint %struct.edge_rec* %718 to i32 ; <i32> [#uses=2] %720 = add i32 %719, 16 ; <i32> [#uses=1] %721 = and i32 %720, 63 ; <i32> [#uses=1] %722 = and i32 %719, -64 ; <i32> [#uses=1] %723 = or i32 %721, %722 ; <i32> [#uses=1] %724 = inttoptr i32 %723 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %725 = getelementptr %struct.edge_rec* %679, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %726 = load %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] + %725 = getelementptr %struct.edge_rec, %struct.edge_rec* %679, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %726 = load %struct.edge_rec*, %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] %727 = ptrtoint %struct.edge_rec* %726 to i32 ; <i32> [#uses=2] %728 = add i32 %727, 16 ; <i32> [#uses=1] %729 = and i32 %728, 63 ; <i32> [#uses=1] %730 = and i32 %727, -64 ; <i32> [#uses=1] %731 = or i32 %729, %730 ; <i32> [#uses=1] %732 = inttoptr i32 %731 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %733 = getelementptr %struct.edge_rec* %732, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %734 = load %struct.edge_rec** %733, align 4 ; <%struct.edge_rec*> [#uses=1] - %735 = getelementptr %struct.edge_rec* %724, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %736 = load %struct.edge_rec** %735, align 4 ; <%struct.edge_rec*> [#uses=1] + %733 = getelementptr %struct.edge_rec, %struct.edge_rec* %732, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %734 = load %struct.edge_rec*, %struct.edge_rec** %733, align 4 ; <%struct.edge_rec*> [#uses=1] + %735 = getelementptr %struct.edge_rec, %struct.edge_rec* %724, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %736 = load %struct.edge_rec*, %struct.edge_rec** %735, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %734, %struct.edge_rec** %735, align 4 store %struct.edge_rec* %736, %struct.edge_rec** %733, align 4 - %737 = load %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] - %738 = load %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] + %737 = load %struct.edge_rec*, %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] + %738 = load %struct.edge_rec*, %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %737, %struct.edge_rec** %725, align 4 store %struct.edge_rec* %738, %struct.edge_rec** %717, align 4 - %739 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] + %739 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] br label %bb9.i do_merge.exit: ; preds = %bb17.i - %740 = getelementptr %struct.edge_rec* %ldo_addr.0.ph.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %741 = load %struct.VERTEX** %740, align 4 ; <%struct.VERTEX*> [#uses=1] + %740 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldo_addr.0.ph.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %741 = load %struct.VERTEX*, %struct.VERTEX** %740, align 4 ; <%struct.VERTEX*> [#uses=1] %742 = icmp eq %struct.VERTEX* %741, %tree_addr.0.i ; <i1> [#uses=1] br i1 %742, label %bb5.loopexit, label %bb2 @@ -969,29 +969,29 @@ bb2: ; preds = %bb2, %do_merge.exit %743 = ptrtoint %struct.edge_rec* %ldo.07 to i32 ; <i32> [#uses=1] %744 = xor i32 %743, 32 ; <i32> [#uses=1] %745 = inttoptr i32 %744 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %746 = getelementptr %struct.edge_rec* %745, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %747 = load %struct.edge_rec** %746, align 4 ; <%struct.edge_rec*> [#uses=3] - %748 = getelementptr %struct.edge_rec* %747, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %749 = load %struct.VERTEX** %748, align 4 ; <%struct.VERTEX*> [#uses=1] + %746 = getelementptr %struct.edge_rec, %struct.edge_rec* %745, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %747 = load %struct.edge_rec*, %struct.edge_rec** %746, align 4 ; <%struct.edge_rec*> [#uses=3] + %748 = getelementptr %struct.edge_rec, %struct.edge_rec* %747, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %749 = load %struct.VERTEX*, %struct.VERTEX** %748, align 4 ; <%struct.VERTEX*> [#uses=1] %750 = icmp eq %struct.VERTEX* %749, %tree_addr.0.i ; <i1> [#uses=1] br i1 %750, label %bb5.loopexit, label %bb2 bb4: ; preds = %bb5.loopexit, %bb4 %rdo.05 = phi %struct.edge_rec* [ %755, %bb4 ], [ %rdo_addr.0.i, %bb5.loopexit ] ; <%struct.edge_rec*> [#uses=1] - %751 = getelementptr %struct.edge_rec* %rdo.05, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %752 = load %struct.edge_rec** %751, align 4 ; <%struct.edge_rec*> [#uses=1] + %751 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdo.05, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %752 = load %struct.edge_rec*, %struct.edge_rec** %751, align 4 ; <%struct.edge_rec*> [#uses=1] %753 = ptrtoint %struct.edge_rec* %752 to i32 ; <i32> [#uses=1] %754 = xor i32 %753, 32 ; <i32> [#uses=1] %755 = inttoptr i32 %754 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %756 = getelementptr %struct.edge_rec* %755, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %757 = load %struct.VERTEX** %756, align 4 ; <%struct.VERTEX*> [#uses=1] + %756 = getelementptr %struct.edge_rec, %struct.edge_rec* %755, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %757 = load %struct.VERTEX*, %struct.VERTEX** %756, align 4 ; <%struct.VERTEX*> [#uses=1] %758 = icmp eq %struct.VERTEX* %757, %extra ; <i1> [#uses=1] br i1 %758, label %bb6, label %bb4 bb5.loopexit: ; preds = %bb2, %do_merge.exit %ldo.0.lcssa = phi %struct.edge_rec* [ %ldo_addr.0.ph.i, %do_merge.exit ], [ %747, %bb2 ] ; <%struct.edge_rec*> [#uses=1] - %759 = getelementptr %struct.edge_rec* %rdo_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %760 = load %struct.VERTEX** %759, align 4 ; <%struct.VERTEX*> [#uses=1] + %759 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdo_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %760 = load %struct.VERTEX*, %struct.VERTEX** %759, align 4 ; <%struct.VERTEX*> [#uses=1] %761 = icmp eq %struct.VERTEX* %760, %extra ; <i1> [#uses=1] br i1 %761, label %bb6, label %bb4 @@ -1002,17 +1002,17 @@ bb6: ; preds = %bb5.loopexit, %bb4 br label %bb15 bb7: ; preds = %bb - %762 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] - %763 = load %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] + %762 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] + %763 = load %struct.VERTEX*, %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] %764 = icmp eq %struct.VERTEX* %763, null ; <i1> [#uses=1] %765 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] - %766 = getelementptr %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] + %766 = getelementptr %struct.edge_rec, %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %765, %struct.edge_rec** %766, align 4 - %767 = getelementptr %struct.edge_rec* %765, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] + %767 = getelementptr %struct.edge_rec, %struct.edge_rec* %765, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] br i1 %764, label %bb10, label %bb11 bb8: ; preds = %entry - %768 = call i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] + %768 = call i32 @puts(i8* getelementptr ([21 x i8], [21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] call void @exit(i32 -1) noreturn nounwind unreachable @@ -1023,15 +1023,15 @@ bb10: ; preds = %bb7 %771 = inttoptr i32 %770 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %772 = add i32 %769, 48 ; <i32> [#uses=1] %773 = inttoptr i32 %772 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %774 = getelementptr %struct.edge_rec* %771, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %774 = getelementptr %struct.edge_rec, %struct.edge_rec* %771, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %773, %struct.edge_rec** %774, align 4 %775 = add i32 %769, 32 ; <i32> [#uses=1] %776 = inttoptr i32 %775 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %777 = getelementptr %struct.edge_rec* %776, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %777 = getelementptr %struct.edge_rec, %struct.edge_rec* %776, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %776, %struct.edge_rec** %777, align 4 - %778 = getelementptr %struct.edge_rec* %776, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %778 = getelementptr %struct.edge_rec, %struct.edge_rec* %776, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %extra, %struct.VERTEX** %778, align 4 - %779 = getelementptr %struct.edge_rec* %773, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %779 = getelementptr %struct.edge_rec, %struct.edge_rec* %773, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %771, %struct.edge_rec** %779, align 4 %780 = xor i32 %769, 32 ; <i32> [#uses=1] br label %bb15 @@ -1043,164 +1043,164 @@ bb11: ; preds = %bb7 %783 = inttoptr i32 %782 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %784 = add i32 %781, 48 ; <i32> [#uses=1] %785 = inttoptr i32 %784 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %786 = getelementptr %struct.edge_rec* %783, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %786 = getelementptr %struct.edge_rec, %struct.edge_rec* %783, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %785, %struct.edge_rec** %786, align 4 %787 = add i32 %781, 32 ; <i32> [#uses=1] %788 = inttoptr i32 %787 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %789 = getelementptr %struct.edge_rec* %788, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %789 = getelementptr %struct.edge_rec, %struct.edge_rec* %788, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %788, %struct.edge_rec** %789, align 4 - %790 = getelementptr %struct.edge_rec* %788, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %790 = getelementptr %struct.edge_rec, %struct.edge_rec* %788, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %tree, %struct.VERTEX** %790, align 4 - %791 = getelementptr %struct.edge_rec* %785, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %791 = getelementptr %struct.edge_rec, %struct.edge_rec* %785, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %783, %struct.edge_rec** %791, align 4 %792 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] - %793 = getelementptr %struct.edge_rec* %792, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] + %793 = getelementptr %struct.edge_rec, %struct.edge_rec* %792, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %792, %struct.edge_rec** %793, align 4 - %794 = getelementptr %struct.edge_rec* %792, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %794 = getelementptr %struct.edge_rec, %struct.edge_rec* %792, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %tree, %struct.VERTEX** %794, align 4 %795 = ptrtoint %struct.edge_rec* %792 to i32 ; <i32> [#uses=5] %796 = add i32 %795, 16 ; <i32> [#uses=1] %797 = inttoptr i32 %796 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %798 = add i32 %795, 48 ; <i32> [#uses=2] %799 = inttoptr i32 %798 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %800 = getelementptr %struct.edge_rec* %797, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %800 = getelementptr %struct.edge_rec, %struct.edge_rec* %797, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %799, %struct.edge_rec** %800, align 4 %801 = add i32 %795, 32 ; <i32> [#uses=1] %802 = inttoptr i32 %801 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %803 = getelementptr %struct.edge_rec* %802, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %803 = getelementptr %struct.edge_rec, %struct.edge_rec* %802, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %802, %struct.edge_rec** %803, align 4 - %804 = getelementptr %struct.edge_rec* %802, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %804 = getelementptr %struct.edge_rec, %struct.edge_rec* %802, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %extra, %struct.VERTEX** %804, align 4 - %805 = getelementptr %struct.edge_rec* %799, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %805 = getelementptr %struct.edge_rec, %struct.edge_rec* %799, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %797, %struct.edge_rec** %805, align 4 %806 = xor i32 %781, 32 ; <i32> [#uses=1] %807 = inttoptr i32 %806 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %808 = getelementptr %struct.edge_rec* %807, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %809 = load %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] + %808 = getelementptr %struct.edge_rec, %struct.edge_rec* %807, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %809 = load %struct.edge_rec*, %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] %810 = ptrtoint %struct.edge_rec* %809 to i32 ; <i32> [#uses=2] %811 = add i32 %810, 16 ; <i32> [#uses=1] %812 = and i32 %811, 63 ; <i32> [#uses=1] %813 = and i32 %810, -64 ; <i32> [#uses=1] %814 = or i32 %812, %813 ; <i32> [#uses=1] %815 = inttoptr i32 %814 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %816 = load %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] + %816 = load %struct.edge_rec*, %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] %817 = ptrtoint %struct.edge_rec* %816 to i32 ; <i32> [#uses=2] %818 = add i32 %817, 16 ; <i32> [#uses=1] %819 = and i32 %818, 63 ; <i32> [#uses=1] %820 = and i32 %817, -64 ; <i32> [#uses=1] %821 = or i32 %819, %820 ; <i32> [#uses=1] %822 = inttoptr i32 %821 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %823 = getelementptr %struct.edge_rec* %822, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %824 = load %struct.edge_rec** %823, align 4 ; <%struct.edge_rec*> [#uses=1] - %825 = getelementptr %struct.edge_rec* %815, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %826 = load %struct.edge_rec** %825, align 4 ; <%struct.edge_rec*> [#uses=1] + %823 = getelementptr %struct.edge_rec, %struct.edge_rec* %822, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %824 = load %struct.edge_rec*, %struct.edge_rec** %823, align 4 ; <%struct.edge_rec*> [#uses=1] + %825 = getelementptr %struct.edge_rec, %struct.edge_rec* %815, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %826 = load %struct.edge_rec*, %struct.edge_rec** %825, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %824, %struct.edge_rec** %825, align 4 store %struct.edge_rec* %826, %struct.edge_rec** %823, align 4 - %827 = load %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] - %828 = load %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] + %827 = load %struct.edge_rec*, %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] + %828 = load %struct.edge_rec*, %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %827, %struct.edge_rec** %793, align 4 store %struct.edge_rec* %828, %struct.edge_rec** %808, align 4 %829 = xor i32 %795, 32 ; <i32> [#uses=3] %830 = inttoptr i32 %829 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %831 = getelementptr %struct.edge_rec* %830, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %832 = load %struct.VERTEX** %831, align 4 ; <%struct.VERTEX*> [#uses=1] + %831 = getelementptr %struct.edge_rec, %struct.edge_rec* %830, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %832 = load %struct.VERTEX*, %struct.VERTEX** %831, align 4 ; <%struct.VERTEX*> [#uses=1] %833 = and i32 %798, 63 ; <i32> [#uses=1] %834 = and i32 %795, -64 ; <i32> [#uses=1] %835 = or i32 %833, %834 ; <i32> [#uses=1] %836 = inttoptr i32 %835 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %837 = getelementptr %struct.edge_rec* %836, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %838 = load %struct.edge_rec** %837, align 4 ; <%struct.edge_rec*> [#uses=1] + %837 = getelementptr %struct.edge_rec, %struct.edge_rec* %836, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %838 = load %struct.edge_rec*, %struct.edge_rec** %837, align 4 ; <%struct.edge_rec*> [#uses=1] %839 = ptrtoint %struct.edge_rec* %838 to i32 ; <i32> [#uses=2] %840 = add i32 %839, 16 ; <i32> [#uses=1] %841 = and i32 %840, 63 ; <i32> [#uses=1] %842 = and i32 %839, -64 ; <i32> [#uses=1] %843 = or i32 %841, %842 ; <i32> [#uses=1] %844 = inttoptr i32 %843 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %845 = load %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] + %845 = load %struct.VERTEX*, %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] %846 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] - %847 = getelementptr %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7] + %847 = getelementptr %struct.edge_rec, %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7] store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4 - %848 = getelementptr %struct.edge_rec* %846, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %848 = getelementptr %struct.edge_rec, %struct.edge_rec* %846, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %832, %struct.VERTEX** %848, align 4 %849 = ptrtoint %struct.edge_rec* %846 to i32 ; <i32> [#uses=6] %850 = add i32 %849, 16 ; <i32> [#uses=2] %851 = inttoptr i32 %850 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %852 = add i32 %849, 48 ; <i32> [#uses=1] %853 = inttoptr i32 %852 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %854 = getelementptr %struct.edge_rec* %851, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %854 = getelementptr %struct.edge_rec, %struct.edge_rec* %851, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %853, %struct.edge_rec** %854, align 4 %855 = add i32 %849, 32 ; <i32> [#uses=1] %856 = inttoptr i32 %855 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] - %857 = getelementptr %struct.edge_rec* %856, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %857 = getelementptr %struct.edge_rec, %struct.edge_rec* %856, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %856, %struct.edge_rec** %857, align 4 - %858 = getelementptr %struct.edge_rec* %856, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] + %858 = getelementptr %struct.edge_rec, %struct.edge_rec* %856, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] store %struct.VERTEX* %845, %struct.VERTEX** %858, align 4 - %859 = getelementptr %struct.edge_rec* %853, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %859 = getelementptr %struct.edge_rec, %struct.edge_rec* %853, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %851, %struct.edge_rec** %859, align 4 - %860 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %860 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] %861 = ptrtoint %struct.edge_rec* %860 to i32 ; <i32> [#uses=2] %862 = add i32 %861, 16 ; <i32> [#uses=1] %863 = and i32 %862, 63 ; <i32> [#uses=1] %864 = and i32 %861, -64 ; <i32> [#uses=1] %865 = or i32 %863, %864 ; <i32> [#uses=1] %866 = inttoptr i32 %865 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %867 = getelementptr %struct.edge_rec* %844, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %868 = load %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] + %867 = getelementptr %struct.edge_rec, %struct.edge_rec* %844, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %868 = load %struct.edge_rec*, %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] %869 = ptrtoint %struct.edge_rec* %868 to i32 ; <i32> [#uses=2] %870 = add i32 %869, 16 ; <i32> [#uses=1] %871 = and i32 %870, 63 ; <i32> [#uses=1] %872 = and i32 %869, -64 ; <i32> [#uses=1] %873 = or i32 %871, %872 ; <i32> [#uses=1] %874 = inttoptr i32 %873 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %875 = getelementptr %struct.edge_rec* %874, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %876 = load %struct.edge_rec** %875, align 4 ; <%struct.edge_rec*> [#uses=1] - %877 = getelementptr %struct.edge_rec* %866, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %878 = load %struct.edge_rec** %877, align 4 ; <%struct.edge_rec*> [#uses=1] + %875 = getelementptr %struct.edge_rec, %struct.edge_rec* %874, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %876 = load %struct.edge_rec*, %struct.edge_rec** %875, align 4 ; <%struct.edge_rec*> [#uses=1] + %877 = getelementptr %struct.edge_rec, %struct.edge_rec* %866, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %878 = load %struct.edge_rec*, %struct.edge_rec** %877, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %876, %struct.edge_rec** %877, align 4 store %struct.edge_rec* %878, %struct.edge_rec** %875, align 4 - %879 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] - %880 = load %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] + %879 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %880 = load %struct.edge_rec*, %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %879, %struct.edge_rec** %867, align 4 store %struct.edge_rec* %880, %struct.edge_rec** %847, align 4 %881 = xor i32 %849, 32 ; <i32> [#uses=3] %882 = inttoptr i32 %881 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %883 = getelementptr %struct.edge_rec* %882, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=6] - %884 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %883 = getelementptr %struct.edge_rec, %struct.edge_rec* %882, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=6] + %884 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] %885 = ptrtoint %struct.edge_rec* %884 to i32 ; <i32> [#uses=2] %886 = add i32 %885, 16 ; <i32> [#uses=1] %887 = and i32 %886, 63 ; <i32> [#uses=1] %888 = and i32 %885, -64 ; <i32> [#uses=1] %889 = or i32 %887, %888 ; <i32> [#uses=1] %890 = inttoptr i32 %889 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %891 = load %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] + %891 = load %struct.edge_rec*, %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] %892 = ptrtoint %struct.edge_rec* %891 to i32 ; <i32> [#uses=2] %893 = add i32 %892, 16 ; <i32> [#uses=1] %894 = and i32 %893, 63 ; <i32> [#uses=1] %895 = and i32 %892, -64 ; <i32> [#uses=1] %896 = or i32 %894, %895 ; <i32> [#uses=1] %897 = inttoptr i32 %896 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %898 = getelementptr %struct.edge_rec* %897, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %899 = load %struct.edge_rec** %898, align 4 ; <%struct.edge_rec*> [#uses=1] - %900 = getelementptr %struct.edge_rec* %890, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %901 = load %struct.edge_rec** %900, align 4 ; <%struct.edge_rec*> [#uses=1] + %898 = getelementptr %struct.edge_rec, %struct.edge_rec* %897, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %899 = load %struct.edge_rec*, %struct.edge_rec** %898, align 4 ; <%struct.edge_rec*> [#uses=1] + %900 = getelementptr %struct.edge_rec, %struct.edge_rec* %890, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %901 = load %struct.edge_rec*, %struct.edge_rec** %900, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %899, %struct.edge_rec** %900, align 4 store %struct.edge_rec* %901, %struct.edge_rec** %898, align 4 - %902 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] - %903 = load %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] + %902 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %903 = load %struct.edge_rec*, %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %902, %struct.edge_rec** %766, align 4 store %struct.edge_rec* %903, %struct.edge_rec** %883, align 4 - %904 = getelementptr %struct.VERTEX* %763, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %905 = load double* %904, align 4 ; <double> [#uses=2] - %906 = getelementptr %struct.VERTEX* %763, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %907 = load double* %906, align 4 ; <double> [#uses=2] - %908 = getelementptr %struct.VERTEX* %extra, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %909 = load double* %908, align 4 ; <double> [#uses=3] - %910 = getelementptr %struct.VERTEX* %extra, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %911 = load double* %910, align 4 ; <double> [#uses=3] - %912 = getelementptr %struct.VERTEX* %tree, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %913 = load double* %912, align 4 ; <double> [#uses=3] - %914 = getelementptr %struct.VERTEX* %tree, i32 0, i32 0, i32 1 ; <double*> [#uses=1] - %915 = load double* %914, align 4 ; <double> [#uses=3] + %904 = getelementptr %struct.VERTEX, %struct.VERTEX* %763, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %905 = load double, double* %904, align 4 ; <double> [#uses=2] + %906 = getelementptr %struct.VERTEX, %struct.VERTEX* %763, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %907 = load double, double* %906, align 4 ; <double> [#uses=2] + %908 = getelementptr %struct.VERTEX, %struct.VERTEX* %extra, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %909 = load double, double* %908, align 4 ; <double> [#uses=3] + %910 = getelementptr %struct.VERTEX, %struct.VERTEX* %extra, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %911 = load double, double* %910, align 4 ; <double> [#uses=3] + %912 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 0, i32 0 ; <double*> [#uses=1] + %913 = load double, double* %912, align 4 ; <double> [#uses=3] + %914 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 0, i32 1 ; <double*> [#uses=1] + %915 = load double, double* %914, align 4 ; <double> [#uses=3] %916 = fsub double %905, %913 ; <double> [#uses=1] %917 = fsub double %911, %915 ; <double> [#uses=1] %918 = fmul double %916, %917 ; <double> [#uses=1] @@ -1227,79 +1227,79 @@ bb14: ; preds = %bb13 %933 = and i32 %849, -64 ; <i32> [#uses=3] %934 = or i32 %932, %933 ; <i32> [#uses=1] %935 = inttoptr i32 %934 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %936 = getelementptr %struct.edge_rec* %935, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %937 = load %struct.edge_rec** %936, align 4 ; <%struct.edge_rec*> [#uses=1] + %936 = getelementptr %struct.edge_rec, %struct.edge_rec* %935, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %937 = load %struct.edge_rec*, %struct.edge_rec** %936, align 4 ; <%struct.edge_rec*> [#uses=1] %938 = ptrtoint %struct.edge_rec* %937 to i32 ; <i32> [#uses=2] %939 = add i32 %938, 16 ; <i32> [#uses=1] %940 = and i32 %939, 63 ; <i32> [#uses=1] %941 = and i32 %938, -64 ; <i32> [#uses=1] %942 = or i32 %940, %941 ; <i32> [#uses=1] %943 = inttoptr i32 %942 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %944 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %944 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] %945 = ptrtoint %struct.edge_rec* %944 to i32 ; <i32> [#uses=2] %946 = add i32 %945, 16 ; <i32> [#uses=1] %947 = and i32 %946, 63 ; <i32> [#uses=1] %948 = and i32 %945, -64 ; <i32> [#uses=1] %949 = or i32 %947, %948 ; <i32> [#uses=1] %950 = inttoptr i32 %949 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %951 = getelementptr %struct.edge_rec* %943, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %952 = load %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] + %951 = getelementptr %struct.edge_rec, %struct.edge_rec* %943, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %952 = load %struct.edge_rec*, %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] %953 = ptrtoint %struct.edge_rec* %952 to i32 ; <i32> [#uses=2] %954 = add i32 %953, 16 ; <i32> [#uses=1] %955 = and i32 %954, 63 ; <i32> [#uses=1] %956 = and i32 %953, -64 ; <i32> [#uses=1] %957 = or i32 %955, %956 ; <i32> [#uses=1] %958 = inttoptr i32 %957 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %959 = getelementptr %struct.edge_rec* %958, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %960 = load %struct.edge_rec** %959, align 4 ; <%struct.edge_rec*> [#uses=1] - %961 = getelementptr %struct.edge_rec* %950, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %962 = load %struct.edge_rec** %961, align 4 ; <%struct.edge_rec*> [#uses=1] + %959 = getelementptr %struct.edge_rec, %struct.edge_rec* %958, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %960 = load %struct.edge_rec*, %struct.edge_rec** %959, align 4 ; <%struct.edge_rec*> [#uses=1] + %961 = getelementptr %struct.edge_rec, %struct.edge_rec* %950, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %962 = load %struct.edge_rec*, %struct.edge_rec** %961, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %960, %struct.edge_rec** %961, align 4 store %struct.edge_rec* %962, %struct.edge_rec** %959, align 4 - %963 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] - %964 = load %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] + %963 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %964 = load %struct.edge_rec*, %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %963, %struct.edge_rec** %951, align 4 store %struct.edge_rec* %964, %struct.edge_rec** %847, align 4 %965 = add i32 %881, 16 ; <i32> [#uses=1] %966 = and i32 %965, 63 ; <i32> [#uses=1] %967 = or i32 %966, %933 ; <i32> [#uses=1] %968 = inttoptr i32 %967 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %969 = getelementptr %struct.edge_rec* %968, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %970 = load %struct.edge_rec** %969, align 4 ; <%struct.edge_rec*> [#uses=1] + %969 = getelementptr %struct.edge_rec, %struct.edge_rec* %968, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %970 = load %struct.edge_rec*, %struct.edge_rec** %969, align 4 ; <%struct.edge_rec*> [#uses=1] %971 = ptrtoint %struct.edge_rec* %970 to i32 ; <i32> [#uses=2] %972 = add i32 %971, 16 ; <i32> [#uses=1] %973 = and i32 %972, 63 ; <i32> [#uses=1] %974 = and i32 %971, -64 ; <i32> [#uses=1] %975 = or i32 %973, %974 ; <i32> [#uses=1] %976 = inttoptr i32 %975 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %977 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %977 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] %978 = ptrtoint %struct.edge_rec* %977 to i32 ; <i32> [#uses=2] %979 = add i32 %978, 16 ; <i32> [#uses=1] %980 = and i32 %979, 63 ; <i32> [#uses=1] %981 = and i32 %978, -64 ; <i32> [#uses=1] %982 = or i32 %980, %981 ; <i32> [#uses=1] %983 = inttoptr i32 %982 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %984 = getelementptr %struct.edge_rec* %976, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %985 = load %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] + %984 = getelementptr %struct.edge_rec, %struct.edge_rec* %976, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] + %985 = load %struct.edge_rec*, %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] %986 = ptrtoint %struct.edge_rec* %985 to i32 ; <i32> [#uses=2] %987 = add i32 %986, 16 ; <i32> [#uses=1] %988 = and i32 %987, 63 ; <i32> [#uses=1] %989 = and i32 %986, -64 ; <i32> [#uses=1] %990 = or i32 %988, %989 ; <i32> [#uses=1] %991 = inttoptr i32 %990 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %992 = getelementptr %struct.edge_rec* %991, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %993 = load %struct.edge_rec** %992, align 4 ; <%struct.edge_rec*> [#uses=1] - %994 = getelementptr %struct.edge_rec* %983, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %995 = load %struct.edge_rec** %994, align 4 ; <%struct.edge_rec*> [#uses=1] + %992 = getelementptr %struct.edge_rec, %struct.edge_rec* %991, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %993 = load %struct.edge_rec*, %struct.edge_rec** %992, align 4 ; <%struct.edge_rec*> [#uses=1] + %994 = getelementptr %struct.edge_rec, %struct.edge_rec* %983, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] + %995 = load %struct.edge_rec*, %struct.edge_rec** %994, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %993, %struct.edge_rec** %994, align 4 store %struct.edge_rec* %995, %struct.edge_rec** %992, align 4 - %996 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] - %997 = load %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] + %996 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %997 = load %struct.edge_rec*, %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %996, %struct.edge_rec** %984, align 4 store %struct.edge_rec* %997, %struct.edge_rec** %883, align 4 %998 = inttoptr i32 %933 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %999 = load %struct.edge_rec** @avail_edge, align 4 ; <%struct.edge_rec*> [#uses=1] - %1000 = getelementptr %struct.edge_rec* %998, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] + %999 = load %struct.edge_rec*, %struct.edge_rec** @avail_edge, align 4 ; <%struct.edge_rec*> [#uses=1] + %1000 = getelementptr %struct.edge_rec, %struct.edge_rec* %998, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %999, %struct.edge_rec** %1000, align 4 store %struct.edge_rec* %998, %struct.edge_rec** @avail_edge, align 4 br label %bb15 diff --git a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll index d477ba9835be..d746b104baf8 100644 --- a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -83,7 +83,7 @@ bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 bb52: ; preds = %cli_calloc.exit - %0 = load i16* undef, align 4 ; <i16> [#uses=1] + %0 = load i16, i16* undef, align 4 ; <i16> [#uses=1] %1 = icmp eq i16 %0, 0 ; <i1> [#uses=1] %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; <i8*> [#uses=1] %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] diff --git a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll index bc4a95c3e00b..156fd8843bcf 100644 --- a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -65,9 +65,9 @@ bb18: ; preds = %bb18, %bb.nph br i1 undef, label %bb18, label %bb22 bb22: ; preds = %bb18, %bb17 - %0 = getelementptr i8* null, i32 10 ; <i8*> [#uses=1] + %0 = getelementptr i8, i8* null, i32 10 ; <i8*> [#uses=1] %1 = bitcast i8* %0 to i16* ; <i16*> [#uses=1] - %2 = load i16* %1, align 2 ; <i16> [#uses=1] + %2 = load i16, i16* %1, align 2 ; <i16> [#uses=1] %3 = add i16 %2, 1 ; <i16> [#uses=1] %4 = zext i16 %3 to i32 ; <i32> [#uses=1] %5 = mul i32 %4, 3 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll index 5003fbdedb27..01591c80362d 100644 --- a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -12,7 +12,7 @@ bb: ; preds = %bb, %entry br i1 undef, label %bb28, label %bb bb28: ; preds = %bb - %0 = load double* @a, align 4 ; <double> [#uses=2] + %0 = load double, double* @a, align 4 ; <double> [#uses=2] %1 = fadd double %0, undef ; <double> [#uses=2] br i1 undef, label %bb59, label %bb60 diff --git a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll index a656c495f796..e277b4cf91a6 100644 --- a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll +++ b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @@ -13,17 +13,17 @@ entry: %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store <4 x i32> %v, <4 x i32>* %v_addr store i32 %f, i32* %f_addr - %1 = load <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1] - %2 = load i32* %f_addr, align 4 ; <i32> [#uses=1] + %1 = load <4 x i32>, <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1] + %2 = load i32, i32* %f_addr, align 4 ; <i32> [#uses=1] %3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1] %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1] %5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1] store <4 x i32> %5, <4 x i32>* %0, align 16 - %6 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %6 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] store <4 x i32> %6, <4 x i32>* %retval, align 16 br label %return return: ; preds = %entry - %retval1 = load <4 x i32>* %retval ; <<4 x i32>> [#uses=1] + %retval1 = load <4 x i32>, <4 x i32>* %retval ; <<4 x i32>> [#uses=1] ret <4 x i32> %retval1 } diff --git a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll index 4b4101556f18..a5e9692a0082 100644 --- a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll +++ b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll @@ -28,8 +28,8 @@ bb7: ; preds = %bb2 bb8: ; preds = %bb7, %entry %2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; <i32> [#uses=3] - %scevgep22 = getelementptr %struct.iovec* %iov, i32 %2, i32 0; <i8**> [#uses=0] - %3 = load i32* %nr_segs, align 4 ; <i32> [#uses=1] + %scevgep22 = getelementptr %struct.iovec, %struct.iovec* %iov, i32 %2, i32 0; <i8**> [#uses=0] + %3 = load i32, i32* %nr_segs, align 4 ; <i32> [#uses=1] %4 = icmp ult i32 %2, %3 ; <i1> [#uses=1] br i1 %4, label %bb, label %bb9 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll index c598fe6e2e1a..0d258e66b7e0 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -9,18 +9,18 @@ target triple = "armv7-apple-darwin9" define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { entry: - %t.idx51.val.i = load double* null ; <double> [#uses=1] + %t.idx51.val.i = load double, double* null ; <double> [#uses=1] br i1 undef, label %bb4.i, label %bb.i bb.i: ; preds = %entry unreachable bb4.i: ; preds = %entry - %0 = load %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2] - %.idx45.i = getelementptr %struct.tree* %0, i32 0, i32 1 ; <double*> [#uses=1] - %.idx45.val.i = load double* %.idx45.i ; <double> [#uses=1] - %.idx46.i = getelementptr %struct.tree* %0, i32 0, i32 2 ; <double*> [#uses=1] - %.idx46.val.i = load double* %.idx46.i ; <double> [#uses=1] + %0 = load %struct.tree*, %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2] + %.idx45.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 1 ; <double*> [#uses=1] + %.idx45.val.i = load double, double* %.idx45.i ; <double> [#uses=1] + %.idx46.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 2 ; <double*> [#uses=1] + %.idx46.val.i = load double, double* %.idx46.i ; <double> [#uses=1] %1 = fsub double 0.000000e+00, %.idx45.val.i ; <double> [#uses=2] %2 = fmul double %1, %1 ; <double> [#uses=1] %3 = fsub double %t.idx51.val.i, %.idx46.val.i ; <double> [#uses=2] diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll index cc92c26aeece..489d4e45236c 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll @@ -32,7 +32,7 @@ bb9: ; preds = %bb7 br label %bb11 bb11: ; preds = %bb9, %bb7 - %1 = getelementptr %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] + %1 = getelementptr %struct.icstruct, %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] store i32 0, i32* %1 ret void } diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll index 382038eb13ef..133fc0588a91 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll @@ -14,14 +14,14 @@ entry: br i1 %p, label %bb8, label %bb1 bb1: ; preds = %entry - %malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village* null, i32 1) to i32)) + %malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village, %struct.Village* null, i32 1) to i32)) %0 = bitcast i8* %malloccall to %struct.Village* %exp2 = call double @ldexp(double 1.000000e+00, i32 %level) nounwind ; <double> [#uses=1] %.c = fptosi double %exp2 to i32 ; <i32> [#uses=1] store i32 %.c, i32* null - %1 = getelementptr %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1] + %1 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1] store %struct.List* null, %struct.List** %1 - %2 = getelementptr %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1] + %2 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1] store %struct.List* null, %struct.List** %2 ret %struct.Village* %0 diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index a016809857e7..2f6e428351d7 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -1,7 +1,9 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin9 -march=arm | FileCheck %s -; CHECK: L_LSDA_0: - +; CHECK: .cfi_lsda 16, [[LABEL:.*]] +; CHECK: .long [[LABEL]]- +; CHECK: [[LABEL]]: +; CHECK: .byte 255 @ @LPStart Encoding = omit %struct.A = type { i32* } @@ -22,14 +24,14 @@ invcont: ; preds = %entry br label %return bb: ; preds = %ppad - %eh_select = load i32* %eh_selector + %eh_select = load i32, i32* %eh_selector store i32 %eh_select, i32* %save_filt.1, align 4 - %eh_value = load i8** %eh_exception + %eh_value = load i8*, i8** %eh_exception store i8* %eh_value, i8** %save_eptr.0, align 4 call void @_ZN1AD1Ev(%struct.A* %a) nounwind - %0 = load i8** %save_eptr.0, align 4 + %0 = load i8*, i8** %save_eptr.0, align 4 store i8* %0, i8** %eh_exception, align 4 - %1 = load i32* %save_filt.1, align 4 + %1 = load i32, i32* %save_filt.1, align 4 store i32 %1, i32* %eh_selector, align 4 br label %Unwind @@ -49,7 +51,7 @@ ppad: ; preds = %lpad br label %bb Unwind: ; preds = %bb - %eh_ptr3 = load i8** %eh_exception + %eh_ptr3 = load i8*, i8** %eh_exception call void @_Unwind_SjLj_Resume(i8* %eh_ptr3) unreachable } @@ -61,8 +63,8 @@ entry: store %struct.A* %this, %struct.A** %this_addr %0 = call i8* @_Znwm(i32 4) %1 = bitcast i8* %0 to i32* - %2 = load %struct.A** %this_addr, align 4 - %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0 + %2 = load %struct.A*, %struct.A** %this_addr, align 4 + %3 = getelementptr inbounds %struct.A, %struct.A* %2, i32 0, i32 0 store i32* %1, i32** %3, align 4 br label %return @@ -77,9 +79,9 @@ entry: %this_addr = alloca %struct.A* %"alloca point" = bitcast i32 0 to i32 store %struct.A* %this, %struct.A** %this_addr - %0 = load %struct.A** %this_addr, align 4 - %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0 - %2 = load i32** %1, align 4 + %0 = load %struct.A*, %struct.A** %this_addr, align 4 + %1 = getelementptr inbounds %struct.A, %struct.A* %0, i32 0, i32 0 + %2 = load i32*, i32** %1, align 4 %3 = bitcast i32* %2 to i8* call void @_ZdlPv(i8* %3) nounwind br label %bb diff --git a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll index b078ec06dbb8..a6d128d9e0ce 100644 --- a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll +++ b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll @@ -4,7 +4,7 @@ define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind { ;CHECK-LABEL: v2regbug: ;CHECK: vzip.16 - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1> ret <4 x i16> %tmp2 } diff --git a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll index 426bd17590b7..4437d37e9f4a 100644 --- a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll +++ b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll @@ -2,8 +2,8 @@ ; pr4939 define void @test(double* %x, double* %y) nounwind { - %1 = load double* %x - %2 = load double* %y + %1 = load double, double* %x + %2 = load double, double* %y %3 = fsub double -0.000000e+00, %1 %4 = fcmp ugt double %2, %3 br i1 %4, label %bb1, label %bb2 diff --git a/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll index 13adb24e2f6f..de927a8f8b66 100644 --- a/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll +++ b/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll @@ -13,10 +13,10 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwin define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind { entry: - %val.i.i = load <4 x float>* undef ; <<4 x float>> [#uses=1] - %val2.i.i = load <4 x float>* null ; <<4 x float>> [#uses=1] - %elt3.i.i = getelementptr inbounds %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1] - %val4.i.i = load <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1] + %val.i.i = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1] + %val2.i.i = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1] + %elt3.i.i = getelementptr inbounds %struct.obb, %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1] + %val4.i.i = load <4 x float>, <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1] %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] %1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1] br label %bb33 diff --git a/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll index dd9a6fd12d7e..b8a1479fd34c 100644 --- a/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll +++ b/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll @@ -16,13 +16,13 @@ define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) n %tmp3738 = inttoptr i32 %tmp37 to float* %tmp39 = add i32 %1, 24 %tmp3940 = inttoptr i32 %tmp39 to float* - %2 = load float* %lsr.iv2641, align 4 - %3 = load float* %tmp2930, align 4 - %4 = load float* %tmp3132, align 4 - %5 = load float* %tmp3334, align 4 - %6 = load float* %tmp3536, align 4 - %7 = load float* %tmp3738, align 4 - %8 = load float* %tmp3940, align 4 + %2 = load float, float* %lsr.iv2641, align 4 + %3 = load float, float* %tmp2930, align 4 + %4 = load float, float* %tmp3132, align 4 + %5 = load float, float* %tmp3334, align 4 + %6 = load float, float* %tmp3536, align 4 + %7 = load float, float* %tmp3738, align 4 + %8 = load float, float* %tmp3940, align 4 %9 = insertelement <4 x float> undef, float %6, i32 0 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer %11 = insertelement <4 x float> %10, float %7, i32 1 diff --git a/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll b/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll index 2ff479b21781..4bbd04705643 100644 --- a/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll +++ b/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll @@ -9,7 +9,7 @@ define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation. entry: %0 = call arm_aapcs_vfpcc %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0] %1 = call arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0] - %val92 = load <4 x float>* null ; <<4 x float>> [#uses=1] + %val92 = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1] %2 = call arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0] ret %struct.1* %this } diff --git a/test/CodeGen/ARM/2009-09-24-spill-align.ll b/test/CodeGen/ARM/2009-09-24-spill-align.ll index 224bd019481d..4502542809f7 100644 --- a/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -7,7 +7,7 @@ entry: %out_poly16_t = alloca i16 ; <i16*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] ; CHECK: vldr - %0 = load <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1] + %0 = load <4 x i16>, <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1] %1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1] store i16 %1, i16* %out_poly16_t, align 2 br label %return diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll index e2ff164502ce..287384fbc214 100644 --- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll +++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll @@ -11,9 +11,9 @@ define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y. %x76 = fmul double %y.0, 0.000000e+00 ; <double> [#uses=1] %x77 = fadd double %y.0, 0.000000e+00 ; <double> [#uses=1] %tmpr = fadd double %x.0, %x76 ; <double> [#uses=1] - %agg.result.0 = getelementptr %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1] + %agg.result.0 = getelementptr %0, %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1] store double %tmpr, double* %agg.result.0, align 8 - %agg.result.1 = getelementptr %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1] + %agg.result.1 = getelementptr %0, %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1] store double %x77, double* %agg.result.1, align 8 ret void } diff --git a/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll index 465368b0ba8d..641036f684b9 100644 --- a/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll +++ b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll @@ -6,8 +6,8 @@ entry: br i1 undef, label %return, label %bb bb: ; preds = %bb, %entry - %0 = load float* undef, align 4 ; <float> [#uses=1] - %1 = load float* null, align 4 ; <float> [#uses=1] + %0 = load float, float* undef, align 4 ; <float> [#uses=1] + %1 = load float, float* null, align 4 ; <float> [#uses=1] %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1] %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2] %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll index de05644fc901..3f47488372b8 100644 --- a/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -9,7 +9,7 @@ entry: br label %do.body, !dbg !0 do.body: ; preds = %entry - call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !{!"0x102"}) + call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5) %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; <i32> [#uses=1] %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; <i32> [#uses=0] br label %do.end, !dbg !0 @@ -22,13 +22,13 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i32 @foo(i32) ssp -!0 = !MDLocation(line: 5, column: 2, scope: !1) -!1 = !{!"0xb\001\001\000", null, !2}; [DW_TAG_lexical_block ] -!2 = !{!"0x2e\00bar\00bar\00bar\004\000\001\000\006\000\000\000", i32 0, !3, null, null, null, null, null, null}; [DW_TAG_subprogram ] -!3 = !{!"0x11\0012\00clang 1.1\001\00\000\00\000", !8, null, !9, null, null, null}; [DW_TAG_compile_unit ] -!4 = !{!"0x100\00count_\005\000", !5, !3, !6}; [ DW_TAG_auto_variable ] -!5 = !{!"0xb\001\001\000", null, !1}; [DW_TAG_lexical_block ] -!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3}; [DW_TAG_base_type ] -!7 = !MDLocation(line: 6, column: 1, scope: !2) -!8 = !{!"genmodes.i", !"/Users/yash/Downloads"} +!0 = !DILocation(line: 5, column: 2, scope: !1) +!1 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !2) +!2 = !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !3) +!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !8, retainedTypes: !9) +!4 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "count_", line: 5, scope: !5, file: !3, type: !6) +!5 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !1) +!6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!7 = !DILocation(line: 6, column: 1, scope: !2) +!8 = !DIFile(filename: "genmodes.i", directory: "/Users/yash/Downloads") !9 = !{i32 0} diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll index b37de9dbbdfd..39f3292e260b 100644 --- a/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -8,7 +8,7 @@ entry: ;CHECK: [sp, #8] ;CHECK: [sp, #12] ;CHECK: [sp] - tail call void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + tail call void (i8*, ...) @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void } diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll index a18a8308044c..1fc10564a460 100644 --- a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll +++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -8,7 +8,7 @@ target triple = "armv7-eabi" define arm_aapcs_vfpcc void @bar(%foo* noalias sret %agg.result, <4 x float> %quat.0) nounwind { entry: %quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2] - %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] + %0 = getelementptr inbounds %foo, %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] store <4 x float> %quat.0, <4 x float>* %0 %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3] %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2] diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll index 2597b413ec7c..154cd65e4ec1 100644 --- a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -8,7 +8,7 @@ entry: bb: ; preds = %bb, %entry ; CHECK: vld1.16 {d16[], d17[]} - %0 = load i16* undef, align 2 + %0 = load i16, i16* undef, align 2 %1 = insertelement <8 x i16> undef, i16 %0, i32 2 %2 = insertelement <8 x i16> %1, i16 undef, i32 3 %3 = mul <8 x i16> %2, %2 diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index 38eb0ea2c891..9632c7730105 100644 --- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -6,7 +6,7 @@ target triple = "armv7-eabi" define arm_aapcs_vfpcc void @foo() { entry: - %0 = load float* null, align 4 ; <float> [#uses=2] + %0 = load float, float* null, align 4 ; <float> [#uses=2] %1 = fmul float %0, undef ; <float> [#uses=2] %2 = fmul float 0.000000e+00, %1 ; <float> [#uses=2] %3 = fmul float %0, %1 ; <float> [#uses=1] @@ -18,7 +18,7 @@ entry: %7 = fsub float %2, undef ; <float> [#uses=1] %8 = fsub float 0.000000e+00, undef ; <float> [#uses=3] %9 = fadd float %2, undef ; <float> [#uses=3] - %10 = load float* undef, align 8 ; <float> [#uses=3] + %10 = load float, float* undef, align 8 ; <float> [#uses=3] %11 = fmul float %8, %10 ; <float> [#uses=1] %12 = fadd float undef, %11 ; <float> [#uses=2] %13 = fmul float undef, undef ; <float> [#uses=1] @@ -30,10 +30,10 @@ entry: %19 = fadd float %18, 0.000000e+00 ; <float> [#uses=1] %20 = fmul float undef, %10 ; <float> [#uses=1] %21 = fadd float %19, %20 ; <float> [#uses=1] - %22 = load float* undef, align 8 ; <float> [#uses=1] + %22 = load float, float* undef, align 8 ; <float> [#uses=1] %23 = fmul float %5, %22 ; <float> [#uses=1] %24 = fadd float %23, undef ; <float> [#uses=1] - %25 = load float* undef, align 8 ; <float> [#uses=2] + %25 = load float, float* undef, align 8 ; <float> [#uses=2] %26 = fmul float %8, %25 ; <float> [#uses=1] %27 = fadd float %24, %26 ; <float> [#uses=1] %28 = fmul float %9, %25 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll index 6cce02dd48cf..07e910b3e07b 100644 --- a/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll @@ -13,11 +13,11 @@ entry: br i1 undef, label %bb85, label %bb bb: ; preds = %entry - %0 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2] - %1 = load float* undef, align 4 ; <float> [#uses=1] + %0 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2] + %1 = load float, float* undef, align 4 ; <float> [#uses=1] %2 = fsub float 0.000000e+00, undef ; <float> [#uses=2] %3 = fmul float 0.000000e+00, undef ; <float> [#uses=1] - %4 = load float* %0, align 4 ; <float> [#uses=3] + %4 = load float, float* %0, align 4 ; <float> [#uses=3] %5 = fmul float %4, %2 ; <float> [#uses=1] %6 = fsub float %3, %5 ; <float> [#uses=1] %7 = fmul float %4, undef ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll index 3ff663124819..9eddcf71cb3b 100644 --- a/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll +++ b/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll @@ -19,22 +19,22 @@ bb2.i: ; preds = %bb br label %bb3.i bb3.i: ; preds = %bb2.i, %bb - %0 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0] + %0 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0] %1 = fsub float 0.000000e+00, undef ; <float> [#uses=1] - %2 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2] - %3 = load float* %2, align 4 ; <float> [#uses=1] - %4 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1] + %2 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2] + %3 = load float, float* %2, align 4 ; <float> [#uses=1] + %4 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1] %5 = fsub float %3, undef ; <float> [#uses=2] - %6 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=2] - %7 = load float* %6, align 4 ; <float> [#uses=1] + %6 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=2] + %7 = load float, float* %6, align 4 ; <float> [#uses=1] %8 = fsub float %7, undef ; <float> [#uses=1] - %9 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=2] - %10 = load float* %9, align 4 ; <float> [#uses=1] + %9 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=2] + %10 = load float, float* %9, align 4 ; <float> [#uses=1] %11 = fsub float %10, undef ; <float> [#uses=2] - %12 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2] - %13 = load float* %12, align 4 ; <float> [#uses=1] + %12 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2] + %13 = load float, float* %12, align 4 ; <float> [#uses=1] %14 = fsub float %13, undef ; <float> [#uses=1] - %15 = load float* undef, align 4 ; <float> [#uses=1] + %15 = load float, float* undef, align 4 ; <float> [#uses=1] %16 = fsub float %15, undef ; <float> [#uses=1] %17 = fmul float %5, %16 ; <float> [#uses=1] %18 = fsub float %17, 0.000000e+00 ; <float> [#uses=5] @@ -44,19 +44,19 @@ bb3.i: ; preds = %bb2.i, %bb %22 = fmul float %5, %11 ; <float> [#uses=1] %23 = fsub float %21, %22 ; <float> [#uses=2] store float %18, float* undef - %24 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 1 ; <float*> [#uses=2] + %24 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 1 ; <float*> [#uses=2] store float %20, float* %24 store float %23, float* undef - %25 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=0] + %25 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=0] %26 = fmul float %18, %18 ; <float> [#uses=1] %27 = fadd float %26, undef ; <float> [#uses=1] %28 = fadd float %27, undef ; <float> [#uses=1] %29 = call arm_aapcs_vfpcc float @sqrtf(float %28) readnone ; <float> [#uses=1] - %30 = load float* null, align 4 ; <float> [#uses=2] - %31 = load float* %4, align 4 ; <float> [#uses=2] - %32 = load float* %2, align 4 ; <float> [#uses=2] - %33 = load float* null, align 4 ; <float> [#uses=3] - %34 = load float* %6, align 4 ; <float> [#uses=2] + %30 = load float, float* null, align 4 ; <float> [#uses=2] + %31 = load float, float* %4, align 4 ; <float> [#uses=2] + %32 = load float, float* %2, align 4 ; <float> [#uses=2] + %33 = load float, float* null, align 4 ; <float> [#uses=3] + %34 = load float, float* %6, align 4 ; <float> [#uses=2] %35 = fsub float %33, %34 ; <float> [#uses=2] %36 = fmul float %20, %35 ; <float> [#uses=1] %37 = fsub float %36, undef ; <float> [#uses=1] @@ -71,12 +71,12 @@ bb3.i: ; preds = %bb2.i, %bb %46 = fadd float %44, %45 ; <float> [#uses=1] %47 = fmul float %33, %43 ; <float> [#uses=1] %48 = fadd float %46, %47 ; <float> [#uses=2] - %49 = load float* %9, align 4 ; <float> [#uses=2] + %49 = load float, float* %9, align 4 ; <float> [#uses=2] %50 = fsub float %30, %49 ; <float> [#uses=1] - %51 = load float* %12, align 4 ; <float> [#uses=3] + %51 = load float, float* %12, align 4 ; <float> [#uses=3] %52 = fsub float %32, %51 ; <float> [#uses=2] - %53 = load float* undef, align 4 ; <float> [#uses=2] - %54 = load float* %24, align 4 ; <float> [#uses=2] + %53 = load float, float* undef, align 4 ; <float> [#uses=2] + %54 = load float, float* %24, align 4 ; <float> [#uses=2] %55 = fmul float %54, undef ; <float> [#uses=1] %56 = fmul float undef, %52 ; <float> [#uses=1] %57 = fsub float %55, %56 ; <float> [#uses=1] @@ -93,7 +93,7 @@ bb3.i: ; preds = %bb2.i, %bb %68 = fsub float %51, %31 ; <float> [#uses=1] %69 = fsub float %53, %33 ; <float> [#uses=1] %70 = fmul float undef, %67 ; <float> [#uses=1] - %71 = load float* undef, align 4 ; <float> [#uses=2] + %71 = load float, float* undef, align 4 ; <float> [#uses=2] %72 = fmul float %71, %69 ; <float> [#uses=1] %73 = fsub float %70, %72 ; <float> [#uses=1] %74 = fmul float %71, %68 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll index 832ff4fa0987..8a14804dcf85 100644 --- a/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll +++ b/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll @@ -11,7 +11,7 @@ define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) { entry: - %0 = load %bar** undef, align 4 ; <%bar*> [#uses=2] + %0 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=2] br i1 false, label %bb85, label %bb bb: ; preds = %entry @@ -21,13 +21,13 @@ bb2.i: ; preds = %bb br label %bb3.i bb3.i: ; preds = %bb2.i, %bb - %1 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1] + %1 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1] %2 = fsub float 0.000000e+00, undef ; <float> [#uses=1] - %3 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1] - %4 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1] + %3 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1] + %4 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1] %5 = fsub float 0.000000e+00, undef ; <float> [#uses=1] - %6 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1] - %7 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1] + %6 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1] + %7 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1] %8 = fsub float undef, undef ; <float> [#uses=1] %9 = fmul float 0.000000e+00, %8 ; <float> [#uses=1] %10 = fmul float %5, 0.000000e+00 ; <float> [#uses=1] @@ -36,17 +36,17 @@ bb3.i: ; preds = %bb2.i, %bb %13 = fmul float 0.000000e+00, undef ; <float> [#uses=1] %14 = fsub float %12, %13 ; <float> [#uses=2] store float %14, float* undef - %15 = getelementptr inbounds %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1] + %15 = getelementptr inbounds %bar, %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1] store float 0.000000e+00, float* %15 %16 = fmul float %11, %11 ; <float> [#uses=1] %17 = fadd float %16, 0.000000e+00 ; <float> [#uses=1] %18 = fadd float %17, undef ; <float> [#uses=1] %19 = call arm_aapcs_vfpcc float @sqrtf(float %18) readnone ; <float> [#uses=2] %20 = fcmp ogt float %19, 0x3F1A36E2E0000000 ; <i1> [#uses=1] - %21 = load float* %1, align 4 ; <float> [#uses=2] - %22 = load float* %3, align 4 ; <float> [#uses=2] - %23 = load float* undef, align 4 ; <float> [#uses=2] - %24 = load float* %4, align 4 ; <float> [#uses=2] + %21 = load float, float* %1, align 4 ; <float> [#uses=2] + %22 = load float, float* %3, align 4 ; <float> [#uses=2] + %23 = load float, float* undef, align 4 ; <float> [#uses=2] + %24 = load float, float* %4, align 4 ; <float> [#uses=2] %25 = fsub float %23, %24 ; <float> [#uses=2] %26 = fmul float 0.000000e+00, %25 ; <float> [#uses=1] %27 = fsub float %26, undef ; <float> [#uses=1] @@ -59,11 +59,11 @@ bb3.i: ; preds = %bb2.i, %bb %34 = fadd float %32, %33 ; <float> [#uses=1] %35 = fmul float %23, %31 ; <float> [#uses=1] %36 = fadd float %34, %35 ; <float> [#uses=1] - %37 = load float* %6, align 4 ; <float> [#uses=2] - %38 = load float* %7, align 4 ; <float> [#uses=2] + %37 = load float, float* %6, align 4 ; <float> [#uses=2] + %38 = load float, float* %7, align 4 ; <float> [#uses=2] %39 = fsub float %22, %38 ; <float> [#uses=2] - %40 = load float* undef, align 4 ; <float> [#uses=1] - %41 = load float* null, align 4 ; <float> [#uses=2] + %40 = load float, float* undef, align 4 ; <float> [#uses=1] + %41 = load float, float* null, align 4 ; <float> [#uses=2] %42 = fmul float %41, undef ; <float> [#uses=1] %43 = fmul float undef, %39 ; <float> [#uses=1] %44 = fsub float %42, %43 ; <float> [#uses=1] @@ -80,7 +80,7 @@ bb3.i: ; preds = %bb2.i, %bb %55 = fmul float undef, undef ; <float> [#uses=1] %56 = fsub float %54, %55 ; <float> [#uses=1] %57 = fmul float undef, %53 ; <float> [#uses=1] - %58 = load float* undef, align 4 ; <float> [#uses=2] + %58 = load float, float* undef, align 4 ; <float> [#uses=2] %59 = fmul float %58, undef ; <float> [#uses=1] %60 = fsub float %57, %59 ; <float> [#uses=1] %61 = fmul float %58, undef ; <float> [#uses=1] @@ -100,7 +100,7 @@ bb3.i: ; preds = %bb2.i, %bb br i1 %72, label %bb4.i97, label %ccc.exit98 bb4.i97: ; preds = %bb3.i - %73 = load %bar** undef, align 4 ; <%bar*> [#uses=0] + %73 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=0] br label %ccc.exit98 ccc.exit98: ; preds = %bb4.i97, %bb3.i diff --git a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll index f89a5de77b3f..8cba9116481e 100644 --- a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll +++ b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll @@ -11,9 +11,9 @@ entry: ;CHECK: vtrn.16 %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> %1 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> - %agg.result1218.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*> + %agg.result1218.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*> store <8 x i16> %0, <8 x i16>* %agg.result1218.0, align 16 - %agg.result12.1.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*> + %agg.result12.1.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*> store <8 x i16> %1, <8 x i16>* %agg.result12.1.0, align 16 ret void } @@ -25,9 +25,9 @@ define void @t2(%struct.int16x8x2_t* nocapture %ptr, <4 x i16> %a.0, <4 x i16> % entry: %0 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 undef, i32 undef, i32 undef, i32 undef> %1 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> - %ptr26.0 = getelementptr inbounds %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 0, i32 0 + %ptr26.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 0, i32 0 store <8 x i16> %0, <8 x i16>* %ptr26.0, align 16 - %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 1, i32 0 + %ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 1, i32 0 store <8 x i16> %1, <8 x i16>* %ptr20.1.0, align 16 ret void } diff --git a/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll index f7adf73263ff..d21b488bb3a0 100644 --- a/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll +++ b/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) { - %1 = load i32* undef ; <i32> [#uses=1] + %1 = load i32, i32* undef ; <i32> [#uses=1] %2 = sub i32 %1, 48 ; <i32> [#uses=1] br i1 undef, label %stack_overflow, label %no_overflow @@ -10,13 +10,13 @@ stack_overflow: ; preds = %0 no_overflow: ; preds = %0 %frame = inttoptr i32 %2 to [17 x i32]* ; <[17 x i32]*> [#uses=4] - %3 = load i32* undef ; <i32> [#uses=1] - %4 = load i32* null ; <i32> [#uses=1] - %5 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1] + %3 = load i32, i32* undef ; <i32> [#uses=1] + %4 = load i32, i32* null ; <i32> [#uses=1] + %5 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1] %6 = bitcast i32* %5 to [8 x i8]** ; <[8 x i8]**> [#uses=1] - %7 = load [8 x i8]** %6 ; <[8 x i8]*> [#uses=1] - %8 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 12 ; <i32*> [#uses=1] - %9 = load i32* %8 ; <i32> [#uses=1] + %7 = load [8 x i8]*, [8 x i8]** %6 ; <[8 x i8]*> [#uses=1] + %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 12 ; <i32*> [#uses=1] + %9 = load i32, i32* %8 ; <i32> [#uses=1] br i1 undef, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow @@ -27,18 +27,18 @@ bci_30: ; preds = %bci_13 bci_46: ; preds = %bci_30 %10 = sub i32 %4, %3 ; <i32> [#uses=1] - %11 = load [8 x i8]** null ; <[8 x i8]*> [#uses=1] + %11 = load [8 x i8]*, [8 x i8]** null ; <[8 x i8]*> [#uses=1] %callee = bitcast [8 x i8]* %11 to [84 x i8]* ; <[84 x i8]*> [#uses=1] %12 = bitcast i8* undef to i32* ; <i32*> [#uses=1] - %base_pc7 = load i32* %12 ; <i32> [#uses=2] + %base_pc7 = load i32, i32* %12 ; <i32> [#uses=2] %13 = add i32 %base_pc7, 0 ; <i32> [#uses=1] %14 = inttoptr i32 %13 to void ([84 x i8]*, i32, [788 x i8]*)** ; <void ([84 x i8]*, i32, [788 x i8]*)**> [#uses=1] - %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)** %14 ; <void ([84 x i8]*, i32, [788 x i8]*)*> [#uses=1] - %15 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 1 ; <i32*> [#uses=1] + %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)*, void ([84 x i8]*, i32, [788 x i8]*)** %14 ; <void ([84 x i8]*, i32, [788 x i8]*)*> [#uses=1] + %15 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 1 ; <i32*> [#uses=1] %16 = ptrtoint i32* %15 to i32 ; <i32> [#uses=1] %stack_pointer_addr9 = bitcast i8* undef to i32* ; <i32*> [#uses=1] store i32 %16, i32* %stack_pointer_addr9 - %17 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 2 ; <i32*> [#uses=1] + %17 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 2 ; <i32*> [#uses=1] store i32 %9, i32* %17 store i32 %10, i32* undef store [84 x i8]* %method, [84 x i8]** undef diff --git a/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll index 5e75d460aa7f..a1923ec2c3e0 100644 --- a/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll +++ b/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll @@ -9,10 +9,10 @@ stack_overflow: ; preds = %0 no_overflow: ; preds = %0 %frame = inttoptr i32 %1 to [17 x i32]* ; <[17 x i32]*> [#uses=4] - %2 = load i32* null ; <i32> [#uses=2] - %3 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1] - %4 = load i32* %3 ; <i32> [#uses=2] - %5 = load [8 x i8]** undef ; <[8 x i8]*> [#uses=2] + %2 = load i32, i32* null ; <i32> [#uses=2] + %3 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1] + %4 = load i32, i32* %3 ; <i32> [#uses=2] + %5 = load [8 x i8]*, [8 x i8]** undef ; <[8 x i8]*> [#uses=2] br i1 undef, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow @@ -33,11 +33,11 @@ no_exception: ; preds = %bci_46 ret void bci_35: ; preds = %bci_30 - %7 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 15 ; <i32*> [#uses=1] + %7 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 15 ; <i32*> [#uses=1] store i32 %2, i32* %7 - %8 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1] + %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1] store i32 %4, i32* %8 - %9 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1] + %9 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1] %10 = bitcast i32* %9 to [8 x i8]** ; <[8 x i8]**> [#uses=1] store [8 x i8]* %5, [8 x i8]** %10 call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7) diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index 6f7db9352188..638b26c73146 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -5,7 +5,7 @@ target triple = "armv4t-apple-darwin10" define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: - tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !0, metadata !{!"0x102"}) + tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1) %0 = add nsw i32 %b, %a, !dbg !9 ; <i32> [#uses=1] ret i32 %0, !dbg !11 } @@ -14,19 +14,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!15} -!0 = !{!"0x101\00b\0093\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] -!1 = !{!"0x2e\00__addvsi3\00__addvsi3\00__addvsi3\0094\000\001\000\006\000\000\000", !12, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!2 = !{!"0x29", !12} ; [ DW_TAG_file_type ] -!12 = !{!"libgcc2.c", !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc"} -!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)\001\00\000\00\000", !12, !13, !13, !14, null, null} ; [ DW_TAG_compile_unit ] -!4 = !{!"0x15\00\000\000\000\000\000\000", !12, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 93, arg: 0, scope: !1, file: !2, type: !6) +!1 = !DISubprogram(name: "__addvsi3", linkageName: "__addvsi3", line: 94, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: null, type: !4) +!2 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc") +!12 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc") +!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", isOptimized: true, emissionKind: 0, file: !12, enums: !13, retainedTypes: !13, subprograms: !14) +!4 = !DISubroutineType(types: !5) !5 = !{!6, !6, !6} -!6 = !{!"0x16\00SItype\00152\000\000\000\000", !12, null, !8} ; [ DW_TAG_typedef ] -!7 = !{!"0x29", !"libgcc2.h", !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", !3} ; [ DW_TAG_file_type ] -!8 = !{!"0x24\00int\000\0032\0032\000\000\005", !12, !2} ; [ DW_TAG_base_type ] -!9 = !MDLocation(line: 95, scope: !10) -!10 = !{!"0xb\0094\000\000", !12, !1} ; [ DW_TAG_lexical_block ] -!11 = !MDLocation(line: 100, scope: !10) -!13 = !{i32 0} +!6 = !DIDerivedType(tag: DW_TAG_typedef, name: "SItype", line: 152, file: !12, baseType: !8) +!7 = !DIFile(filename: "libgcc2.h", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc") +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!9 = !DILocation(line: 95, scope: !10) +!10 = distinct !DILexicalBlock(line: 94, column: 0, file: !12, scope: !1) +!11 = !DILocation(line: 100, scope: !10) +!13 = !{} !14 = !{!1} -!15 = !{i32 1, !"Debug Info Version", i32 2} +!15 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll index 7d4cc6e3a75a..5f5489a1ca74 100644 --- a/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll +++ b/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll @@ -82,17 +82,17 @@ cond_true1369.preheader: ; preds = %cond_true1254 ret void bb1567: ; preds = %cond_true1254 - %tmp1591 = load i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1] + %tmp1591 = load i64, i64* getelementptr inbounds (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1] %tmp1572 = tail call fastcc i32 @FirstOne() ; <i32> [#uses=1] - %tmp1594 = load i32* undef ; <i32> [#uses=1] + %tmp1594 = load i32, i32* undef ; <i32> [#uses=1] %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; <i8> [#uses=1] %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1] %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1] %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1] %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1] %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1] - %tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1] - %tmp1599 = load i32* %tmp1598 ; <i32> [#uses=1] + %tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1] + %tmp1599 = load i32, i32* %tmp1598 ; <i32> [#uses=1] %tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1] br i1 undef, label %cond_next1637, label %cond_true1607 diff --git a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll index 946164321a2c..deb588403265 100644 --- a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -16,15 +16,15 @@ entry: %vla10 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] %vla14 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] %vla18 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] - %tmp21 = load i32* undef ; <i32> [#uses=1] + %tmp21 = load i32, i32* undef ; <i32> [#uses=1] %0 = mul i32 1, %tmp21 ; <i32> [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1] - call void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + call void (...) @zz(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) br i1 undef, label %if.then, label %if.end36 if.then: ; preds = %entry - %call = call i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] - %call35 = call i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] + %call = call i32 (...) @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] + %call35 = call i32 (...) @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] unreachable if.end36: ; preds = %entry diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index b040b2d91cd6..24469cc3717e 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -16,12 +16,12 @@ entry: ; THUMB-DAG: movs [[VAL:r[0-9]+]], #0 ; THUMB-NOT: str {{[a-z0-9]+}}, [{{[a-z0-9]+}}], {{[a-z0-9]+}} ; THUMB: str [[VAL]], [r[[ADDR]]] - %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1] + %0 = getelementptr inbounds %struct.foo, %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1] store i32 0, i32* inttoptr (i32 8 to i32*), align 8 br i1 %tst, label %bb.nph96, label %bb3 bb3: ; preds = %entry - %1 = load i64* %0, align 4 ; <i64> [#uses=0] + %1 = load i64, i64* %0, align 4 ; <i64> [#uses=0] ret i8 42 bb.nph96: ; preds = %entry diff --git a/test/CodeGen/ARM/2010-05-19-Shuffles.ll b/test/CodeGen/ARM/2010-05-19-Shuffles.ll index 587c0afcb714..94d0f4abfb7e 100644 --- a/test/CodeGen/ARM/2010-05-19-Shuffles.ll +++ b/test/CodeGen/ARM/2010-05-19-Shuffles.ll @@ -14,7 +14,7 @@ define <8 x i8> @f2(<8 x i8> %x) nounwind { } define void @f3(<4 x i64>* %xp) nounwind { - %x = load <4 x i64>* %xp + %x = load <4 x i64>, <4 x i64>* %xp %y = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 1> store <4 x i64> %y, <4 x i64>* %xp ret void diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll index 5bc08b037a1c..6a6ccf3d0a01 100644 --- a/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -3,36 +3,36 @@ define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { entry: - %0 = load float* %fltp + %0 = load float, float* %fltp %1 = insertelement <4 x float> undef, float %0, i32 0 %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer %3 = shl i32 %packedValue, 16 %4 = ashr i32 %3, 30 %.sum = add i32 %4, 4 - %5 = getelementptr inbounds float* %table, i32 %.sum + %5 = getelementptr inbounds float, float* %table, i32 %.sum ;CHECK: vldr s - %6 = load float* %5, align 4 + %6 = load float, float* %5, align 4 %tmp11 = insertelement <4 x float> undef, float %6, i32 0 %7 = shl i32 %packedValue, 18 %8 = ashr i32 %7, 30 %.sum12 = add i32 %8, 4 - %9 = getelementptr inbounds float* %table, i32 %.sum12 + %9 = getelementptr inbounds float, float* %table, i32 %.sum12 ;CHECK: vldr s - %10 = load float* %9, align 4 + %10 = load float, float* %9, align 4 %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1 %11 = shl i32 %packedValue, 20 %12 = ashr i32 %11, 30 %.sum13 = add i32 %12, 4 - %13 = getelementptr inbounds float* %table, i32 %.sum13 + %13 = getelementptr inbounds float, float* %table, i32 %.sum13 ;CHECK: vldr s - %14 = load float* %13, align 4 + %14 = load float, float* %13, align 4 %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2 %15 = shl i32 %packedValue, 22 %16 = ashr i32 %15, 30 %.sum14 = add i32 %16, 4 - %17 = getelementptr inbounds float* %table, i32 %.sum14 + %17 = getelementptr inbounds float, float* %table, i32 %.sum14 ;CHECK: vldr s - %18 = load float* %17, align 4 + %18 = load float, float* %17, align 4 %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3 %19 = fmul <4 x float> %tmp5, %2 %20 = bitcast float* %fltp to i8* diff --git a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll index f7ceb6e7e480..f86c3ba9ef6e 100644 --- a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll +++ b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -6,7 +6,7 @@ define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { entry: %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; <i128*> [#uses=1] - %srcval = load i128* %0, align 8 ; <i128> [#uses=2] + %srcval = load i128, i128* %0, align 8 ; <i128> [#uses=2] %tmp6 = trunc i128 %srcval to i64 ; <i64> [#uses=1] %tmp8 = lshr i128 %srcval, 64 ; <i128> [#uses=1] %tmp9 = trunc i128 %tmp8 to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll index 816a6d4f4b93..6f55ac058054 100644 --- a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll +++ b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -13,15 +13,15 @@ define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind { entry: %xcenter = alloca i32, align 4 ; <i32*> [#uses=2] - %0 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] + %0 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] %1 = icmp eq i32 %0, 4 ; <i1> [#uses=1] br i1 %1, label %bb, label %return bb: ; preds = %bb445, %entry - %2 = load %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2] - %3 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1] + %2 = load %struct.cellbox*, %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2] + %3 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1] store i32 undef, i32* %3, align 4 - %4 = load i32* undef, align 4 ; <i32> [#uses=3] + %4 = load i32, i32* undef, align 4 ; <i32> [#uses=3] %5 = icmp eq i32 undef, 1 ; <i1> [#uses=1] br i1 %5, label %bb10, label %bb445 @@ -29,12 +29,12 @@ bb10: ; preds = %bb br i1 undef, label %bb11, label %bb445 bb11: ; preds = %bb10 - %6 = load %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3] - %7 = load %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1] - %8 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1] - %9 = load i32* %8, align 4 ; <i32> [#uses=3] - %10 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1] - %11 = load i32* %10, align 4 ; <i32> [#uses=1] + %6 = load %struct.tilebox*, %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3] + %7 = load %struct.termbox*, %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1] + %8 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1] + %9 = load i32, i32* %8, align 4 ; <i32> [#uses=3] + %10 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1] + %11 = load i32, i32* %10, align 4 ; <i32> [#uses=1] br i1 false, label %bb12, label %bb13 bb12: ; preds = %bb11 @@ -67,7 +67,7 @@ bb21: ; preds = %bb13 %25 = zext i1 %not.461 to i32 ; <i32> [#uses=1] %iftmp.43.0 = add i32 %23, %iftmp.41.0.neg ; <i32> [#uses=1] %26 = add i32 %iftmp.43.0, %25 ; <i32> [#uses=1] - %27 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1] + %27 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1] store i32 %26, i32* %27, align 4 %28 = fptosi double undef to i32 ; <i32> [#uses=1] %iftmp.45.0 = add i32 %28, %iftmp.40.0.neg ; <i32> [#uses=1] @@ -77,7 +77,7 @@ bb21: ; preds = %bb13 bb36: ; preds = %bb43.loopexit, %bb36 %termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1] - %30 = load i32* undef, align 4 ; <i32> [#uses=1] + %30 = load i32, i32* undef, align 4 ; <i32> [#uses=1] %31 = sub nsw i32 %30, %9 ; <i32> [#uses=1] %32 = sitofp i32 %31 to double ; <double> [#uses=1] %33 = fdiv double %32, 0.000000e+00 ; <double> [#uses=1] @@ -92,8 +92,8 @@ bb36: ; preds = %bb43.loopexit, %bb3 %iftmp.47.0 = add i32 %39, %iftmp.40.0.neg ; <i32> [#uses=1] %40 = add i32 %iftmp.47.0, 0 ; <i32> [#uses=1] store i32 %40, i32* undef, align 4 - %41 = getelementptr inbounds %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1] - %42 = load %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2] + %41 = getelementptr inbounds %struct.termbox, %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1] + %42 = load %struct.termbox*, %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2] %43 = icmp eq %struct.termbox* %42, null ; <i1> [#uses=1] br i1 %43, label %bb52.loopexit, label %bb36 @@ -127,9 +127,9 @@ bb248: ; preds = %bb322, %bb.nph485 br i1 %45, label %bb322, label %bb249 bb249: ; preds = %bb248 - %46 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1] - %47 = load %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1] - %48 = getelementptr inbounds %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1] + %46 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1] + %47 = load %struct.tilebox*, %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1] + %48 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1] store i32 undef, i32* %48, align 4 unreachable @@ -137,7 +137,7 @@ bb322: ; preds = %bb248 br i1 undef, label %bb248, label %bb445 bb445: ; preds = %bb322, %bb10, %bb - %49 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] + %49 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] %50 = icmp eq i32 %49, 4 ; <i1> [#uses=1] br i1 %50, label %bb, label %return diff --git a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll index ac8e80904eda..bead8d9781e8 100755 --- a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll +++ b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll @@ -33,9 +33,9 @@ define %"struct.llvm::Init"* @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9 ;CHECK: bx r12 @ TAILCALL entry: %.loc = alloca i32 ; <i32*> [#uses=2] - %tmp.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; <i8*> [#uses=1] + %tmp.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; <i8*> [#uses=1] %0 = bitcast i8* %tmp.i to %"struct.llvm::Init"** ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i = load %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2] + %tmp2.i = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2] %1 = icmp eq %"struct.llvm::Init"* %tmp2.i, null ; <i1> [#uses=1] br i1 %1, label %entry.return_crit_edge, label %tmpbb @@ -52,17 +52,17 @@ tmpbb: ; preds = %entry br label %return if.then: ; preds = %tmpbb - %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; <i8**> [#uses=1] - %tmp3.i.i.i.i = load i8** %tmp2.i.i.i.i ; <i8*> [#uses=2] - %arrayidx.i.i.i.i = getelementptr inbounds i8* %tmp3.i.i.i.i, i32 -12 ; <i8*> [#uses=1] + %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; <i8**> [#uses=1] + %tmp3.i.i.i.i = load i8*, i8** %tmp2.i.i.i.i ; <i8*> [#uses=2] + %arrayidx.i.i.i.i = getelementptr inbounds i8, i8* %tmp3.i.i.i.i, i32 -12 ; <i8*> [#uses=1] %tmp.i.i.i = bitcast i8* %arrayidx.i.i.i.i to i32* ; <i32*> [#uses=1] - %tmp2.i.i.i = load i32* %tmp.i.i.i ; <i32> [#uses=1] - %tmp.i5 = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1] - %tmp2.i.i = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; <i8*> [#uses=1] + %tmp2.i.i.i = load i32, i32* %tmp.i.i.i ; <i32> [#uses=1] + %tmp.i5 = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1] + %tmp2.i.i = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; <i8*> [#uses=1] %4 = bitcast i8* %tmp2.i.i to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] - %tmp3.i.i6 = load %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1] + %tmp3.i.i6 = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1] %tmp5.i.i = bitcast %"class.std::vector"* %tmp.i5 to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] - %tmp6.i.i = load %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5] + %tmp6.i.i = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5] %sub.ptr.lhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp3.i.i6 to i32 ; <i32> [#uses=1] %sub.ptr.rhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp6.i.i to i32 ; <i32> [#uses=1] %sub.ptr.sub.i.i = sub i32 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i.i ; <i32> [#uses=1] @@ -71,14 +71,14 @@ if.then: ; preds = %tmpbb codeRepl: ; preds = %if.then %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, %"class.llvm::RecordVal"* %tmp6.i.i, i32 %tmp2.i.i.i, i8* %tmp3.i.i.i.i, i32* %.loc) ; <i1> [#uses=1] - %.reload = load i32* %.loc ; <i32> [#uses=3] + %.reload = load i32, i32* %.loc ; <i32> [#uses=3] br i1 %targetBlock, label %for.cond.i.return_crit_edge, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit for.cond.i.return_crit_edge: ; preds = %codeRepl br label %return _ZN4llvm6Record8getValueENS_9StringRefE.exit: ; preds = %codeRepl - %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2] + %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2] %tobool5 = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, null ; <i1> [#uses=1] br i1 %tobool5, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, label %if.then6 @@ -100,8 +100,8 @@ land.lhs.true.return_crit_edge: ; preds = %land.lhs.true br label %return lor.lhs.false: ; preds = %land.lhs.true - %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i4 = load %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2] + %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i4 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2] %5 = icmp eq %"struct.llvm::Init"* %tmp2.i4, null ; <i1> [#uses=1] br i1 %5, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1 @@ -121,21 +121,21 @@ tmpbb1: ; preds = %lor.lhs.false br label %if.end if.end: ; preds = %.if.end_crit_edge, %lor.lhs.false.if.end_crit_edge, %if.then6.if.end_crit_edge - %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i2 = load %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3] + %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i2 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3] %8 = bitcast %"class.llvm::StringInit"* %this to %"struct.llvm::Init"* ; <%"struct.llvm::Init"*> [#uses=1] %cmp19 = icmp eq %"struct.llvm::Init"* %tmp2.i2, %8 ; <i1> [#uses=1] br i1 %cmp19, label %cond.false, label %cond.end cond.false: ; preds = %if.end - tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn + tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8], [116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn unreachable cond.end: ; preds = %if.end %9 = bitcast %"struct.llvm::Init"* %tmp2.i2 to %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)***> [#uses=1] - %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] - %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] - %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1] + %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] + %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] + %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1] %call25 = tail call %"struct.llvm::Init"* %11(%"struct.llvm::Init"* %tmp2.i2, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) ; <%"struct.llvm::Init"*> [#uses=1] ret %"struct.llvm::Init"* %call25 diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll index 18b3be0aba5c..95bb2769759e 100644 --- a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll +++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -7,21 +7,21 @@ target triple = "thumbv7-apple-darwin3.0.0-iphoneos" define void @x0(i8* nocapture %buf, i32 %nbytes) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i8* %buf, i64 0, metadata !0, metadata !{!"0x102"}), !dbg !15 - tail call void @llvm.dbg.value(metadata i32 %nbytes, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !16 - %tmp = load i32* @length, !dbg !17 ; <i32> [#uses=3] + tail call void @llvm.dbg.value(metadata i8* %buf, i64 0, metadata !0, metadata !DIExpression()), !dbg !15 + tail call void @llvm.dbg.value(metadata i32 %nbytes, i64 0, metadata !8, metadata !DIExpression()), !dbg !16 + %tmp = load i32, i32* @length, !dbg !17 ; <i32> [#uses=3] %cmp = icmp eq i32 %tmp, -1, !dbg !17 ; <i1> [#uses=1] %cmp.not = xor i1 %cmp, true ; <i1> [#uses=1] %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !17 ; <i1> [#uses=1] %or.cond = and i1 %cmp.not, %cmp3 ; <i1> [#uses=1] - tail call void @llvm.dbg.value(metadata i32 %tmp, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !17 + tail call void @llvm.dbg.value(metadata i32 %tmp, i64 0, metadata !8, metadata !DIExpression()), !dbg !17 %nbytes.addr.0 = select i1 %or.cond, i32 %tmp, i32 %nbytes ; <i32> [#uses=1] - tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !19 + tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !DIExpression()), !dbg !19 br label %while.cond, !dbg !20 while.cond: ; preds = %while.body, %entry %0 = phi i32 [ 0, %entry ], [ %inc, %while.body ] ; <i32> [#uses=3] - %buf.addr.0 = getelementptr i8* %buf, i32 %0 ; <i8*> [#uses=1] + %buf.addr.0 = getelementptr i8, i8* %buf, i32 %0 ; <i8*> [#uses=1] %cmp7 = icmp ult i32 %0, %nbytes.addr.0, !dbg !20 ; <i1> [#uses=1] br i1 %cmp7, label %land.rhs, label %while.end, !dbg !20 @@ -47,30 +47,30 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.lv.fn = !{!0, !8, !10, !12} !llvm.dbg.gv = !{!14} -!0 = !{!"0x101\00buf\004\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] -!1 = !{!"0x2e\00x0\00x0\00x0\005\000\001\000\006\000\000\000", !26, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!2 = !{!"0x29", !26} ; [ DW_TAG_file_type ] -!3 = !{!"0x11\0012\00clang 2.0\001\00\00\00\00", !26, null, null, null, null, null} ; [ DW_TAG_compile_unit ] -!4 = !{!"0x15\00\000\000\000\000\000\000", !26, !2, null, !5, null} ; [ DW_TAG_subroutine_type ] +!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "buf", line: 4, arg: 0, scope: !1, file: !2, type: !6) +!1 = !DISubprogram(name: "x0", linkageName: "x0", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !26, scope: null, type: !4) +!2 = !DIFile(filename: "t.c", directory: "/private/tmp") +!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 2.0", isOptimized: true, file: !26) +!4 = !DISubroutineType(types: !5) !5 = !{null} -!6 = !{!"0xf\00\000\0032\0032\000\000", !26, !2, !7} ; [ DW_TAG_pointer_type ] -!7 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !26, !2} ; [ DW_TAG_base_type ] -!8 = !{!"0x101\00nbytes\004\000", !1, !2, !9} ; [ DW_TAG_arg_variable ] -!9 = !{!"0x24\00unsigned long\000\0032\0032\000\000\007", !26, !2} ; [ DW_TAG_base_type ] -!10 = !{!"0x100\00nread\006\000", !11, !2, !9} ; [ DW_TAG_auto_variable ] -!11 = !{!"0xb\005\001\000", !26, !1} ; [ DW_TAG_lexical_block ] -!12 = !{!"0x100\00c\007\000", !11, !2, !13} ; [ DW_TAG_auto_variable ] -!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !26, !2} ; [ DW_TAG_base_type ] -!14 = !{!"0x34\00length\00length\00length\001\000\001", !2, !2, !13, i32* @length} ; [ DW_TAG_variable ] -!15 = !MDLocation(line: 4, column: 24, scope: !1) -!16 = !MDLocation(line: 4, column: 43, scope: !1) -!17 = !MDLocation(line: 9, column: 2, scope: !11) +!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !26, scope: !2, baseType: !7) +!7 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) +!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "nbytes", line: 4, arg: 0, scope: !1, file: !2, type: !9) +!9 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned long", size: 32, align: 32, encoding: DW_ATE_unsigned) +!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "nread", line: 6, scope: !11, file: !2, type: !9) +!11 = distinct !DILexicalBlock(line: 5, column: 1, file: !26, scope: !1) +!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 7, scope: !11, file: !2, type: !13) +!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!14 = !DIGlobalVariable(name: "length", linkageName: "length", line: 1, isLocal: false, isDefinition: true, scope: !2, file: !2, type: !13, variable: i32* @length) +!15 = !DILocation(line: 4, column: 24, scope: !1) +!16 = !DILocation(line: 4, column: 43, scope: !1) +!17 = !DILocation(line: 9, column: 2, scope: !11) !18 = !{i32 0} -!19 = !MDLocation(line: 10, column: 2, scope: !11) -!20 = !MDLocation(line: 11, column: 2, scope: !11) -!21 = !MDLocation(line: 12, column: 3, scope: !22) -!22 = !{!"0xb\0011\0045\000", !26, !11} ; [ DW_TAG_lexical_block ] -!23 = !MDLocation(line: 13, column: 3, scope: !22) -!24 = !MDLocation(line: 14, column: 2, scope: !22) -!25 = !MDLocation(line: 15, column: 1, scope: !11) -!26 = !{!"t.c", !"/private/tmp"} +!19 = !DILocation(line: 10, column: 2, scope: !11) +!20 = !DILocation(line: 11, column: 2, scope: !11) +!21 = !DILocation(line: 12, column: 3, scope: !22) +!22 = distinct !DILexicalBlock(line: 11, column: 45, file: !26, scope: !11) +!23 = !DILocation(line: 13, column: 3, scope: !22) +!24 = !DILocation(line: 14, column: 2, scope: !22) +!25 = !DILocation(line: 15, column: 1, scope: !11) +!26 = !DIFile(filename: "t.c", directory: "/private/tmp") diff --git a/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll index fcabc900afa6..03362a8e51f9 100644 --- a/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll +++ b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll @@ -7,8 +7,8 @@ define i32 @main(i32 %argc, i8** %argv) nounwind { entry: %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1] store <2 x i64> %0, <2 x i64>* undef, align 16 - %val4723 = load <8 x i16>* undef ; <<8 x i16>> [#uses=1] - call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind + %val4723 = load <8 x i16>, <8 x i16>* undef ; <<8 x i16>> [#uses=1] + call void @PrintShortX(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind ret i32 undef } diff --git a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll index 80822c2c426b..b02efea929fa 100644 --- a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll +++ b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll @@ -9,7 +9,7 @@ target triple = "thumbv7-apple-darwin10.0.0" @d = internal global i32 0, align 4 ; <i32*> [#uses=6] @_ZTVN10__cxxabiv117__class_type_infoE = external global i8* ; <i8**> [#uses=1] @_ZTS1A = internal constant [3 x i8] c"1A\00" ; <[3 x i8]*> [#uses=1] -@_ZTI1A = internal constant %0 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1] +@_ZTI1A = internal constant %0 { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1] @.str2 = private constant [18 x i8] c"c == %d, d == %d\0A\00" ; <[18 x i8]*> [#uses=1] @.str3 = private constant [16 x i8] c"A(const A&) %d\0A\00" ; <[16 x i8]*> [#uses=1] @.str4 = private constant [9 x i8] c"~A() %d\0A\00" ; <[9 x i8]*> [#uses=1] @@ -29,10 +29,10 @@ declare void @_Unwind_SjLj_Resume(i8*) define internal void @_ZN1AD1Ev(%struct.A* nocapture %this) nounwind ssp align 2 { entry: - %tmp.i = getelementptr inbounds %struct.A* %this, i32 0, i32 0 ; <i32*> [#uses=1] - %tmp2.i = load i32* %tmp.i ; <i32> [#uses=1] - %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; <i32> [#uses=0] - %tmp3.i = load i32* @d ; <i32> [#uses=1] + %tmp.i = getelementptr inbounds %struct.A, %struct.A* %this, i32 0, i32 0 ; <i32*> [#uses=1] + %tmp2.i = load i32, i32* %tmp.i ; <i32> [#uses=1] + %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; <i32> [#uses=0] + %tmp3.i = load i32, i32* @d ; <i32> [#uses=1] %inc.i = add nsw i32 %tmp3.i, 1 ; <i32> [#uses=1] store i32 %inc.i, i32* @d ret void @@ -42,11 +42,11 @@ declare void @__cxa_throw(i8*, i8*, i8*) define i32 @main() ssp { entry: - %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8]* @str, i32 0, i32 0)) ; <i32> [#uses=0] + %puts.i = tail call i32 @puts(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @str, i32 0, i32 0)) ; <i32> [#uses=0] %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind ; <i8*> [#uses=2] %tmp2.i.i.i = bitcast i8* %exception.i to i32* ; <i32*> [#uses=1] store i32 1, i32* %tmp2.i.i.i - %call.i.i.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; <i32> [#uses=0] + %call.i.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; <i32> [#uses=0] invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (%0* @_ZTI1A to i8*), i8* bitcast (void (%struct.A*)* @_ZN1AD1Ev to i8*)) noreturn to label %.noexc unwind label %lpad @@ -55,17 +55,17 @@ entry: try.cont: ; preds = %lpad %0 = tail call i8* @__cxa_get_exception_ptr(i8* %exn) nounwind ; <i8*> [#uses=0] - %call.i.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0] + %call.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0] %1 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind ; <i8*> [#uses=0] - %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @str1, i32 0, i32 0)) ; <i32> [#uses=0] - %call.i.i3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0] - %tmp3.i.i = load i32* @d ; <i32> [#uses=1] + %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 0)) ; <i32> [#uses=0] + %call.i.i3 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; <i32> [#uses=0] + %tmp3.i.i = load i32, i32* @d ; <i32> [#uses=1] %inc.i.i4 = add nsw i32 %tmp3.i.i, 1 ; <i32> [#uses=1] store i32 %inc.i.i4, i32* @d tail call void @__cxa_end_catch() - %tmp13 = load i32* @d ; <i32> [#uses=1] - %call14 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; <i32> [#uses=0] - %tmp16 = load i32* @d ; <i32> [#uses=1] + %tmp13 = load i32, i32* @d ; <i32> [#uses=1] + %call14 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; <i32> [#uses=0] + %tmp16 = load i32, i32* @d ; <i32> [#uses=1] %cmp = icmp ne i32 %tmp16, 2 ; <i1> [#uses=1] %conv = zext i1 %cmp to i32 ; <i32> [#uses=1] ret i32 %conv diff --git a/test/CodeGen/ARM/2010-08-04-EHCrash.ll b/test/CodeGen/ARM/2010-08-04-EHCrash.ll index 4b47085afd5e..13214c521530 100644 --- a/test/CodeGen/ARM/2010-08-04-EHCrash.ll +++ b/test/CodeGen/ARM/2010-08-04-EHCrash.ll @@ -12,17 +12,17 @@ entry: br label %return bb: ; No predecessors! - %eh_select = load i32* %eh_selector ; <i32> [#uses=1] + %eh_select = load i32, i32* %eh_selector ; <i32> [#uses=1] store i32 %eh_select, i32* %save_filt.936, align 4 - %eh_value = load i8** %eh_exception ; <i8*> [#uses=1] + %eh_value = load i8*, i8** %eh_exception ; <i8*> [#uses=1] store i8* %eh_value, i8** %save_eptr.935, align 4 invoke arm_apcscc void @func3() to label %invcont unwind label %lpad invcont: ; preds = %bb - %tmp6 = load i8** %save_eptr.935, align 4 ; <i8*> [#uses=1] + %tmp6 = load i8*, i8** %save_eptr.935, align 4 ; <i8*> [#uses=1] store i8* %tmp6, i8** %eh_exception, align 4 - %tmp7 = load i32* %save_filt.936, align 4 ; <i32> [#uses=1] + %tmp7 = load i32, i32* %save_filt.936, align 4 ; <i32> [#uses=1] store i32 %tmp7, i32* %eh_selector, align 4 br label %Unwind @@ -38,7 +38,7 @@ lpad: ; preds = %bb cleanup %exn = extractvalue { i8*, i32 } %eh_ptr, 0 store i8* %exn, i8** %eh_exception - %eh_ptr13 = load i8** %eh_exception ; <i8*> [#uses=1] + %eh_ptr13 = load i8*, i8** %eh_exception ; <i8*> [#uses=1] %eh_select14 = extractvalue { i8*, i32 } %eh_ptr, 1 store i32 %eh_select14, i32* %eh_selector br label %ppad @@ -47,7 +47,7 @@ ppad: br label %bb12 Unwind: - %eh_ptr15 = load i8** %eh_exception + %eh_ptr15 = load i8*, i8** %eh_exception call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr15) unreachable } diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index f71a6c9732a6..953e2bbf291c 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -6,20 +6,20 @@ define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp { entry: %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !24 - call void @llvm.dbg.value(metadata %struct.SVal* %location, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !24 + call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !DIExpression()), !dbg !24 + call void @llvm.dbg.value(metadata %struct.SVal* %location, i64 0, metadata !25, metadata !DIExpression()), !dbg !24 %0 = icmp ne i32 %i, 0, !dbg !27 ; <i1> [#uses=1] br i1 %0, label %bb, label %bb1, !dbg !27 bb: ; preds = %entry - %1 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1] - %2 = load i32* %1, align 8, !dbg !29 ; <i32> [#uses=1] + %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; <i32*> [#uses=1] + %2 = load i32, i32* %1, align 8, !dbg !29 ; <i32> [#uses=1] %3 = add i32 %2, %i, !dbg !29 ; <i32> [#uses=1] br label %bb2, !dbg !29 bb1: ; preds = %entry - %4 = getelementptr inbounds %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1] - %5 = load i32* %4, align 8, !dbg !30 ; <i32> [#uses=1] + %4 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; <i32*> [#uses=1] + %5 = load i32, i32* %4, align 8, !dbg !30 ; <i32> [#uses=1] %6 = sub i32 %5, 1, !dbg !30 ; <i32> [#uses=1] br label %bb2, !dbg !30 @@ -34,10 +34,10 @@ return: ; preds = %bb2 define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { entry: %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !{!"0x102"}), !dbg !34 - %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1] + call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !DIExpression()), !dbg !34 + %0 = getelementptr inbounds %struct.SVal, %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; <i8**> [#uses=1] store i8* null, i8** %0, align 8, !dbg !34 - %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1] + %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; <i32*> [#uses=1] store i32 0, i32* %1, align 8, !dbg !34 br label %return, !dbg !34 @@ -52,20 +52,20 @@ entry: %0 = alloca %struct.SVal ; <%struct.SVal*> [#uses=3] %v = alloca %struct.SVal ; <%struct.SVal*> [#uses=4] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - call void @llvm.dbg.declare(metadata %struct.SVal* %v, metadata !38, metadata !{!"0x102"}), !dbg !41 + call void @llvm.dbg.declare(metadata %struct.SVal* %v, metadata !38, metadata !DIExpression()), !dbg !41 call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41 - %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1] + %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; <i32*> [#uses=1] store i32 1, i32* %1, align 8, !dbg !42 - %2 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] - %3 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] - %4 = load i8** %3, align 8, !dbg !43 ; <i8*> [#uses=1] + %2 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] + %3 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; <i8**> [#uses=1] + %4 = load i8*, i8** %3, align 8, !dbg !43 ; <i8*> [#uses=1] store i8* %4, i8** %2, align 8, !dbg !43 - %5 = getelementptr inbounds %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] - %6 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] - %7 = load i32* %6, align 8, !dbg !43 ; <i32> [#uses=1] + %5 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] + %6 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; <i32*> [#uses=1] + %7 = load i32, i32* %6, align 8, !dbg !43 ; <i32> [#uses=1] store i32 %7, i32* %5, align 8, !dbg !43 %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; <i32> [#uses=0] - call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !{!"0x102"}), !dbg !43 + call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !DIExpression()), !dbg !43 br label %return, !dbg !45 return: ; preds = %entry @@ -77,53 +77,53 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!49} -!0 = !{!"0x2e\00SVal\00SVal\00\0011\000\000\000\006\000\000\000", !48, !1, !14, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!1 = !{!"0x13\00SVal\001\00128\0064\000\000\000", !48, null, null, !4, null, null, null} ; [ DW_TAG_structure_type ] [SVal] [line 1, size 128, align 64, offset 0] [def] [from ] -!2 = !{!"0x29", !48} ; [ DW_TAG_file_type ] -!3 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\001", !48, !47, !47, !46, !47, !47} ; [ DW_TAG_compile_unit ] +!0 = !DISubprogram(name: "SVal", line: 11, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14) +!1 = !DICompositeType(tag: DW_TAG_structure_type, name: "SVal", line: 1, size: 128, align: 64, file: !48, elements: !4) +!2 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330") +!3 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 1, file: !48, enums: !47, retainedTypes: !47, subprograms: !46, globals: !47, imports: !47) !4 = !{!5, !7, !0, !9} -!5 = !{!"0xd\00Data\007\0064\0064\000\000", !48, !1, !6} ; [ DW_TAG_member ] -!6 = !{!"0xf\00\000\0064\0064\000\000", !48, null, null} ; [ DW_TAG_pointer_type ] -!7 = !{!"0xd\00Kind\008\0032\0032\0064\000", !48, !1, !8} ; [ DW_TAG_member ] -!8 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !48, null} ; [ DW_TAG_base_type ] -!9 = !{!"0x2e\00~SVal\00~SVal\00\0012\000\000\000\006\000\000\000", !48, !1, !10, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!10 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!5 = !DIDerivedType(tag: DW_TAG_member, name: "Data", line: 7, size: 64, align: 64, file: !48, scope: !1, baseType: !6) +!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, baseType: null) +!7 = !DIDerivedType(tag: DW_TAG_member, name: "Kind", line: 8, size: 32, align: 32, offset: 64, file: !48, scope: !1, baseType: !8) +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) +!9 = !DISubprogram(name: "~SVal", line: 12, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !10) +!10 = !DISubroutineType(types: !11) !11 = !{null, !12, !13} -!12 = !{!"0xf\00\000\0064\0064\000\0064", !48, null, !1} ; [ DW_TAG_pointer_type ] -!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !48, null} ; [ DW_TAG_base_type ] -!14 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!12 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, flags: DIFlagArtificial, file: !48, baseType: !1) +!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!14 = !DISubroutineType(types: !15) !15 = !{null, !12} -!16 = !{!"0x2e\00SVal\00SVal\00_ZN4SValC1Ev\0011\000\001\000\006\000\000\000", !48, !1, !14, null, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null} ; [ DW_TAG_subprogram ] -!17 = !{!"0x2e\00foo\00foo\00_Z3fooi4SVal\0016\000\001\000\006\000\000\000", !48, !2, !18, null, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null} ; [ DW_TAG_subprogram ] -!18 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!16 = !DISubprogram(name: "SVal", linkageName: "_ZN4SValC1Ev", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14, function: void (%struct.SVal*)* @_ZN4SValC1Ev) +!17 = !DISubprogram(name: "foo", linkageName: "_Z3fooi4SVal", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !18, function: i32 (i32, %struct.SVal*)* @_Z3fooi4SVal) +!18 = !DISubroutineType(types: !19) !19 = !{!13, !13, !1} -!20 = !{!"0x2e\00main\00main\00main\0023\000\001\000\006\000\000\000", !48, !2, !21, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ] -!21 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!20 = !DISubprogram(name: "main", linkageName: "main", line: 23, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !21, function: i32 ()* @main) +!21 = !DISubroutineType(types: !22) !22 = !{!13} -!23 = !{!"0x101\00i\0016\000", !17, !2, !13} ; [ DW_TAG_arg_variable ] -!24 = !MDLocation(line: 16, scope: !17) -!25 = !{!"0x101\00location\0016\000", !17, !2, !26} ; [ DW_TAG_arg_variable ] -!26 = !{!"0x10\00SVal\000\0064\0064\000\000", !48, !2, !1} ; [ DW_TAG_reference_type ] -!27 = !MDLocation(line: 17, scope: !28) -!28 = !{!"0xb\0016\000\002", !2, !17} ; [ DW_TAG_lexical_block ] -!29 = !MDLocation(line: 18, scope: !28) -!30 = !MDLocation(line: 20, scope: !28) -!31 = !{!"0x101\00this\0011\000", !16, !2, !32} ; [ DW_TAG_arg_variable ] -!32 = !{!"0x26\00\000\0064\0064\000\0064", !48, !2, !33} ; [ DW_TAG_const_type ] -!33 = !{!"0xf\00\000\0064\0064\000\000", !48, !2, !1} ; [ DW_TAG_pointer_type ] -!34 = !MDLocation(line: 11, scope: !16) -!35 = !MDLocation(line: 11, scope: !36) -!36 = !{!"0xb\0011\000\001", !48, !37} ; [ DW_TAG_lexical_block ] -!37 = !{!"0xb\0011\000\000", !48, !16} ; [ DW_TAG_lexical_block ] -!38 = !{!"0x100\00v\0024\000", !39, !2, !1} ; [ DW_TAG_auto_variable ] -!39 = !{!"0xb\0023\000\004", !48, !40} ; [ DW_TAG_lexical_block ] -!40 = !{!"0xb\0023\000\003", !48, !20} ; [ DW_TAG_lexical_block ] -!41 = !MDLocation(line: 24, scope: !39) -!42 = !MDLocation(line: 25, scope: !39) -!43 = !MDLocation(line: 26, scope: !39) -!44 = !{!"0x100\00k\0026\000", !39, !2, !13} ; [ DW_TAG_auto_variable ] -!45 = !MDLocation(line: 27, scope: !39) +!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 16, arg: 0, scope: !17, file: !2, type: !13) +!24 = !DILocation(line: 16, scope: !17) +!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "location", line: 16, arg: 0, scope: !17, file: !2, type: !26) +!26 = !DIDerivedType(tag: DW_TAG_reference_type, name: "SVal", size: 64, align: 64, file: !48, scope: !2, baseType: !1) +!27 = !DILocation(line: 17, scope: !28) +!28 = distinct !DILexicalBlock(line: 16, column: 0, file: !2, scope: !17) +!29 = !DILocation(line: 18, scope: !28) +!30 = !DILocation(line: 20, scope: !28) +!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 0, scope: !16, file: !2, type: !32) +!32 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !48, scope: !2, baseType: !33) +!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, scope: !2, baseType: !1) +!34 = !DILocation(line: 11, scope: !16) +!35 = !DILocation(line: 11, scope: !36) +!36 = distinct !DILexicalBlock(line: 11, column: 0, file: !48, scope: !37) +!37 = distinct !DILexicalBlock(line: 11, column: 0, file: !48, scope: !16) +!38 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "v", line: 24, scope: !39, file: !2, type: !1) +!39 = distinct !DILexicalBlock(line: 23, column: 0, file: !48, scope: !40) +!40 = distinct !DILexicalBlock(line: 23, column: 0, file: !48, scope: !20) +!41 = !DILocation(line: 24, scope: !39) +!42 = !DILocation(line: 25, scope: !39) +!43 = !DILocation(line: 26, scope: !39) +!44 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 26, scope: !39, file: !2, type: !13) +!45 = !DILocation(line: 27, scope: !39) !46 = !{!16, !17, !20} !47 = !{} -!48 = !{!"small.cc", !"/Users/manav/R8248330"} -!49 = !{i32 1, !"Debug Info Version", i32 2} +!48 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330") +!49 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll index 80a19649635a..09428ce9c339 100644 --- a/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll +++ b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll @@ -34,34 +34,34 @@ bb28.i: ; preds = %bb28.i, %bb27.i presymmetry.exit: ; preds = %bb28.i %tmp175387 = or i32 undef, 12 - %scevgep101.i = getelementptr i32* %in, i32 undef + %scevgep101.i = getelementptr i32, i32* %in, i32 undef %tmp189401 = or i32 undef, 7 - %scevgep97.i = getelementptr i32* %in, i32 undef + %scevgep97.i = getelementptr i32, i32* %in, i32 undef %tmp198410 = or i32 undef, 1 - %scevgep.i48 = getelementptr i32* %in, i32 undef - %0 = load i32* %scevgep.i48, align 4 + %scevgep.i48 = getelementptr i32, i32* %in, i32 undef + %0 = load i32, i32* %scevgep.i48, align 4 %1 = add nsw i32 %0, 0 store i32 %1, i32* undef, align 4 %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1 %2 = shl i32 %asmresult1.i.i34.i.i.i, 1 - %3 = load i32* null, align 4 - %4 = load i32* undef, align 4 + %3 = load i32, i32* null, align 4 + %4 = load i32, i32* undef, align 4 %5 = sub nsw i32 %3, %4 - %6 = load i32* undef, align 4 - %7 = load i32* null, align 4 + %6 = load i32, i32* undef, align 4 + %7 = load i32, i32* null, align 4 %8 = sub nsw i32 %6, %7 - %9 = load i32* %scevgep97.i, align 4 - %10 = load i32* undef, align 4 + %9 = load i32, i32* %scevgep97.i, align 4 + %10 = load i32, i32* undef, align 4 %11 = sub nsw i32 %9, %10 - %12 = load i32* null, align 4 - %13 = load i32* %scevgep101.i, align 4 + %12 = load i32, i32* null, align 4 + %13 = load i32, i32* %scevgep101.i, align 4 %14 = sub nsw i32 %12, %13 - %15 = load i32* %scevgep.i48, align 4 - %16 = load i32* null, align 4 + %15 = load i32, i32* %scevgep.i48, align 4 + %16 = load i32, i32* null, align 4 %17 = add nsw i32 %16, %15 %18 = sub nsw i32 %15, %16 - %19 = load i32* undef, align 4 + %19 = load i32, i32* undef, align 4 %20 = add nsw i32 %19, %2 %21 = sub nsw i32 %19, %2 %22 = add nsw i32 %14, %5 diff --git a/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/test/CodeGen/ARM/2010-12-08-tpsoft.ll index 1351a26756ef..9dfe4da27677 100644 --- a/test/CodeGen/ARM/2010-12-08-tpsoft.ll +++ b/test/CodeGen/ARM/2010-12-08-tpsoft.ll @@ -12,7 +12,7 @@ define arm_aapcs_vfpcc i32 @main() nounwind { entry: - %0 = load i32* @i, align 4 + %0 = load i32, i32* @i, align 4 switch i32 %0, label %bb2 [ i32 12, label %bb i32 13, label %bb1 diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index f13bc1214a5a..f04e053b2e04 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -12,14 +12,9 @@ ; ASM: .type array00,%object @ @array00 ; ASM-NEXT: .local array00 ; ASM-NEXT: .comm array00,80,1 -; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals +; ASM-NEXT: .type sum,%object @ @sum -; OBJ: Sections [ -; OBJ: Section { -; OBJ: Index: 4 -; OBJ-NEXT: Name: .bss - ; OBJ: Symbols [ ; OBJ: Symbol { ; OBJ: Name: array00 @@ -31,9 +26,9 @@ ; OBJ-NEXT: Section: .bss define i32 @main(i32 %argc) nounwind { - %1 = load i32* @sum, align 4 - %2 = getelementptr [80 x i8]* @array00, i32 0, i32 %argc - %3 = load i8* %2 + %1 = load i32, i32* @sum, align 4 + %2 = getelementptr [80 x i8], [80 x i8]* @array00, i32 0, i32 %argc + %3 = load i8, i8* %2 %4 = zext i8 %3 to i32 %5 = add i32 %1, %4 ret i32 %5 diff --git a/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll b/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll index a2f50b587b22..783c82eb88b7 100644 --- a/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll +++ b/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll @@ -9,7 +9,7 @@ entry: br label %bb bb: - %p.2 = getelementptr [8096 x i8]* %buf, i32 0, i32 0 + %p.2 = getelementptr [8096 x i8], [8096 x i8]* %buf, i32 0, i32 0 store i8 undef, i8* %p.2, align 1 ret void } diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 67dda672719c..9a5baf21b8fb 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -1,4 +1,4 @@ -; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s +; RUN: llc -arm-global-merge -global-merge-group-by-use=false -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" @@ -30,9 +30,9 @@ target triple = "thumbv7-apple-darwin10" define zeroext i8 @get1(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30 - %0 = load i8* @x1, align 4, !dbg !30 - tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !10, metadata !DIExpression()), !dbg !30 + %0 = load i8, i8* @x1, align 4, !dbg !30 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !11, metadata !DIExpression()), !dbg !30 store i8 %a, i8* @x1, align 4, !dbg !30 ret i8 %0, !dbg !31 } @@ -41,36 +41,36 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon define zeroext i8 @get2(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !32 - %0 = load i8* @x2, align 4, !dbg !32 - tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !32 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !18, metadata !DIExpression()), !dbg !32 + %0 = load i8, i8* @x2, align 4, !dbg !32 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !DIExpression()), !dbg !32 store i8 %a, i8* @x2, align 4, !dbg !32 ret i8 %0, !dbg !33 } define zeroext i8 @get3(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !34 - %0 = load i8* @x3, align 4, !dbg !34 - tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !34 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !21, metadata !DIExpression()), !dbg !34 + %0 = load i8, i8* @x3, align 4, !dbg !34 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !22, metadata !DIExpression()), !dbg !34 store i8 %a, i8* @x3, align 4, !dbg !34 ret i8 %0, !dbg !35 } define zeroext i8 @get4(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !36 - %0 = load i8* @x4, align 4, !dbg !36 - tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !36 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !24, metadata !DIExpression()), !dbg !36 + %0 = load i8, i8* @x4, align 4, !dbg !36 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !25, metadata !DIExpression()), !dbg !36 store i8 %a, i8* @x4, align 4, !dbg !36 ret i8 %0, !dbg !37 } define zeroext i8 @get5(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38 - %0 = load i8* @x5, align 4, !dbg !38 - tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !38 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !27, metadata !DIExpression()), !dbg !38 + %0 = load i8, i8* @x5, align 4, !dbg !38 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !28, metadata !DIExpression()), !dbg !38 store i8 %a, i8* @x5, align 4, !dbg !38 ret i8 %0, !dbg !39 } @@ -78,46 +78,46 @@ entry: !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!49} -!0 = !{!"0x2e\00get1\00get1\00get1\004\000\001\000\006\00256\001\004", !47, !1, !3, null, i8 (i8)* @get1, null, null, !42} ; [ DW_TAG_subprogram ] -!1 = !{!"0x29", !47} ; [ DW_TAG_file_type ] -!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)\001\00\000\00\000", !47, !48, !48, !40, !41, !48} ; [ DW_TAG_compile_unit ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !47, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DISubprogram(name: "get1", linkageName: "get1", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !47, scope: !1, type: !3, function: i8 (i8)* @get1, variables: !42) +!1 = !DIFile(filename: "foo.c", directory: "/tmp/") +!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", isOptimized: true, emissionKind: 0, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) +!3 = !DISubroutineType(types: !4) !4 = !{!5, !5} -!5 = !{!"0x24\00_Bool\000\008\008\000\000\002", !47, !1} ; [ DW_TAG_base_type ] -!6 = !{!"0x2e\00get2\00get2\00get2\007\000\001\000\006\00256\001\007", !47, !1, !3, null, i8 (i8)* @get2, null, null, !43} ; [ DW_TAG_subprogram ] -!7 = !{!"0x2e\00get3\00get3\00get3\0010\000\001\000\006\00256\001\0010", !47, !1, !3, null, i8 (i8)* @get3, null, null, !44} ; [ DW_TAG_subprogram ] -!8 = !{!"0x2e\00get4\00get4\00get4\0013\000\001\000\006\00256\001\0013", !47, !1, !3, null, i8 (i8)* @get4, null, null, !45} ; [ DW_TAG_subprogram ] -!9 = !{!"0x2e\00get5\00get5\00get5\0016\000\001\000\006\00256\001\0016", !47, !1, !3, null, i8 (i8)* @get5, null, null, !46} ; [ DW_TAG_subprogram ] -!10 = !{!"0x101\00a\004\000", !0, !1, !5} ; [ DW_TAG_arg_variable ] -!11 = !{!"0x100\00b\004\000", !12, !1, !5} ; [ DW_TAG_auto_variable ] -!12 = !{!"0xb\004\000\000", !47, !0} ; [ DW_TAG_lexical_block ] -!13 = !{!"0x34\00x1\00x1\00\003\001\001", !1, !1, !5, i8* @x1, null} ; [ DW_TAG_variable ] -!14 = !{!"0x34\00x2\00x2\00\006\001\001", !1, !1, !5, i8* @x2, null} ; [ DW_TAG_variable ] -!15 = !{!"0x34\00x3\00x3\00\009\001\001", !1, !1, !5, i8* @x3, null} ; [ DW_TAG_variable ] -!16 = !{!"0x34\00x4\00x4\00\0012\001\001", !1, !1, !5, i8* @x4, null} ; [ DW_TAG_variable ] -!17 = !{!"0x34\00x5\00x5\00\0015\000\001", !1, !1, !5, i8* @x5, null} ; [ DW_TAG_variable ] -!18 = !{!"0x101\00a\007\000", !6, !1, !5} ; [ DW_TAG_arg_variable ] -!19 = !{!"0x100\00b\007\000", !20, !1, !5} ; [ DW_TAG_auto_variable ] -!20 = !{!"0xb\007\000\001", !47, !6} ; [ DW_TAG_lexical_block ] -!21 = !{!"0x101\00a\0010\000", !7, !1, !5} ; [ DW_TAG_arg_variable ] -!22 = !{!"0x100\00b\0010\000", !23, !1, !5} ; [ DW_TAG_auto_variable ] -!23 = !{!"0xb\0010\000\002", !47, !7} ; [ DW_TAG_lexical_block ] -!24 = !{!"0x101\00a\0013\000", !8, !1, !5} ; [ DW_TAG_arg_variable ] -!25 = !{!"0x100\00b\0013\000", !26, !1, !5} ; [ DW_TAG_auto_variable ] -!26 = !{!"0xb\0013\000\003", !47, !8} ; [ DW_TAG_lexical_block ] -!27 = !{!"0x101\00a\0016\000", !9, !1, !5} ; [ DW_TAG_arg_variable ] -!28 = !{!"0x100\00b\0016\000", !29, !1, !5} ; [ DW_TAG_auto_variable ] -!29 = !{!"0xb\0016\000\004", !47, !9} ; [ DW_TAG_lexical_block ] -!30 = !MDLocation(line: 4, scope: !0) -!31 = !MDLocation(line: 4, scope: !12) -!32 = !MDLocation(line: 7, scope: !6) -!33 = !MDLocation(line: 7, scope: !20) -!34 = !MDLocation(line: 10, scope: !7) -!35 = !MDLocation(line: 10, scope: !23) -!36 = !MDLocation(line: 13, scope: !8) -!37 = !MDLocation(line: 13, scope: !26) -!38 = !MDLocation(line: 16, scope: !9) -!39 = !MDLocation(line: 16, scope: !29) +!5 = !DIBasicType(tag: DW_TAG_base_type, name: "_Bool", size: 8, align: 8, encoding: DW_ATE_boolean) +!6 = !DISubprogram(name: "get2", linkageName: "get2", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !47, scope: !1, type: !3, function: i8 (i8)* @get2, variables: !43) +!7 = !DISubprogram(name: "get3", linkageName: "get3", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !47, scope: !1, type: !3, function: i8 (i8)* @get3, variables: !44) +!8 = !DISubprogram(name: "get4", linkageName: "get4", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !47, scope: !1, type: !3, function: i8 (i8)* @get4, variables: !45) +!9 = !DISubprogram(name: "get5", linkageName: "get5", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !47, scope: !1, type: !3, function: i8 (i8)* @get5, variables: !46) +!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 0, scope: !0, file: !1, type: !5) +!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 4, scope: !12, file: !1, type: !5) +!12 = distinct !DILexicalBlock(line: 4, column: 0, file: !47, scope: !0) +!13 = !DIGlobalVariable(name: "x1", line: 3, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x1) +!14 = !DIGlobalVariable(name: "x2", line: 6, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x2) +!15 = !DIGlobalVariable(name: "x3", line: 9, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x3) +!16 = !DIGlobalVariable(name: "x4", line: 12, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x4) +!17 = !DIGlobalVariable(name: "x5", line: 15, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x5) +!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 7, arg: 0, scope: !6, file: !1, type: !5) +!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 7, scope: !20, file: !1, type: !5) +!20 = distinct !DILexicalBlock(line: 7, column: 0, file: !47, scope: !6) +!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 10, arg: 0, scope: !7, file: !1, type: !5) +!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 10, scope: !23, file: !1, type: !5) +!23 = distinct !DILexicalBlock(line: 10, column: 0, file: !47, scope: !7) +!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 13, arg: 0, scope: !8, file: !1, type: !5) +!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 13, scope: !26, file: !1, type: !5) +!26 = distinct !DILexicalBlock(line: 13, column: 0, file: !47, scope: !8) +!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 16, arg: 0, scope: !9, file: !1, type: !5) +!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 16, scope: !29, file: !1, type: !5) +!29 = distinct !DILexicalBlock(line: 16, column: 0, file: !47, scope: !9) +!30 = !DILocation(line: 4, scope: !0) +!31 = !DILocation(line: 4, scope: !12) +!32 = !DILocation(line: 7, scope: !6) +!33 = !DILocation(line: 7, scope: !20) +!34 = !DILocation(line: 10, scope: !7) +!35 = !DILocation(line: 10, scope: !23) +!36 = !DILocation(line: 13, scope: !8) +!37 = !DILocation(line: 13, scope: !26) +!38 = !DILocation(line: 16, scope: !9) +!39 = !DILocation(line: 16, scope: !29) !40 = !{!0, !6, !7, !8, !9} !41 = !{!13, !14, !15, !16, !17} !42 = !{!10, !11} @@ -125,6 +125,6 @@ entry: !44 = !{!21, !22} !45 = !{!24, !25} !46 = !{!27, !28} -!47 = !{!"foo.c", !"/tmp/"} +!47 = !DIFile(filename: "foo.c", directory: "/tmp/") !48 = !{} -!49 = !{i32 1, !"Debug Info Version", i32 2} +!49 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll b/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll index 3950c9e081f7..8403dd991360 100644 --- a/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll +++ b/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll @@ -19,7 +19,7 @@ bb3: ; preds = %bb, %entry br i1 %tst, label %bb46, label %bb8 bb8: ; preds = %bb3 - %1 = getelementptr inbounds i8* %0, i32 0 + %1 = getelementptr inbounds i8, i8* %0, i32 0 store i8 0, i8* %1, align 1 %2 = call i32 @ptou() nounwind ; CHECK: umull [[REGISTER:lr|r[0-9]+]], diff --git a/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll index f3d788818afc..e96641bf6671 100644 --- a/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll +++ b/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll @@ -39,12 +39,12 @@ bb134: ; preds = %bb131 unreachable bb135: ; preds = %meshBB396 - %uriHash.1.phi.load = load i32* undef - %.load120 = load i8*** %.SV116 - %.phi24 = load i8* null - %.phi26 = load i8** null + %uriHash.1.phi.load = load i32, i32* undef + %.load120 = load i8**, i8*** %.SV116 + %.phi24 = load i8, i8* null + %.phi26 = load i8*, i8** null store i8 %.phi24, i8* %.phi26, align 1 - %0 = getelementptr inbounds i8* %.phi26, i32 1 + %0 = getelementptr inbounds i8, i8* %.phi26, i32 1 store i8* %0, i8** %.load120, align 4 ; CHECK: mul [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], @@ -52,7 +52,7 @@ bb135: ; preds = %meshBB396 %1 = mul i32 %uriHash.1.phi.load, 1000003 %2 = xor i32 0, %1 store i32 %2, i32* null - %3 = load i8* null, align 1 + %3 = load i8, i8* null, align 1 %4 = icmp eq i8 %3, 0 store i8* %0, i8** undef br i1 %4, label %meshBB472, label %bb131 diff --git a/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll index 81babe0b4b19..c447a1f25b65 100644 --- a/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll +++ b/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll @@ -17,10 +17,10 @@ bb: ; preds = %entry bb1: ; preds = %entry %0 = call %struct.ui* @vn_pp_to_ui(i32* undef) nounwind call void @llvm.memset.p0i8.i32(i8* undef, i8 0, i32 40, i32 4, i1 false) - %1 = getelementptr inbounds %struct.ui* %0, i32 0, i32 0 + %1 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 0 store %struct.mo* undef, %struct.mo** %1, align 4 - %2 = getelementptr inbounds %struct.ui* %0, i32 0, i32 5 - %3 = load i64* %2, align 4 + %2 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 5 + %3 = load i64, i64* %2, align 4 %4 = call i32 @mo_create_nnm(%struct.mo* undef, i64 %3, i32** undef) nounwind br i1 undef, label %bb3, label %bb2 diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll index 837feb6e85c2..92bdd19a7b3d 100644 --- a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll +++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll @@ -18,11 +18,11 @@ for.body.lr.ph: for.body: ; preds = %_Z14printIsNotZeroi.exit17.for.body_crit_edge, %for.body.lr.ph %tmp3 = phi i1 [ false, %for.body.lr.ph ], [ %phitmp27, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ] %i.022 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ] - %x = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0 - %y = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1 + %x = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0 + %y = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1 %inc = add i32 %i.022, 1 - %tmp8 = load i32* %x, align 4 - %tmp11 = load i32* %y, align 4 + %tmp8 = load i32, i32* %x, align 4 + %tmp11 = load i32, i32* %y, align 4 %mul = mul nsw i32 %tmp11, %tmp8 %tobool.i14 = icmp eq i32 %mul, 0 br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16 @@ -34,8 +34,8 @@ _Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi br label %_Z14printIsNotZeroi.exit17.for.body_crit_edge _Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17 - %b.phi.trans.insert = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3 - %tmp3.pre = load i8* %b.phi.trans.insert, align 1 + %b.phi.trans.insert = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3 + %tmp3.pre = load i8, i8* %b.phi.trans.insert, align 1 %phitmp27 = icmp eq i8 %val8, 0 br label %for.body diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll index f3dd3dd5811e..7f603157c5d3 100644 --- a/test/CodeGen/ARM/2011-04-07-schediv.ll +++ b/test/CodeGen/ARM/2011-04-07-schediv.ll @@ -18,10 +18,10 @@ entry: bb: ; preds = %entry, %bb %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] %tmp = mul i32 %j.05, %src_copy_start_index - %uglygep = getelementptr i8* %src_copy_start6, i32 %tmp + %uglygep = getelementptr i8, i8* %src_copy_start6, i32 %tmp %src_copy_start_addr.04 = bitcast i8* %uglygep to float* - %dst_copy_start_addr.03 = getelementptr float* %dst_copy_start, i32 %j.05 - %1 = load float* %src_copy_start_addr.04, align 4 + %dst_copy_start_addr.03 = getelementptr float, float* %dst_copy_start, i32 %j.05 + %1 = load float, float* %src_copy_start_addr.04, align 4 store float %1, float* %dst_copy_start_addr.03, align 4 %2 = add i32 %j.05, 1 %exitcond = icmp eq i32 %2, %src_width diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll index e30c9c615053..54fc9b049b8e 100644 --- a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll +++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll @@ -18,8 +18,8 @@ for.body: ; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}} ; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}} ; CHECK-NOT: mov r{{[0-9]+}}, #{{[01]}} - %arrayidx = getelementptr i32* %A, i32 %0 - %tmp4 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr i32, i32* %A, i32 %0 + %tmp4 = load i32, i32* %arrayidx, align 4 %cmp6 = icmp eq i32 %tmp4, %value br i1 %cmp6, label %return, label %for.inc diff --git a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll index e9a6793a768a..8ad654fc8f9d 100644 --- a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll +++ b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll @@ -7,7 +7,7 @@ target triple = "thumbv7-apple-darwin10.0.0" define void @_Z8TestCasev() nounwind ssp { entry: %a = alloca float, align 4 - %tmp = load float* %a, align 4 + %tmp = load float, float* %a, align 4 call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0 ret void } diff --git a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll index e712e08ddb6a..f17884e0fa41 100644 --- a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll +++ b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll @@ -12,7 +12,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - tail call void (...)* @g(i32 %a, i32 %b) nounwind + tail call void (...) @g(i32 %a, i32 %b) nounwind br label %if.end if.end: ; preds = %if.then, %entry diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll index 5404cf57a59f..864e2917b7bb 100644 --- a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll +++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll @@ -12,7 +12,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - tail call void (...)* @h(i32 %a, i32 %b) nounwind + tail call void (...) @h(i32 %a, i32 %b) nounwind br label %if.end if.end: ; preds = %if.then, %entry @@ -31,7 +31,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - tail call void (...)* @h(i32 %a, i32 %b) nounwind + tail call void (...) @h(i32 %a, i32 %b) nounwind br label %if.end if.end: ; preds = %if.then, %entry diff --git a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll index 057c19948c35..ee6d79c39f2f 100644 --- a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll +++ b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll @@ -22,7 +22,7 @@ entry: %block_count = alloca i32, align 4 %index_cache = alloca i32, align 4 store i32 0, i32* %index_cache, align 4 - %tmp = load i32* @G, align 4 + %tmp = load i32, i32* @G, align 4 %tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind switch i32 %tmp1, label %bb8 [ i32 0, label %bb @@ -31,7 +31,7 @@ entry: ] bb: - %tmp2 = load i32* @G, align 4 + %tmp2 = load i32, i32* @G, align 4 %tmp4 = icmp eq i32 %tmp2, 0 br i1 %tmp4, label %bb1, label %bb8 @@ -41,14 +41,14 @@ bb1: ; CHECK: blx _Get ; CHECK: umull ; CHECK: blx _foo - %tmp5 = load i32* %block_size, align 4 - %tmp6 = load i32* %block_count, align 4 + %tmp5 = load i32, i32* %block_size, align 4 + %tmp6 = load i32, i32* %block_count, align 4 %tmp7 = call %struct.FF* @Get() nounwind store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4 %tmp10 = zext i32 %tmp6 to i64 %tmp11 = zext i32 %tmp5 to i64 %tmp12 = mul nsw i64 %tmp10, %tmp11 - %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind + %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind br label %bb8 bb4: diff --git a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll index 091d037356de..aac8f7b3a026 100644 --- a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll +++ b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -arm-global-merge -global-merge-group-by-use=false | FileCheck %s ; CHECK: .zerofill __DATA,__bss,__MergedGlobals,16,2 @prev = external global [0 x i16] diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 3edc946825bb..067c719f491c 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -1,4 +1,4 @@ -; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s +; RUN: llc -arm-global-merge -global-merge-group-by-use=false -filetype=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s ; Check debug info output for merged global. ; DW_AT_location @@ -29,41 +29,41 @@ target triple = "thumbv7-apple-macosx10.7.0" @x5 = global i32 0, align 4 define i32 @get1(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30 - %1 = load i32* @x1, align 4, !dbg !31 - tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !31 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !10, metadata !DIExpression()), !dbg !30 + %1 = load i32, i32* @x1, align 4, !dbg !31 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !11, metadata !DIExpression()), !dbg !31 store i32 %a, i32* @x1, align 4, !dbg !31 ret i32 %1, !dbg !31 } define i32 @get2(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !32 - %1 = load i32* @x2, align 4, !dbg !33 - tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !33 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !DIExpression()), !dbg !32 + %1 = load i32, i32* @x2, align 4, !dbg !33 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !14, metadata !DIExpression()), !dbg !33 store i32 %a, i32* @x2, align 4, !dbg !33 ret i32 %1, !dbg !33 } define i32 @get3(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !34 - %1 = load i32* @x3, align 4, !dbg !35 - tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !35 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !16, metadata !DIExpression()), !dbg !34 + %1 = load i32, i32* @x3, align 4, !dbg !35 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !17, metadata !DIExpression()), !dbg !35 store i32 %a, i32* @x3, align 4, !dbg !35 ret i32 %1, !dbg !35 } define i32 @get4(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !36 - %1 = load i32* @x4, align 4, !dbg !37 - tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !37 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !19, metadata !DIExpression()), !dbg !36 + %1 = load i32, i32* @x4, align 4, !dbg !37 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !20, metadata !DIExpression()), !dbg !37 store i32 %a, i32* @x4, align 4, !dbg !37 ret i32 %1, !dbg !37 } define i32 @get5(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38 - %1 = load i32* @x5, align 4, !dbg !39 - tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !27, metadata !DIExpression()), !dbg !38 + %1 = load i32, i32* @x5, align 4, !dbg !39 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !28, metadata !DIExpression()), !dbg !39 store i32 %a, i32* @x5, align 4, !dbg !39 ret i32 %1, !dbg !39 } @@ -73,43 +73,43 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!49} -!0 = !{!"0x11\0012\00clang\001\00\000\00\001", !47, !48, !48, !40, !41, !48} ; [ DW_TAG_compile_unit ] -!1 = !{!"0x2e\00get1\00get1\00\005\000\001\000\006\00256\001\005", !47, !2, !3, null, i32 (i32)* @get1, null, null, !42} ; [ DW_TAG_subprogram ] [line 5] [def] [get1] -!2 = !{!"0x29", !47} ; [ DW_TAG_file_type ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !47, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 1, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) +!1 = !DISubprogram(name: "get1", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !47, scope: !2, type: !3, function: i32 (i32)* @get1, variables: !42) +!2 = !DIFile(filename: "ss3.c", directory: "/private/tmp") +!3 = !DISubroutineType(types: !4) !4 = !{!5} -!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ] -!6 = !{!"0x2e\00get2\00get2\00\008\000\001\000\006\00256\001\008", !47, !2, !3, null, i32 (i32)* @get2, null, null, !43} ; [ DW_TAG_subprogram ] [line 8] [def] [get2] -!7 = !{!"0x2e\00get3\00get3\00\0011\000\001\000\006\00256\001\0011", !47, !2, !3, null, i32 (i32)* @get3, null, null, !44} ; [ DW_TAG_subprogram ] [line 11] [def] [get3] -!8 = !{!"0x2e\00get4\00get4\00\0014\000\001\000\006\00256\001\0014", !47, !2, !3, null, i32 (i32)* @get4, null, null, !45} ; [ DW_TAG_subprogram ] [line 14] [def] [get4] -!9 = !{!"0x2e\00get5\00get5\00\0017\000\001\000\006\00256\001\0017", !47, !2, !3, null, i32 (i32)* @get5, null, null, !46} ; [ DW_TAG_subprogram ] [line 17] [def] [get5] -!10 = !{!"0x101\00a\0016777221\000", !1, !2, !5} ; [ DW_TAG_arg_variable ] -!11 = !{!"0x100\00b\005\000", !12, !2, !5} ; [ DW_TAG_auto_variable ] -!12 = !{!"0xb\005\0019\000", !47, !1} ; [ DW_TAG_lexical_block ] -!13 = !{!"0x101\00a\0016777224\000", !6, !2, !5} ; [ DW_TAG_arg_variable ] -!14 = !{!"0x100\00b\008\000", !15, !2, !5} ; [ DW_TAG_auto_variable ] -!15 = !{!"0xb\008\0017\001", !47, !6} ; [ DW_TAG_lexical_block ] -!16 = !{!"0x101\00a\0016777227\000", !7, !2, !5} ; [ DW_TAG_arg_variable ] -!17 = !{!"0x100\00b\0011\000", !18, !2, !5} ; [ DW_TAG_auto_variable ] -!18 = !{!"0xb\0011\0019\002", !47, !7} ; [ DW_TAG_lexical_block ] -!19 = !{!"0x101\00a\0016777230\000", !8, !2, !5} ; [ DW_TAG_arg_variable ] -!20 = !{!"0x100\00b\0014\000", !21, !2, !5} ; [ DW_TAG_auto_variable ] -!21 = !{!"0xb\0014\0019\003", !47, !8} ; [ DW_TAG_lexical_block ] -!25 = !{!"0x34\00x1\00x1\00\004\001\001", !0, !2, !5, i32* @x1, null} ; [ DW_TAG_variable ] -!26 = !{!"0x34\00x2\00x2\00\007\001\001", !0, !2, !5, i32* @x2, null} ; [ DW_TAG_variable ] -!27 = !{!"0x101\00a\0016777233\000", !9, !2, !5} ; [ DW_TAG_arg_variable ] -!28 = !{!"0x100\00b\0017\000", !29, !2, !5} ; [ DW_TAG_auto_variable ] -!29 = !{!"0xb\0017\0019\004", !47, !9} ; [ DW_TAG_lexical_block ] -!30 = !MDLocation(line: 5, column: 16, scope: !1) -!31 = !MDLocation(line: 5, column: 32, scope: !12) -!32 = !MDLocation(line: 8, column: 14, scope: !6) -!33 = !MDLocation(line: 8, column: 29, scope: !15) -!34 = !MDLocation(line: 11, column: 16, scope: !7) -!35 = !MDLocation(line: 11, column: 32, scope: !18) -!36 = !MDLocation(line: 14, column: 16, scope: !8) -!37 = !MDLocation(line: 14, column: 32, scope: !21) -!38 = !MDLocation(line: 17, column: 16, scope: !9) -!39 = !MDLocation(line: 17, column: 32, scope: !29) +!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!6 = !DISubprogram(name: "get2", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !47, scope: !2, type: !3, function: i32 (i32)* @get2, variables: !43) +!7 = !DISubprogram(name: "get3", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !47, scope: !2, type: !3, function: i32 (i32)* @get3, variables: !44) +!8 = !DISubprogram(name: "get4", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !47, scope: !2, type: !3, function: i32 (i32)* @get4, variables: !45) +!9 = !DISubprogram(name: "get5", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 17, file: !47, scope: !2, type: !3, function: i32 (i32)* @get5, variables: !46) +!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 5, arg: 1, scope: !1, file: !2, type: !5) +!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 5, scope: !12, file: !2, type: !5) +!12 = distinct !DILexicalBlock(line: 5, column: 19, file: !47, scope: !1) +!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 8, arg: 1, scope: !6, file: !2, type: !5) +!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 8, scope: !15, file: !2, type: !5) +!15 = distinct !DILexicalBlock(line: 8, column: 17, file: !47, scope: !6) +!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 11, arg: 1, scope: !7, file: !2, type: !5) +!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 11, scope: !18, file: !2, type: !5) +!18 = distinct !DILexicalBlock(line: 11, column: 19, file: !47, scope: !7) +!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 14, arg: 1, scope: !8, file: !2, type: !5) +!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 14, scope: !21, file: !2, type: !5) +!21 = distinct !DILexicalBlock(line: 14, column: 19, file: !47, scope: !8) +!25 = !DIGlobalVariable(name: "x1", line: 4, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !5, variable: i32* @x1) +!26 = !DIGlobalVariable(name: "x2", line: 7, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !5, variable: i32* @x2) +!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 17, arg: 1, scope: !9, file: !2, type: !5) +!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 17, scope: !29, file: !2, type: !5) +!29 = distinct !DILexicalBlock(line: 17, column: 19, file: !47, scope: !9) +!30 = !DILocation(line: 5, column: 16, scope: !1) +!31 = !DILocation(line: 5, column: 32, scope: !12) +!32 = !DILocation(line: 8, column: 14, scope: !6) +!33 = !DILocation(line: 8, column: 29, scope: !15) +!34 = !DILocation(line: 11, column: 16, scope: !7) +!35 = !DILocation(line: 11, column: 32, scope: !18) +!36 = !DILocation(line: 14, column: 16, scope: !8) +!37 = !DILocation(line: 14, column: 32, scope: !21) +!38 = !DILocation(line: 17, column: 16, scope: !9) +!39 = !DILocation(line: 17, column: 32, scope: !29) !40 = !{!1, !6, !7, !8, !9} !41 = !{!25, !26} !42 = !{!10, !11} @@ -117,6 +117,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !44 = !{!16, !17} !45 = !{!19, !20} !46 = !{!27, !28} -!47 = !{!"ss3.c", !"/private/tmp"} +!47 = !DIFile(filename: "ss3.c", directory: "/private/tmp") !48 = !{} -!49 = !{i32 1, !"Debug Info Version", i32 2} +!49 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/2011-08-29-SchedCycle.ll b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll index be188ef630f2..fb8454479508 100644 --- a/test/CodeGen/ARM/2011-08-29-SchedCycle.ll +++ b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll @@ -32,7 +32,7 @@ define void @t() nounwind { entry: - %tmp = load i64* undef, align 4 + %tmp = load i64, i64* undef, align 4 %tmp5 = udiv i64 %tmp, 30 %tmp13 = and i64 %tmp5, 64739244643450880 %tmp16 = sub i64 0, %tmp13 diff --git a/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll index 6647ed8106d5..d9b38b5e5735 100644 --- a/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll +++ b/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll @@ -17,13 +17,13 @@ bb25.lr.ph: ; preds = %entry bb.i: ; preds = %bb5.i %1 = shl nsw i32 %k_addr.0.i, 1 %.sum8.i = add i32 %1, -1 - %2 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum8.i - %3 = load i32* %2, align 4 + %2 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum8.i + %3 = load i32, i32* %2, align 4 br i1 false, label %bb5.i, label %bb4.i bb4.i: ; preds = %bb.i %.sum10.i = add i32 %k_addr.0.i, -1 - %4 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum10.i + %4 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum10.i store i32 %3, i32* %4, align 4 br label %bb5.i diff --git a/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll b/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll index 8fe91028e0c2..2561af707d75 100644 --- a/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll +++ b/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll @@ -11,12 +11,12 @@ target triple = "armv7-none-linux-gnueabi" @z2 = common global <4 x i16> zeroinitializer define void @f() { - %1 = load <3 x i16>* @x1 - %2 = load <3 x i16>* @y1 + %1 = load <3 x i16>, <3 x i16>* @x1 + %2 = load <3 x i16>, <3 x i16>* @y1 %3 = sdiv <3 x i16> %1, %2 store <3 x i16> %3, <3 x i16>* @z1 - %4 = load <4 x i16>* @x2 - %5 = load <4 x i16>* @y2 + %4 = load <4 x i16>, <4 x i16>* @x2 + %5 = load <4 x i16>, <4 x i16>* @y2 %6 = sdiv <4 x i16> %4, %5 store <4 x i16> %6, <4 x i16>* @z2 ret void diff --git a/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll index c6f4a93def13..53e3bed53831 100644 --- a/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll +++ b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll @@ -4,7 +4,7 @@ ; ARM target specific dag combine created a cycle in DAG. define void @t() nounwind ssp { - %1 = load i64* undef, align 4 + %1 = load i64, i64* undef, align 4 %2 = shl i32 5, 0 %3 = zext i32 %2 to i64 %4 = and i64 %1, %3 diff --git a/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll index 09db740b7f76..86596d6282fd 100644 --- a/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll +++ b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll @@ -4,16 +4,16 @@ target triple = "armv6-none-linux-gnueabi" define void @sample_test(i8* %.T0348, i16* nocapture %sourceA, i16* nocapture %destValues) { L.entry: - %0 = call i32 (...)* @get_index(i8* %.T0348, i32 0) + %0 = call i32 (...) @get_index(i8* %.T0348, i32 0) %1 = bitcast i16* %destValues to i8* %2 = mul i32 %0, 6 - %3 = getelementptr i8* %1, i32 %2 + %3 = getelementptr i8, i8* %1, i32 %2 %4 = bitcast i8* %3 to <3 x i16>* - %5 = load <3 x i16>* %4, align 1 + %5 = load <3 x i16>, <3 x i16>* %4, align 1 %6 = bitcast i16* %sourceA to i8* - %7 = getelementptr i8* %6, i32 %2 + %7 = getelementptr i8, i8* %6, i32 %2 %8 = bitcast i8* %7 to <3 x i16>* - %9 = load <3 x i16>* %8, align 1 + %9 = load <3 x i16>, <3 x i16>* %8, align 1 %10 = or <3 x i16> %9, %5 store <3 x i16> %10, <3 x i16>* %4, align 1 ret void diff --git a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll index a707a92c9fa0..e7059716c49b 100644 --- a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll +++ b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll @@ -7,8 +7,8 @@ define void @test_neon_vector_add_2xi8() nounwind { ; CHECK-LABEL: test_neon_vector_add_2xi8: - %1 = load <2 x i8>* @i8_src1 - %2 = load <2 x i8>* @i8_src2 + %1 = load <2 x i8>, <2 x i8>* @i8_src1 + %2 = load <2 x i8>, <2 x i8>* @i8_src2 %3 = add <2 x i8> %1, %2 store <2 x i8> %3, <2 x i8>* @i8_res ret void @@ -16,8 +16,8 @@ define void @test_neon_vector_add_2xi8() nounwind { define void @test_neon_ld_st_volatile_with_ashr_2xi8() { ; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8: - %1 = load volatile <2 x i8>* @i8_src1 - %2 = load volatile <2 x i8>* @i8_src2 + %1 = load volatile <2 x i8>, <2 x i8>* @i8_src1 + %2 = load volatile <2 x i8>, <2 x i8>* @i8_src2 %3 = ashr <2 x i8> %1, %2 store volatile <2 x i8> %3, <2 x i8>* @i8_res ret void diff --git a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll index c1554d848c44..6dc9d4b7025d 100644 --- a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll +++ b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll @@ -8,7 +8,7 @@ declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind define void @test_neon_call_return_v2i16() { ; CHECK-LABEL: test_neon_call_return_v2i16: - %1 = load <2 x i16>* @src1_v2i16 + %1 = load <2 x i16>, <2 x i16>* @src1_v2i16 %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind store <2 x i16> %2, <2 x i16>* @res_v2i16 ret void diff --git a/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll b/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll index c50461a42d8b..1da93bdd7c94 100644 --- a/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll +++ b/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll @@ -4,7 +4,7 @@ define <2 x i32> @test1(<2 x double>* %A) { ; CHECK: test1 ; CHECK: vcvt.s32.f64 ; CHECK: vcvt.s32.f64 - %tmp1 = load <2 x double>* %A + %tmp1 = load <2 x double>, <2 x double>* %A %tmp2 = fptosi <2 x double> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } @@ -13,7 +13,7 @@ define <2 x i32> @test2(<2 x double>* %A) { ; CHECK: test2 ; CHECK: vcvt.u32.f64 ; CHECK: vcvt.u32.f64 - %tmp1 = load <2 x double>* %A + %tmp1 = load <2 x double>, <2 x double>* %A %tmp2 = fptoui <2 x double> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } @@ -22,7 +22,7 @@ define <2 x double> @test3(<2 x i32>* %A) { ; CHECK: test3 ; CHECK: vcvt.f64.s32 ; CHECK: vcvt.f64.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = sitofp <2 x i32> %tmp1 to <2 x double> ret <2 x double> %tmp2 } @@ -31,7 +31,7 @@ define <2 x double> @test4(<2 x i32>* %A) { ; CHECK: test4 ; CHECK: vcvt.f64.u32 ; CHECK: vcvt.f64.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = uitofp <2 x i32> %tmp1 to <2 x double> ret <2 x double> %tmp2 } diff --git a/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll index 52aa0bfaa545..7f4057143a07 100644 --- a/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll +++ b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll @@ -18,38 +18,38 @@ target triple = "thumbv7-apple-ios" define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind { entry: store double 1.000000e+00, double* null, align 4 - %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1 + %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1 store double 0.000000e+00, double* %arrayidx5.1.i, align 4 - %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2 + %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2 store double 0.000000e+00, double* %arrayidx5.2.i, align 4 - %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0 + %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0 store double 0.000000e+00, double* %arrayidx5.114.i, align 4 - %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1 + %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60, %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1 store double 1.000000e+00, double* %arrayidx5.1.1.i, align 4 store double 0.000000e+00, double* null, align 4 store double 1.000000e+00, double* null, align 4 store double 0.000000e+00, double* null, align 4 %call = tail call double @cos(double %angle) nounwind readnone %call1 = tail call double @sin(double %angle) nounwind readnone - %0 = load double* %V1, align 4 - %arrayidx2 = getelementptr inbounds double* %V1, i32 1 - %1 = load double* %arrayidx2, align 4 + %0 = load double, double* %V1, align 4 + %arrayidx2 = getelementptr inbounds double, double* %V1, i32 1 + %1 = load double, double* %arrayidx2, align 4 %mul = fmul double %0, %1 %sub = fsub double 1.000000e+00, %call %mul3 = fmul double %mul, %sub - %2 = load double* undef, align 4 + %2 = load double, double* undef, align 4 %mul5 = fmul double %2, %call1 %add = fadd double %mul3, %mul5 store double %add, double* %arrayidx5.1.i, align 4 - %3 = load double* %V1, align 4 + %3 = load double, double* %V1, align 4 %mul11 = fmul double %3, undef %mul13 = fmul double %mul11, %sub - %4 = load double* %arrayidx2, align 4 + %4 = load double, double* %arrayidx2, align 4 %mul15 = fmul double %4, %call1 %sub16 = fsub double %mul13, %mul15 store double %sub16, double* %arrayidx5.2.i, align 4 - %5 = load double* %V1, align 4 - %6 = load double* %arrayidx2, align 4 + %5 = load double, double* %V1, align 4 + %6 = load double, double* %arrayidx2, align 4 %mul22 = fmul double %5, %6 %mul24 = fmul double %mul22, %sub %sub27 = fsub double %mul24, undef diff --git a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll index bc496b99f4a6..d820d688fde9 100644 --- a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll +++ b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll @@ -15,14 +15,14 @@ define hidden void @foo() { ; CHECK: ldr.w ; CHECK-NOT: ldm entry: - %tmp13 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1 - %tmp15 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1 - %tmp17 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1 - %tmp19 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1 - %tmp = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1 - %tmp3 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1 - %tmp4 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1 - %tmp5 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1 + %tmp13 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1 + %tmp15 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1 + %tmp17 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1 + %tmp19 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1 + %tmp = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1 + %tmp3 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1 + %tmp4 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1 + %tmp5 = load i32, i32* getelementptr inbounds (%struct.InformationBlock, %struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1 %insert21 = insertvalue [4 x i32] undef, i32 %tmp13, 0 %insert23 = insertvalue [4 x i32] %insert21, i32 %tmp15, 1 %insert25 = insertvalue [4 x i32] %insert23, i32 %tmp17, 2 diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index 86b58c8186b0..404aca13cdba 100644 --- a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -16,7 +16,7 @@ define void @test_sqrt(<4 x float>* %X) nounwind { ; CHECK: vst1.64 {{.*}} L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -48,7 +48,7 @@ define void @test_cos(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -79,7 +79,7 @@ define void @test_exp(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -110,7 +110,7 @@ define void @test_exp2(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -141,7 +141,7 @@ define void @test_log10(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -172,7 +172,7 @@ define void @test_log(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -203,7 +203,7 @@ define void @test_log2(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -236,7 +236,7 @@ define void @test_pow(<4 x float>* %X) nounwind { L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> <float 2., float 2., float 2., float 2.>) store <4 x float> %1, <4 x float>* %X, align 16 @@ -259,7 +259,7 @@ define void @test_powi(<4 x float>* %X) nounwind { L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2) store <4 x float> %1, <4 x float>* %X, align 16 @@ -292,7 +292,7 @@ define void @test_sin(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -323,7 +323,7 @@ define void @test_floor(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void diff --git a/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll b/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll index 0c90f4cf949a..0d324404d7be 100644 --- a/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll +++ b/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll @@ -8,9 +8,9 @@ target triple = "thumbv7-apple-darwin10" @x2 = internal global i64 12 define i64 @f() { - %ax = load i32* @x1 + %ax = load i32, i32* @x1 %a = zext i32 %ax to i64 - %b = load i64* @x2 + %b = load i64, i64* @x2 %c = add i64 %a, %b ret i64 %c } diff --git a/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/test/CodeGen/ARM/2011-12-14-machine-sink.ll index 9334bf36d805..88019f450e36 100644 --- a/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -5,7 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- target triple = "thumbv7-apple-ios4.0.0" ; STATS-NOT: machine-sink -define i32 @foo(i32 %h) nounwind readonly ssp { +define i32 @foo(i32 %h, i32 %arg1) nounwind readonly ssp { entry: br label %for.cond @@ -14,33 +14,26 @@ for.cond: ; preds = %for.body, %entry br i1 %cmp, label %for.body, label %if.end299 for.body: ; preds = %for.cond - %v.5 = select i1 undef, i32 undef, i32 0 - %0 = load i8* undef, align 1 + %cond0 = icmp ne i32 %arg1, 42 + %v.5 = select i1 %cond0, i32 undef, i32 0 + %0 = load i8, i8* undef, align 1 %conv88 = zext i8 %0 to i32 %sub89 = sub nsw i32 0, %conv88 - %v.8 = select i1 undef, i32 undef, i32 %sub89 - %1 = load i8* null, align 1 + %cond1 = icmp ne i32 %arg1, 23 + %v.8 = select i1 %cond1, i32 undef, i32 %sub89 + %1 = load i8, i8* null, align 1 %conv108 = zext i8 %1 to i32 - %2 = load i8* undef, align 1 + %2 = load i8, i8* undef, align 1 %conv110 = zext i8 %2 to i32 %sub111 = sub nsw i32 %conv108, %conv110 %cmp112 = icmp slt i32 %sub111, 0 %sub115 = sub nsw i32 0, %sub111 - %v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111 - %add62 = add i32 0, %v.5 - %add73 = add i32 %add62, 0 - %add84 = add i32 %add73, 0 - %add95 = add i32 %add84, %v.8 - %add106 = add i32 %add95, 0 - %add117 = add i32 %add106, %v.10 - %add128 = add i32 %add117, 0 - %add139 = add i32 %add128, 0 - %add150 = add i32 %add139, 0 - %add161 = add i32 %add150, 0 - %add172 = add i32 %add161, 0 + %abs = select i1 %cmp112, i32 %sub115, i32 %sub111 + %add95 = add i32 %v.5, %v.8 + %add117 = add i32 %add95, %abs br i1 undef, label %for.cond, label %if.end299 if.end299: ; preds = %for.body, %for.cond - %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] + %s.10 = phi i32 [ %add117, %for.body ], [ 0, %for.cond ] ret i32 %s.10 } diff --git a/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll b/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll index ddb76326947c..40d1f628aaae 100644 --- a/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll +++ b/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll @@ -22,13 +22,13 @@ bb: store i32 %b, i32* %tmp1, align 4 store i8* %d, i8** %tmp2, align 4 store i1 false, i1* %tmp3 - %tmp7 = load i8** %c + %tmp7 = load i8*, i8** %c %tmp10 = invoke %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* %tmp7, i8* %d, %0* null) to label %bb11 unwind label %bb15 bb11: ; preds = %bb store %0* %tmp10, %0** %myException, align 4 - %tmp12 = load %0** %myException, align 4 + %tmp12 = load %0*, %0** %myException, align 4 %tmp13 = bitcast %0* %tmp12 to i8* invoke void @objc_exception_throw(i8* %tmp13) noreturn to label %bb14 unwind label %bb15 diff --git a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll index 0f1c452b8678..3f827f8e702f 100644 --- a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll +++ b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -18,7 +18,7 @@ bb3: ; preds = %bb4, %bb2 br i1 %tmp, label %bb4, label %bb67 bb4: ; preds = %bb3 - %tmp5 = load <4 x i32>* undef, align 16 + %tmp5 = load <4 x i32>, <4 x i32>* undef, align 16 %tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607> %tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216> %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float> @@ -41,9 +41,9 @@ bb4: ; preds = %bb3 %tmp24 = trunc i128 %tmp23 to i64 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1 - %tmp27 = load float* undef, align 4 + %tmp27 = load float, float* undef, align 4 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3 - %tmp29 = load <4 x i32>* undef, align 16 + %tmp29 = load <4 x i32>, <4 x i32>* undef, align 16 %tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607> %tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216> %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float> @@ -52,10 +52,10 @@ bb4: ; preds = %bb3 %tmp35 = fmul <4 x float> %tmp34, undef %tmp36 = fmul <4 x float> %tmp35, undef %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp38 = load float* undef, align 4 + %tmp38 = load float, float* undef, align 4 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0 %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp41 = load float* undef, align 4 + %tmp41 = load float, float* undef, align 4 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3 %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer %tmp44 = fmul <4 x float> %tmp33, %tmp43 @@ -64,10 +64,10 @@ bb4: ; preds = %bb3 %tmp47 = fmul <4 x float> %tmp46, %tmp36 %tmp48 = fadd <4 x float> undef, %tmp47 %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp50 = load float* undef, align 4 + %tmp50 = load float, float* undef, align 4 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3 %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind - %tmp54 = load float* %tmp52, align 4 + %tmp54 = load float, float* %tmp52, align 4 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3 %tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind diff --git a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll index 61623ec1b6a4..b70b7f6f3b2e 100644 --- a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -7,7 +7,7 @@ target triple = "armv7-none-linux-eabi" ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE. define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 { bb: - %tmp = load <2 x float>* undef, align 8 + %tmp = load <2 x float>, <2 x float>* undef, align 8 %tmp2 = extractelement <2 x float> %tmp, i32 0 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1 diff --git a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll index a9e2ebb7fe12..2484f0d42ed3 100644 --- a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -56,9 +56,9 @@ bb3: ; preds = %bb2 %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float> %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> - %tmp42 = load <4 x float>* null, align 16 + %tmp42 = load <4 x float>, <4 x float>* null, align 16 %tmp43 = fmul <4 x float> %tmp42, %tmp41 - %tmp44 = load <4 x float>* undef, align 16 + %tmp44 = load <4 x float>, <4 x float>* undef, align 16 %tmp45 = fadd <4 x float> undef, %tmp43 %tmp46 = fadd <4 x float> undef, %tmp45 %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64> @@ -76,7 +76,7 @@ bb3: ; preds = %bb2 %tmp59 = fmul <4 x float> undef, %tmp58 %tmp60 = fadd <4 x float> %tmp59, undef %tmp61 = fadd <4 x float> %tmp60, zeroinitializer - %tmp62 = load void (i8*, i8*)** undef, align 4 + %tmp62 = load void (i8*, i8*)*, void (i8*, i8*)** undef, align 4 call arm_aapcs_vfpcc void %tmp62(i8* sret undef, i8* undef) nounwind %tmp63 = bitcast <4 x float> %tmp46 to i128 %tmp64 = bitcast <4 x float> %tmp54 to i128 @@ -96,7 +96,7 @@ bb3: ; preds = %bb2 call arm_aapcs_vfpcc void @bar(i8* sret null, [8 x i64] %tmp77) nounwind %tmp78 = call arm_aapcs_vfpcc i8* null(i8* null) nounwind %tmp79 = bitcast i8* %tmp78 to i512* - %tmp80 = load i512* %tmp79, align 16 + %tmp80 = load i512, i512* %tmp79, align 16 %tmp81 = lshr i512 %tmp80, 128 %tmp82 = trunc i512 %tmp80 to i128 %tmp83 = trunc i512 %tmp81 to i128 diff --git a/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll b/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll index 6c7aaad7c692..b0411384b96a 100644 --- a/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll +++ b/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll @@ -10,7 +10,7 @@ target triple = "armv7-none-linux-gnueabi" @foo = external global %0, align 16 define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind { - %4 = load <4 x float>* getelementptr inbounds (%0* @foo, i32 0, i32 0), align 16 + %4 = load <4 x float>, <4 x float>* getelementptr inbounds (%0, %0* @foo, i32 0, i32 0), align 16 %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 diff --git a/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll b/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll index 6206cd74d584..6fb760c4bcc7 100644 --- a/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll +++ b/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll @@ -7,7 +7,7 @@ define void @test_hi_short3(<3 x i16> * nocapture %srcA, <2 x i16> * nocapture %dst) nounwind { entry: ; CHECK: vst1.32 - %0 = load <3 x i16> * %srcA, align 8 + %0 = load <3 x i16> , <3 x i16> * %srcA, align 8 %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef> store <2 x i16> %1, <2 x i16> * %dst, align 4 ret void diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index a288015d6016..6f92613fa1ff 100644 --- a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -27,13 +27,13 @@ define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store volatile i32 65540, i32* %p1, align 4 - %0 = load volatile i32* %p2, align 4 + %0 = load volatile i32, i32* %p2, align 4 ret i32 %0 } define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store i32 65540, i32* %p1, align 4 - %0 = load i32* %p2, align 4 + %0 = load i32, i32* %p2, align 4 ret i32 %0 } diff --git a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll index 70e307934559..6e0b828ad24f 100644 --- a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll +++ b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll @@ -129,7 +129,7 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable %45 = fmul <4 x float> undef, undef %46 = fmul <4 x float> %45, %43 %47 = fmul <4 x float> undef, %44 - %48 = load <4 x float>* undef, align 8 + %48 = load <4 x float>, <4 x float>* undef, align 8 %49 = bitcast <4 x float> %48 to <2 x i64> %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1> %51 = bitcast <1 x i64> %50 to <2 x float> diff --git a/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll b/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll index bdcd1b6ad4b7..576dff4d001e 100644 --- a/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll +++ b/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll @@ -6,7 +6,7 @@ target triple = "armv7-none-linux-gnueabi" define void @test_hi_char8() noinline { entry: - %0 = load <4 x i8>* undef, align 1 + %0 = load <4 x i8>, <4 x i8>* undef, align 1 store <4 x i8> %0, <4 x i8>* null, align 4 ret void } diff --git a/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/test/CodeGen/ARM/2012-08-09-neon-extload.ll index a7108253cb62..285a431a6ecf 100644 --- a/test/CodeGen/ARM/2012-08-09-neon-extload.ll +++ b/test/CodeGen/ARM/2012-08-09-neon-extload.ll @@ -14,7 +14,7 @@ define void @test_v2i8tov2i32() { ; CHECK-LABEL: test_v2i8tov2i32: - %i8val = load <2 x i8>* @var_v2i8 + %i8val = load <2 x i8>, <2 x i8>* @var_v2i8 %i32val = sext <2 x i8> %i8val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 @@ -28,7 +28,7 @@ define void @test_v2i8tov2i32() { define void @test_v2i8tov2i64() { ; CHECK-LABEL: test_v2i8tov2i64: - %i8val = load <2 x i8>* @var_v2i8 + %i8val = load <2 x i8>, <2 x i8>* @var_v2i8 %i64val = sext <2 x i8> %i8val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 @@ -46,7 +46,7 @@ define void @test_v2i8tov2i64() { define void @test_v4i8tov4i16() { ; CHECK-LABEL: test_v4i8tov4i16: - %i8val = load <4 x i8>* @var_v4i8 + %i8val = load <4 x i8>, <4 x i8>* @var_v4i8 %i16val = sext <4 x i8> %i8val to <4 x i16> store <4 x i16> %i16val, <4 x i16>* @var_v4i16 @@ -61,7 +61,7 @@ define void @test_v4i8tov4i16() { define void @test_v4i8tov4i32() { ; CHECK-LABEL: test_v4i8tov4i32: - %i8val = load <4 x i8>* @var_v4i8 + %i8val = load <4 x i8>, <4 x i8>* @var_v4i8 %i16val = sext <4 x i8> %i8val to <4 x i32> store <4 x i32> %i16val, <4 x i32>* @var_v4i32 @@ -75,7 +75,7 @@ define void @test_v4i8tov4i32() { define void @test_v2i16tov2i32() { ; CHECK-LABEL: test_v2i16tov2i32: - %i16val = load <2 x i16>* @var_v2i16 + %i16val = load <2 x i16>, <2 x i16>* @var_v2i16 %i32val = sext <2 x i16> %i16val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 @@ -90,7 +90,7 @@ define void @test_v2i16tov2i32() { define void @test_v2i16tov2i64() { ; CHECK-LABEL: test_v2i16tov2i64: - %i16val = load <2 x i16>* @var_v2i16 + %i16val = load <2 x i16>, <2 x i16>* @var_v2i16 %i64val = sext <2 x i16> %i16val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 diff --git a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll index e8d4fb22a59f..3a851d68f0a4 100644 --- a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll +++ b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll @@ -15,7 +15,7 @@ define void @sextload_v4i8_c(<4 x i8>* %v) nounwind { ;CHECK-LABEL: sextload_v4i8_c: entry: - %0 = load <4 x i8>* %v, align 8 + %0 = load <4 x i8>, <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> ;CHECK: vmull %v1 = mul <4 x i32> %v0, <i32 3, i32 3, i32 3, i32 3> @@ -28,7 +28,7 @@ entry: define void @sextload_v2i8_c(<2 x i8>* %v) nounwind { ;CHECK-LABEL: sextload_v2i8_c: entry: - %0 = load <2 x i8>* %v, align 8 + %0 = load <2 x i8>, <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, <i64 3, i64 3> @@ -41,7 +41,7 @@ entry: define void @sextload_v2i16_c(<2 x i16>* %v) nounwind { ;CHECK-LABEL: sextload_v2i16_c: entry: - %0 = load <2 x i16>* %v, align 8 + %0 = load <2 x i16>, <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, <i64 3, i64 3> @@ -56,10 +56,10 @@ entry: define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind { ;CHECK-LABEL: sextload_v4i8_v: entry: - %0 = load <4 x i8>* %v, align 8 + %0 = load <4 x i8>, <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> - %1 = load <4 x i8>* %p, align 8 + %1 = load <4 x i8>, <4 x i8>* %p, align 8 %v2 = sext <4 x i8> %1 to <4 x i32> ;CHECK: vmull %v1 = mul <4 x i32> %v0, %v2 @@ -72,10 +72,10 @@ entry: define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind { ;CHECK-LABEL: sextload_v2i8_v: entry: - %0 = load <2 x i8>* %v, align 8 + %0 = load <2 x i8>, <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> - %1 = load <2 x i8>* %p, align 8 + %1 = load <2 x i8>, <2 x i8>* %p, align 8 %v2 = sext <2 x i8> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 @@ -88,10 +88,10 @@ entry: define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind { ;CHECK-LABEL: sextload_v2i16_v: entry: - %0 = load <2 x i16>* %v, align 8 + %0 = load <2 x i16>, <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> - %1 = load <2 x i16>* %p, align 8 + %1 = load <2 x i16>, <2 x i16>* %p, align 8 %v2 = sext <2 x i16> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 @@ -106,10 +106,10 @@ entry: define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind { ;CHECK-LABEL: sextload_v4i8_vs: entry: - %0 = load <4 x i8>* %v, align 8 + %0 = load <4 x i8>, <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> - %1 = load <4 x i16>* %p, align 8 + %1 = load <4 x i16>, <4 x i16>* %p, align 8 %v2 = sext <4 x i16> %1 to <4 x i32> ;CHECK: vmull %v1 = mul <4 x i32> %v0, %v2 @@ -122,10 +122,10 @@ entry: define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind { ;CHECK-LABEL: sextload_v2i8_vs: entry: - %0 = load <2 x i8>* %v, align 8 + %0 = load <2 x i8>, <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> - %1 = load <2 x i16>* %p, align 8 + %1 = load <2 x i16>, <2 x i16>* %p, align 8 %v2 = sext <2 x i16> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 @@ -138,10 +138,10 @@ entry: define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind { ;CHECK-LABEL: sextload_v2i16_vs: entry: - %0 = load <2 x i16>* %v, align 8 + %0 = load <2 x i16>, <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> - %1 = load <2 x i32>* %p, align 8 + %1 = load <2 x i32>, <2 x i32>* %p, align 8 %v2 = sext <2 x i32> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 diff --git a/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll index ec7f72d7c2e8..545bfc73c590 100644 --- a/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll +++ b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll @@ -21,17 +21,17 @@ define void @findEdges(i8*) nounwind ssp { %6 = phi i8* [ %19, %5 ], [ %0, %1 ] %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1) %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0 - %9 = getelementptr inbounds i8* null, i32 3 + %9 = getelementptr inbounds i8, i8* null, i32 3 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1) %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1) %13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0 %14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1 - %15 = getelementptr inbounds i8* %6, i32 3 + %15 = getelementptr inbounds i8, i8* %6, i32 3 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1) %17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1 %18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2 - %19 = getelementptr inbounds i8* %6, i32 48 + %19 = getelementptr inbounds i8, i8* %6, i32 48 %20 = bitcast <16 x i8> %13 to <2 x i64> %21 = bitcast <16 x i8> %8 to <2 x i64> %22 = bitcast <16 x i8> %14 to <2 x i64> diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index f864c8cbfcb5..4a1341c4d6e7 100644 --- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -10,7 +10,9 @@ declare void @llvm.va_end(i8*) nounwind ; CHECK-LABEL: test_byval_8_bytes_alignment: define void @test_byval_8_bytes_alignment(i32 %i, ...) { entry: -; CHECK: stm r0, {r1, r2, r3} +; CHECK: sub sp, sp, #12 +; CHECK: sub sp, sp, #4 +; CHECK: stmib sp, {r1, r2, r3} %g = alloca i8* %g1 = bitcast i8** %g to i8* call void @llvm.va_start(i8* %g1) @@ -31,7 +33,7 @@ entry: ; CHECK: movw r0, #555 define i32 @main() { entry: - call void (i32, ...)* @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val) + call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val) ret i32 0 } @@ -44,9 +46,9 @@ declare void @f(double); ; CHECK-NOT: str r1 define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind { entry: - %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0 - %0 = load double* %a - call void (double)* @f(double %0) + %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 + %0 = load double, double* %a + call void (double) @f(double %0) ret void } @@ -58,6 +60,6 @@ entry: ; CHECK: movw r0, #555 define i32 @main_fixed_arg() { entry: - call void (i32, %struct_t*)* @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val) + call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val) ret i32 0 } diff --git a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll index c9ccc103e2fa..34af9026b52e 100644 --- a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll +++ b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll @@ -12,8 +12,8 @@ declare i32 @printf(i8*, ...) ; CHECK: vldr d16, [sp, #8] define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind { entry: - %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0 - %0 = load double* %a - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %0) + %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 + %0 = load double, double* %a + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %0) ret void } diff --git a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll index 0028eec80f44..ff3b7e16188e 100644 --- a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll +++ b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll @@ -10,8 +10,9 @@ define void @t(i32 %a, %struct.s* byval %s) nounwind { entry: ; Here we need to only check proper start address of restored %s argument. -; CHECK: sub sp, sp, #16 +; CHECK: sub sp, sp, #12 ; CHECK: push {r11, lr} +; CHECK: sub sp, sp, #4 ; CHECK: add r0, sp, #12 ; CHECK: stm r0, {r1, r2, r3} ; CHECK: add r0, sp, #12 diff --git a/test/CodeGen/ARM/2013-01-21-PR14992.ll b/test/CodeGen/ARM/2013-01-21-PR14992.ll index 014686feee0e..4c1f2a741e47 100644 --- a/test/CodeGen/ARM/2013-01-21-PR14992.ll +++ b/test/CodeGen/ARM/2013-01-21-PR14992.ll @@ -6,12 +6,12 @@ ;CHECK-LABEL: foo: define i32 @foo(i32* %a) nounwind optsize { entry: - %0 = load i32* %a, align 4 - %arrayidx1 = getelementptr inbounds i32* %a, i32 1 - %1 = load i32* %arrayidx1, align 4 - %arrayidx2 = getelementptr inbounds i32* %a, i32 2 - %2 = load i32* %arrayidx2, align 4 - %add.ptr = getelementptr inbounds i32* %a, i32 3 + %0 = load i32, i32* %a, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 1 + %1 = load i32, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 2 + %2 = load i32, i32* %arrayidx2, align 4 + %add.ptr = getelementptr inbounds i32, i32* %a, i32 3 ;Make sure we do not have a duplicated register in the front of the reg list ;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}}, ;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]], diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll index c5eba7d4773c..c38dd16f0d27 100644 --- a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll +++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll @@ -2,26 +2,26 @@ ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s ;CHECK-LABEL: foo: -;CHECK: sub sp, sp, #8 +;CHECK: sub sp, sp, #16 ;CHECK: push {r11, lr} -;CHECK: str r0, [sp, #12] -;CHECK: add r0, sp, #12 +;CHECK: str r0, [sp, #8] +;CHECK: add r0, sp, #8 ;CHECK: bl fooUseParam ;CHECK: pop {r11, lr} -;CHECK: add sp, sp, #8 +;CHECK: add sp, sp, #16 ;CHECK: mov pc, lr ;CHECK-LABEL: foo2: -;CHECK: sub sp, sp, #8 +;CHECK: sub sp, sp, #16 ;CHECK: push {r11, lr} ;CHECK: str r0, [sp, #8] ;CHECK: add r0, sp, #8 -;CHECK: str r2, [sp, #12] +;CHECK: str r2, [sp, #16] ;CHECK: bl fooUseParam -;CHECK: add r0, sp, #12 +;CHECK: add r0, sp, #16 ;CHECK: bl fooUseParam ;CHECK: pop {r11, lr} -;CHECK: add sp, sp, #8 +;CHECK: add sp, sp, #16 ;CHECK: mov pc, lr ;CHECK-LABEL: doFoo: diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll index 446403d79cac..5e82b0925b24 100644 --- a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll +++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll @@ -33,7 +33,7 @@ define void @foo2(double %p0, ; --> D0 %struct_t* byval %p10) ; --> Stack+8 { entry: -;CHECK: push.w {r11, lr} +;CHECK: push {r7, lr} ;CHECK-NOT: stm ;CHECK: add r0, sp, #16 ;CHECK: bl fooUseStruct diff --git a/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll b/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll index 459992818749..6c8b0ff2de19 100644 --- a/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll +++ b/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll @@ -9,9 +9,9 @@ define void @sample_test(<8 x i64> * %secondSource, <8 x i64> * %source, <8 x i6 entry: ; Load %source - %s0 = load <8 x i64> * %source, align 64 - %arrayidx64 = getelementptr inbounds <8 x i64> * %source, i32 6 - %s120 = load <8 x i64> * %arrayidx64, align 64 + %s0 = load <8 x i64> , <8 x i64> * %source, align 64 + %arrayidx64 = getelementptr inbounds <8 x i64>, <8 x i64> * %source, i32 6 + %s120 = load <8 x i64> , <8 x i64> * %arrayidx64, align 64 %s122 = bitcast <8 x i64> %s120 to i512 %data.i.i677.48.extract.shift = lshr i512 %s122, 384 %data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64 @@ -33,9 +33,9 @@ entry: %s130 = insertelement <8 x i64> %s129, i64 %data.i.i677.56.extract.trunc, i32 7 ; Load %secondSource - %s1 = load <8 x i64> * %secondSource, align 64 - %arrayidx67 = getelementptr inbounds <8 x i64> * %secondSource, i32 6 - %s121 = load <8 x i64> * %arrayidx67, align 64 + %s1 = load <8 x i64> , <8 x i64> * %secondSource, align 64 + %arrayidx67 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 6 + %s121 = load <8 x i64> , <8 x i64> * %arrayidx67, align 64 %s131 = bitcast <8 x i64> %s121 to i512 %data.i1.i676.48.extract.shift = lshr i512 %s131, 384 %data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64 @@ -61,10 +61,10 @@ entry: %vecinit35.i.i700 = shufflevector <8 x i64> %vecinit28.i.i699, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 13, i32 undef, i32 undef> %vecinit42.i.i701 = shufflevector <8 x i64> %vecinit35.i.i700, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 undef> %vecinit49.i.i702 = shufflevector <8 x i64> %vecinit42.i.i701, <8 x i64> %s130, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15> - %arrayidx72 = getelementptr inbounds <8 x i64> * %dest, i32 6 + %arrayidx72 = getelementptr inbounds <8 x i64>, <8 x i64> * %dest, i32 6 store <8 x i64> %vecinit49.i.i702, <8 x i64> * %arrayidx72, align 64 - %arrayidx78 = getelementptr inbounds <8 x i64> * %secondSource, i32 7 - %s141 = load <8 x i64> * %arrayidx78, align 64 + %arrayidx78 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 7 + %s141 = load <8 x i64> , <8 x i64> * %arrayidx78, align 64 %s151 = bitcast <8 x i64> %s141 to i512 %data.i1.i649.32.extract.shift = lshr i512 %s151, 256 %data.i1.i649.32.extract.trunc = trunc i512 %data.i1.i649.32.extract.shift to i64 @@ -76,7 +76,7 @@ entry: %data.i1.i649.8.extract.shift = lshr i512 %s151, 64 %data.i1.i649.8.extract.trunc = trunc i512 %data.i1.i649.8.extract.shift to i64 %s155 = insertelement <8 x i64> %s154, i64 %data.i1.i649.8.extract.trunc, i32 3 - %arrayidx83 = getelementptr inbounds <8 x i64> * %dest, i32 7 + %arrayidx83 = getelementptr inbounds <8 x i64>, <8 x i64> * %dest, i32 7 store <8 x i64> %s155, <8 x i64> * %arrayidx83, align 64 ret void } diff --git a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll index 0e0537ec5bfc..d18dbd2db9b4 100644 --- a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll +++ b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll @@ -14,8 +14,8 @@ define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) { entry: %conv = sext i16 %b to i32 %conv1 = sext i8 %E to i32 - %call = tail call i32 (i8*, ...)* @printf( - i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), ; --> R0 + %call = tail call i32 (i8*, ...) @printf( + i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), ; --> R0 i32 %a, ; --> R1 i32 %conv, ; --> R2 double %C, ; --> SP, NCRN := R4 diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll index e79a3ba741ec..c93d2a2d34fb 100644 --- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll @@ -21,11 +21,12 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP i32 %p2, ; --> R3, NSAA=SP+8 i32 %p3) #0 { ; --> SP+4, NSAA=SP+12 entry: - ;CHECK: sub sp, #8 - ;CHECK: push.w {r11, lr} - ;CHECK: add r0, sp, #8 - ;CHECK: str r2, [sp, #12] - ;CHECK: str r1, [sp, #8] + ;CHECK: sub sp, #12 + ;CHECK: push {r7, lr} + ;CHECK: sub sp, #4 + ;CHECK: add r0, sp, #12 + ;CHECK: str r2, [sp, #16] + ;CHECK: str r1, [sp, #12] ;CHECK: bl fooUseStruct call void @fooUseStruct(%st_t* %p1) ret void diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll index 212bbc2ee9c8..944a60c06107 100644 --- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll @@ -19,7 +19,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP i32 %p2) #0 { ; --> SP+24, NSAA=SP+24 entry: - ;CHECK: push.w {r11, lr} + ;CHECK: push {r7, lr} ;CHECK: ldr r0, [sp, #32] ;CHECK: bl fooUseI32 call void @fooUseI32(i32 %p2) diff --git a/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll b/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll index efb82027b70d..aabbfae8b879 100644 --- a/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll +++ b/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll @@ -7,46 +7,46 @@ entry: %add = add nsw i32 %mul17, %w %sub19 = sub i32 %add, %Width %sub20 = add i32 %sub19, -1 - %arrayidx21 = getelementptr inbounds i8* %call1, i32 %sub20 - %0 = load i8* %arrayidx21, align 1 + %arrayidx21 = getelementptr inbounds i8, i8* %call1, i32 %sub20 + %0 = load i8, i8* %arrayidx21, align 1 %conv22 = zext i8 %0 to i32 - %arrayidx25 = getelementptr inbounds i8* %call1, i32 %sub19 - %1 = load i8* %arrayidx25, align 1 + %arrayidx25 = getelementptr inbounds i8, i8* %call1, i32 %sub19 + %1 = load i8, i8* %arrayidx25, align 1 %conv26 = zext i8 %1 to i32 %mul23189 = add i32 %conv26, %conv22 %add30 = add i32 %sub19, 1 - %arrayidx31 = getelementptr inbounds i8* %call1, i32 %add30 - %2 = load i8* %arrayidx31, align 1 + %arrayidx31 = getelementptr inbounds i8, i8* %call1, i32 %add30 + %2 = load i8, i8* %arrayidx31, align 1 %conv32 = zext i8 %2 to i32 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1] %add28190 = add i32 %mul23189, %conv32 %sub35 = add i32 %add, -1 - %arrayidx36 = getelementptr inbounds i8* %call1, i32 %sub35 - %3 = load i8* %arrayidx36, align 1 + %arrayidx36 = getelementptr inbounds i8, i8* %call1, i32 %sub35 + %3 = load i8, i8* %arrayidx36, align 1 %conv37 = zext i8 %3 to i32 %add34191 = add i32 %add28190, %conv37 - %arrayidx40 = getelementptr inbounds i8* %call1, i32 %add - %4 = load i8* %arrayidx40, align 1 + %arrayidx40 = getelementptr inbounds i8, i8* %call1, i32 %add + %4 = load i8, i8* %arrayidx40, align 1 %conv41 = zext i8 %4 to i32 %mul42 = mul nsw i32 %conv41, 255 %add44 = add i32 %add, 1 - %arrayidx45 = getelementptr inbounds i8* %call1, i32 %add44 - %5 = load i8* %arrayidx45, align 1 + %arrayidx45 = getelementptr inbounds i8, i8* %call1, i32 %add44 + %5 = load i8, i8* %arrayidx45, align 1 %conv46 = zext i8 %5 to i32 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1] %add49 = add i32 %add, %Width %sub50 = add i32 %add49, -1 - %arrayidx51 = getelementptr inbounds i8* %call1, i32 %sub50 - %6 = load i8* %arrayidx51, align 1 + %arrayidx51 = getelementptr inbounds i8, i8* %call1, i32 %sub50 + %6 = load i8, i8* %arrayidx51, align 1 %conv52 = zext i8 %6 to i32 - %arrayidx56 = getelementptr inbounds i8* %call1, i32 %add49 - %7 = load i8* %arrayidx56, align 1 + %arrayidx56 = getelementptr inbounds i8, i8* %call1, i32 %add49 + %7 = load i8, i8* %arrayidx56, align 1 %conv57 = zext i8 %7 to i32 %add61 = add i32 %add49, 1 - %arrayidx62 = getelementptr inbounds i8* %call1, i32 %add61 - %8 = load i8* %arrayidx62, align 1 + %arrayidx62 = getelementptr inbounds i8, i8* %call1, i32 %add61 + %8 = load i8, i8* %arrayidx62, align 1 %conv63 = zext i8 %8 to i32 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] ; CHECK-NEXT: ldrb{{[.w]*}} r{{[0-9]*}}, [r{{[0-9]*}}, #1] @@ -58,7 +58,7 @@ entry: %add65 = add i32 %tmp196, %mul42 %9 = lshr i32 %add65, 8 %conv68 = trunc i32 %9 to i8 - %arrayidx69 = getelementptr inbounds i8* %call3, i32 %add + %arrayidx69 = getelementptr inbounds i8, i8* %call3, i32 %add store i8 %conv68, i8* %arrayidx69, align 1 ret i8 %conv68 } diff --git a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll index 7bf03a16c6fb..3c20c6b53633 100644 --- a/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll +++ b/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll @@ -4,7 +4,7 @@ %struct.S227 = type { [49 x i32], i32 } define void @check227( - i32 %b, + i32 %b, %struct.S227* byval nocapture %arg0, %struct.S227* %arg1) { ; b --> R0 @@ -13,14 +13,16 @@ define void @check227( entry: -;CHECK: sub sp, sp, #16 +;CHECK: sub sp, sp, #12 ;CHECK: push {r11, lr} +;CHECK: sub sp, sp, #4 ;CHECK: add r0, sp, #12 ;CHECK: stm r0, {r1, r2, r3} ;CHECK: ldr r0, [sp, #212] ;CHECK: bl useInt +;CHECK: add sp, sp, #4 ;CHECK: pop {r11, lr} -;CHECK: add sp, sp, #16 +;CHECK: add sp, sp, #12 %0 = ptrtoint %struct.S227* %arg1 to i32 tail call void @useInt(i32 %0) diff --git a/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll b/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll index 0130f7ab68f5..617271264b4f 100644 --- a/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll +++ b/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll @@ -10,7 +10,7 @@ define arm_aapcscc void @f2(i8 signext %a) #0 { entry: %a.addr = alloca i8, align 1 store i8 %a, i8* %a.addr, align 1 - %0 = load i8* %a.addr, align 1 + %0 = load i8, i8* %a.addr, align 1 %conv = sext i8 %0 to i32 %shr = ashr i32 %conv, 56 %conv1 = trunc i32 %shr to i8 diff --git a/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll b/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll index 05a4ef05e958..979df3072fbf 100644 --- a/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll +++ b/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll @@ -17,7 +17,7 @@ entry: ; CHECK: vorr q9, q9, q10 ; CHECK: vst1.32 {d18, d19}, [r0] vector.body: - %wide.load = load <4 x i32>* undef, align 4 + %wide.load = load <4 x i32>, <4 x i32>* undef, align 4 %0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936> %1 = sub <4 x i32> %wide.load, zeroinitializer %2 = and <4 x i32> %1, <i32 16711680, i32 16711680, i32 16711680, i32 16711680> diff --git a/test/CodeGen/ARM/2013-10-11-select-stalls.ll b/test/CodeGen/ARM/2013-10-11-select-stalls.ll index 33c0587226a8..d6045c7b8c8c 100644 --- a/test/CodeGen/ARM/2013-10-11-select-stalls.ll +++ b/test/CodeGen/ARM/2013-10-11-select-stalls.ll @@ -7,7 +7,7 @@ define <16 x i8> @multiselect(i32 %avail, i8* %foo, i8* %bar) { entry: %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %foo, i32 1) %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1) - %and = and i32 %avail, 1 + %and = and i32 %avail, 3 %tobool = icmp eq i32 %and, 0 %retv = select i1 %tobool, <16 x i8> %vld1, <16 x i8> %vld2 ret <16 x i8> %retv diff --git a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll index 6c0fbd00bd1a..ef575f4c41ec 100644 --- a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -4,7 +4,7 @@ define void @vst(i8* %m, [4 x i64] %v) { entry: ; CHECK: vst: -; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use> +; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill> %v0 = extractvalue [4 x i64] %v, 0 %v1 = extractvalue [4 x i64] %v, 1 @@ -38,13 +38,13 @@ entry: define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { ; CHECK: vtbx4: ; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use> - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x4_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3 - %tmp7 = load <8 x i8>* %C + %tmp7 = load <8 x i8>, <8 x i8>* %C %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7) call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8) ret <8 x i8> %tmp8 diff --git a/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll b/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll index 33bfa2fa61cd..5b2fc57359ad 100644 --- a/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll +++ b/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll @@ -13,15 +13,16 @@ declare void @usePtr(%struct8bytes8align*) ; c -> sp+0..sp+7 define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) { ; CHECK-LABEL: foo1 -; CHECK: sub sp, sp, #16 +; CHECK: sub sp, sp, #12 ; CHECK: push {r11, lr} +; CHECK: sub sp, sp, #4 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #12 ; CHECK: stm [[SCRATCH]], {r1, r2, r3} ; CHECK: ldr r0, [sp, #24] ; CHECK: ldr r1, [sp, #28] ; CHECK: bl useLong ; CHECK: pop {r11, lr} -; CHECK: add sp, sp, #16 +; CHECK: add sp, sp, #12 call void @useLong(i64 %c) ret void diff --git a/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll b/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll index df7d2457e763..1abc40f2c16e 100644 --- a/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll +++ b/test/CodeGen/ARM/2014-07-18-earlyclobber-str-post.ll @@ -8,7 +8,7 @@ define i32* @earlyclobber-str-post(i32* %addr) nounwind { ; CHECK-NOT: str r[[REG:[0-9]+]], [r[[REG]]], #4 %val = ptrtoint i32* %addr to i32 store i32 %val, i32* %addr - %new = getelementptr i32* %addr, i32 1 + %new = getelementptr i32, i32* %addr, i32 1 ret i32* %new } @@ -18,7 +18,7 @@ define i16* @earlyclobber-strh-post(i16* %addr) nounwind { %val = ptrtoint i16* %addr to i32 %tr = trunc i32 %val to i16 store i16 %tr, i16* %addr - %new = getelementptr i16* %addr, i32 1 + %new = getelementptr i16, i16* %addr, i32 1 ret i16* %new } @@ -28,6 +28,6 @@ define i8* @earlyclobber-strb-post(i8* %addr) nounwind { %val = ptrtoint i8* %addr to i32 %tr = trunc i32 %val to i8 store i8 %tr, i8* %addr - %new = getelementptr i8* %addr, i32 1 + %new = getelementptr i8, i8* %addr, i32 1 ret i8* %new } diff --git a/test/CodeGen/ARM/2014-08-04-muls-it.ll b/test/CodeGen/ARM/2014-08-04-muls-it.ll index 4636bff880a8..5ba1347433db 100644 --- a/test/CodeGen/ARM/2014-08-04-muls-it.ll +++ b/test/CodeGen/ARM/2014-08-04-muls-it.ll @@ -17,9 +17,7 @@ if.end: ; preds = %if.then, %entry ; CHECK-LABEL: function ; CHECK: cmp r0, r1 -; CHECK: bne [[LABEL:[.*]]] ; CHECK-NOT: mulseq r0, r0, r0 -; CHECK: [[LABEL]] -; CHECK: muls r0, r0, r0 +; CHECK: muleq r0, r0, r0 ; CHECK: bx lr diff --git a/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll b/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll index f3cc3d82121f..2efd91f503e5 100644 --- a/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll +++ b/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll @@ -1,55 +1,48 @@ ; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V4T ; RUN: llc -mtriple=thumbv6m-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V6M -; CHECK-LABEL: foo -define i32 @foo(i32 %z, ...) #0 { -entry: - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - %d = alloca i32, align 4 - %e = alloca i32, align 4 - %f = alloca i32, align 4 - %g = alloca i32, align 4 - %h = alloca i32, align 4 +; CHECK-LABEL: test1 +define i32 @test1(i32* %p) { - store i32 1, i32* %a, align 4 - store i32 2, i32* %b, align 4 - store i32 3, i32* %c, align 4 - store i32 4, i32* %d, align 4 - store i32 5, i32* %e, align 4 - store i32 6, i32* %f, align 4 - store i32 7, i32* %g, align 4 - store i32 8, i32* %h, align 4 +; Offsets less than 8 can be generated in a single add +; CHECK: adds [[NEWBASE:r[0-9]]], r0, #4 + %1 = getelementptr inbounds i32, i32* %p, i32 1 + %2 = getelementptr inbounds i32, i32* %p, i32 2 + %3 = getelementptr inbounds i32, i32* %p, i32 3 + %4 = getelementptr inbounds i32, i32* %p, i32 4 - %0 = load i32* %a, align 4 - %1 = load i32* %b, align 4 - %2 = load i32* %c, align 4 - %3 = load i32* %d, align 4 - %4 = load i32* %e, align 4 - %5 = load i32* %f, align 4 - %6 = load i32* %g, align 4 - %7 = load i32* %h, align 4 - - %add = add nsw i32 %0, %1 - %add4 = add nsw i32 %add, %2 - %add5 = add nsw i32 %add4, %3 - %add6 = add nsw i32 %add5, %4 - %add7 = add nsw i32 %add6, %5 - %add8 = add nsw i32 %add7, %6 - %add9 = add nsw i32 %add8, %7 +; CHECK-NEXT: ldm [[NEWBASE]], + %5 = load i32, i32* %1, align 4 + %6 = load i32, i32* %2, align 4 + %7 = load i32, i32* %3, align 4 + %8 = load i32, i32* %4, align 4 - %addz = add nsw i32 %add9, %z - call void @llvm.va_start(i8* null) - ret i32 %addz + %9 = add nsw i32 %5, %6 + %10 = add nsw i32 %9, %7 + %11 = add nsw i32 %10, %8 + ret i32 %11 +} -; CHECK: sub sp, #40 -; CHECK-NEXT: add [[BASE:r[0-9]]], sp, #8 +; CHECK-LABEL: test2 +define i32 @test2(i32* %p) { -; CHECK-V4T: movs [[NEWBASE:r[0-9]]], [[BASE]] -; CHECK-V6M: mov [[NEWBASE:r[0-9]]], [[BASE]] +; Offsets >=8 require a mov and an add +; CHECK-V4T: movs [[NEWBASE:r[0-9]]], r0 +; CHECK-V6M: mov [[NEWBASE:r[0-9]]], r0 ; CHECK-NEXT: adds [[NEWBASE]], #8 + %1 = getelementptr inbounds i32, i32* %p, i32 2 + %2 = getelementptr inbounds i32, i32* %p, i32 3 + %3 = getelementptr inbounds i32, i32* %p, i32 4 + %4 = getelementptr inbounds i32, i32* %p, i32 5 + ; CHECK-NEXT: ldm [[NEWBASE]], -} + %5 = load i32, i32* %1, align 4 + %6 = load i32, i32* %2, align 4 + %7 = load i32, i32* %3, align 4 + %8 = load i32, i32* %4, align 4 -declare void @llvm.va_start(i8*) nounwind + %9 = add nsw i32 %5, %6 + %10 = add nsw i32 %9, %7 + %11 = add nsw i32 %10, %8 + ret i32 %11 +} diff --git a/test/CodeGen/ARM/MergeConsecutiveStores.ll b/test/CodeGen/ARM/MergeConsecutiveStores.ll index 06c87e986a83..3f7d625244bd 100644 --- a/test/CodeGen/ARM/MergeConsecutiveStores.ll +++ b/test/CodeGen/ARM/MergeConsecutiveStores.ll @@ -12,17 +12,17 @@ define void @MergeLoadStoreBaseIndexOffset(i32* %a, i8* %b, i8* %c, i32 %n) { %.09 = phi i32 [ %n, %0 ], [ %11, %1 ] %.08 = phi i8* [ %b, %0 ], [ %10, %1 ] %.0 = phi i32* [ %a, %0 ], [ %2, %1 ] - %2 = getelementptr inbounds i32* %.0, i32 1 - %3 = load i32* %.0, align 1 - %4 = getelementptr inbounds i8* %c, i32 %3 - %5 = load i8* %4, align 1 + %2 = getelementptr inbounds i32, i32* %.0, i32 1 + %3 = load i32, i32* %.0, align 1 + %4 = getelementptr inbounds i8, i8* %c, i32 %3 + %5 = load i8, i8* %4, align 1 %6 = add i32 %3, 1 - %7 = getelementptr inbounds i8* %c, i32 %6 - %8 = load i8* %7, align 1 + %7 = getelementptr inbounds i8, i8* %c, i32 %6 + %8 = load i8, i8* %7, align 1 store i8 %5, i8* %.08, align 1 - %9 = getelementptr inbounds i8* %.08, i32 1 + %9 = getelementptr inbounds i8, i8* %.08, i32 1 store i8 %8, i8* %9, align 1 - %10 = getelementptr inbounds i8* %.08, i32 2 + %10 = getelementptr inbounds i8, i8* %.08, i32 2 %11 = add nsw i32 %.09, -1 %12 = icmp eq i32 %11, 0 br i1 %12, label %13, label %1 @@ -44,18 +44,18 @@ define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) { %.09 = phi i32 [ %n, %0 ], [ %12, %1 ] %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] - %2 = getelementptr inbounds i8* %.0, i32 1 - %3 = load i8* %.0, align 1 + %2 = getelementptr inbounds i8, i8* %.0, i32 1 + %3 = load i8, i8* %.0, align 1 %4 = sext i8 %3 to i32 - %5 = getelementptr inbounds i8* %c, i32 %4 - %6 = load i8* %5, align 1 + %5 = getelementptr inbounds i8, i8* %c, i32 %4 + %6 = load i8, i8* %5, align 1 %7 = add i32 %4, 1 - %8 = getelementptr inbounds i8* %c, i32 %7 - %9 = load i8* %8, align 1 + %8 = getelementptr inbounds i8, i8* %c, i32 %7 + %9 = load i8, i8* %8, align 1 store i8 %6, i8* %.08, align 1 - %10 = getelementptr inbounds i8* %.08, i32 1 + %10 = getelementptr inbounds i8, i8* %.08, i32 1 store i8 %9, i8* %10, align 1 - %11 = getelementptr inbounds i8* %.08, i32 2 + %11 = getelementptr inbounds i8, i8* %.08, i32 2 %12 = add nsw i32 %.09, -1 %13 = icmp eq i32 %12, 0 br i1 %13, label %14, label %1 @@ -76,19 +76,19 @@ define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) { %.09 = phi i32 [ %n, %0 ], [ %12, %1 ] %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] - %2 = getelementptr inbounds i8* %.0, i32 1 - %3 = load i8* %.0, align 1 + %2 = getelementptr inbounds i8, i8* %.0, i32 1 + %3 = load i8, i8* %.0, align 1 %4 = sext i8 %3 to i32 - %5 = getelementptr inbounds i8* %c, i32 %4 - %6 = load i8* %5, align 1 + %5 = getelementptr inbounds i8, i8* %c, i32 %4 + %6 = load i8, i8* %5, align 1 %7 = add i8 %3, 1 %wrap.4 = sext i8 %7 to i32 - %8 = getelementptr inbounds i8* %c, i32 %wrap.4 - %9 = load i8* %8, align 1 + %8 = getelementptr inbounds i8, i8* %c, i32 %wrap.4 + %9 = load i8, i8* %8, align 1 store i8 %6, i8* %.08, align 1 - %10 = getelementptr inbounds i8* %.08, i32 1 + %10 = getelementptr inbounds i8, i8* %.08, i32 1 store i8 %9, i8* %10, align 1 - %11 = getelementptr inbounds i8* %.08, i32 2 + %11 = getelementptr inbounds i8, i8* %.08, i32 2 %12 = add nsw i32 %.09, -1 %13 = icmp eq i32 %12, 0 br i1 %13, label %14, label %1 diff --git a/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll b/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll index a82f6141dbb3..a314259e499e 100644 --- a/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll +++ b/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll @@ -10,10 +10,10 @@ entry: %i.addr = alloca i32, align 4 %buffer = alloca [4096 x i8], align 1 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 %rem = urem i32 %0, 4096 - %arrayidx = getelementptr inbounds [4096 x i8]* %buffer, i32 0, i32 %rem - %1 = load volatile i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem + %1 = load volatile i8, i8* %arrayidx, align 1 ret i8 %1 } diff --git a/test/CodeGen/ARM/Windows/dllimport.ll b/test/CodeGen/ARM/Windows/dllimport.ll index bc737bd41827..6786be3322e3 100644 --- a/test/CodeGen/ARM/Windows/dllimport.ll +++ b/test/CodeGen/ARM/Windows/dllimport.ll @@ -8,7 +8,7 @@ declare dllimport arm_aapcs_vfpcc i32 @external() declare arm_aapcs_vfpcc i32 @internal() define arm_aapcs_vfpcc i32 @get_var() { - %1 = load i32* @var, align 4 + %1 = load i32, i32* @var, align 4 ret i32 %1 } @@ -20,7 +20,7 @@ define arm_aapcs_vfpcc i32 @get_var() { ; CHECK: bx lr define arm_aapcs_vfpcc i32 @get_ext() { - %1 = load i32* @ext, align 4 + %1 = load i32, i32* @ext, align 4 ret i32 %1 } diff --git a/test/CodeGen/ARM/Windows/frame-register.ll b/test/CodeGen/ARM/Windows/frame-register.ll index 31167d7352e3..7ecfc1a71714 100644 --- a/test/CodeGen/ARM/Windows/frame-register.ll +++ b/test/CodeGen/ARM/Windows/frame-register.ll @@ -8,12 +8,12 @@ entry: %i.addr = alloca i32, align 4 %j = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 %add = add nsw i32 %0, 1 store i32 %add, i32* %j, align 4 - %1 = load i32* %j, align 4 + %1 = load i32, i32* %j, align 4 call void @callee(i32 %1) - %2 = load i32* %j, align 4 + %2 = load i32, i32* %j, align 4 %add1 = add nsw i32 %2, 1 ret i32 %add1 } diff --git a/test/CodeGen/ARM/Windows/long-calls.ll b/test/CodeGen/ARM/Windows/long-calls.ll index e35f414579af..21c95fac91c5 100644 --- a/test/CodeGen/ARM/Windows/long-calls.ll +++ b/test/CodeGen/ARM/Windows/long-calls.ll @@ -10,7 +10,7 @@ entry: } ; CHECK-LABEL: caller -; CHECK: ldr [[REG:r[0-9]+]], [[CPI:.LCPI[_0-9]+]] +; CHECK: ldr [[REG:r[0-9]+]], [[CPI:LCPI[_0-9]+]] ; CHECK: bx [[REG]] ; CHECK: .align 2 ; CHECK: [[CPI]]: diff --git a/test/CodeGen/ARM/Windows/movw-movt-relocations.ll b/test/CodeGen/ARM/Windows/movw-movt-relocations.ll index 3ae6428d3a6b..c21aee087cf4 100644 --- a/test/CodeGen/ARM/Windows/movw-movt-relocations.ll +++ b/test/CodeGen/ARM/Windows/movw-movt-relocations.ll @@ -10,8 +10,8 @@ ; Function Attrs: nounwind optsize readonly define i32 @relocation(i32 %j, i32 %k) { entry: - %0 = load i32* @i, align 4 - %1 = load i32* @j, align 4 + %0 = load i32, i32* @i, align 4 + %1 = load i32, i32* @j, align 4 %add = add nsw i32 %1, %0 ret i32 %add } diff --git a/test/CodeGen/ARM/Windows/pic.ll b/test/CodeGen/ARM/Windows/pic.ll index 28d371f45217..9ef7c35c5530 100644 --- a/test/CodeGen/ARM/Windows/pic.ll +++ b/test/CodeGen/ARM/Windows/pic.ll @@ -5,7 +5,7 @@ define arm_aapcs_vfpcc i8 @return_external() { entry: - %0 = load i8* @external, align 1 + %0 = load i8, i8* @external, align 1 ret i8 %0 } diff --git a/test/CodeGen/ARM/Windows/read-only-data.ll b/test/CodeGen/ARM/Windows/read-only-data.ll index 0438d68b55c6..c387d1d5137c 100644 --- a/test/CodeGen/ARM/Windows/read-only-data.ll +++ b/test/CodeGen/ARM/Windows/read-only-data.ll @@ -6,7 +6,7 @@ declare arm_aapcs_vfpcc void @callee(i8*) define arm_aapcs_vfpcc void @function() { entry: - call arm_aapcs_vfpcc void @callee(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0)) + call arm_aapcs_vfpcc void @callee(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0)) ret void } diff --git a/test/CodeGen/ARM/Windows/stack-probe-non-default.ll b/test/CodeGen/ARM/Windows/stack-probe-non-default.ll new file mode 100644 index 000000000000..d66e93ad34ee --- /dev/null +++ b/test/CodeGen/ARM/Windows/stack-probe-non-default.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple thumbv7-windows -mcpu cortex-a9 -o - %s \ +; RUN: | FileCheck %s -check-prefix CHECK-DEFAULT-CODE-MODEL + +; RUN: llc -mtriple thumbv7-windows -mcpu cortex-a9 -code-model large -o - %s \ +; RUN: | FileCheck %s -check-prefix CHECK-LARGE-CODE-MODEL + +declare dllimport arm_aapcs_vfpcc void @initialise(i8*) + +define dllexport arm_aapcs_vfpcc signext i8 @function(i32 %offset) #0 { +entry: + %buffer = alloca [4096 x i8], align 1 + %0 = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 0 + call arm_aapcs_vfpcc void @initialise(i8* %0) + %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %offset + %1 = load i8, i8* %arrayidx, align 1 + ret i8 %1 +} + +attributes #0 = { "stack-probe-size"="8096" } + +; CHECK-DEFAULT-CODE-MODEL-NOT: __chkstk +; CHECK-DEFAULT-CODE-MODEL: sub.w sp, sp, #4096 + +; CHECK-LARGE-CODE-MODEL-NOT: movw r12, :lower16:__chkstk +; CHECK-LARGE-CODE-MODEL-NOT: movt r12, :upper16:__chkstk +; CHECK-LARGE-CODE-MODEL: sub.w sp, sp, #4096 + diff --git a/test/CodeGen/ARM/Windows/vla.ll b/test/CodeGen/ARM/Windows/vla.ll index 56901dee0dfa..1c0632e25e55 100644 --- a/test/CodeGen/ARM/Windows/vla.ll +++ b/test/CodeGen/ARM/Windows/vla.ll @@ -8,8 +8,8 @@ define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) { entry: %vla = alloca i8, i32 %sz, align 1 - %arrayidx = getelementptr inbounds i8* %vla, i32 %idx - %0 = load volatile i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %vla, i32 %idx + %0 = load volatile i8, i8* %arrayidx, align 1 ret i8 %0 } diff --git a/test/CodeGen/ARM/a15-partial-update.ll b/test/CodeGen/ARM/a15-partial-update.ll index 5747253d56b7..576eb7a24393 100644 --- a/test/CodeGen/ARM/a15-partial-update.ll +++ b/test/CodeGen/ARM/a15-partial-update.ll @@ -10,7 +10,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) { ; generated. ; CHECK-NOT: vmov.{{.*}} d{{[0-9]+}}, - %tmp2 = load float* %A, align 4 + %tmp2 = load float, float* %A, align 4 %tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1 ret <2 x float> %tmp3 } @@ -27,9 +27,9 @@ loop: ; CHECK: vmov.{{.*}} d{{[0-9]+}}, %oldcount = phi i32 [0, %entry], [%newcount, %loop] %newcount = add i32 %oldcount, 1 - %p1 = getelementptr <4 x i8> *%in, i32 %newcount - %p2 = getelementptr <4 x i8> *%out, i32 %newcount - %tmp1 = load <4 x i8> *%p1, align 4 + %p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount + %p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount + %tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4 store <4 x i8> %tmp1, <4 x i8> *%p2 %cmp = icmp eq i32 %newcount, %n br i1 %cmp, label %loop, label %ret diff --git a/test/CodeGen/ARM/addrmode.ll b/test/CodeGen/ARM/addrmode.ll index 8fd1da791f1f..52bb9a20662e 100644 --- a/test/CodeGen/ARM/addrmode.ll +++ b/test/CodeGen/ARM/addrmode.ll @@ -4,14 +4,14 @@ define i32 @t1(i32 %a) { %b = mul i32 %a, 9 %c = inttoptr i32 %b to i32* - %d = load i32* %c + %d = load i32, i32* %c ret i32 %d } define i32 @t2(i32 %a) { %b = mul i32 %a, -7 %c = inttoptr i32 %b to i32* - %d = load i32* %c + %d = load i32, i32* %c ret i32 %d } diff --git a/test/CodeGen/ARM/aggregate-padding.ll b/test/CodeGen/ARM/aggregate-padding.ll new file mode 100644 index 000000000000..bc46a9cdf913 --- /dev/null +++ b/test/CodeGen/ARM/aggregate-padding.ll @@ -0,0 +1,101 @@ +; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s + +; [2 x i64] should be contiguous when split (e.g. we shouldn't try to align all +; i32 components to 64 bits). Also makes sure i64 based types are properly +; aligned on the stack. +define i64 @test_i64_contiguous_on_stack([8 x double], float, i32 %in, [2 x i64] %arg) nounwind { +; CHECK-LABEL: test_i64_contiguous_on_stack: +; CHECK-DAG: ldr [[LO0:r[0-9]+]], [sp, #8] +; CHECK-DAG: ldr [[HI0:r[0-9]+]], [sp, #12] +; CHECK-DAG: ldr [[LO1:r[0-9]+]], [sp, #16] +; CHECK-DAG: ldr [[HI1:r[0-9]+]], [sp, #20] +; CHECK: adds r0, [[LO0]], [[LO1]] +; CHECK: adc r1, [[HI0]], [[HI1]] + + %val1 = extractvalue [2 x i64] %arg, 0 + %val2 = extractvalue [2 x i64] %arg, 1 + %sum = add i64 %val1, %val2 + ret i64 %sum +} + +; [2 x i64] should try to use looks for 4 regs, not 8 (which might happen if the +; i64 -> i32, i32 split wasn't handled correctly). +define i64 @test_2xi64_uses_4_regs([8 x double], float, [2 x i64] %arg) nounwind { +; CHECK-LABEL: test_2xi64_uses_4_regs: +; CHECK-DAG: mov r0, r2 +; CHECK-DAG: mov r1, r3 + + %val = extractvalue [2 x i64] %arg, 1 + ret i64 %val +} + +; An aggregate should be able to split between registers and stack if there is +; nothing else on the stack. +define i32 @test_aggregates_split([8 x double], i32, [4 x i32] %arg) nounwind { +; CHECK-LABEL: test_aggregates_split: +; CHECK: ldr [[VAL3:r[0-9]+]], [sp] +; CHECK: add r0, r1, [[VAL3]] + + %val0 = extractvalue [4 x i32] %arg, 0 + %val3 = extractvalue [4 x i32] %arg, 3 + %sum = add i32 %val0, %val3 + ret i32 %sum +} + +; If an aggregate has to be moved entirely onto the stack, nothing should be +; able to use r0-r3 any more. Also checks that [2 x i64] properly aligned when +; it uses regs. +define i32 @test_no_int_backfilling([8 x double], float, i32, [2 x i64], i32 %arg) nounwind { +; CHECK-LABEL: test_no_int_backfilling: +; CHECK: ldr r0, [sp, #24] + ret i32 %arg +} + +; Even if the argument was successfully allocated as reg block, there should be +; no backfillig to r1. +define i32 @test_no_int_backfilling_regsonly(i32, [1 x i64], i32 %arg) { +; CHECK-LABEL: test_no_int_backfilling_regsonly: +; CHECK: ldr r0, [sp] + ret i32 %arg +} + +; If an aggregate has to be moved entirely onto the stack, nothing should be +; able to use r0-r3 any more. +define float @test_no_float_backfilling([7 x double], [4 x i32], i32, [4 x double], float %arg) nounwind { +; CHECK-LABEL: test_no_float_backfilling: +; CHECK: vldr s0, [sp, #40] + ret float %arg +} + +; They're a bit pointless, but types like [N x i8] should work as well. +define i8 @test_i8_in_regs(i32, [3 x i8] %arg) { +; CHECK-LABEL: test_i8_in_regs: +; CHECK: add r0, r1, r3 + %val0 = extractvalue [3 x i8] %arg, 0 + %val2 = extractvalue [3 x i8] %arg, 2 + %sum = add i8 %val0, %val2 + ret i8 %sum +} + +define i16 @test_i16_split(i32, i32, [3 x i16] %arg) { +; CHECK-LABEL: test_i16_split: +; CHECK: ldrh [[VAL2:r[0-9]+]], [sp] +; CHECK: add r0, r2, [[VAL2]] + %val0 = extractvalue [3 x i16] %arg, 0 + %val2 = extractvalue [3 x i16] %arg, 2 + %sum = add i16 %val0, %val2 + ret i16 %sum +} + +; Beware: on the stack each i16 still gets a 32-bit slot, the array is not +; packed. +define i16 @test_i16_forced_stack([8 x double], double, i32, i32, [3 x i16] %arg) { +; CHECK-LABEL: test_i16_forced_stack: +; CHECK-DAG: ldrh [[VAL0:r[0-9]+]], [sp, #8] +; CHECK-DAG: ldrh [[VAL2:r[0-9]+]], [sp, #16] +; CHECK: add r0, [[VAL0]], [[VAL2]] + %val0 = extractvalue [3 x i16] %arg, 0 + %val2 = extractvalue [3 x i16] %arg, 2 + %sum = add i16 %val0, %val2 + ret i16 %sum +} diff --git a/test/CodeGen/ARM/aliases.ll b/test/CodeGen/ARM/aliases.ll index 5a737ad995ac..04ca3e875487 100644 --- a/test/CodeGen/ARM/aliases.ll +++ b/test/CodeGen/ARM/aliases.ll @@ -33,12 +33,12 @@ define i32 @foo_f() { define i32 @test() { entry: - %tmp = load i32* @foo1 - %tmp1 = load i32* @foo2 - %tmp0 = load i32* @bar_i + %tmp = load i32, i32* @foo1 + %tmp1 = load i32, i32* @foo2 + %tmp0 = load i32, i32* @bar_i %tmp2 = call i32 @foo_f() %tmp3 = add i32 %tmp, %tmp2 - %tmp4 = call %FunTy* @bar_f() + %tmp4 = call i32 @bar_f() %tmp5 = add i32 %tmp3, %tmp4 %tmp6 = add i32 %tmp1, %tmp5 %tmp7 = add i32 %tmp6, %tmp0 diff --git a/test/CodeGen/ARM/alloc-no-stack-realign.ll b/test/CodeGen/ARM/alloc-no-stack-realign.ll index 24c28baff881..600fb6aa44b1 100644 --- a/test/CodeGen/ARM/alloc-no-stack-realign.ll +++ b/test/CodeGen/ARM/alloc-no-stack-realign.ll @@ -9,8 +9,8 @@ define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" { entry: ; NO-REALIGN-LABEL: test1 -; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128] -; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16 +; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]] +; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]! ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] @@ -21,21 +21,19 @@ entry: ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] -; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16 -; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]! ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] -; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16 -; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 - %0 = load <16 x float>* @T3_retval, align 16 + %0 = load <16 x float>, <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval - %1 = load <16 x float>* %retval + %1 = load <16 x float>, <16 x float>* %retval store <16 x float> %1, <16 x float>* %agg.result, align 16 ret void } @@ -44,8 +42,8 @@ define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp { entry: ; REALIGN-LABEL: test2 ; REALIGN: bfc sp, #0, #6 -; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128] -; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16 +; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]] +; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]! ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] @@ -65,13 +63,12 @@ entry: ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] ; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] -; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16 -; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] +; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 - %0 = load <16 x float>* @T3_retval, align 16 + %0 = load <16 x float>, <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval - %1 = load <16 x float>* %retval + %1 = load <16 x float>, <16 x float>* %retval store <16 x float> %1, <16 x float>* %agg.result, align 16 ret void } diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll index e7fbf9f28eff..3b1d8dd09153 100644 --- a/test/CodeGen/ARM/arguments.ll +++ b/test/CodeGen/ARM/arguments.ll @@ -18,7 +18,7 @@ define i32 @f2() nounwind optsize { ; DARWIN-LABEL: f2: ; DARWIN: mov r3, #128 entry: - %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1] + %0 = tail call i32 (i32, ...) @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1] %not. = icmp ne i32 %0, 128 ; <i1> [#uses=1] %.0 = zext i1 %not. to i32 ; <i32> [#uses=1] ret i32 %.0 diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll index 14eef832e693..04eae8f9afec 100644 --- a/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -8,12 +8,12 @@ %struct.Foo = type { i8* } -; ARM: foo -; THUMB: foo -; T2: foo +; ARM-LABEL: foo: +; THUMB-LABEL: foo: +; T2-LABEL: foo: define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 { entry: - %scevgep = getelementptr %struct.Foo* %this, i32 1 + %scevgep = getelementptr %struct.Foo, %struct.Foo* %this, i32 1 br label %tailrecurse tailrecurse: ; preds = %sw.bb, %entry @@ -21,8 +21,8 @@ tailrecurse: ; preds = %sw.bb, %entry %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ] %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ] %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8** - %scevgep5 = getelementptr i8** %lsr.iv24, i32 -1 - %tmp2 = load i8** %scevgep5 + %scevgep5 = getelementptr i8*, i8** %lsr.iv24, i32 -1 + %tmp2 = load i8*, i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 ; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 @@ -49,20 +49,20 @@ tailrecurse.switch: ; preds = %tailrecurse ; V8-NEXT: beq ; V8-NEXT: %tailrecurse.switch ; V8: cmp -; V8-NEXT: beq +; V8-NEXT: bne ; V8-NEXT: b ; The trailing space in the last line checks that the branch is unconditional switch i32 %and, label %sw.epilog [ i32 1, label %sw.bb i32 3, label %sw.bb6 i32 2, label %sw.bb8 - ] + ], !prof !1 sw.bb: ; preds = %tailrecurse.switch, %tailrecurse %shl = shl i32 %acc.tr, 1 %or = or i32 %and, %shl %lsr.iv.next = add i32 %lsr.iv, 1 - %scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1 + %scevgep3 = getelementptr %struct.Foo, %struct.Foo* %lsr.iv2, i32 1 br label %tailrecurse sw.bb6: ; preds = %tailrecurse.switch @@ -70,7 +70,7 @@ sw.bb6: ; preds = %tailrecurse.switch sw.bb8: ; preds = %tailrecurse.switch %tmp1 = add i32 %acc.tr, %lsr.iv - %add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1 + %add.ptr11 = getelementptr inbounds %struct.Foo, %struct.Foo* %this, i32 %tmp1 ret %struct.Foo* %add.ptr11 sw.epilog: ; preds = %tailrecurse.switch @@ -83,14 +83,14 @@ sw.epilog: ; preds = %tailrecurse.switch %struct.S = type { i8* (i8*)*, [1 x i8] } -; ARM: bar -; THUMB: bar -; T2: bar +; ARM-LABEL: bar: +; THUMB-LABEL: bar: +; T2-LABEL: bar: ; V8-LABEL: bar: define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { entry: - %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0 - %1 = load i8* %0, align 1 + %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0 + %1 = load i8, i8* %0, align 1 %2 = zext i8 %1 to i32 ; ARM: ands ; THUMB: ands @@ -103,8 +103,8 @@ entry: bb: ; preds = %entry ; V8-NEXT: %bb - %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0 - %6 = load i8* %5, align 1 + %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0 + %6 = load i8, i8* %5, align 1 %7 = zext i8 %6 to i32 ; ARM: andsne ; THUMB: ands @@ -134,3 +134,27 @@ bb4: ; preds = %bb2 return: ; preds = %bb2, %bb, %entry ret i8 1 } + + +; We were looking through multiple COPY instructions to find an AND we might +; fold into a TST, but in doing so we changed the register being tested allowing +; folding of unrelated tests (in this case, a TST against r1 was eliminated in +; favour of an AND of r0). + +; ARM-LABEL: test_tst_assessment: +; THUMB-LABEL: test_tst_assessment: +; T2-LABEL: test_tst_assessment: +; V8-LABEL: test_tst_assessment: +define i32 @test_tst_assessment(i1 %lhs, i1 %rhs) { + %lhs32 = zext i1 %lhs to i32 + %rhs32 = zext i1 %rhs to i32 + %diff = sub nsw i32 %lhs32, %rhs32 +; ARM: tst r1, #1 +; THUMB: movs [[RTMP:r[0-9]+]], #1 +; THUMB: tst r1, [[RTMP]] +; T2: tst.w r1, #1 +; V8: tst.w r1, #1 + ret i32 %diff +} + +!1 = !{!"branch_weights", i32 1, i32 1, i32 3, i32 2 } diff --git a/test/CodeGen/ARM/arm-asm.ll b/test/CodeGen/ARM/arm-asm.ll index e869abeb2dd6..f9199ff82b38 100644 --- a/test/CodeGen/ARM/arm-asm.ll +++ b/test/CodeGen/ARM/arm-asm.ll @@ -2,6 +2,6 @@ define void @frame_dummy() { entry: - %tmp1 = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null ) ; <void (i8*)*> [#uses=0] + %tmp1 = tail call void (i8*)* (void (i8*)*) asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null ) ; <void (i8*)*> [#uses=0] ret void } diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll index 580f7e7a90c7..67d468e8abd2 100644 --- a/test/CodeGen/ARM/arm-modifier.ll +++ b/test/CodeGen/ARM/arm-modifier.ll @@ -6,8 +6,8 @@ entry: %scale2.addr = alloca float, align 4 store float %scale, float* %scale.addr, align 4 store float %scale2, float* %scale2.addr, align 4 - %tmp = load float* %scale.addr, align 4 - %tmp1 = load float* %scale2.addr, align 4 + %tmp = load float, float* %scale.addr, align 4 + %tmp1 = load float, float* %scale2.addr, align 4 call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind ret i32 0 } @@ -49,8 +49,8 @@ entry: ; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}} ; CHECK: adds {{lr|r[0-9]+}}, [[REG1]] ; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}} -%tmp = load i64* @f3_var, align 4 -%tmp1 = load i64* @f3_var2, align 4 +%tmp = load i64, i64* @f3_var, align 4 +%tmp1 = load i64, i64* @f3_var2, align 4 %0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind store i64 %0, i64* @f3_var, align 4 %1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** @f3_ptr) nounwind diff --git a/test/CodeGen/ARM/arm-negative-stride.ll b/test/CodeGen/ARM/arm-negative-stride.ll index 7decb974e268..2ea15cf429e1 100644 --- a/test/CodeGen/ARM/arm-negative-stride.ll +++ b/test/CodeGen/ARM/arm-negative-stride.ll @@ -12,7 +12,7 @@ entry: bb: ; preds = %bb, %entry %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] %i_addr.09.0 = sub i32 %i, %indvar ; <i32> [#uses=1] - %tmp2 = getelementptr i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1] + %tmp2 = getelementptr i32, i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1] store i32 %A, i32* %tmp2 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] icmp eq i32 %indvar.next, %i ; <i1>:1 [#uses=1] @@ -34,7 +34,7 @@ entry: bb: ; preds = %bb, %entry %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] %i_addr.09.0 = sub i32 %i, %indvar ; <i32> [#uses=1] - %tmp2 = getelementptr i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1] + %tmp2 = getelementptr i32, i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1] store i32 %A, i32* %tmp2 store i32 %indvar, i32* null %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] diff --git a/test/CodeGen/ARM/arm-ttype-target2.ll b/test/CodeGen/ARM/arm-ttype-target2.ll index 4d61cb5bb3a5..754a16d90877 100644 --- a/test/CodeGen/ARM/arm-ttype-target2.ll +++ b/test/CodeGen/ARM/arm-ttype-target2.ll @@ -2,7 +2,7 @@ @_ZTVN10__cxxabiv117__class_type_infoE = external global i8* @_ZTS3Foo = linkonce_odr constant [5 x i8] c"3Foo\00" -@_ZTI3Foo = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([5 x i8]* @_ZTS3Foo, i32 0, i32 0) } +@_ZTI3Foo = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @_ZTS3Foo, i32 0, i32 0) } define i32 @main() { entry: diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 0c0769f1b145..7510d6ccdc33 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -214,7 +214,7 @@ define i64 @test8(i64* %ptr) { ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: dmb {{ish$}} - %r = load atomic i64* %ptr seq_cst, align 8 + %r = load atomic i64, i64* %ptr seq_cst, align 8 ret i64 %r } diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll index af13dfc80d2d..5db81781a7f7 100644 --- a/test/CodeGen/ARM/atomic-load-store.ll +++ b/test/CodeGen/ARM/atomic-load-store.ll @@ -44,7 +44,7 @@ define i32 @test2(i32* %ptr) { ; THUMBM-LABEL: test2 ; THUMBM: ldr ; THUMBM: dmb sy - %val = load atomic i32* %ptr seq_cst, align 4 + %val = load atomic i32, i32* %ptr seq_cst, align 4 ret i32 %val } @@ -76,7 +76,7 @@ define void @test3(i8* %ptr1, i8* %ptr2) { ; ARMV6-NOT: mcr ; THUMBM-LABEL: test3 ; THUMBM-NOT: dmb sy - %val = load atomic i8* %ptr1 unordered, align 1 + %val = load atomic i8, i8* %ptr1 unordered, align 1 store atomic i8 %val, i8* %ptr2 unordered, align 1 ret void } @@ -87,7 +87,7 @@ define void @test4(i8* %ptr1, i8* %ptr2) { ; THUMBONE: ___sync_lock_test_and_set_1 ; ARMV6-LABEL: test4 ; THUMBM-LABEL: test4 - %val = load atomic i8* %ptr1 seq_cst, align 1 + %val = load atomic i8, i8* %ptr1 seq_cst, align 1 store atomic i8 %val, i8* %ptr2 seq_cst, align 1 ret void } @@ -95,7 +95,7 @@ define void @test4(i8* %ptr1, i8* %ptr2) { define i64 @test_old_load_64bit(i64* %p) { ; ARMV4-LABEL: test_old_load_64bit ; ARMV4: ___sync_val_compare_and_swap_8 - %1 = load atomic i64* %p seq_cst, align 8 + %1 = load atomic i64, i64* %p seq_cst, align 8 ret i64 %1 } diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll index 1ac86485c556..db32bffdd5d1 100644 --- a/test/CodeGen/ARM/atomic-op.ll +++ b/test/CodeGen/ARM/atomic-op.ll @@ -25,7 +25,7 @@ entry: store i32 3855, i32* %ort store i32 3855, i32* %xort store i32 4, i32* %temp - %tmp = load i32* %temp + %tmp = load i32, i32* %temp ; CHECK: ldrex ; CHECK: add ; CHECK: strex @@ -308,8 +308,8 @@ define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) { define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind { ; CHECK-LABEL: load_load_add_acquire - %val1 = load atomic i32* %mem1 acquire, align 4 - %val2 = load atomic i32* %mem2 acquire, align 4 + %val1 = load atomic i32, i32* %mem1 acquire, align 4 + %val2 = load atomic i32, i32* %mem2 acquire, align 4 %tmp = add i32 %val1, %val2 ; CHECK: ldr {{r[0-9]}}, [r0] @@ -353,7 +353,7 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) { define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) { ; CHECK-LABEL: load_fence_store_monotonic - %val = load atomic i32* %mem1 monotonic, align 4 + %val = load atomic i32, i32* %mem1 monotonic, align 4 fence seq_cst store atomic i32 %val, i32* %mem2 monotonic, align 4 diff --git a/test/CodeGen/ARM/atomic-ops-v8.ll b/test/CodeGen/ARM/atomic-ops-v8.ll index 7072aaaf733d..db5007b0758d 100644 --- a/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1166,7 +1166,7 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { define i8 @test_atomic_load_monotonic_i8() nounwind { ; CHECK-LABEL: test_atomic_load_monotonic_i8: - %val = load atomic i8* @var8 monotonic, align 1 + %val = load atomic i8, i8* @var8 monotonic, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 @@ -1183,7 +1183,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i8* - %val = load atomic i8* %addr monotonic, align 1 + %val = load atomic i8, i8* %addr monotonic, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK-LE: ldrb r0, [r0, r2] @@ -1196,7 +1196,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { define i8 @test_atomic_load_acquire_i8() nounwind { ; CHECK-LABEL: test_atomic_load_acquire_i8: - %val = load atomic i8* @var8 acquire, align 1 + %val = load atomic i8, i8* @var8 acquire, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 @@ -1213,7 +1213,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind { define i8 @test_atomic_load_seq_cst_i8() nounwind { ; CHECK-LABEL: test_atomic_load_seq_cst_i8: - %val = load atomic i8* @var8 seq_cst, align 1 + %val = load atomic i8, i8* @var8 seq_cst, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 @@ -1230,7 +1230,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind { define i16 @test_atomic_load_monotonic_i16() nounwind { ; CHECK-LABEL: test_atomic_load_monotonic_i16: - %val = load atomic i16* @var16 monotonic, align 2 + %val = load atomic i16, i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 @@ -1251,7 +1251,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i32* - %val = load atomic i32* %addr monotonic, align 4 + %val = load atomic i32, i32* %addr monotonic, align 4 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK-LE: ldr r0, [r0, r2] @@ -1264,7 +1264,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind define i64 @test_atomic_load_seq_cst_i64() nounwind { ; CHECK-LABEL: test_atomic_load_seq_cst_i64: - %val = load atomic i64* @var64 seq_cst, align 8 + %val = load atomic i64, i64* @var64 seq_cst, align 8 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 @@ -1296,7 +1296,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) %addr = inttoptr i64 %addr_int to i8* store atomic i8 %val, i8* %addr monotonic, align 1 -; CHECK-LE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp] +; CHECK-LE: ldr{{b?(\.w)?}} [[VAL:r[0-9]+]], [sp] ; CHECK-LE: strb [[VAL]], [r0, r2] ; CHECK-BE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp, #3] ; CHECK-BE: strb [[VAL]], [r1, r3] @@ -1399,7 +1399,7 @@ define i32 @not.barriers(i32* %var, i1 %cond) { ; CHECK-LABEL: not.barriers: br i1 %cond, label %atomic_ver, label %simple_ver simple_ver: - %oldval = load i32* %var + %oldval = load i32, i32* %var %newval = add nsw i32 %oldval, -1 store i32 %newval, i32* %var br label %somewhere diff --git a/test/CodeGen/ARM/available_externally.ll b/test/CodeGen/ARM/available_externally.ll index d925b5c77706..055074738e5c 100644 --- a/test/CodeGen/ARM/available_externally.ll +++ b/test/CodeGen/ARM/available_externally.ll @@ -5,7 +5,7 @@ @B = external hidden constant i32 define i32 @t1() { - %tmp = load i32* @A + %tmp = load i32, i32* @A store i32 %tmp, i32* @B ret i32 %tmp } diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll index 0217a4a8fb83..c3de07e03b6b 100644 --- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -30,19 +30,19 @@ while.body: ; CHECK-NOT: muls %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] - %0 = load i32* %ptr1.addr.09, align 4 - %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1 - %1 = load i32* %arrayidx1, align 4 - %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2 - %2 = load i32* %arrayidx3, align 4 - %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3 - %3 = load i32* %arrayidx4, align 4 - %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4 + %0 = load i32, i32* %ptr1.addr.09, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1 + %1 = load i32, i32* %arrayidx1, align 4 + %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2 + %2 = load i32, i32* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3 + %3 = load i32, i32* %arrayidx4, align 4 + %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4 %mul = mul i32 %1, %0 %mul5 = mul i32 %mul, %2 %mul6 = mul i32 %mul5, %3 store i32 %mul6, i32* %ptr2.addr.08, align 4 - %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1 + %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1 %tobool = icmp eq i32* %incdec.ptr, null br i1 %tobool, label %while.end, label %while.body @@ -64,19 +64,19 @@ while.body: ; CHECK: muls %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] - %0 = load i32* %ptr1.addr.09, align 4 - %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1 - %1 = load i32* %arrayidx1, align 4 - %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2 - %2 = load i32* %arrayidx3, align 4 - %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3 - %3 = load i32* %arrayidx4, align 4 - %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4 + %0 = load i32, i32* %ptr1.addr.09, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1 + %1 = load i32, i32* %arrayidx1, align 4 + %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2 + %2 = load i32, i32* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3 + %3 = load i32, i32* %arrayidx4, align 4 + %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4 %mul = mul i32 %1, %0 %mul5 = mul i32 %mul, %2 %mul6 = mul i32 %mul5, %3 store i32 %mul6, i32* %ptr2.addr.08, align 4 - %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1 + %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1 %tobool = icmp eq i32* %incdec.ptr, null br i1 %tobool, label %while.end, label %while.body @@ -92,21 +92,21 @@ entry: ; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: if.then ; CHECK-NOT: movs - %0 = load double* %q, align 4 + %0 = load double, double* %q, align 4 %cmp = fcmp olt double %0, 1.000000e+01 - %incdec.ptr1 = getelementptr inbounds i32* %p, i32 1 + %incdec.ptr1 = getelementptr inbounds i32, i32* %p, i32 1 br i1 %cmp, label %if.then, label %if.else if.then: store i32 7, i32* %p, align 4 - %incdec.ptr2 = getelementptr inbounds i32* %p, i32 2 + %incdec.ptr2 = getelementptr inbounds i32, i32* %p, i32 2 store i32 8, i32* %incdec.ptr1, align 4 store i32 9, i32* %incdec.ptr2, align 4 br label %if.end if.else: store i32 3, i32* %p, align 4 - %incdec.ptr5 = getelementptr inbounds i32* %p, i32 2 + %incdec.ptr5 = getelementptr inbounds i32, i32* %p, i32 2 store i32 5, i32* %incdec.ptr1, align 4 store i32 6, i32* %incdec.ptr5, align 4 br label %if.end diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll index bce09da7618a..0661960d1ae0 100644 --- a/test/CodeGen/ARM/bfi.ll +++ b/test/CodeGen/ARM/bfi.ll @@ -9,7 +9,7 @@ entry: ; CHECK: f1 ; CHECK: mov r2, #10 ; CHECK: bfi r1, r2, #22, #4 - %0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1] + %0 = load i32, i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1] %1 = and i32 %0, -62914561 ; <i32> [#uses=1] %2 = or i32 %1, 41943040 ; <i32> [#uses=1] store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4 diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll index 46f49e9fab20..edb0c1a5a54a 100644 --- a/test/CodeGen/ARM/bfx.ll +++ b/test/CodeGen/ARM/bfx.ll @@ -41,13 +41,13 @@ entry: %and1 = lshr i32 %x, 16 %shr2 = and i32 %and1, 255 %shr4 = lshr i32 %x, 24 - %arrayidx = getelementptr inbounds i32* %ctx, i32 %shr4 - %0 = load i32* %arrayidx, align 4 - %arrayidx5 = getelementptr inbounds i32* %ctx, i32 %shr2 - %1 = load i32* %arrayidx5, align 4 + %arrayidx = getelementptr inbounds i32, i32* %ctx, i32 %shr4 + %0 = load i32, i32* %arrayidx, align 4 + %arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2 + %1 = load i32, i32* %arrayidx5, align 4 %add = add i32 %1, %0 - %arrayidx6 = getelementptr inbounds i32* %ctx, i32 %shr - %2 = load i32* %arrayidx6, align 4 + %arrayidx6 = getelementptr inbounds i32, i32* %ctx, i32 %shr + %2 = load i32, i32* %arrayidx6, align 4 %add7 = add i32 %add, %2 ret i32 %add7 } diff --git a/test/CodeGen/ARM/big-endian-neon-bitconv.ll b/test/CodeGen/ARM/big-endian-neon-bitconv.ll index 427d2e731428..b5a840a48f7a 100644 --- a/test/CodeGen/ARM/big-endian-neon-bitconv.ll +++ b/test/CodeGen/ARM/big-endian-neon-bitconv.ll @@ -19,7 +19,7 @@ define void @conv_i64_to_v8i8( i64 %val, <8 x i8>* %store ) { ; CHECK-LABEL: conv_i64_to_v8i8: ; CHECK: vrev64.8 %v = bitcast i64 %val to <8 x i8> - %w = load <8 x i8>* @v8i8 + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w store <8 x i8> %a, <8 x i8>* %store ret void @@ -28,8 +28,8 @@ define void @conv_i64_to_v8i8( i64 %val, <8 x i8>* %store ) { define void @conv_v8i8_to_i64( <8 x i8>* %load, <8 x i8>* %store ) { ; CHECK-LABEL: conv_v8i8_to_i64: ; CHECK: vrev64.8 - %v = load <8 x i8>* %load - %w = load <8 x i8>* @v8i8 + %v = load <8 x i8>, <8 x i8>* %load + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w %f = bitcast <8 x i8> %a to i64 call void @conv_i64_to_v8i8( i64 %f, <8 x i8>* %store ) @@ -40,7 +40,7 @@ define void @conv_i64_to_v4i16( i64 %val, <4 x i16>* %store ) { ; CHECK-LABEL: conv_i64_to_v4i16: ; CHECK: vrev64.16 %v = bitcast i64 %val to <4 x i16> - %w = load <4 x i16>* @v4i16 + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w store <4 x i16> %a, <4 x i16>* %store ret void @@ -49,8 +49,8 @@ define void @conv_i64_to_v4i16( i64 %val, <4 x i16>* %store ) { define void @conv_v4i16_to_i64( <4 x i16>* %load, <4 x i16>* %store ) { ; CHECK-LABEL: conv_v4i16_to_i64: ; CHECK: vrev64.16 - %v = load <4 x i16>* %load - %w = load <4 x i16>* @v4i16 + %v = load <4 x i16>, <4 x i16>* %load + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w %f = bitcast <4 x i16> %a to i64 call void @conv_i64_to_v4i16( i64 %f, <4 x i16>* %store ) @@ -61,7 +61,7 @@ define void @conv_i64_to_v2i32( i64 %val, <2 x i32>* %store ) { ; CHECK-LABEL: conv_i64_to_v2i32: ; CHECK: vrev64.32 %v = bitcast i64 %val to <2 x i32> - %w = load <2 x i32>* @v2i32 + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w store <2 x i32> %a, <2 x i32>* %store ret void @@ -70,8 +70,8 @@ define void @conv_i64_to_v2i32( i64 %val, <2 x i32>* %store ) { define void @conv_v2i32_to_i64( <2 x i32>* %load, <2 x i32>* %store ) { ; CHECK-LABEL: conv_v2i32_to_i64: ; CHECK: vrev64.32 - %v = load <2 x i32>* %load - %w = load <2 x i32>* @v2i32 + %v = load <2 x i32>, <2 x i32>* %load + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w %f = bitcast <2 x i32> %a to i64 call void @conv_i64_to_v2i32( i64 %f, <2 x i32>* %store ) @@ -82,7 +82,7 @@ define void @conv_i64_to_v2f32( i64 %val, <2 x float>* %store ) { ; CHECK-LABEL: conv_i64_to_v2f32: ; CHECK: vrev64.32 %v = bitcast i64 %val to <2 x float> - %w = load <2 x float>* @v2f32 + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w store <2 x float> %a, <2 x float>* %store ret void @@ -91,8 +91,8 @@ define void @conv_i64_to_v2f32( i64 %val, <2 x float>* %store ) { define void @conv_v2f32_to_i64( <2 x float>* %load, <2 x float>* %store ) { ; CHECK-LABEL: conv_v2f32_to_i64: ; CHECK: vrev64.32 - %v = load <2 x float>* %load - %w = load <2 x float>* @v2f32 + %v = load <2 x float>, <2 x float>* %load + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w %f = bitcast <2 x float> %a to i64 call void @conv_i64_to_v2f32( i64 %f, <2 x float>* %store ) @@ -103,7 +103,7 @@ define void @conv_f64_to_v8i8( double %val, <8 x i8>* %store ) { ; CHECK-LABEL: conv_f64_to_v8i8: ; CHECK: vrev64.8 %v = bitcast double %val to <8 x i8> - %w = load <8 x i8>* @v8i8 + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w store <8 x i8> %a, <8 x i8>* %store ret void @@ -112,8 +112,8 @@ define void @conv_f64_to_v8i8( double %val, <8 x i8>* %store ) { define void @conv_v8i8_to_f64( <8 x i8>* %load, <8 x i8>* %store ) { ; CHECK-LABEL: conv_v8i8_to_f64: ; CHECK: vrev64.8 - %v = load <8 x i8>* %load - %w = load <8 x i8>* @v8i8 + %v = load <8 x i8>, <8 x i8>* %load + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w %f = bitcast <8 x i8> %a to double call void @conv_f64_to_v8i8( double %f, <8 x i8>* %store ) @@ -124,7 +124,7 @@ define void @conv_f64_to_v4i16( double %val, <4 x i16>* %store ) { ; CHECK-LABEL: conv_f64_to_v4i16: ; CHECK: vrev64.16 %v = bitcast double %val to <4 x i16> - %w = load <4 x i16>* @v4i16 + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w store <4 x i16> %a, <4 x i16>* %store ret void @@ -133,8 +133,8 @@ define void @conv_f64_to_v4i16( double %val, <4 x i16>* %store ) { define void @conv_v4i16_to_f64( <4 x i16>* %load, <4 x i16>* %store ) { ; CHECK-LABEL: conv_v4i16_to_f64: ; CHECK: vrev64.16 - %v = load <4 x i16>* %load - %w = load <4 x i16>* @v4i16 + %v = load <4 x i16>, <4 x i16>* %load + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w %f = bitcast <4 x i16> %a to double call void @conv_f64_to_v4i16( double %f, <4 x i16>* %store ) @@ -145,7 +145,7 @@ define void @conv_f64_to_v2i32( double %val, <2 x i32>* %store ) { ; CHECK-LABEL: conv_f64_to_v2i32: ; CHECK: vrev64.32 %v = bitcast double %val to <2 x i32> - %w = load <2 x i32>* @v2i32 + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w store <2 x i32> %a, <2 x i32>* %store ret void @@ -154,8 +154,8 @@ define void @conv_f64_to_v2i32( double %val, <2 x i32>* %store ) { define void @conv_v2i32_to_f64( <2 x i32>* %load, <2 x i32>* %store ) { ; CHECK-LABEL: conv_v2i32_to_f64: ; CHECK: vrev64.32 - %v = load <2 x i32>* %load - %w = load <2 x i32>* @v2i32 + %v = load <2 x i32>, <2 x i32>* %load + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w %f = bitcast <2 x i32> %a to double call void @conv_f64_to_v2i32( double %f, <2 x i32>* %store ) @@ -166,7 +166,7 @@ define void @conv_f64_to_v2f32( double %val, <2 x float>* %store ) { ; CHECK-LABEL: conv_f64_to_v2f32: ; CHECK: vrev64.32 %v = bitcast double %val to <2 x float> - %w = load <2 x float>* @v2f32 + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w store <2 x float> %a, <2 x float>* %store ret void @@ -175,8 +175,8 @@ define void @conv_f64_to_v2f32( double %val, <2 x float>* %store ) { define void @conv_v2f32_to_f64( <2 x float>* %load, <2 x float>* %store ) { ; CHECK-LABEL: conv_v2f32_to_f64: ; CHECK: vrev64.32 - %v = load <2 x float>* %load - %w = load <2 x float>* @v2f32 + %v = load <2 x float>, <2 x float>* %load + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w %f = bitcast <2 x float> %a to double call void @conv_f64_to_v2f32( double %f, <2 x float>* %store ) @@ -190,7 +190,7 @@ define void @conv_i128_to_v16i8( i128 %val, <16 x i8>* %store ) { ; CHECK-LABEL: conv_i128_to_v16i8: ; CHECK: vrev32.8 %v = bitcast i128 %val to <16 x i8> - %w = load <16 x i8>* @v16i8 + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w store <16 x i8> %a, <16 x i8>* %store ret void @@ -199,8 +199,8 @@ define void @conv_i128_to_v16i8( i128 %val, <16 x i8>* %store ) { define void @conv_v16i8_to_i128( <16 x i8>* %load, <16 x i8>* %store ) { ; CHECK-LABEL: conv_v16i8_to_i128: ; CHECK: vrev32.8 - %v = load <16 x i8>* %load - %w = load <16 x i8>* @v16i8 + %v = load <16 x i8>, <16 x i8>* %load + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w %f = bitcast <16 x i8> %a to i128 call void @conv_i128_to_v16i8( i128 %f, <16 x i8>* %store ) @@ -211,7 +211,7 @@ define void @conv_i128_to_v8i16( i128 %val, <8 x i16>* %store ) { ; CHECK-LABEL: conv_i128_to_v8i16: ; CHECK: vrev32.16 %v = bitcast i128 %val to <8 x i16> - %w = load <8 x i16>* @v8i16 + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w store <8 x i16> %a, <8 x i16>* %store ret void @@ -220,8 +220,8 @@ define void @conv_i128_to_v8i16( i128 %val, <8 x i16>* %store ) { define void @conv_v8i16_to_i128( <8 x i16>* %load, <8 x i16>* %store ) { ; CHECK-LABEL: conv_v8i16_to_i128: ; CHECK: vrev32.16 - %v = load <8 x i16>* %load - %w = load <8 x i16>* @v8i16 + %v = load <8 x i16>, <8 x i16>* %load + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w %f = bitcast <8 x i16> %a to i128 call void @conv_i128_to_v8i16( i128 %f, <8 x i16>* %store ) @@ -232,7 +232,7 @@ define void @conv_i128_to_v4i32( i128 %val, <4 x i32>* %store ) { ; CHECK-LABEL: conv_i128_to_v4i32: ; CHECK: vrev64.32 %v = bitcast i128 %val to <4 x i32> - %w = load <4 x i32>* @v4i32 + %w = load <4 x i32>, <4 x i32>* @v4i32 %a = add <4 x i32> %v, %w store <4 x i32> %a, <4 x i32>* %store ret void @@ -241,8 +241,8 @@ define void @conv_i128_to_v4i32( i128 %val, <4 x i32>* %store ) { define void @conv_v4i32_to_i128( <4 x i32>* %load, <4 x i32>* %store ) { ; CHECK-LABEL: conv_v4i32_to_i128: ; CHECK: vrev64.32 - %v = load <4 x i32>* %load - %w = load <4 x i32>* @v4i32 + %v = load <4 x i32>, <4 x i32>* %load + %w = load <4 x i32>, <4 x i32>* @v4i32 %a = add <4 x i32> %v, %w %f = bitcast <4 x i32> %a to i128 call void @conv_i128_to_v4i32( i128 %f, <4 x i32>* %store ) @@ -253,7 +253,7 @@ define void @conv_i128_to_v4f32( i128 %val, <4 x float>* %store ) { ; CHECK-LABEL: conv_i128_to_v4f32: ; CHECK: vrev64.32 %v = bitcast i128 %val to <4 x float> - %w = load <4 x float>* @v4f32 + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w store <4 x float> %a, <4 x float>* %store ret void @@ -262,8 +262,8 @@ define void @conv_i128_to_v4f32( i128 %val, <4 x float>* %store ) { define void @conv_v4f32_to_i128( <4 x float>* %load, <4 x float>* %store ) { ; CHECK-LABEL: conv_v4f32_to_i128: ; CHECK: vrev64.32 - %v = load <4 x float>* %load - %w = load <4 x float>* @v4f32 + %v = load <4 x float>, <4 x float>* %load + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w %f = bitcast <4 x float> %a to i128 call void @conv_i128_to_v4f32( i128 %f, <4 x float>* %store ) @@ -274,7 +274,7 @@ define void @conv_f128_to_v2f64( fp128 %val, <2 x double>* %store ) { ; CHECK-LABEL: conv_f128_to_v2f64: ; CHECK: vrev64.32 %v = bitcast fp128 %val to <2 x double> - %w = load <2 x double>* @v2f64 + %w = load <2 x double>, <2 x double>* @v2f64 %a = fadd <2 x double> %v, %w store <2 x double> %a, <2 x double>* %store ret void @@ -283,8 +283,8 @@ define void @conv_f128_to_v2f64( fp128 %val, <2 x double>* %store ) { define void @conv_v2f64_to_f128( <2 x double>* %load, <2 x double>* %store ) { ; CHECK-LABEL: conv_v2f64_to_f128: ; CHECK: vrev64.32 - %v = load <2 x double>* %load - %w = load <2 x double>* @v2f64 + %v = load <2 x double>, <2 x double>* %load + %w = load <2 x double>, <2 x double>* @v2f64 %a = fadd <2 x double> %v, %w %f = bitcast <2 x double> %a to fp128 call void @conv_f128_to_v2f64( fp128 %f, <2 x double>* %store ) @@ -295,7 +295,7 @@ define void @conv_f128_to_v16i8( fp128 %val, <16 x i8>* %store ) { ; CHECK-LABEL: conv_f128_to_v16i8: ; CHECK: vrev32.8 %v = bitcast fp128 %val to <16 x i8> - %w = load <16 x i8>* @v16i8 + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w store <16 x i8> %a, <16 x i8>* %store ret void @@ -304,8 +304,8 @@ define void @conv_f128_to_v16i8( fp128 %val, <16 x i8>* %store ) { define void @conv_v16i8_to_f128( <16 x i8>* %load, <16 x i8>* %store ) { ; CHECK-LABEL: conv_v16i8_to_f128: ; CHECK: vrev32.8 - %v = load <16 x i8>* %load - %w = load <16 x i8>* @v16i8 + %v = load <16 x i8>, <16 x i8>* %load + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w %f = bitcast <16 x i8> %a to fp128 call void @conv_f128_to_v16i8( fp128 %f, <16 x i8>* %store ) @@ -316,7 +316,7 @@ define void @conv_f128_to_v8i16( fp128 %val, <8 x i16>* %store ) { ; CHECK-LABEL: conv_f128_to_v8i16: ; CHECK: vrev32.16 %v = bitcast fp128 %val to <8 x i16> - %w = load <8 x i16>* @v8i16 + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w store <8 x i16> %a, <8 x i16>* %store ret void @@ -325,8 +325,8 @@ define void @conv_f128_to_v8i16( fp128 %val, <8 x i16>* %store ) { define void @conv_v8i16_to_f128( <8 x i16>* %load, <8 x i16>* %store ) { ; CHECK-LABEL: conv_v8i16_to_f128: ; CHECK: vrev32.16 - %v = load <8 x i16>* %load - %w = load <8 x i16>* @v8i16 + %v = load <8 x i16>, <8 x i16>* %load + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w %f = bitcast <8 x i16> %a to fp128 call void @conv_f128_to_v8i16( fp128 %f, <8 x i16>* %store ) @@ -337,7 +337,7 @@ define void @conv_f128_to_v4f32( fp128 %val, <4 x float>* %store ) { ; CHECK-LABEL: conv_f128_to_v4f32: ; CHECK: vrev64.32 %v = bitcast fp128 %val to <4 x float> - %w = load <4 x float>* @v4f32 + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w store <4 x float> %a, <4 x float>* %store ret void @@ -346,8 +346,8 @@ define void @conv_f128_to_v4f32( fp128 %val, <4 x float>* %store ) { define void @conv_v4f32_to_f128( <4 x float>* %load, <4 x float>* %store ) { ; CHECK-LABEL: conv_v4f32_to_f128: ; CHECK: vrev64.32 - %v = load <4 x float>* %load - %w = load <4 x float>* @v4f32 + %v = load <4 x float>, <4 x float>* %load + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w %f = bitcast <4 x float> %a to fp128 call void @conv_f128_to_v4f32( fp128 %f, <4 x float>* %store ) diff --git a/test/CodeGen/ARM/big-endian-neon-extend.ll b/test/CodeGen/ARM/big-endian-neon-extend.ll index 931c6c3979c6..f8542b708b8a 100644 --- a/test/CodeGen/ARM/big-endian-neon-extend.ll +++ b/test/CodeGen/ARM/big-endian-neon-extend.ll @@ -2,11 +2,14 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i8_to_2i64: -; CHECK: vld1.16 {[[REG:d[0-9]+]] -; CHECK: vmov.i64 {{q[0-9]+}}, #0xff -; CHECK: vrev16.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] - %1 = load <2 x i8>* %loadaddr +; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16] +; CHECK-NEXT: vrev16.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] +; CHECK-NEXT: bx lr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr ret void @@ -14,11 +17,13 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i16_to_2i64: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vmov.i64 {{q[0-9]+}}, #0xffff -; CHECK: vrev32.16 [[REG]], [[REG]] -; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]] - %1 = load <2 x i16>* %loadaddr +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] +; CHECK-NEXT: bx lr + %1 = load <2 x i16>, <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr ret void @@ -27,9 +32,14 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i8_to_2i32: -; CHECK: vld1.16 {[[REG:d[0-9]+]] -; CHECK: vrev16.8 [[REG]], [[REG]] - %1 = load <2 x i8>* %loadaddr +; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16] +; CHECK-NEXT: vrev16.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] +; CHECK-NEXT: vstr [[REG]], [r1] +; CHECK-NEXT: bx lr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr ret void @@ -37,10 +47,13 @@ define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i16_to_2i32: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vrev32.16 [[REG]], [[REG]] -; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]] - %1 = load <2 x i16>* %loadaddr +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] +; CHECK-NEXT: vstr [[REG]], [r1] +; CHECK-NEXT: bx lr + %1 = load <2 x i16>, <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr ret void @@ -48,10 +61,16 @@ define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeadd define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i8_to_2i16: -; CHECK: vld1.16 {[[REG:d[0-9]+]] -; CHECK: vrev16.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] - %1 = load <2 x i8>* %loadaddr +; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16] +; CHECK-NEXT: vrev16.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] +; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}} +; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}} +; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32] +; CHECK-NEXT: bx lr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i16> store <2 x i16> %2, <2 x i16>* %storeaddr ret void @@ -59,10 +78,14 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) { ; CHECK-LABEL: vector_ext_4i8_to_4i32: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vrev32.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] - %1 = load <4 x i8>* %loadaddr +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vrev32.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] +; CHECK-NEXT: bx lr + %1 = load <4 x i8>, <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i32> store <4 x i32> %2, <4 x i32>* %storeaddr ret void @@ -70,12 +93,14 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) { ; CHECK-LABEL: vector_ext_4i8_to_4i16: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vrev32.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] - %1 = load <4 x i8>* %loadaddr +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vrev32.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vrev64.16 [[REG]], [[REG]] +; CHECK-NEXT: vstr [[REG]], [r1] +; CHECK-NEXT: bx lr + %1 = load <4 x i8>, <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i16> store <4 x i16> %2, <4 x i16>* %storeaddr ret void } - diff --git a/test/CodeGen/ARM/big-endian-neon-trunc-store.ll b/test/CodeGen/ARM/big-endian-neon-trunc-store.ll index 65147ad5d3f7..cbfc46ed255b 100644 --- a/test/CodeGen/ARM/big-endian-neon-trunc-store.ll +++ b/test/CodeGen/ARM/big-endian-neon-trunc-store.ll @@ -6,7 +6,7 @@ define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* % ; CHECK: vrev32.16 [[REG]], [[REG]] ; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]] ; CHECK: vrev32.16 [[REG]], [[REG2]] - %1 = load <2 x i64>* %loadaddr + %1 = load <2 x i64>, <2 x i64>* %loadaddr %2 = trunc <2 x i64> %1 to <2 x i16> store <2 x i16> %2, <2 x i16>* %storeaddr ret void @@ -18,7 +18,7 @@ define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %st ; CHECK: vrev16.8 [[REG]], [[REG]] ; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]] ; CHECK: vrev32.8 [[REG]], [[REG2]] - %1 = load <4 x i32>* %loadaddr + %1 = load <4 x i32>, <4 x i32>* %loadaddr %2 = trunc <4 x i32> %1 to <4 x i8> store <4 x i8> %2, <4 x i8>* %storeaddr ret void diff --git a/test/CodeGen/ARM/big-endian-ret-f64.ll b/test/CodeGen/ARM/big-endian-ret-f64.ll index 614bfc0a5b3a..f83e0864100c 100644 --- a/test/CodeGen/ARM/big-endian-ret-f64.ll +++ b/test/CodeGen/ARM/big-endian-ret-f64.ll @@ -6,7 +6,7 @@ define double @fn() { ; CHECK: ldr r0, [sp] ; CHECK: ldr r1, [sp, #4] %r = alloca double, align 8 - %1 = load double* %r, align 8 + %1 = load double, double* %r, align 8 ret double %1 } diff --git a/test/CodeGen/ARM/big-endian-vector-caller.ll b/test/CodeGen/ARM/big-endian-vector-caller.ll index d01b0a7c974f..54bda66c54a9 100644 --- a/test/CodeGen/ARM/big-endian-vector-caller.ll +++ b/test/CodeGen/ARM/big-endian-vector-caller.ll @@ -7,7 +7,7 @@ define void @test_i64_f64(double* %p, i64* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call i64 @test_i64_f64_helper(double %2) %4 = add i64 %3, %3 @@ -23,7 +23,7 @@ define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2) %4 = add i64 %3, %3 @@ -39,7 +39,7 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2) %4 = add i64 %3, %3 @@ -55,7 +55,7 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2) %4 = add i64 %3, %3 @@ -71,7 +71,7 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2) %4 = add i64 %3, %3 @@ -87,7 +87,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2) %4 = add i64 %3, %3 @@ -102,7 +102,7 @@ declare double @test_f64_i64_helper(i64 %p) define void @test_f64_i64(i64* %p, double* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call double @test_f64_i64_helper(i64 %2) %4 = fadd double %3, %3 @@ -119,7 +119,7 @@ define void @test_f64_v1i64(<1 x i64>* %p, double* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call double @test_f64_v1i64_helper(<1 x i64> %2) %4 = fadd double %3, %3 @@ -136,7 +136,7 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call double @test_f64_v2f32_helper(<2 x float> %2) %4 = fadd double %3, %3 @@ -153,7 +153,7 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call double @test_f64_v2i32_helper(<2 x i32> %2) %4 = fadd double %3, %3 @@ -170,7 +170,7 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call double @test_f64_v4i16_helper(<4 x i16> %2) %4 = fadd double %3, %3 @@ -187,7 +187,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call double @test_f64_v8i8_helper(<8 x i8> %2) %4 = fadd double %3, %3 @@ -203,7 +203,7 @@ declare <1 x i64> @test_v1i64_i64_helper(i64 %p) define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2) %4 = add <1 x i64> %3, %3 @@ -220,7 +220,7 @@ define void @test_v1i64_f64(double* %p, <1 x i64>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <1 x i64> @test_v1i64_f64_helper(double %2) %4 = add <1 x i64> %3, %3 @@ -237,7 +237,7 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) { ; HARD: vrev64.32 d0 ; SOFT: vadd.f32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2) %4 = add <1 x i64> %3, %3 @@ -255,7 +255,7 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) { ; SOFT: vadd.i32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2) %4 = add <1 x i64> %3, %3 @@ -272,7 +272,7 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2) %4 = add <1 x i64> %3, %3 @@ -289,7 +289,7 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2) %4 = add <1 x i64> %3, %3 @@ -305,7 +305,7 @@ declare <2 x float> @test_v2f32_i64_helper(i64 %p) define void @test_v2f32_i64(i64* %p, <2 x float>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2) %4 = fadd <2 x float> %3, %3 @@ -322,7 +322,7 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x float> @test_v2f32_f64_helper(double %2) %4 = fadd <2 x float> %3, %3 @@ -339,7 +339,7 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2) %4 = fadd <2 x float> %3, %3 @@ -357,7 +357,7 @@ define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) { ; SOFT: vadd.i32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2) %4 = fadd <2 x float> %3, %3 @@ -374,7 +374,7 @@ define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2) %4 = fadd <2 x float> %3, %3 @@ -391,7 +391,7 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2) %4 = fadd <2 x float> %3, %3 @@ -407,7 +407,7 @@ declare <2 x i32> @test_v2i32_i64_helper(i64 %p) define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2) %4 = add <2 x i32> %3, %3 @@ -424,7 +424,7 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x i32> @test_v2i32_f64_helper(double %2) %4 = add <2 x i32> %3, %3 @@ -441,7 +441,7 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2) %4 = add <2 x i32> %3, %3 @@ -460,7 +460,7 @@ define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) { ; SOFT: vadd.f32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2) %4 = add <2 x i32> %3, %3 @@ -477,7 +477,7 @@ define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2) %4 = add <2 x i32> %3, %3 @@ -494,7 +494,7 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2) %4 = add <2 x i32> %3, %3 @@ -510,7 +510,7 @@ declare <4 x i16> @test_v4i16_i64_helper(i64 %p) define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2) %4 = add <4 x i16> %3, %3 @@ -527,7 +527,7 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <4 x i16> @test_v4i16_f64_helper(double %2) %4 = add <4 x i16> %3, %3 @@ -544,7 +544,7 @@ define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2) %4 = add <4 x i16> %3, %3 @@ -563,7 +563,7 @@ define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) { ; SOFT: vadd.f32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2) %4 = add <4 x i16> %3, %3 @@ -582,7 +582,7 @@ define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) { ; SOFT: vadd.i32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2) %4 = add <4 x i16> %3, %3 @@ -599,7 +599,7 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2) %4 = add <4 x i16> %3, %3 @@ -615,7 +615,7 @@ declare <8 x i8> @test_v8i8_i64_helper(i64 %p) define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2) %4 = add <8 x i8> %3, %3 @@ -632,7 +632,7 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <8 x i8> @test_v8i8_f64_helper(double %2) %4 = add <8 x i8> %3, %3 @@ -649,7 +649,7 @@ define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2) %4 = add <8 x i8> %3, %3 @@ -666,7 +666,7 @@ define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2) %4 = add <8 x i8> %3, %3 @@ -683,7 +683,7 @@ define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2) %4 = add <8 x i8> %3, %3 @@ -700,7 +700,7 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2) %4 = add <8 x i8> %3, %3 @@ -720,7 +720,7 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) { ; SOFT: vmov r3, r2, [[REG2]] ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2) %4 = fadd fp128 %3, %3 @@ -735,7 +735,7 @@ define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2) %4 = fadd fp128 %3, %3 @@ -750,7 +750,7 @@ define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2) %4 = fadd fp128 %3, %3 @@ -765,7 +765,7 @@ define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2) %4 = fadd fp128 %3, %3 @@ -780,7 +780,7 @@ define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2) %4 = fadd fp128 %3, %3 @@ -795,7 +795,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2) %4 = fadd fp128 %3, %3 @@ -807,7 +807,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { ; CHECK-LABEL: test_v2f64_f128: declare <2 x double> @test_v2f64_f128_helper(fp128 %p) define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2) %4 = fadd <2 x double> %3, %3 @@ -824,7 +824,7 @@ define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2) %4 = fadd <2 x double> %3, %3 @@ -840,7 +840,7 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2) %4 = fadd <2 x double> %3, %3 @@ -856,7 +856,7 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2) %4 = fadd <2 x double> %3, %3 @@ -872,7 +872,7 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2) %4 = fadd <2 x double> %3, %3 @@ -888,7 +888,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2) %4 = fadd <2 x double> %3, %3 @@ -901,7 +901,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { ; CHECK-LABEL: test_v2i64_f128: declare <2 x i64> @test_v2i64_f128_helper(fp128 %p) define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2) %4 = add <2 x i64> %3, %3 @@ -918,7 +918,7 @@ define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) { ; SOFT: vmov r3, r2, [[REG2]] ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2) %4 = add <2 x i64> %3, %3 @@ -934,7 +934,7 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2) %4 = add <2 x i64> %3, %3 @@ -950,7 +950,7 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2) %4 = add <2 x i64> %3, %3 @@ -966,7 +966,7 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2) %4 = add <2 x i64> %3, %3 @@ -982,7 +982,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2) %4 = add <2 x i64> %3, %3 @@ -995,7 +995,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) { ; CHECK-LABEL: test_v4f32_f128: declare <4 x float> @test_v4f32_f128_helper(fp128 %p) define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2) %4 = fadd <4 x float> %3, %3 @@ -1012,7 +1012,7 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2) %4 = fadd <4 x float> %3, %3 @@ -1028,7 +1028,7 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2) %4 = fadd <4 x float> %3, %3 @@ -1044,7 +1044,7 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2) %4 = fadd <4 x float> %3, %3 @@ -1060,7 +1060,7 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2) %4 = fadd <4 x float> %3, %3 @@ -1076,7 +1076,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2) %4 = fadd <4 x float> %3, %3 @@ -1089,7 +1089,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) { ; CHECK-LABEL: test_v4i32_f128: declare <4 x i32> @test_v4i32_f128_helper(fp128 %p) define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2) %4 = add <4 x i32> %3, %3 @@ -1106,7 +1106,7 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2) %4 = add <4 x i32> %3, %3 @@ -1122,7 +1122,7 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2) %4 = add <4 x i32> %3, %3 @@ -1138,7 +1138,7 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2) %4 = add <4 x i32> %3, %3 @@ -1154,7 +1154,7 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2) %4 = add <4 x i32> %3, %3 @@ -1170,7 +1170,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2) %4 = add <4 x i32> %3, %3 @@ -1183,7 +1183,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) { ; CHECK-LABEL: test_v8i16_f128: declare <8 x i16> @test_v8i16_f128_helper(fp128 %p) define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2) %4 = add <8 x i16> %3, %3 @@ -1200,7 +1200,7 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2) %4 = add <8 x i16> %3, %3 @@ -1216,7 +1216,7 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2) %4 = add <8 x i16> %3, %3 @@ -1232,7 +1232,7 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2) %4 = add <8 x i16> %3, %3 @@ -1248,7 +1248,7 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2) %4 = add <8 x i16> %3, %3 @@ -1264,7 +1264,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2) %4 = add <8 x i16> %3, %3 @@ -1277,7 +1277,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) { ; CHECK-LABEL: test_v16i8_f128: declare <16 x i8> @test_v16i8_f128_helper(fp128 %p) define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2) %4 = add <16 x i8> %3, %3 @@ -1294,7 +1294,7 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2) %4 = add <16 x i8> %3, %3 @@ -1310,7 +1310,7 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2) %4 = add <16 x i8> %3, %3 @@ -1326,7 +1326,7 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2) %4 = add <16 x i8> %3, %3 @@ -1342,7 +1342,7 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2) %4 = add <16 x i8> %3, %3 @@ -1358,7 +1358,7 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2) %4 = add <16 x i8> %3, %3 diff --git a/test/CodeGen/ARM/bswap16.ll b/test/CodeGen/ARM/bswap16.ll index 70c62d294eec..dc0e468b72dc 100644 --- a/test/CodeGen/ARM/bswap16.ll +++ b/test/CodeGen/ARM/bswap16.ll @@ -4,7 +4,7 @@ define void @test1(i16* nocapture %data) { entry: - %0 = load i16* %data, align 2 + %0 = load i16, i16* %data, align 2 %1 = tail call i16 @llvm.bswap.i16(i16 %0) store i16 %1, i16* %data, align 2 ret void @@ -30,7 +30,7 @@ entry: define i16 @test3(i16* nocapture %data) { entry: - %0 = load i16* %data, align 2 + %0 = load i16, i16* %data, align 2 %1 = tail call i16 @llvm.bswap.i16(i16 %0) ret i16 %1 diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index 2e382308bf51..1982fa98ef41 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -7,6 +7,8 @@ ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST +; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi | FileCheck %s --check-prefix=V6M +; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=ARM1156T2F-S-FAST ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING @@ -53,9 +55,21 @@ ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus | FileCheck %s --check-prefix=CORTEX-M0PLUS +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0PLUS-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 | FileCheck %s --check-prefix=CORTEX-M1 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M1-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 | FileCheck %s --check-prefix=SC000 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC000-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M3-FAST ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 | FileCheck %s --check-prefix=SC300 +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC300-FAST +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-SOFT-FAST ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD @@ -67,15 +81,26 @@ ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4 | FileCheck %s --check-prefix=CORTEX-R4 +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4f | FileCheck %s --check-prefix=CORTEX-R4F ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 | FileCheck %s --check-prefix=CORTEX-R7 +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R7-FAST +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A +; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A-FAST +; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-CHECK-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-NOFPU @@ -92,10 +117,17 @@ ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -arm-reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE +; ARMv8.1a (AArch32) +; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; ARMv8a (AArch32) ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; ARMv7a ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN @@ -113,6 +145,11 @@ ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; ARMv6k +; RUN: llc < %s -mtriple=armv6k-none-netbsd-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; ARMv6m ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-no-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN @@ -162,6 +199,8 @@ ; V6-FAST-NOT: .eabi_attribute 22 ; V6-FAST: .eabi_attribute 23, 1 +;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for +;; V6-M, however we don't model the OS extension so this is fine. ; V6M: .eabi_attribute 6, 12 ; V6M-NOT: .eabi_attribute 7 ; V6M: .eabi_attribute 8, 0 @@ -723,6 +762,102 @@ ; CORTEX-M0-FAST-NOT: .eabi_attribute 22 ; CORTEX-M0-FAST: .eabi_attribute 23, 1 +; CORTEX-M0PLUS: .cpu cortex-m0plus +; CORTEX-M0PLUS: .eabi_attribute 6, 12 +; CORTEX-M0PLUS-NOT: .eabi_attribute 7 +; CORTEX-M0PLUS: .eabi_attribute 8, 0 +; CORTEX-M0PLUS: .eabi_attribute 9, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-M0PLUS: .eabi_attribute 20, 1 +; CORTEX-M0PLUS: .eabi_attribute 21, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 22 +; CORTEX-M0PLUS: .eabi_attribute 23, 3 +; CORTEX-M0PLUS: .eabi_attribute 24, 1 +; CORTEX-M0PLUS: .eabi_attribute 25, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 27 +; CORTEX-M0PLUS-NOT: .eabi_attribute 28 +; CORTEX-M0PLUS-NOT: .eabi_attribute 36 +; CORTEX-M0PLUS: .eabi_attribute 38, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 42 +; CORTEX-M0PLUS-NOT: .eabi_attribute 44 +; CORTEX-M0PLUS-NOT: .eabi_attribute 68 + +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 19 +;; Despite the M0+ CPU having no FPU in this scenario, we chose to +;; flush to positive zero here. There's no hardware support doing +;; this, but the fast maths software library might and such behaviour +;; would match hardware support on this architecture revision if it +;; existed. +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 20 +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 21 +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 22 +; CORTEX-M0PLUS-FAST: .eabi_attribute 23, 1 + +; CORTEX-M1: .cpu cortex-m1 +; CORTEX-M1: .eabi_attribute 6, 12 +; CORTEX-M1-NOT: .eabi_attribute 7 +; CORTEX-M1: .eabi_attribute 8, 0 +; CORTEX-M1: .eabi_attribute 9, 1 +; CORTEX-M1-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-M1: .eabi_attribute 20, 1 +; CORTEX-M1: .eabi_attribute 21, 1 +; CORTEX-M1-NOT: .eabi_attribute 22 +; CORTEX-M1: .eabi_attribute 23, 3 +; CORTEX-M1: .eabi_attribute 24, 1 +; CORTEX-M1: .eabi_attribute 25, 1 +; CORTEX-M1-NOT: .eabi_attribute 27 +; CORTEX-M1-NOT: .eabi_attribute 28 +; CORTEX-M1-NOT: .eabi_attribute 36 +; CORTEX-M1: .eabi_attribute 38, 1 +; CORTEX-M1-NOT: .eabi_attribute 42 +; CORTEX-M1-NOT: .eabi_attribute 44 +; CORTEX-M1-NOT: .eabi_attribute 68 + +; CORTEX-M1-FAST-NOT: .eabi_attribute 19 +;; Despite the M1 CPU having no FPU in this scenario, we chose to +;; flush to positive zero here. There's no hardware support doing +;; this, but the fast maths software library might and such behaviour +;; would match hardware support on this architecture revision if it +;; existed. +; CORTEX-M1-FAST-NOT: .eabi_attribute 20 +; CORTEX-M1-FAST-NOT: .eabi_attribute 21 +; CORTEX-M1-FAST-NOT: .eabi_attribute 22 +; CORTEX-M1-FAST: .eabi_attribute 23, 1 + +; SC000: .cpu sc000 +; SC000: .eabi_attribute 6, 12 +; SC000-NOT: .eabi_attribute 7 +; SC000: .eabi_attribute 8, 0 +; SC000: .eabi_attribute 9, 1 +; SC000-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; SC000: .eabi_attribute 20, 1 +; SC000: .eabi_attribute 21, 1 +; SC000-NOT: .eabi_attribute 22 +; SC000: .eabi_attribute 23, 3 +; SC000: .eabi_attribute 24, 1 +; SC000: .eabi_attribute 25, 1 +; SC000-NOT: .eabi_attribute 27 +; SC000-NOT: .eabi_attribute 28 +; SC000-NOT: .eabi_attribute 36 +; SC000: .eabi_attribute 38, 1 +; SC000-NOT: .eabi_attribute 42 +; SC000-NOT: .eabi_attribute 44 +; SC000-NOT: .eabi_attribute 68 + +; SC000-FAST-NOT: .eabi_attribute 19 +;; Despite the SC000 CPU having no FPU in this scenario, we chose to +;; flush to positive zero here. There's no hardware support doing +;; this, but the fast maths software library might and such behaviour +;; would match hardware support on this architecture revision if it +;; existed. +; SC000-FAST-NOT: .eabi_attribute 20 +; SC000-FAST-NOT: .eabi_attribute 21 +; SC000-FAST-NOT: .eabi_attribute 22 +; SC000-FAST: .eabi_attribute 23, 1 + ; CORTEX-M3: .cpu cortex-m3 ; CORTEX-M3: .eabi_attribute 6, 10 ; CORTEX-M3: .eabi_attribute 7, 77 @@ -753,6 +888,36 @@ ; CORTEX-M3-FAST-NOT: .eabi_attribute 22 ; CORTEX-M3-FAST: .eabi_attribute 23, 1 +; SC300: .cpu sc300 +; SC300: .eabi_attribute 6, 10 +; SC300: .eabi_attribute 7, 77 +; SC300: .eabi_attribute 8, 0 +; SC300: .eabi_attribute 9, 2 +; SC300-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; SC300: .eabi_attribute 20, 1 +; SC300: .eabi_attribute 21, 1 +; SC300-NOT: .eabi_attribute 22 +; SC300: .eabi_attribute 23, 3 +; SC300: .eabi_attribute 24, 1 +; SC300: .eabi_attribute 25, 1 +; SC300-NOT: .eabi_attribute 27 +; SC300-NOT: .eabi_attribute 28 +; SC300-NOT: .eabi_attribute 36 +; SC300: .eabi_attribute 38, 1 +; SC300-NOT: .eabi_attribute 42 +; SC300-NOT: .eabi_attribute 44 +; SC300-NOT: .eabi_attribute 68 + +; SC300-FAST-NOT: .eabi_attribute 19 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; SC300-FAST: .eabi_attribute 20, 2 +; SC300-FAST-NOT: .eabi_attribute 21 +; SC300-FAST-NOT: .eabi_attribute 22 +; SC300-FAST: .eabi_attribute 23, 1 + ; CORTEX-M4-SOFT: .cpu cortex-m4 ; CORTEX-M4-SOFT: .eabi_attribute 6, 13 ; CORTEX-M4-SOFT: .eabi_attribute 7, 77 @@ -835,6 +1000,7 @@ ; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27 ; CORTEX-M7: .eabi_attribute 36, 1 ; CORTEX-M7: .eabi_attribute 38, 1 +; CORTEX-M7-NOT: .eabi_attribute 44 ; CORTEX-M7: .eabi_attribute 14, 0 ; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 19 @@ -848,6 +1014,49 @@ ; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 22 ; CORTEX-M7-NOFPU-FAST: .eabi_attribute 23, 1 +; CORTEX-R4: .cpu cortex-r4 +; CORTEX-R4: .eabi_attribute 6, 10 +; CORTEX-R4: .eabi_attribute 7, 82 +; CORTEX-R4: .eabi_attribute 8, 1 +; CORTEX-R4: .eabi_attribute 9, 2 +; CORTEX-R4-NOT: .fpu vfpv3-d16 +; CORTEX-R4-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-R4: .eabi_attribute 20, 1 +; CORTEX-R4: .eabi_attribute 21, 1 +; CORTEX-R4-NOT: .eabi_attribute 22 +; CORTEX-R4: .eabi_attribute 23, 3 +; CORTEX-R4: .eabi_attribute 24, 1 +; CORTEX-R4: .eabi_attribute 25, 1 +; CORTEX-R4-NOT: .eabi_attribute 28 +; CORTEX-R4-NOT: .eabi_attribute 36 +; CORTEX-R4: .eabi_attribute 38, 1 +; CORTEX-R4-NOT: .eabi_attribute 42 +; CORTEX-R4-NOT: .eabi_attribute 44 +; CORTEX-R4-NOT: .eabi_attribute 68 + +; CORTEX-R4F: .cpu cortex-r4f +; CORTEX-R4F: .eabi_attribute 6, 10 +; CORTEX-R4F: .eabi_attribute 7, 82 +; CORTEX-R4F: .eabi_attribute 8, 1 +; CORTEX-R4F: .eabi_attribute 9, 2 +; CORTEX-R4F: .fpu vfpv3-d16 +; CORTEX-R4F-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-R4F: .eabi_attribute 20, 1 +; CORTEX-R4F: .eabi_attribute 21, 1 +; CORTEX-R4F-NOT: .eabi_attribute 22 +; CORTEX-R4F: .eabi_attribute 23, 3 +; CORTEX-R4F: .eabi_attribute 24, 1 +; CORTEX-R4F: .eabi_attribute 25, 1 +; CORTEX-R4F: .eabi_attribute 27, 1 +; CORTEX-R4F-NOT: .eabi_attribute 28 +; CORTEX-R4F-NOT: .eabi_attribute 36 +; CORTEX-R4F: .eabi_attribute 38, 1 +; CORTEX-R4F-NOT: .eabi_attribute 42 +; CORTEX-R4F-NOT: .eabi_attribute 44 +; CORTEX-R4F-NOT: .eabi_attribute 68 + ; CORTEX-R5: .cpu cortex-r5 ; CORTEX-R5: .eabi_attribute 6, 10 ; CORTEX-R5: .eabi_attribute 7, 82 @@ -877,6 +1086,35 @@ ; CORTEX-R5-FAST-NOT: .eabi_attribute 22 ; CORTEX-R5-FAST: .eabi_attribute 23, 1 +; CORTEX-R7: .cpu cortex-r7 +; CORTEX-R7: .eabi_attribute 6, 10 +; CORTEX-R7: .eabi_attribute 7, 82 +; CORTEX-R7: .eabi_attribute 8, 1 +; CORTEX-R7: .eabi_attribute 9, 2 +; CORTEX-R7: .fpu vfpv3-d16 +; CORTEX-R7-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-R7: .eabi_attribute 20, 1 +; CORTEX-R7: .eabi_attribute 21, 1 +; CORTEX-R7-NOT: .eabi_attribute 22 +; CORTEX-R7: .eabi_attribute 23, 3 +; CORTEX-R7: .eabi_attribute 24, 1 +; CORTEX-R7: .eabi_attribute 25, 1 +; CORTEX-R7: .eabi_attribute 27, 1 +; CORTEX-R7-NOT: .eabi_attribute 28 +; CORTEX-R7-NOT: .eabi_attribute 36 +; CORTEX-R7: .eabi_attribute 38, 1 +; CORTEX-R7: .eabi_attribute 42, 1 +; CORTEX-R7: .eabi_attribute 44, 2 +; CORTEX-R7-NOT: .eabi_attribute 68 + +; CORTEX-R7-FAST-NOT: .eabi_attribute 19 +;; The R7 has the VFPv3 FP unit, which always flushes preserving sign. +; CORTEX-R7-FAST: .eabi_attribute 20, 2 +; CORTEX-R7-FAST-NOT: .eabi_attribute 21 +; CORTEX-R7-FAST-NOT: .eabi_attribute 22 +; CORTEX-R7-FAST: .eabi_attribute 23, 1 + ; CORTEX-A53: .cpu cortex-a53 ; CORTEX-A53: .eabi_attribute 6, 14 ; CORTEX-A53: .eabi_attribute 7, 65 @@ -937,6 +1175,65 @@ ; CORTEX-A57-FAST-NOT: .eabi_attribute 22 ; CORTEX-A57-FAST: .eabi_attribute 23, 1 +; CORTEX-A72: .cpu cortex-a72 +; CORTEX-A72: .eabi_attribute 6, 14 +; CORTEX-A72: .eabi_attribute 7, 65 +; CORTEX-A72: .eabi_attribute 8, 1 +; CORTEX-A72: .eabi_attribute 9, 2 +; CORTEX-A72: .fpu crypto-neon-fp-armv8 +; CORTEX-A72: .eabi_attribute 12, 3 +; CORTEX-A72-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A72: .eabi_attribute 20, 1 +; CORTEX-A72: .eabi_attribute 21, 1 +; CORTEX-A72-NOT: .eabi_attribute 22 +; CORTEX-A72: .eabi_attribute 23, 3 +; CORTEX-A72: .eabi_attribute 24, 1 +; CORTEX-A72: .eabi_attribute 25, 1 +; CORTEX-A72-NOT: .eabi_attribute 27 +; CORTEX-A72-NOT: .eabi_attribute 28 +; CORTEX-A72: .eabi_attribute 36, 1 +; CORTEX-A72: .eabi_attribute 38, 1 +; CORTEX-A72: .eabi_attribute 42, 1 +; CORTEX-A72-NOT: .eabi_attribute 44 +; CORTEX-A72: .eabi_attribute 68, 3 + +; CORTEX-A72-FAST-NOT: .eabi_attribute 19 +;; The A72 has the ARMv8 FP unit, which always flushes preserving sign. +; CORTEX-A72-FAST: .eabi_attribute 20, 2 +; CORTEX-A72-FAST-NOT: .eabi_attribute 21 +; CORTEX-A72-FAST-NOT: .eabi_attribute 22 +; CORTEX-A72-FAST: .eabi_attribute 23, 1 + +; GENERIC-ARMV8_1-A: .eabi_attribute 6, 14 +; GENERIC-ARMV8_1-A: .eabi_attribute 7, 65 +; GENERIC-ARMV8_1-A: .eabi_attribute 8, 1 +; GENERIC-ARMV8_1-A: .eabi_attribute 9, 2 +; GENERIC-ARMV8_1-A: .fpu crypto-neon-fp-armv8 +; GENERIC-ARMV8_1-A: .eabi_attribute 12, 4 +; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; GENERIC-ARMV8_1-A: .eabi_attribute 20, 1 +; GENERIC-ARMV8_1-A: .eabi_attribute 21, 1 +; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 22 +; GENERIC-ARMV8_1-A: .eabi_attribute 23, 3 +; GENERIC-ARMV8_1-A: .eabi_attribute 24, 1 +; GENERIC-ARMV8_1-A: .eabi_attribute 25, 1 +; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 27 +; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 28 +; GENERIC-ARMV8_1-A: .eabi_attribute 36, 1 +; GENERIC-ARMV8_1-A: .eabi_attribute 38, 1 +; GENERIC-ARMV8_1-A: .eabi_attribute 42, 1 +; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 44 +; GENERIC-ARMV8_1-A: .eabi_attribute 68, 3 + +; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 19 +;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign. +; GENERIC-ARMV8_1-A-FAST: .eabi_attribute 20, 2 +; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 21 +; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 22 +; GENERIC-ARMV8_1-A-FAST: .eabi_attribute 23, 1 + ; RELOC-PIC: .eabi_attribute 15, 1 ; RELOC-PIC: .eabi_attribute 16, 1 ; RELOC-PIC: .eabi_attribute 17, 2 diff --git a/test/CodeGen/ARM/bx_fold.ll b/test/CodeGen/ARM/bx_fold.ll index 5533038fb828..f6651ae8004e 100644 --- a/test/CodeGen/ARM/bx_fold.ll +++ b/test/CodeGen/ARM/bx_fold.ll @@ -6,7 +6,7 @@ entry: bb: ; preds = %bb1 %gep.upgrd.1 = zext i32 %indvar to i64 ; <i64> [#uses=1] - %tmp7 = getelementptr i8* %L, i64 %gep.upgrd.1 ; <i8*> [#uses=1] + %tmp7 = getelementptr i8, i8* %L, i64 %gep.upgrd.1 ; <i8*> [#uses=1] store i8 0, i8* %tmp7 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] br label %bb1 @@ -14,7 +14,7 @@ bb: ; preds = %bb1 bb1: ; preds = %bb, %entry %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3] %i.0 = bitcast i32 %indvar to i32 ; <i32> [#uses=2] - %tmp = tail call i32 (...)* @bar( ) ; <i32> [#uses=1] + %tmp = tail call i32 (...) @bar( ) ; <i32> [#uses=1] %tmp2 = add i32 %i.0, %tmp ; <i32> [#uses=1] %Ptr_addr.0 = sub i32 %Ptr, %tmp2 ; <i32> [#uses=0] %tmp12 = icmp eq i32 %i.0, %Ptr ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/byval-align.ll b/test/CodeGen/ARM/byval-align.ll new file mode 100644 index 000000000000..a26b5a795756 --- /dev/null +++ b/test/CodeGen/ARM/byval-align.ll @@ -0,0 +1,76 @@ +; RUN: llc -mtriple=thumbv7-apple-ios8.0 %s -o - | FileCheck %s + +; This checks that alignments greater than 4 are respected by APCS +; targets. Mostly here to make sure *some* correct code is created after some +; simplifying refactoring; at the time of writing there were no actual APCS +; users of byval alignments > 4, so no real calls for ABI stability. + +; "byval align 16" can't fit in any regs with an i8* taking up r0. +define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) { +; CHECK-LABEL: test_align16: +; CHECK-NOT: sub sp +; CHECK: push {r4, r7, lr} +; CHECK: add r7, sp, #4 + +; CHECK: ldr r0, [r7, #8] + + call void @bar() + %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0 + %val = load i32, i32* %valptr + ret i32 %val +} + +; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the +; space taken up by arg regs). +define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) { +; CHECK-LABEL: test_align8: +; CHECK: sub sp, #8 +; CHECK: push {r4, r7, lr} +; CHECK: add r7, sp, #4 + +; CHECK-DAG: str r2, [r7, #8] +; CHECK-DAG: str r3, [r7, #12] + +; CHECK: ldr r0, [r7, #8] + + call void @bar() + %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0 + %val = load i32, i32* %valptr + ret i32 %val +} + +; "byval align 32" can't fit in regs no matter what: it would be misaligned +; unless the incoming stack was deliberately misaligned. +define i32 @test_align32(i8*, [4 x i32]* byval align 32 %b) { +; CHECK-LABEL: test_align32: +; CHECK-NOT: sub sp +; CHECK: push {r4, r7, lr} +; CHECK: add r7, sp, #4 + +; CHECK: ldr r0, [r7, #8] + + call void @bar() + %valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0 + %val = load i32, i32* %valptr + ret i32 %val +} + +; When passing an object "byval align N", the stack must be at least N-aligned. +define void @test_call_align16() { +; CHECK-LABEL: test_call_align16: +; CHECK: push {r4, r7, lr} +; CHECK: add r7, sp, #4 + +; CHECK: mov [[TMP:r[0-9]+]], sp +; CHECK: bfc [[TMP]], #0, #4 +; CHECK: mov sp, [[TMP]] + +; While we're here, make sure the caller also puts it at sp + ; CHECK: mov r[[BASE:[0-9]+]], sp + ; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]] + call i32 @test_align16(i8* null, [4 x i32]* byval align 16 @var) + ret void +} + +@var = global [4 x i32] zeroinitializer +declare void @bar() diff --git a/test/CodeGen/ARM/cache-intrinsic.ll b/test/CodeGen/ARM/cache-intrinsic.ll index 6048917ee9a3..12b55c7081db 100644 --- a/test/CodeGen/ARM/cache-intrinsic.ll +++ b/test/CodeGen/ARM/cache-intrinsic.ll @@ -10,10 +10,10 @@ define i32 @main() { entry: %retval = alloca i32, align 4 store i32 0, i32* %retval - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0)) - %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8]* @.str1, i32 0, i32 0)) #3 - call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3 - %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8]* @buffer, i32 0, i32 0)) + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0)) + %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str1, i32 0, i32 0)) #3 + call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3 + %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0)) ret i32 0 } diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index a35fd7476465..b2b6aaec8131 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -24,7 +24,7 @@ define void @t2() { ; CHECKT2D: ldr ; CHECKT2D-NEXT: ldr ; CHECKT2D-NEXT: bx r0 - %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] + %tmp = load i32 ()*, i32 ()** @t ; <i32 ()*> [#uses=1] %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] ret void } @@ -153,7 +153,7 @@ define i32 @t9() nounwind { ; CHECKT2D: b.w ___divsi3 %lock = alloca %class.MutexLock, align 1 %1 = call %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock* %lock) - %2 = load i32* @x, align 4 + %2 = load i32, i32* @x, align 4 %3 = sdiv i32 1000, %2 %4 = call %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock* %lock) ret i32 %3 @@ -170,7 +170,7 @@ define float @libcall_tc_test2(float* nocapture %a, float %b) { ; CHECKT2D-LABEL: libcall_tc_test2: ; CHECKT2D: blx _floorf ; CHECKT2D: b.w _truncf - %1 = load float* %a, align 4 + %1 = load float, float* %a, align 4 %call = tail call float @floorf(float %1) store float %call, float* %a, align 4 %call1 = tail call float @truncf(float %b) diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index f6301cf02032..87252a91e1b0 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -20,7 +20,7 @@ define void @f() { define void @g.upgrd.1() { ; CHECKV4: mov lr, pc ; CHECKV5: blx - %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] + %tmp = load i32 ()*, i32 ()** @t ; <i32 ()*> [#uses=1] %tmp.upgrd.2 = call i32 %tmp( ) ; <i32> [#uses=0] ret void } @@ -30,10 +30,10 @@ define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind { ; CHECKV4: bx r{{.*}} BB0: %5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1] - %t35 = load volatile i32* %5 ; <i32> [#uses=1] + %t35 = load volatile i32, i32* %5 ; <i32> [#uses=1] %6 = inttoptr i32 %t35 to i32** ; <i32**> [#uses=1] - %7 = getelementptr i32** %6, i32 86 ; <i32**> [#uses=1] - %8 = load i32** %7 ; <i32*> [#uses=1] + %7 = getelementptr i32*, i32** %6, i32 86 ; <i32**> [#uses=1] + %8 = load i32*, i32** %7 ; <i32*> [#uses=1] %9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; <i32* (i32, i32*, i32, i32*, i32*, i32*)*> [#uses=1] %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1] ret i32* %10 diff --git a/test/CodeGen/ARM/call_nolink.ll b/test/CodeGen/ARM/call_nolink.ll index 48fa3a62ffb0..0cd5bcd086c8 100644 --- a/test/CodeGen/ARM/call_nolink.ll +++ b/test/CodeGen/ARM/call_nolink.ll @@ -22,32 +22,32 @@ bb115.i.i.bb115.i.i_crit_edge: ; preds = %bb115.i.i bb115.i.i: ; preds = %bb115.i.i.bb115.i.i_crit_edge, %newFuncRoot %i_addr.3210.0.i.i = phi i32 [ %tmp166.i.i, %bb115.i.i.bb115.i.i_crit_edge ], [ 0, %newFuncRoot ] ; <i32> [#uses=7] - %tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0 ; <i32*> [#uses=1] - %tmp125.i.i = load i32* %tmp124.i.i ; <i32> [#uses=1] - %tmp126.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp125.i.i ; <i32*> [#uses=1] - %tmp127.i.i = load i32* %tmp126.i.i ; <i32> [#uses=1] - %tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1 ; <i32*> [#uses=1] - %tmp132.i.i = load i32* %tmp131.i.i ; <i32> [#uses=1] - %tmp133.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp132.i.i ; <i32*> [#uses=1] - %tmp134.i.i = load i32* %tmp133.i.i ; <i32> [#uses=1] - %tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2 ; <i32*> [#uses=1] - %tmp139.i.i = load i32* %tmp138.i.i ; <i32> [#uses=1] - %tmp140.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp139.i.i ; <i32*> [#uses=1] - %tmp141.i.i = load i32* %tmp140.i.i ; <i32> [#uses=1] + %tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0 ; <i32*> [#uses=1] + %tmp125.i.i = load i32, i32* %tmp124.i.i ; <i32> [#uses=1] + %tmp126.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp125.i.i ; <i32*> [#uses=1] + %tmp127.i.i = load i32, i32* %tmp126.i.i ; <i32> [#uses=1] + %tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1 ; <i32*> [#uses=1] + %tmp132.i.i = load i32, i32* %tmp131.i.i ; <i32> [#uses=1] + %tmp133.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp132.i.i ; <i32*> [#uses=1] + %tmp134.i.i = load i32, i32* %tmp133.i.i ; <i32> [#uses=1] + %tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2 ; <i32*> [#uses=1] + %tmp139.i.i = load i32, i32* %tmp138.i.i ; <i32> [#uses=1] + %tmp140.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp139.i.i ; <i32*> [#uses=1] + %tmp141.i.i = load i32, i32* %tmp140.i.i ; <i32> [#uses=1] %tmp143.i.i = add i32 %i_addr.3210.0.i.i, 12 ; <i32> [#uses=1] - %tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0 ; <i32*> [#uses=1] - %tmp147.i.i = load i32* %tmp146.i.i ; <i32> [#uses=1] - %tmp149.i.i = getelementptr [13 x %struct.anon]* @isa, i32 0, i32 %tmp147.i.i, i32 0 ; <i32 (i32, i32, i32)**> [#uses=1] - %tmp150.i.i = load i32 (i32, i32, i32)** %tmp149.i.i ; <i32 (i32, i32, i32)*> [#uses=1] + %tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0 ; <i32*> [#uses=1] + %tmp147.i.i = load i32, i32* %tmp146.i.i ; <i32> [#uses=1] + %tmp149.i.i = getelementptr [13 x %struct.anon], [13 x %struct.anon]* @isa, i32 0, i32 %tmp147.i.i, i32 0 ; <i32 (i32, i32, i32)**> [#uses=1] + %tmp150.i.i = load i32 (i32, i32, i32)*, i32 (i32, i32, i32)** %tmp149.i.i ; <i32 (i32, i32, i32)*> [#uses=1] %tmp154.i.i = tail call i32 %tmp150.i.i( i32 %tmp127.i.i, i32 %tmp134.i.i, i32 %tmp141.i.i ) ; <i32> [#uses=1] - %tmp155.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp143.i.i ; <i32*> [#uses=1] + %tmp155.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp143.i.i ; <i32*> [#uses=1] store i32 %tmp154.i.i, i32* %tmp155.i.i - %tmp159.i.i = getelementptr [2 x i32]* @counter, i32 0, i32 %i_addr.3210.0.i.i ; <i32*> [#uses=2] - %tmp160.i.i = load i32* %tmp159.i.i ; <i32> [#uses=1] + %tmp159.i.i = getelementptr [2 x i32], [2 x i32]* @counter, i32 0, i32 %i_addr.3210.0.i.i ; <i32*> [#uses=2] + %tmp160.i.i = load i32, i32* %tmp159.i.i ; <i32> [#uses=1] %tmp161.i.i = add i32 %tmp160.i.i, 1 ; <i32> [#uses=1] store i32 %tmp161.i.i, i32* %tmp159.i.i %tmp166.i.i = add i32 %i_addr.3210.0.i.i, 1 ; <i32> [#uses=2] - %tmp168.i.i = load i32* @numi ; <i32> [#uses=1] + %tmp168.i.i = load i32, i32* @numi ; <i32> [#uses=1] icmp slt i32 %tmp166.i.i, %tmp168.i.i ; <i1>:0 [#uses=1] br i1 %0, label %bb115.i.i.bb115.i.i_crit_edge, label %bb115.i.i.bb170.i.i_crit_edge.exitStub } diff --git a/test/CodeGen/ARM/coalesce-dbgvalue.ll b/test/CodeGen/ARM/coalesce-dbgvalue.ll index 4e5fb5e5c60f..cd2ab257207a 100644 --- a/test/CodeGen/ARM/coalesce-dbgvalue.ll +++ b/test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -27,11 +27,11 @@ for.cond1: ; preds = %for.end9, %for.cond for.body2: ; preds = %for.cond1 store i32 %storemerge11, i32* @b, align 4, !dbg !26 - tail call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !28 - %0 = load i64* @a, align 8, !dbg !29 + tail call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !11, metadata !DIExpression()), !dbg !28 + %0 = load i64, i64* @a, align 8, !dbg !29 %xor = xor i64 %0, %e.1.ph, !dbg !29 %conv3 = trunc i64 %xor to i32, !dbg !29 - tail call void @llvm.dbg.value(metadata i32 %conv3, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !29 + tail call void @llvm.dbg.value(metadata i32 %conv3, i64 0, metadata !10, metadata !DIExpression()), !dbg !29 %tobool4 = icmp eq i32 %conv3, 0, !dbg !29 br i1 %tobool4, label %land.end, label %land.rhs, !dbg !29 @@ -44,7 +44,7 @@ land.end: ; preds = %land.rhs, %for.body %1 = phi i1 [ false, %for.body2 ], [ %tobool5, %land.rhs ] %land.ext = zext i1 %1 to i32 %call6 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32, i32*)*)(i32 %land.ext, i32* null) #3 - %2 = load i32* @b, align 4, !dbg !26 + %2 = load i32, i32* @b, align 4, !dbg !26 %inc8 = add nsw i32 %2, 1, !dbg !26 %phitmp = and i64 %xor, 4294967295, !dbg !26 br label %for.cond1.outer, !dbg !26 @@ -52,7 +52,7 @@ land.end: ; preds = %land.rhs, %for.body for.cond1.outer: ; preds = %land.end, %for.cond1.preheader %storemerge11.ph = phi i32 [ %inc8, %land.end ], [ 0, %for.cond1.preheader ] %e.1.ph = phi i64 [ %phitmp, %land.end ], [ 0, %for.cond1.preheader ] - %3 = load i32* @d, align 4, !dbg !31 + %3 = load i32, i32* @d, align 4, !dbg !31 %tobool10 = icmp eq i32 %3, 0, !dbg !31 br label %for.cond1 @@ -79,33 +79,33 @@ attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = !{!"0x11\0012\00clang version 3.4 (trunk 182024) (llvm/trunk 182023)\001\00\000\00\000", !1, !2, !2, !3, !15, !2} ; [ DW_TAG_compile_unit ] [/d/b/pr16110.c] [DW_LANG_C99] -!1 = !{!"pr16110.c", !"/d/b"} +!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 182024) (llvm/trunk 182023)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !15, imports: !2) +!1 = !DIFile(filename: "pr16110.c", directory: "/d/b") !2 = !{} !3 = !{!4} -!4 = !{!"0x2e\00pr16110\00pr16110\00\007\000\001\000\006\000\001\007", !1, !5, !6, null, i32 ()* @pr16110, null, null, !9} ; [ DW_TAG_subprogram ] [line 7] [def] [pr16110] -!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/d/b/pr16110.c] -!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !DISubprogram(name: "pr16110", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 7, file: !1, scope: !5, type: !6, function: i32 ()* @pr16110, variables: !9) +!5 = !DIFile(filename: "pr16110.c", directory: "/d/b") +!6 = !DISubroutineType(types: !7) !7 = !{!8} -!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !9 = !{!10, !11} -!10 = !{!"0x100\00e\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [e] [line 8] -!11 = !{!"0x100\00f\0013\000", !12, !5, !14} ; [ DW_TAG_auto_variable ] [f] [line 13] -!12 = !{!"0xb\0012\000\002", !1, !13} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] -!13 = !{!"0xb\0012\000\001", !1, !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] -!14 = !{!"0xf\00\000\0032\0032\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int] +!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 8, scope: !4, file: !5, type: !8) +!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f", line: 13, scope: !12, file: !5, type: !14) +!12 = distinct !DILexicalBlock(line: 12, column: 0, file: !1, scope: !13) +!13 = distinct !DILexicalBlock(line: 12, column: 0, file: !1, scope: !4) +!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !8) !15 = !{!16, !18, !19, !20} -!16 = !{!"0x34\00a\00a\00\001\000\001", null, !5, !17, i64* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def] -!17 = !{!"0x24\00long long int\000\0064\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [long long int] [line 0, size 64, align 32, offset 0, enc DW_ATE_signed] -!18 = !{!"0x34\00b\00b\00\002\000\001", null, !5, !8, i32* @b, null} ; [ DW_TAG_variable ] [b] [line 2] [def] -!19 = !{!"0x34\00c\00c\00\003\000\001", null, !5, !8, i32* @c, null} ; [ DW_TAG_variable ] [c] [line 3] [def] -!20 = !{!"0x34\00d\00d\00\004\000\001", null, !5, !8, i32* @d, null} ; [ DW_TAG_variable ] [d] [line 4] [def] -!21 = !MDLocation(line: 10, scope: !22) -!22 = !{!"0xb\0010\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] -!26 = !MDLocation(line: 12, scope: !13) +!16 = !DIGlobalVariable(name: "a", line: 1, isLocal: false, isDefinition: true, scope: null, file: !5, type: !17, variable: i64* @a) +!17 = !DIBasicType(tag: DW_TAG_base_type, name: "long long int", size: 64, align: 32, encoding: DW_ATE_signed) +!18 = !DIGlobalVariable(name: "b", line: 2, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @b) +!19 = !DIGlobalVariable(name: "c", line: 3, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @c) +!20 = !DIGlobalVariable(name: "d", line: 4, isLocal: false, isDefinition: true, scope: null, file: !5, type: !8, variable: i32* @d) +!21 = !DILocation(line: 10, scope: !22) +!22 = distinct !DILexicalBlock(line: 10, column: 0, file: !1, scope: !4) +!26 = !DILocation(line: 12, scope: !13) !27 = !{i32* null} -!28 = !MDLocation(line: 13, scope: !12) -!29 = !MDLocation(line: 14, scope: !12) -!31 = !MDLocation(line: 16, scope: !4) -!32 = !MDLocation(line: 18, scope: !4) -!33 = !{i32 1, !"Debug Info Version", i32 2} +!28 = !DILocation(line: 13, scope: !12) +!29 = !DILocation(line: 14, scope: !12) +!31 = !DILocation(line: 16, scope: !4) +!32 = !DILocation(line: 18, scope: !4) +!33 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll index e7bd5f41bb4b..72fefeacfc5b 100644 --- a/test/CodeGen/ARM/coalesce-subregs.ll +++ b/test/CodeGen/ARM/coalesce-subregs.ll @@ -16,7 +16,7 @@ entry: %0 = bitcast float* %p to i8* %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4) %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1 - %add.ptr = getelementptr inbounds float* %p, i32 8 + %add.ptr = getelementptr inbounds float, float* %p, i32 8 %1 = bitcast float* %add.ptr to i8* tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4) ret void @@ -29,7 +29,7 @@ entry: %0 = bitcast float* %p to i8* %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4) %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1 - %add.ptr = getelementptr inbounds float* %p, i32 8 + %add.ptr = getelementptr inbounds float, float* %p, i32 8 %1 = bitcast float* %add.ptr to i8* %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4) %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0 @@ -50,7 +50,7 @@ do.body: ; preds = %do.body, %entry %qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ] %c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ] %p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ] - %add.ptr = getelementptr inbounds float* %p.addr.0, i32 8 + %add.ptr = getelementptr inbounds float, float* %p.addr.0, i32 8 %1 = bitcast float* %add.ptr to i8* %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4) %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0 @@ -85,29 +85,29 @@ declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounw ; CHECK-NOT: vorr define void @f3(float* %p, float* %q) nounwind ssp { entry: - %arrayidx = getelementptr inbounds float* %p, i32 3 - %0 = load float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, float* %p, i32 3 + %0 = load float, float* %arrayidx, align 4 %vecins = insertelement <2 x float> undef, float %0, i32 1 %tobool = icmp eq float* %q, null br i1 %tobool, label %if.else, label %if.then if.then: ; preds = %entry - %1 = load float* %q, align 4 - %arrayidx2 = getelementptr inbounds float* %q, i32 1 - %2 = load float* %arrayidx2, align 4 + %1 = load float, float* %q, align 4 + %arrayidx2 = getelementptr inbounds float, float* %q, i32 1 + %2 = load float, float* %arrayidx2, align 4 %add = fadd float %1, %2 %vecins3 = insertelement <2 x float> %vecins, float %add, i32 0 br label %if.end if.else: ; preds = %entry - %arrayidx4 = getelementptr inbounds float* %p, i32 2 - %3 = load float* %arrayidx4, align 4 + %arrayidx4 = getelementptr inbounds float, float* %p, i32 2 + %3 = load float, float* %arrayidx4, align 4 %vecins5 = insertelement <2 x float> %vecins, float %3, i32 0 br label %if.end if.end: ; preds = %if.else, %if.then %x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ] - %add.ptr = getelementptr inbounds float* %p, i32 4 + %add.ptr = getelementptr inbounds float, float* %p, i32 4 %4 = bitcast float* %add.ptr to i8* tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4) ret void @@ -129,9 +129,9 @@ entry: br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - %1 = load float* %q, align 4 - %arrayidx1 = getelementptr inbounds float* %q, i32 1 - %2 = load float* %arrayidx1, align 4 + %1 = load float, float* %q, align 4 + %arrayidx1 = getelementptr inbounds float, float* %q, i32 1 + %2 = load float, float* %arrayidx1, align 4 %add = fadd float %1, %2 %vecins = insertelement <2 x float> %vld1, float %add, i32 1 br label %if.end @@ -164,13 +164,13 @@ entry: br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - %arrayidx = getelementptr inbounds float* %q, i32 1 - %1 = load float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, float* %q, i32 1 + %1 = load float, float* %arrayidx, align 4 %add4 = fadd float %vecext, %1 - %2 = load float* %q, align 4 + %2 = load float, float* %q, align 4 %add6 = fadd float %vecext1, %2 - %arrayidx7 = getelementptr inbounds float* %q, i32 2 - %3 = load float* %arrayidx7, align 4 + %arrayidx7 = getelementptr inbounds float, float* %q, i32 2 + %3 = load float, float* %arrayidx7, align 4 %add8 = fadd float %vecext2, %3 br label %if.end @@ -231,7 +231,7 @@ bb3: ; preds = %bb12, %bb br i1 undef, label %bb10, label %bb12 bb10: ; preds = %bb3 - %tmp11 = load <4 x float>* undef, align 8 + %tmp11 = load <4 x float>, <4 x float>* undef, align 8 br label %bb12 bb12: ; preds = %bb10, %bb3 @@ -293,7 +293,6 @@ bb: ; CHECK: adjustCopiesBackFrom ; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom ; is tempted to remove it. -; CHECK: %if.else3 ; CHECK: vorr d define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret %agg.result, <2 x i64> %in) { entry: @@ -334,7 +333,7 @@ for.body: ; preds = %for.end, %entry br i1 undef, label %for.body29, label %for.end for.body29: ; preds = %for.body29, %for.body - %0 = load <2 x double>* null, align 1 + %0 = load <2 x double>, <2 x double>* null, align 1 %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer %mul41 = fmul <2 x double> undef, %splat40 %add42 = fadd <2 x double> undef, %mul41 diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll index 70d85c91c8ca..bf5cf52d8b54 100644 --- a/test/CodeGen/ARM/code-placement.ll +++ b/test/CodeGen/ARM/code-placement.ll @@ -18,8 +18,8 @@ bb: ; CHECK: bx lr %list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ] %next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ] - %1 = getelementptr inbounds %struct.list_head* %list_addr.05, i32 0, i32 0 - %2 = load %struct.list_head** %1, align 4 + %1 = getelementptr inbounds %struct.list_head, %struct.list_head* %list_addr.05, i32 0, i32 0 + %2 = load %struct.list_head*, %struct.list_head** %1, align 4 store %struct.list_head* %next.04, %struct.list_head** %1, align 4 %3 = icmp eq %struct.list_head* %2, null br i1 %3, label %bb2, label %bb @@ -45,8 +45,8 @@ bb1: ; preds = %bb2.preheader, %bb1 %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2] %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1] %tmp17 = sub i32 %i.07, %indvar ; <i32> [#uses=1] - %scevgep = getelementptr i32* %src, i32 %tmp17 ; <i32*> [#uses=1] - %1 = load i32* %scevgep, align 4 ; <i32> [#uses=1] + %scevgep = getelementptr i32, i32* %src, i32 %tmp17 ; <i32*> [#uses=1] + %1 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1] %2 = add nsw i32 %1, %sum.08 ; <i32> [#uses=2] %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] %exitcond = icmp eq i32 %indvar.next, %size ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/combine-movc-sub.ll b/test/CodeGen/ARM/combine-movc-sub.ll new file mode 100644 index 000000000000..6a5f7bdd38e9 --- /dev/null +++ b/test/CodeGen/ARM/combine-movc-sub.ll @@ -0,0 +1,63 @@ +; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-unknown" + +; The subtract instruction %3 will be optimized (combined and predicated) with the select +; inside the loop. In this case, the kill flag on the subtract should be removed or else +; it will fail verification. + +%struct.PROOFSEARCH_HELP = type { %struct.LIST_HELP*, %struct.LIST_HELP*, %struct.LIST_HELP*, %struct.LIST_HELP*, %struct.SHARED_INDEX_NODE*, %struct.LIST_HELP*, %struct.SHARED_INDEX_NODE*, %struct.LIST_HELP*, %struct.SORTTHEORY_HELP*, %struct.SORTTHEORY_HELP*, %struct.SORTTHEORY_HELP*, %struct.SHARED_INDEX_NODE*, %struct.LIST_HELP*, i32*, i32*, %struct.LIST_HELP*, i32, i32, i32, i32, i32, i32, i32, i32 } +%struct.SORTTHEORY_HELP = type { %struct.st*, [4000 x %struct.NODE_HELP*], %struct.LIST_HELP*, %struct.LIST_HELP*, i32 } +%struct.st = type { %struct.subst*, %struct.LIST_HELP*, %struct.LIST_HELP*, i16, i16 } +%struct.subst = type { %struct.subst*, i32, %struct.term* } +%struct.term = type { i32, %union.anon, %struct.LIST_HELP*, i32, i32 } +%union.anon = type { %struct.LIST_HELP* } +%struct.NODE_HELP = type { %struct.LIST_HELP*, i32, i32, i32, %struct.LIST_HELP*, i32 } +%struct.SHARED_INDEX_NODE = type { %struct.st*, [3001 x %struct.term*], [4000 x %struct.term*], i32 } +%struct.LIST_HELP = type { %struct.LIST_HELP*, i8* } +%struct.CLAUSE_HELP = type { i32, i32, i32, i32, i32*, i32, %struct.LIST_HELP*, %struct.LIST_HELP*, i32, i32, %struct.LITERAL_HELP**, i32, i32, i32, i32 } +%struct.LITERAL_HELP = type { i32, i32, i32, %struct.CLAUSE_HELP*, %struct.term* } + +declare void @foo(%struct.PROOFSEARCH_HELP*, %struct.CLAUSE_HELP*) + +; CHECK-LABEL: @test +; CHECK: it +; CHECK-NEXT: sub + +define hidden fastcc %struct.LIST_HELP* @test(%struct.PROOFSEARCH_HELP* %Search, %struct.LIST_HELP* %ClauseList, i32 %Level, %struct.LIST_HELP** nocapture %New) { +entry: + %cmp4.i.i = icmp ugt i32 %Level, 31 + %0 = add i32 %Level, -32 + %1 = lshr i32 %0, 5 + %2 = shl nuw i32 %1, 5 + %3 = sub i32 %0, %2 + %4 = add nuw nsw i32 %1, 1 + br label %for.body + +for.body: ; preds = %for.inc, %entry + %Scan.038 = phi %struct.LIST_HELP* [ %ClauseList, %entry ], [ %9, %for.inc ] + %car.i33 = getelementptr inbounds %struct.LIST_HELP, %struct.LIST_HELP* %Scan.038, i32 0, i32 1 + %5 = bitcast i8** %car.i33 to %struct.CLAUSE_HELP** + %6 = load %struct.CLAUSE_HELP*, %struct.CLAUSE_HELP** %5, align 4 + %. = add i32 %4, 10 + %.Level = select i1 %cmp4.i.i, i32 %3, i32 %Level + %splitfield.i = getelementptr inbounds %struct.CLAUSE_HELP, %struct.CLAUSE_HELP* %6, i32 0, i32 4 + %7 = load i32*, i32** %splitfield.i, align 4 + %arrayidx.i = getelementptr inbounds i32, i32* %7, i32 %. + %8 = load i32, i32* %arrayidx.i, align 4 + %shl.i = shl i32 1, %.Level + %and.i = and i32 %8, %shl.i + %cmp4.i = icmp eq i32 %and.i, 0 + br i1 %cmp4.i, label %for.inc, label %if.then + +if.then: ; preds = %for.body + tail call void @foo(%struct.PROOFSEARCH_HELP* %Search, %struct.CLAUSE_HELP* %6) + store i8* null, i8** %car.i33, align 4 + br label %for.inc + +for.inc: ; preds = %if.then, %for.body + %cdr.i = getelementptr inbounds %struct.LIST_HELP, %struct.LIST_HELP* %Scan.038, i32 0, i32 0 + %9 = load %struct.LIST_HELP*, %struct.LIST_HELP** %cdr.i, align 4 + br label %for.body +} diff --git a/test/CodeGen/ARM/commute-movcc.ll b/test/CodeGen/ARM/commute-movcc.ll index fbc25b45b6ff..2978d317ad78 100644 --- a/test/CodeGen/ARM/commute-movcc.ll +++ b/test/CodeGen/ARM/commute-movcc.ll @@ -31,8 +31,8 @@ for.body: ; preds = %entry, %if.end8 %i.012 = phi i32 [ 0, %entry ], [ %inc, %if.end8 ] %BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ] %BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ] - %arrayidx = getelementptr inbounds i32* %a, i32 %i.012 - %0 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.012 + %0 = load i32, i32* %arrayidx, align 4 %mul = mul i32 %0, %0 %sub = add nsw i32 %i.012, -5 %cmp2 = icmp eq i32 %sub, %Pref diff --git a/test/CodeGen/ARM/compare-call.ll b/test/CodeGen/ARM/compare-call.ll index 323eb1f2dd3c..f45ed73adb71 100644 --- a/test/CodeGen/ARM/compare-call.ll +++ b/test/CodeGen/ARM/compare-call.ll @@ -2,14 +2,14 @@ define void @test3(float* %glob, i32 %X) { entry: - %tmp = load float* %glob ; <float> [#uses=1] - %tmp2 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1] - %tmp3 = load float* %tmp2 ; <float> [#uses=1] + %tmp = load float, float* %glob ; <float> [#uses=1] + %tmp2 = getelementptr float, float* %glob, i32 2 ; <float*> [#uses=1] + %tmp3 = load float, float* %tmp2 ; <float> [#uses=1] %tmp.upgrd.1 = fcmp ogt float %tmp, %tmp3 ; <i1> [#uses=1] br i1 %tmp.upgrd.1, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp.upgrd.2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp.upgrd.2 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/ARM/copy-paired-reg.ll b/test/CodeGen/ARM/copy-paired-reg.ll index 17a4461c682b..453fac4b1504 100644 --- a/test/CodeGen/ARM/copy-paired-reg.ll +++ b/test/CodeGen/ARM/copy-paired-reg.ll @@ -11,7 +11,7 @@ define void @f() { store atomic i64 0, i64* %c seq_cst, align 8 store atomic i64 0, i64* %d seq_cst, align 8 - %e = load atomic i64* %d seq_cst, align 8 + %e = load atomic i64, i64* %d seq_cst, align 8 ret void } diff --git a/test/CodeGen/ARM/crash-O0.ll b/test/CodeGen/ARM/crash-O0.ll index 8855bb99aaf9..f92af999be51 100644 --- a/test/CodeGen/ARM/crash-O0.ll +++ b/test/CodeGen/ARM/crash-O0.ll @@ -21,8 +21,8 @@ entry: %letter = alloca i8 ; <i8*> [#uses=0] %prodvers = alloca [256 x i8] ; <[256 x i8]*> [#uses=1] %buildver = alloca [256 x i8] ; <[256 x i8]*> [#uses=0] - call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* getelementptr inbounds ([256 x i8], [256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) %prodvers2 = bitcast [256 x i8]* %prodvers to i8* ; <i8*> [#uses=1] - call void @llvm.memcpy.p0i8.p0i8.i32(i8* %prodvers2, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %prodvers2, i8* getelementptr inbounds ([256 x i8], [256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) unreachable } diff --git a/test/CodeGen/ARM/crash-greedy-v6.ll b/test/CodeGen/ARM/crash-greedy-v6.ll index e165dbdf087a..287c081ac5ec 100644 --- a/test/CodeGen/ARM/crash-greedy-v6.ll +++ b/test/CodeGen/ARM/crash-greedy-v6.ll @@ -32,13 +32,13 @@ for.body: ; preds = %for.body, %for.body ; SOURCE-SCHED: cmp ; SOURCE-SCHED: bne %i.031 = phi i32 [ 0, %for.body.lr.ph ], [ %0, %for.body ] - %arrayidx11 = getelementptr float* %t, i32 %i.031 - %arrayidx15 = getelementptr float* %u, i32 %i.031 - %arrayidx19 = getelementptr i8* %red, i32 %i.031 - %arrayidx22 = getelementptr i8* %green, i32 %i.031 - %arrayidx25 = getelementptr i8* %blue, i32 %i.031 - %arrayidx28 = getelementptr i8* %alpha, i32 %i.031 - %tmp12 = load float* %arrayidx11, align 4 + %arrayidx11 = getelementptr float, float* %t, i32 %i.031 + %arrayidx15 = getelementptr float, float* %u, i32 %i.031 + %arrayidx19 = getelementptr i8, i8* %red, i32 %i.031 + %arrayidx22 = getelementptr i8, i8* %green, i32 %i.031 + %arrayidx25 = getelementptr i8, i8* %blue, i32 %i.031 + %arrayidx28 = getelementptr i8, i8* %alpha, i32 %i.031 + %tmp12 = load float, float* %arrayidx11, align 4 tail call fastcc void @sample_3d_nearest(i8* %tObj, i8* undef, float undef, float %tmp12, float undef, i8* %arrayidx19, i8* %arrayidx22, i8* %arrayidx25, i8* %arrayidx28) %0 = add i32 %i.031, 1 %exitcond = icmp eq i32 %0, %n diff --git a/test/CodeGen/ARM/crash.ll b/test/CodeGen/ARM/crash.ll index 4e3e2010b07a..3b01d8113b9c 100644 --- a/test/CodeGen/ARM/crash.ll +++ b/test/CodeGen/ARM/crash.ll @@ -5,7 +5,7 @@ define void @func() nounwind { entry: - %tmp = load i32* undef, align 4 + %tmp = load i32, i32* undef, align 4 br label %bb1 bb1: @@ -17,7 +17,7 @@ bb1: bb2: %tmp120 = add i32 %tmp119, 0 - %scevgep810.i = getelementptr %struct.foo* null, i32 %tmp120, i32 1 + %scevgep810.i = getelementptr %struct.foo, %struct.foo* null, i32 %tmp120, i32 1 store i32 undef, i32* %scevgep810.i, align 4 br i1 undef, label %bb2, label %bb3 diff --git a/test/CodeGen/ARM/cse-call.ll b/test/CodeGen/ARM/cse-call.ll index eff5de5a2428..4e61a3495b80 100644 --- a/test/CodeGen/ARM/cse-call.ll +++ b/test/CodeGen/ARM/cse-call.ll @@ -23,8 +23,8 @@ while.body37: ; preds = %while.body37, %entr br i1 false, label %while.end42, label %while.body37 while.end42: ; preds = %while.body37, %entry - %. = select i1 undef, i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man1, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man2, i32 0, i32 0) - %.92 = select i1 undef, i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man2, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8]* @F_floatmul.man1, i32 0, i32 0) + %. = select i1 undef, i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man1, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man2, i32 0, i32 0) + %.92 = select i1 undef, i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man2, i32 0, i32 0), i8* getelementptr inbounds ([200 x i8], [200 x i8]* @F_floatmul.man1, i32 0, i32 0) tail call void bitcast (void (...)* @S_trimzeros to void (i8*)*)(i8* %.92) nounwind %call47 = tail call i32 @strlen(i8* %.) nounwind unreachable diff --git a/test/CodeGen/ARM/cse-ldrlit.ll b/test/CodeGen/ARM/cse-ldrlit.ll index 3f5d4c2e3c29..4f369d0a78ea 100644 --- a/test/CodeGen/ARM/cse-ldrlit.ll +++ b/test/CodeGen/ARM/cse-ldrlit.ll @@ -9,11 +9,11 @@ declare void @bar(i32*) define void @foo() { - %flag = load i32* getelementptr inbounds([16 x i32]* @var, i32 0, i32 1) + %flag = load i32, i32* getelementptr inbounds([16 x i32], [16 x i32]* @var, i32 0, i32 1) %tst = icmp eq i32 %flag, 0 br i1 %tst, label %true, label %false true: - tail call void @bar(i32* getelementptr inbounds([16 x i32]* @var, i32 0, i32 4)) + tail call void @bar(i32* getelementptr inbounds([16 x i32], [16 x i32]* @var, i32 0, i32 4)) ret void false: ret void diff --git a/test/CodeGen/ARM/cse-libcalls.ll b/test/CodeGen/ARM/cse-libcalls.ll index 4f5b7592c844..1255ec5a78f1 100644 --- a/test/CodeGen/ARM/cse-libcalls.ll +++ b/test/CodeGen/ARM/cse-libcalls.ll @@ -10,7 +10,7 @@ target triple = "i386-apple-darwin8" define double @u_f_nonbon(double %lambda) nounwind { entry: - %tmp19.i.i = load double* null, align 4 ; <double> [#uses=2] + %tmp19.i.i = load double, double* null, align 4 ; <double> [#uses=2] %tmp6.i = fcmp olt double %tmp19.i.i, 1.000000e+00 ; <i1> [#uses=1] %dielectric.0.i = select i1 %tmp6.i, double 1.000000e+00, double %tmp19.i.i ; <double> [#uses=1] %tmp10.i4 = fdiv double 0x4074C2D71F36262D, %dielectric.0.i ; <double> [#uses=1] diff --git a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll index 8950abdef6a3..8b7153503b1f 100644 --- a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll +++ b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll @@ -2,10 +2,10 @@ ; CHECK-LABEL: f: define float @f(<4 x i16>* nocapture %in) { - ; CHECK: vldr + ; CHECK: vld1 ; CHECK: vmovl.u16 ; CHECK-NOT: vand - %1 = load <4 x i16>* %in + %1 = load <4 x i16>, <4 x i16>* %in ; CHECK: vcvt.f32.u32 %2 = uitofp <4 x i16> %1 to <4 x float> %3 = extractelement <4 x float> %2, i32 0 @@ -21,7 +21,7 @@ define float @f(<4 x i16>* nocapture %in) { define float @g(<4 x i16>* nocapture %in) { ; CHECK: vldr - %1 = load <4 x i16>* %in + %1 = load <4 x i16>, <4 x i16>* %in ; CHECK-NOT: uxth %2 = extractelement <4 x i16> %1, i32 0 ; CHECK: vcvt.f32.u32 diff --git a/test/CodeGen/ARM/darwin-section-order.ll b/test/CodeGen/ARM/darwin-section-order.ll deleted file mode 100644 index 701028c0a537..000000000000 --- a/test/CodeGen/ARM/darwin-section-order.ll +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s - -; CHECK: .section __TEXT,__text,regular,pure_instructions -; CHECK: .section __TEXT,myprecious -; CHECK: .section __TEXT,__textcoal_nt,coalesced,pure_instructions -; CHECK: .section __TEXT,__const_coal,coalesced -; CHECK: .section __TEXT,__picsymbolstub4,symbol_stubs,none,16 -; CHECK: .section __TEXT,__StaticInit,regular,pure_instructions - - -define void @normal() nounwind readnone { -; CHECK: .section __TEXT,__text,regular,pure_instructions -; CHECK: _normal: - ret void -} - -define void @special() nounwind readnone section "__TEXT,myprecious" { -; CHECK: .section __TEXT,myprecious -; CHECK: _special: - ret void -} diff --git a/test/CodeGen/ARM/debug-frame-large-stack.ll b/test/CodeGen/ARM/debug-frame-large-stack.ll index 1addf639bfe4..1f814e70d543 100644 --- a/test/CodeGen/ARM/debug-frame-large-stack.ll +++ b/test/CodeGen/ARM/debug-frame-large-stack.ll @@ -48,7 +48,7 @@ define i32 @test3() { %tmp = alloca i32, align 4 %a = alloca [805306369 x i8], align 16 store i32 0, i32* %tmp - %tmp1 = load i32* %tmp + %tmp1 = load i32, i32* %tmp ret i32 %tmp1 } diff --git a/test/CodeGen/ARM/debug-frame-vararg.ll b/test/CodeGen/ARM/debug-frame-vararg.ll index 05521d80646c..19e55fe02354 100644 --- a/test/CodeGen/ARM/debug-frame-vararg.ll +++ b/test/CodeGen/ARM/debug-frame-vararg.ll @@ -25,90 +25,88 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} -!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99] -!1 = !{!"var.c", !"/tmp"} +!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!1 = !DIFile(filename: "var.c", directory: "/tmp") !2 = !{} !3 = !{!4} -!4 = !{!"0x2e\00sum\00sum\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, i32 (i32, ...)* @sum, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum] -!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/var.c] -!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !DISubprogram(name: "sum", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 (i32, ...)* @sum, variables: !2) +!5 = !DIFile(filename: "var.c", directory: "/tmp") +!6 = !DISubroutineType(types: !7) !7 = !{!8, !8} -!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !9 = !{i32 2, !"Dwarf Version", i32 4} -!10 = !{i32 1, !"Debug Info Version", i32 2} +!10 = !{i32 1, !"Debug Info Version", i32 3} !11 = !{!"clang version 3.5 "} -!12 = !{!"0x101\00count\0016777221\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [count] [line 5] -!13 = !MDLocation(line: 5, scope: !4) -!14 = !{!"0x100\00vl\006\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [vl] [line 6] -!15 = !{!"0x16\00va_list\0030\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list] -!16 = !{!"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", !"/tmp"} -!17 = !{!"0x16\00__builtin_va_list\006\000\000\000\000", !1, null, !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list] -!18 = !{!"0x13\00__va_list\006\0032\0032\000\000\000", !1, null, null, !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ] +!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8) +!13 = !DILocation(line: 5, scope: !4) +!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vl", line: 6, scope: !4, file: !5, type: !15) +!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "va_list", line: 30, file: !16, baseType: !17) +!16 = !DIFile(filename: "/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", directory: "/tmp") +!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__builtin_va_list", line: 6, file: !1, baseType: !18) +!18 = !DICompositeType(tag: DW_TAG_structure_type, name: "__va_list", line: 6, size: 32, align: 32, file: !1, elements: !19) !19 = !{!20} -!20 = !{!"0xd\00__ap\006\0032\0032\000\000", !1, !18, !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ] -!21 = !{!"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ] -!22 = !MDLocation(line: 6, scope: !4) -!23 = !MDLocation(line: 7, scope: !4) -!24 = !{!"0x100\00sum\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [sum] [line 8] -!25 = !MDLocation(line: 8, scope: !4) -!26 = !{!"0x100\00i\009\000", !27, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 9] -!27 = !{!"0xb\009\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!28 = !MDLocation(line: 9, scope: !27) -!29 = !MDLocation(line: 10, scope: !30) -!30 = !{!"0xb\009\000\001", !1, !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!31 = !MDLocation(line: 11, scope: !30) -!32 = !MDLocation(line: 12, scope: !4) -!33 = !MDLocation(line: 13, scope: !4) +!20 = !DIDerivedType(tag: DW_TAG_member, name: "__ap", line: 6, size: 32, align: 32, file: !1, scope: !18, baseType: !21) +!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: null) +!22 = !DILocation(line: 6, scope: !4) +!23 = !DILocation(line: 7, scope: !4) +!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "sum", line: 8, scope: !4, file: !5, type: !8) +!25 = !DILocation(line: 8, scope: !4) +!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 9, scope: !27, file: !5, type: !8) +!27 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !4) +!28 = !DILocation(line: 9, scope: !27) +!29 = !DILocation(line: 10, scope: !30) +!30 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !27) +!31 = !DILocation(line: 11, scope: !30) +!32 = !DILocation(line: 12, scope: !4) +!33 = !DILocation(line: 13, scope: !4) ; CHECK-FP-LABEL: sum ; CHECK-FP: .cfi_startproc -; CHECK-FP: sub sp, sp, #16 -; CHECK-FP: .cfi_def_cfa_offset 16 +; CHECK-FP: sub sp, sp, #12 +; CHECK-FP: .cfi_def_cfa_offset 12 ; CHECK-FP: push {r4, lr} +; CHECK-FP: .cfi_def_cfa_offset 20 +; CHECK-FP: .cfi_offset lr, -16 +; CHECK-FP: .cfi_offset r4, -20 +; CHECK-FP: sub sp, sp, #4 ; CHECK-FP: .cfi_def_cfa_offset 24 -; CHECK-FP: .cfi_offset lr, -20 -; CHECK-FP: .cfi_offset r4, -24 -; CHECK-FP: sub sp, sp, #8 -; CHECK-FP: .cfi_def_cfa_offset 32 ; CHECK-FP-ELIM-LABEL: sum ; CHECK-FP-ELIM: .cfi_startproc -; CHECK-FP-ELIM: sub sp, sp, #16 -; CHECK-FP-ELIM: .cfi_def_cfa_offset 16 +; CHECK-FP-ELIM: sub sp, sp, #12 +; CHECK-FP-ELIM: .cfi_def_cfa_offset 12 ; CHECK-FP-ELIM: push {r4, r10, r11, lr} -; CHECK-FP-ELIM: .cfi_def_cfa_offset 32 -; CHECK-FP-ELIM: .cfi_offset lr, -20 -; CHECK-FP-ELIM: .cfi_offset r11, -24 -; CHECK-FP-ELIM: .cfi_offset r10, -28 -; CHECK-FP-ELIM: .cfi_offset r4, -32 +; CHECK-FP-ELIM: .cfi_def_cfa_offset 28 +; CHECK-FP-ELIM: .cfi_offset lr, -16 +; CHECK-FP-ELIM: .cfi_offset r11, -20 +; CHECK-FP-ELIM: .cfi_offset r10, -24 +; CHECK-FP-ELIM: .cfi_offset r4, -28 ; CHECK-FP-ELIM: add r11, sp, #8 -; CHECK-FP-ELIM: .cfi_def_cfa r11, 24 +; CHECK-FP-ELIM: .cfi_def_cfa r11, 20 ; CHECK-THUMB-FP-LABEL: sum ; CHECK-THUMB-FP: .cfi_startproc -; CHECK-THUMB-FP: sub sp, #16 -; CHECK-THUMB-FP: .cfi_def_cfa_offset 16 -; CHECK-THUMB-FP: push {r4, r5, r7, lr} -; CHECK-THUMB-FP: .cfi_def_cfa_offset 32 -; CHECK-THUMB-FP: .cfi_offset lr, -20 -; CHECK-THUMB-FP: .cfi_offset r7, -24 -; CHECK-THUMB-FP: .cfi_offset r5, -28 -; CHECK-THUMB-FP: .cfi_offset r4, -32 -; CHECK-THUMB-FP: sub sp, #8 -; CHECK-THUMB-FP: .cfi_def_cfa_offset 40 +; CHECK-THUMB-FP: sub sp, #12 +; CHECK-THUMB-FP: .cfi_def_cfa_offset 12 +; CHECK-THUMB-FP: push {r4, lr} +; CHECK-THUMB-FP: .cfi_def_cfa_offset 20 +; CHECK-THUMB-FP: .cfi_offset lr, -16 +; CHECK-THUMB-FP: .cfi_offset r4, -20 +; CHECK-THUMB-FP: sub sp, #4 +; CHECK-THUMB-FP: .cfi_def_cfa_offset 24 ; CHECK-THUMB-FP-ELIM-LABEL: sum ; CHECK-THUMB-FP-ELIM: .cfi_startproc -; CHECK-THUMB-FP-ELIM: sub sp, #16 -; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 16 -; CHECK-THUMB-FP-ELIM: push {r4, r5, r7, lr} -; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 32 -; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -20 -; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -24 -; CHECK-THUMB-FP-ELIM: .cfi_offset r5, -28 -; CHECK-THUMB-FP-ELIM: .cfi_offset r4, -32 +; CHECK-THUMB-FP-ELIM: sub sp, #12 +; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 12 +; CHECK-THUMB-FP-ELIM: push {r4, r6, r7, lr} +; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 28 +; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -16 +; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -20 +; CHECK-THUMB-FP-ELIM: .cfi_offset r6, -24 +; CHECK-THUMB-FP-ELIM: .cfi_offset r4, -28 ; CHECK-THUMB-FP-ELIM: add r7, sp, #8 -; CHECK-THUMB-FP-ELIM: .cfi_def_cfa r7, 24 +; CHECK-THUMB-FP-ELIM: .cfi_def_cfa r7, 20 define i32 @sum(i32 %count, ...) { entry: @@ -120,11 +118,11 @@ entry: for.body: ; preds = %entry, %for.body %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %ap.cur = load i8** %vl, align 4 - %ap.next = getelementptr i8* %ap.cur, i32 4 + %ap.cur = load i8*, i8** %vl, align 4 + %ap.next = getelementptr i8, i8* %ap.cur, i32 4 store i8* %ap.next, i8** %vl, align 4 %0 = bitcast i8* %ap.cur to i32* - %1 = load i32* %0, align 4 + %1 = load i32, i32* %0, align 4 %call = call i32 @foo(i32 %1) #1 %inc = add nsw i32 %i.05, 1 %exitcond = icmp eq i32 %inc, %count diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll index 16e2c4c59f96..134829254e3f 100644 --- a/test/CodeGen/ARM/debug-frame.ll +++ b/test/CodeGen/ARM/debug-frame.ll @@ -128,41 +128,41 @@ declare void @_ZSt9terminatev() !llvm.module.flags = !{!10, !11} !llvm.ident = !{!12} -!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/exp.cpp] [DW_LANG_C_plus_plus] -!1 = !{!"exp.cpp", !"/tmp"} +!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!1 = !DIFile(filename: "exp.cpp", directory: "/tmp") !2 = !{} !3 = !{!4} -!4 = !{!"0x2e\00test\00test\00_Z4testiiiiiddddd\004\000\001\000\006\00256\000\005", !1, !5, !6, null, void (i32, i32, i32, i32, i32, double, double, double, double, double)* @_Z4testiiiiiddddd, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 5] [test] -!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/exp.cpp] -!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !DISubprogram(name: "test", linkageName: "_Z4testiiiiiddddd", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: void (i32, i32, i32, i32, i32, double, double, double, double, double)* @_Z4testiiiiiddddd, variables: !2) +!5 = !DIFile(filename: "exp.cpp", directory: "/tmp") +!6 = !DISubroutineType(types: !7) !7 = !{null, !8, !8, !8, !8, !8, !9, !9, !9, !9, !9} -!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] -!9 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float] +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!9 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float) !10 = !{i32 2, !"Dwarf Version", i32 4} -!11 = !{i32 1, !"Debug Info Version", i32 2} +!11 = !{i32 1, !"Debug Info Version", i32 3} !12 = !{!"clang version 3.5 "} -!13 = !{!"0x101\00a\0016777220\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 4] -!14 = !MDLocation(line: 4, scope: !4) -!15 = !{!"0x101\00b\0033554436\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [b] [line 4] -!16 = !{!"0x101\00c\0050331652\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [c] [line 4] -!17 = !{!"0x101\00d\0067108868\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [d] [line 4] -!18 = !{!"0x101\00e\0083886084\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [e] [line 4] -!19 = !{!"0x101\00m\00100663301\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [m] [line 5] -!20 = !MDLocation(line: 5, scope: !4) -!21 = !{!"0x101\00n\00117440517\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [n] [line 5] -!22 = !{!"0x101\00p\00134217733\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [p] [line 5] -!23 = !{!"0x101\00q\00150994949\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [q] [line 5] -!24 = !{!"0x101\00r\00167772165\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [r] [line 5] -!25 = !MDLocation(line: 7, scope: !26) -!26 = !{!"0xb\006\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp] -!27 = !MDLocation(line: 8, scope: !26) -!28 = !MDLocation(line: 11, scope: !26) -!29 = !MDLocation(line: 9, scope: !30) -!30 = !{!"0xb\008\000\001", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp] -!31 = !MDLocation(line: 10, scope: !30) -!32 = !MDLocation(line: 10, scope: !4) -!33 = !MDLocation(line: 11, scope: !4) -!34 = !MDLocation(line: 11, scope: !30) +!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 1, scope: !4, file: !5, type: !8) +!14 = !DILocation(line: 4, scope: !4) +!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 4, arg: 2, scope: !4, file: !5, type: !8) +!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !4, file: !5, type: !8) +!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "d", line: 4, arg: 4, scope: !4, file: !5, type: !8) +!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "e", line: 4, arg: 5, scope: !4, file: !5, type: !8) +!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "m", line: 5, arg: 6, scope: !4, file: !5, type: !9) +!20 = !DILocation(line: 5, scope: !4) +!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "n", line: 5, arg: 7, scope: !4, file: !5, type: !9) +!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 5, arg: 8, scope: !4, file: !5, type: !9) +!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "q", line: 5, arg: 9, scope: !4, file: !5, type: !9) +!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 5, arg: 10, scope: !4, file: !5, type: !9) +!25 = !DILocation(line: 7, scope: !26) +!26 = distinct !DILexicalBlock(line: 6, column: 0, file: !1, scope: !4) +!27 = !DILocation(line: 8, scope: !26) +!28 = !DILocation(line: 11, scope: !26) +!29 = !DILocation(line: 9, scope: !30) +!30 = distinct !DILexicalBlock(line: 8, column: 0, file: !1, scope: !4) +!31 = !DILocation(line: 10, scope: !30) +!32 = !DILocation(line: 10, scope: !4) +!33 = !DILocation(line: 11, scope: !4) +!34 = !DILocation(line: 11, scope: !30) ; CHECK-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-FP: .cfi_startproc @@ -179,7 +179,7 @@ declare void @_ZSt9terminatev() ; CHECK-FP: .cfi_offset r4, -36 ; CHECK-FP: add r11, sp, #28 ; CHECK-FP: .cfi_def_cfa r11, 8 -; CHECK-FP: sub sp, sp, #28 +; CHECK-FP: sub sp, sp, #44 ; CHECK-FP: .cfi_endproc ; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd: @@ -195,8 +195,8 @@ declare void @_ZSt9terminatev() ; CHECK-FP-ELIM: .cfi_offset r6, -28 ; CHECK-FP-ELIM: .cfi_offset r5, -32 ; CHECK-FP-ELIM: .cfi_offset r4, -36 -; CHECK-FP-ELIM: sub sp, sp, #28 -; CHECK-FP-ELIM: .cfi_def_cfa_offset 64 +; CHECK-FP-ELIM: sub sp, sp, #36 +; CHECK-FP-ELIM: .cfi_def_cfa_offset 72 ; CHECK-FP-ELIM: .cfi_endproc ; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd: @@ -264,14 +264,14 @@ declare void @_ZSt9terminatev() ; CHECK-THUMB-V7-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-THUMB-V7-FP: .cfi_startproc -; CHECK-THUMB-V7-FP: push.w {r4, r7, r11, lr} +; CHECK-THUMB-V7-FP: push {r4, r6, r7, lr} ; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 16 ; CHECK-THUMB-V7-FP: .cfi_offset lr, -4 -; CHECK-THUMB-V7-FP: .cfi_offset r11, -8 -; CHECK-THUMB-V7-FP: .cfi_offset r7, -12 +; CHECK-THUMB-V7-FP: .cfi_offset r7, -8 +; CHECK-THUMB-V7-FP: .cfi_offset r6, -12 ; CHECK-THUMB-V7-FP: .cfi_offset r4, -16 -; CHECK-THUMB-V7-FP: add r7, sp, #4 -; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 12 +; CHECK-THUMB-V7-FP: add r7, sp, #8 +; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 8 ; CHECK-THUMB-V7-FP: vpush {d8, d9, d10, d11, d12} ; CHECK-THUMB-V7-FP: .cfi_offset d12, -24 ; CHECK-THUMB-V7-FP: .cfi_offset d11, -32 @@ -300,14 +300,14 @@ declare void @_ZSt9terminatev() ; CHECK-THUMB-V7-FP-NOIAS-LABEL: _Z4testiiiiiddddd: ; CHECK-THUMB-V7-FP-NOIAS: .cfi_startproc -; CHECK-THUMB-V7-FP-NOIAS: push.w {r4, r7, r11, lr} +; CHECK-THUMB-V7-FP-NOIAS: push {r4, r6, r7, lr} ; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa_offset 16 ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 14, -4 -; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 11, -8 -; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -12 +; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -8 +; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 6, -12 ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 4, -16 -; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #4 -; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 12 +; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #8 +; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 8 ; CHECK-THUMB-V7-FP-NOIAS: vpush {d8, d9, d10, d11, d12} ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 268, -24 ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 267, -32 @@ -404,11 +404,11 @@ entry: ; CHECK-THUMB-V7-FP-ELIM-LABEL: test2: ; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc -; CHECK-THUMB-V7-FP-ELIM: push.w {r11, lr} +; CHECK-THUMB-V7-FP-ELIM: push {r7, lr} ; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 8 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4 -; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8 -; CHECK-THUMB-V7-FP-ELIM: pop.w {r11, pc} +; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8 +; CHECK-THUMB-V7-FP-ELIM: pop {r7, pc} ; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc @@ -522,13 +522,13 @@ entry: ; CHECK-THUMB-V7-FP-ELIM-LABEL: test3: ; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc -; CHECK-THUMB-V7-FP-ELIM: push.w {r4, r5, r11, lr} +; CHECK-THUMB-V7-FP-ELIM: push {r4, r5, r7, lr} ; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 16 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4 -; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8 +; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r5, -12 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r4, -16 -; CHECK-THUMB-V7-FP-ELIM: pop.w {r4, r5, r11, pc} +; CHECK-THUMB-V7-FP-ELIM: pop {r4, r5, r7, pc} ; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index 8679589a4865..84eae77794a4 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -7,13 +7,13 @@ target triple = "thumbv7-apple-ios" %struct.tag_s = type { i32, i32, i32 } define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp { - tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !20 - tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !21 - tail call void @llvm.dbg.value(metadata i64 %x, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !22 - tail call void @llvm.dbg.value(metadata i64 %y, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !23 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, i64 0, metadata !5, metadata !DIExpression()), !dbg !20 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, i64 0, metadata !13, metadata !DIExpression()), !dbg !21 + tail call void @llvm.dbg.value(metadata i64 %x, i64 0, metadata !14, metadata !DIExpression()), !dbg !22 + tail call void @llvm.dbg.value(metadata i64 %y, i64 0, metadata !17, metadata !DIExpression()), !dbg !23 ;CHECK: @DEBUG_VALUE: foo:y <- [R7+8] - tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !24 - tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !25 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, i64 0, metadata !18, metadata !DIExpression()), !dbg !24 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, i64 0, metadata !19, metadata !DIExpression()), !dbg !25 %1 = icmp eq %struct.tag_s* %c, null, !dbg !26 br i1 %1, label %3, label %2, !dbg !26 @@ -32,37 +32,37 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = !{!"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)\001\00\000\00\001", !32, !4, !4, !30, null, null} ; [ DW_TAG_compile_unit ] -!1 = !{!"0x2e\00foo\00foo\00\0011\000\001\000\006\00256\001\0011", !2, !2, !3, null, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, !31} ; [ DW_TAG_subprogram ] [line 11] [def] [foo] -!2 = !{!"0x29", !32} ; [ DW_TAG_file_type ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !32, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !32, enums: !{}, retainedTypes: !{}, subprograms: !30, imports: null) +!1 = !DISubprogram(name: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !2, scope: !2, type: !3, function: void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, variables: !31) +!2 = !DIFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772") +!3 = !DISubroutineType(types: !4) !4 = !{null} -!5 = !{!"0x101\00this\0016777227\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] -!6 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !7} ; [ DW_TAG_pointer_type ] -!7 = !{!"0x13\00tag_s\005\0096\0032\000\000\000", !32, !0, null, !8, null, null, null} ; [ DW_TAG_structure_type ] [tag_s] [line 5, size 96, align 32, offset 0] [def] [from ] +!5 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 1, scope: !1, file: !2, type: !6) +!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !7) +!7 = !DICompositeType(tag: DW_TAG_structure_type, name: "tag_s", line: 5, size: 96, align: 32, file: !32, scope: !0, elements: !8) !8 = !{!9, !11, !12} -!9 = !{!"0xd\00x\006\0032\0032\000\000", !32, !7, !10} ; [ DW_TAG_member ] -!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ] -!11 = !{!"0xd\00y\007\0032\0032\0032\000", !32, !7, !10} ; [ DW_TAG_member ] -!12 = !{!"0xd\00z\008\0032\0032\0064\000", !32, !7, !10} ; [ DW_TAG_member ] -!13 = !{!"0x101\00c\0033554443\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] -!14 = !{!"0x101\00x\0050331659\000", !1, !2, !15} ; [ DW_TAG_arg_variable ] -!15 = !{!"0x16\00UInt64\001\000\000\000\000", !32, !0, !16} ; [ DW_TAG_typedef ] -!16 = !{!"0x24\00long long unsigned int\000\0064\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] -!17 = !{!"0x101\00y\0067108875\000", !1, !2, !15} ; [ DW_TAG_arg_variable ] -!18 = !{!"0x101\00ptr1\0083886091\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] -!19 = !{!"0x101\00ptr2\00100663307\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] -!20 = !MDLocation(line: 11, column: 24, scope: !1) -!21 = !MDLocation(line: 11, column: 44, scope: !1) -!22 = !MDLocation(line: 11, column: 54, scope: !1) -!23 = !MDLocation(line: 11, column: 64, scope: !1) -!24 = !MDLocation(line: 11, column: 81, scope: !1) -!25 = !MDLocation(line: 11, column: 101, scope: !1) -!26 = !MDLocation(line: 12, column: 3, scope: !27) -!27 = !{!"0xb\0011\00107\000", !2, !1} ; [ DW_TAG_lexical_block ] -!28 = !MDLocation(line: 13, column: 5, scope: !27) -!29 = !MDLocation(line: 14, column: 1, scope: !27) +!9 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 6, size: 32, align: 32, file: !32, scope: !7, baseType: !10) +!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!11 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 7, size: 32, align: 32, offset: 32, file: !32, scope: !7, baseType: !10) +!12 = !DIDerivedType(tag: DW_TAG_member, name: "z", line: 8, size: 32, align: 32, offset: 64, file: !32, scope: !7, baseType: !10) +!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 2, scope: !1, file: !2, type: !6) +!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 11, arg: 3, scope: !1, file: !2, type: !15) +!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "UInt64", line: 1, file: !32, scope: !0, baseType: !16) +!16 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 32, encoding: DW_ATE_unsigned) +!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 11, arg: 4, scope: !1, file: !2, type: !15) +!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr1", line: 11, arg: 5, scope: !1, file: !2, type: !6) +!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr2", line: 11, arg: 6, scope: !1, file: !2, type: !6) +!20 = !DILocation(line: 11, column: 24, scope: !1) +!21 = !DILocation(line: 11, column: 44, scope: !1) +!22 = !DILocation(line: 11, column: 54, scope: !1) +!23 = !DILocation(line: 11, column: 64, scope: !1) +!24 = !DILocation(line: 11, column: 81, scope: !1) +!25 = !DILocation(line: 11, column: 101, scope: !1) +!26 = !DILocation(line: 12, column: 3, scope: !27) +!27 = distinct !DILexicalBlock(line: 11, column: 107, file: !2, scope: !1) +!28 = !DILocation(line: 13, column: 5, scope: !27) +!29 = !DILocation(line: 14, column: 1, scope: !27) !30 = !{!1} !31 = !{!5, !13, !14, !17, !18, !19} -!32 = !{!"one.c", !"/Volumes/Athwagate/R10048772"} -!33 = !{i32 1, !"Debug Info Version", i32 2} +!32 = !DIFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772") +!33 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index 3bf6ad91c86e..366102755174 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -31,62 +31,62 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load %1 = alloca %0*, align 4 %bounds = alloca %struct.CR, align 4 %data = alloca %struct.CR, align 4 - call void @llvm.dbg.value(metadata i8* %.block_descriptor, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !129 + call void @llvm.dbg.value(metadata i8* %.block_descriptor, i64 0, metadata !27, metadata !DIExpression()), !dbg !129 store %0* %loadedMydata, %0** %1, align 4 - call void @llvm.dbg.declare(metadata %0** %1, metadata !130, metadata !{!"0x102"}), !dbg !131 + call void @llvm.dbg.declare(metadata %0** %1, metadata !130, metadata !DIExpression()), !dbg !131 %2 = bitcast %struct.CR* %bounds to %1* - %3 = getelementptr %1* %2, i32 0, i32 0 + %3 = getelementptr %1, %1* %2, i32 0, i32 0 store [4 x i32] %bounds.coerce0, [4 x i32]* %3 - call void @llvm.dbg.declare(metadata %struct.CR* %bounds, metadata !132, metadata !{!"0x102"}), !dbg !133 + call void @llvm.dbg.declare(metadata %struct.CR* %bounds, metadata !132, metadata !DIExpression()), !dbg !133 %4 = bitcast %struct.CR* %data to %1* - %5 = getelementptr %1* %4, i32 0, i32 0 + %5 = getelementptr %1, %1* %4, i32 0, i32 0 store [4 x i32] %data.coerce0, [4 x i32]* %5 - call void @llvm.dbg.declare(metadata %struct.CR* %data, metadata !134, metadata !{!"0x102"}), !dbg !135 + call void @llvm.dbg.declare(metadata %struct.CR* %data, metadata !134, metadata !DIExpression()), !dbg !135 %6 = bitcast i8* %.block_descriptor to %2* - %7 = getelementptr inbounds %2* %6, i32 0, i32 6 + %7 = getelementptr inbounds %2, %2* %6, i32 0, i32 6 call void @llvm.dbg.declare(metadata %2* %6, metadata !136, metadata !163), !dbg !137 call void @llvm.dbg.declare(metadata %2* %6, metadata !138, metadata !164), !dbg !137 call void @llvm.dbg.declare(metadata %2* %6, metadata !139, metadata !165), !dbg !140 - %8 = load %0** %1, align 4, !dbg !141 - %9 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141 + %8 = load %0*, %0** %1, align 4, !dbg !141 + %9 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141 %10 = bitcast %0* %8 to i8*, !dbg !141 %11 = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %10, i8* %9), !dbg !141 %12 = bitcast i8* %11 to %0*, !dbg !141 - %13 = getelementptr inbounds %2* %6, i32 0, i32 5, !dbg !141 - %14 = load i8** %13, !dbg !141 + %13 = getelementptr inbounds %2, %2* %6, i32 0, i32 5, !dbg !141 + %14 = load i8*, i8** %13, !dbg !141 %15 = bitcast i8* %14 to %struct.__block_byref_mydata*, !dbg !141 - %16 = getelementptr inbounds %struct.__block_byref_mydata* %15, i32 0, i32 1, !dbg !141 - %17 = load %struct.__block_byref_mydata** %16, !dbg !141 - %18 = getelementptr inbounds %struct.__block_byref_mydata* %17, i32 0, i32 6, !dbg !141 + %16 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %15, i32 0, i32 1, !dbg !141 + %17 = load %struct.__block_byref_mydata*, %struct.__block_byref_mydata** %16, !dbg !141 + %18 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %17, i32 0, i32 6, !dbg !141 store %0* %12, %0** %18, align 4, !dbg !141 - %19 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !143 - %20 = load %3** %19, align 4, !dbg !143 - %21 = load i32* @"OBJC_IVAR_$_MyWork._data", !dbg !143 + %19 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !143 + %20 = load %3*, %3** %19, align 4, !dbg !143 + %21 = load i32, i32* @"OBJC_IVAR_$_MyWork._data", !dbg !143 %22 = bitcast %3* %20 to i8*, !dbg !143 - %23 = getelementptr inbounds i8* %22, i32 %21, !dbg !143 + %23 = getelementptr inbounds i8, i8* %22, i32 %21, !dbg !143 %24 = bitcast i8* %23 to %struct.CR*, !dbg !143 %25 = bitcast %struct.CR* %24 to i8*, !dbg !143 %26 = bitcast %struct.CR* %data to i8*, !dbg !143 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %25, i8* %26, i32 16, i32 4, i1 false), !dbg !143 - %27 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !144 - %28 = load %3** %27, align 4, !dbg !144 - %29 = load i32* @"OBJC_IVAR_$_MyWork._bounds", !dbg !144 + %27 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !144 + %28 = load %3*, %3** %27, align 4, !dbg !144 + %29 = load i32, i32* @"OBJC_IVAR_$_MyWork._bounds", !dbg !144 %30 = bitcast %3* %28 to i8*, !dbg !144 - %31 = getelementptr inbounds i8* %30, i32 %29, !dbg !144 + %31 = getelementptr inbounds i8, i8* %30, i32 %29, !dbg !144 %32 = bitcast i8* %31 to %struct.CR*, !dbg !144 %33 = bitcast %struct.CR* %32 to i8*, !dbg !144 %34 = bitcast %struct.CR* %bounds to i8*, !dbg !144 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %33, i8* %34, i32 16, i32 4, i1 false), !dbg !144 - %35 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !145 - %36 = load %3** %35, align 4, !dbg !145 - %37 = getelementptr inbounds %2* %6, i32 0, i32 5, !dbg !145 - %38 = load i8** %37, !dbg !145 + %35 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !145 + %36 = load %3*, %3** %35, align 4, !dbg !145 + %37 = getelementptr inbounds %2, %2* %6, i32 0, i32 5, !dbg !145 + %38 = load i8*, i8** %37, !dbg !145 %39 = bitcast i8* %38 to %struct.__block_byref_mydata*, !dbg !145 - %40 = getelementptr inbounds %struct.__block_byref_mydata* %39, i32 0, i32 1, !dbg !145 - %41 = load %struct.__block_byref_mydata** %40, !dbg !145 - %42 = getelementptr inbounds %struct.__block_byref_mydata* %41, i32 0, i32 6, !dbg !145 - %43 = load %0** %42, align 4, !dbg !145 - %44 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_222", !dbg !145 + %40 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %39, i32 0, i32 1, !dbg !145 + %41 = load %struct.__block_byref_mydata*, %struct.__block_byref_mydata** %40, !dbg !145 + %42 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %41, i32 0, i32 6, !dbg !145 + %43 = load %0*, %0** %42, align 4, !dbg !145 + %44 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_222", !dbg !145 %45 = bitcast %3* %36 to i8*, !dbg !145 call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %0*)*)(i8* %45, i8* %44, %0* %43), !dbg !145 ret void, !dbg !146 @@ -95,169 +95,169 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!162} -!0 = !{!"0x11\0016\00Apple clang version 2.1\000\00\002\00\001", !153, !147, !26, !148, null, null} ; [ DW_TAG_compile_unit ] -!1 = !{!"0x4\00\00248\0032\0032\000\000\000", !160, !0, null, !3, null, null, null} ; [ DW_TAG_enumeration_type ] [line 248, size 32, align 32, offset 0] [def] [from ] -!2 = !{!"0x29", !160} ; [ DW_TAG_file_type ] +!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !153, enums: !147, retainedTypes: !{}, subprograms: !148) +!1 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 248, size: 32, align: 32, file: !160, scope: !0, elements: !3) +!2 = !DIFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm") !3 = !{!4} -!4 = !{!"0x28\00Ver1\000"} ; [ DW_TAG_enumerator ] -!5 = !{!"0x4\00Mode\0079\0032\0032\000\000\000", !160, !0, null, !7, null, null, null} ; [ DW_TAG_enumeration_type ] [Mode] [line 79, size 32, align 32, offset 0] [def] [from ] -!6 = !{!"0x29", !161} ; [ DW_TAG_file_type ] +!4 = !DIEnumerator(name: "Ver1", value: 0) ; [ DW_TAG_enumerator ] +!5 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Mode", line: 79, size: 32, align: 32, file: !160, scope: !0, elements: !7) +!6 = !DIFile(filename: "header2.h", directory: "/Volumes/Sandbox/llvm") !7 = !{!8} -!8 = !{!"0x28\00One\000"} ; [ DW_TAG_enumerator ] -!9 = !{!"0x4\00\0015\0032\0032\000\000\000", !149, !0, null, !11, null, null, null} ; [ DW_TAG_enumeration_type ] [line 15, size 32, align 32, offset 0] [def] [from ] -!10 = !{!"0x29", !149} ; [ DW_TAG_file_type ] +!8 = !DIEnumerator(name: "One", value: 0) ; [ DW_TAG_enumerator ] +!9 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 15, size: 32, align: 32, file: !149, scope: !0, elements: !11) +!10 = !DIFile(filename: "header3.h", directory: "/Volumes/Sandbox/llvm") !11 = !{!12, !13} -!12 = !{!"0x28\00Unknown\000"} ; [ DW_TAG_enumerator ] -!13 = !{!"0x28\00Known\001"} ; [ DW_TAG_enumerator ] -!14 = !{!"0x4\00\0020\0032\0032\000\000\000", !150, !0, null, !16, null, null, null} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [def] [from ] -!15 = !{!"0x29", !150} ; [ DW_TAG_file_type ] +!12 = !DIEnumerator(name: "Unknown", value: 0) ; [ DW_TAG_enumerator ] +!13 = !DIEnumerator(name: "Known", value: 1) ; [ DW_TAG_enumerator ] +!14 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 20, size: 32, align: 32, file: !150, scope: !0, elements: !16) +!15 = !DIFile(filename: "Private.h", directory: "/Volumes/Sandbox/llvm") !16 = !{!17, !18} -!17 = !{!"0x28\00Single\000"} ; [ DW_TAG_enumerator ] -!18 = !{!"0x28\00Double\001"} ; [ DW_TAG_enumerator ] -!19 = !{!"0x4\00\0014\0032\0032\000\000\000", !151, !0, null, !21, null, null, null} ; [ DW_TAG_enumeration_type ] [line 14, size 32, align 32, offset 0] [def] [from ] -!20 = !{!"0x29", !151} ; [ DW_TAG_file_type ] +!17 = !DIEnumerator(name: "Single", value: 0) ; [ DW_TAG_enumerator ] +!18 = !DIEnumerator(name: "Double", value: 1) ; [ DW_TAG_enumerator ] +!19 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 14, size: 32, align: 32, file: !151, scope: !0, elements: !21) +!20 = !DIFile(filename: "header4.h", directory: "/Volumes/Sandbox/llvm") !21 = !{!22} -!22 = !{!"0x28\00Eleven\000"} ; [ DW_TAG_enumerator ] -!23 = !{!"0x2e\00foobar_func_block_invoke_0\00foobar_func_block_invoke_0\00\00609\001\001\000\006\00256\000\00609", !152, !24, !25, null, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null} ; [ DW_TAG_subprogram ] [line 609] [local] [def] [foobar_func_block_invoke_0] -!24 = !{!"0x29", !152} ; [ DW_TAG_file_type ] -!25 = !{!"0x15\00\000\000\000\000\000\000", !152, !24, null, !26, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!22 = !DIEnumerator(name: "Eleven", value: 0) ; [ DW_TAG_enumerator ] +!23 = !DISubprogram(name: "foobar_func_block_invoke_0", line: 609, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 609, file: !152, scope: !24, type: !25, function: void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0) +!24 = !DIFile(filename: "MyLibrary.m", directory: "/Volumes/Sandbox/llvm") +!25 = !DISubroutineType(types: !26) !26 = !{null} -!27 = !{!"0x101\00.block_descriptor\0016777825\0064", !23, !24, !28} ; [ DW_TAG_arg_variable ] -!28 = !{!"0xf\00\000\0032\000\000\000", null, !0, !29} ; [ DW_TAG_pointer_type ] -!29 = !{!"0x13\00__block_literal_14\00609\00256\0032\000\000\000", !152, !24, null, !30, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_14] [line 609, size 256, align 32, offset 0] [def] [from ] +!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: ".block_descriptor", line: 609, arg: 1, flags: DIFlagArtificial, scope: !23, file: !24, type: !28) +!28 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, scope: !0, baseType: !29) +!29 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_14", line: 609, size: 256, align: 32, file: !152, scope: !24, elements: !30) !30 = !{!31, !33, !35, !36, !37, !48, !89, !124} -!31 = !{!"0xd\00__isa\00609\0032\0032\000\000", !152, !24, !32} ; [ DW_TAG_member ] -!32 = !{!"0xf\00\000\0032\0032\000\000", null, !0, null} ; [ DW_TAG_pointer_type ] -!33 = !{!"0xd\00__flags\00609\0032\0032\0032\000", !152, !24, !34} ; [ DW_TAG_member ] -!34 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ] -!35 = !{!"0xd\00__reserved\00609\0032\0032\0064\000", !152, !24, !34} ; [ DW_TAG_member ] -!36 = !{!"0xd\00__FuncPtr\00609\0032\0032\0096\000", !152, !24, !32} ; [ DW_TAG_member ] -!37 = !{!"0xd\00__descriptor\00609\0032\0032\00128\000", !152, !24, !38} ; [ DW_TAG_member ] -!38 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !39} ; [ DW_TAG_pointer_type ] -!39 = !{!"0x13\00__block_descriptor_withcopydispose\00307\00128\0032\000\000\000", !153, !0, null, !41, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor_withcopydispose] [line 307, size 128, align 32, offset 0] [def] [from ] -!40 = !{!"0x29", !153} ; [ DW_TAG_file_type ] +!31 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", line: 609, size: 32, align: 32, file: !152, scope: !24, baseType: !32) +!32 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: null) +!33 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", line: 609, size: 32, align: 32, offset: 32, file: !152, scope: !24, baseType: !34) +!34 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!35 = !DIDerivedType(tag: DW_TAG_member, name: "__reserved", line: 609, size: 32, align: 32, offset: 64, file: !152, scope: !24, baseType: !34) +!36 = !DIDerivedType(tag: DW_TAG_member, name: "__FuncPtr", line: 609, size: 32, align: 32, offset: 96, file: !152, scope: !24, baseType: !32) +!37 = !DIDerivedType(tag: DW_TAG_member, name: "__descriptor", line: 609, size: 32, align: 32, offset: 128, file: !152, scope: !24, baseType: !38) +!38 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !39) +!39 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_descriptor_withcopydispose", line: 307, size: 128, align: 32, file: !153, scope: !0, elements: !41) +!40 = !DIFile(filename: "MyLibrary.i", directory: "/Volumes/Sandbox/llvm") !41 = !{!42, !44, !45, !47} -!42 = !{!"0xd\00reserved\00307\0032\0032\000\000", !153, !40, !43} ; [ DW_TAG_member ] -!43 = !{!"0x24\00long unsigned int\000\0032\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] -!44 = !{!"0xd\00Size\00307\0032\0032\0032\000", !153, !40, !43} ; [ DW_TAG_member ] -!45 = !{!"0xd\00CopyFuncPtr\00307\0032\0032\0064\000", !153, !40, !46} ; [ DW_TAG_member ] -!46 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !32} ; [ DW_TAG_pointer_type ] -!47 = !{!"0xd\00DestroyFuncPtr\00307\0032\0032\0096\000", !153, !40, !46} ; [ DW_TAG_member ] -!48 = !{!"0xd\00mydata\00609\0032\0032\00160\000", !152, !24, !49} ; [ DW_TAG_member ] -!49 = !{!"0xf\00\000\0032\000\000\000", null, !0, !50} ; [ DW_TAG_pointer_type ] -!50 = !{!"0x13\00\000\00224\000\000\0016\000", !152, !24, null, !51, null, null, null} ; [ DW_TAG_structure_type ] [line 0, size 224, align 0, offset 0] [def] [from ] +!42 = !DIDerivedType(tag: DW_TAG_member, name: "reserved", line: 307, size: 32, align: 32, file: !153, scope: !40, baseType: !43) +!43 = !DIBasicType(tag: DW_TAG_base_type, name: "long unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) +!44 = !DIDerivedType(tag: DW_TAG_member, name: "Size", line: 307, size: 32, align: 32, offset: 32, file: !153, scope: !40, baseType: !43) +!45 = !DIDerivedType(tag: DW_TAG_member, name: "CopyFuncPtr", line: 307, size: 32, align: 32, offset: 64, file: !153, scope: !40, baseType: !46) +!46 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !32) +!47 = !DIDerivedType(tag: DW_TAG_member, name: "DestroyFuncPtr", line: 307, size: 32, align: 32, offset: 96, file: !153, scope: !40, baseType: !46) +!48 = !DIDerivedType(tag: DW_TAG_member, name: "mydata", line: 609, size: 32, align: 32, offset: 160, file: !152, scope: !24, baseType: !49) +!49 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, scope: !0, baseType: !50) +!50 = !DICompositeType(tag: DW_TAG_structure_type, size: 224, flags: DIFlagBlockByrefStruct, file: !152, scope: !24, elements: !51) !51 = !{!52, !53, !54, !55, !56, !57, !58} -!52 = !{!"0xd\00__isa\000\0032\0032\000\000", !152, !24, !32} ; [ DW_TAG_member ] -!53 = !{!"0xd\00__forwarding\000\0032\0032\0032\000", !152, !24, !32} ; [ DW_TAG_member ] -!54 = !{!"0xd\00__flags\000\0032\0032\0064\000", !152, !24, !34} ; [ DW_TAG_member ] -!55 = !{!"0xd\00__size\000\0032\0032\0096\000", !152, !24, !34} ; [ DW_TAG_member ] -!56 = !{!"0xd\00__copy_helper\000\0032\0032\00128\000", !152, !24, !32} ; [ DW_TAG_member ] -!57 = !{!"0xd\00__destroy_helper\000\0032\0032\00160\000", !152, !24, !32} ; [ DW_TAG_member ] -!58 = !{!"0xd\00mydata\000\0032\0032\00192\000", !152, !24, !59} ; [ DW_TAG_member ] -!59 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !60} ; [ DW_TAG_pointer_type ] -!60 = !{!"0x13\00UIMydata\0026\00128\0032\000\000\0016", !154, !24, null, !62, null, null, null} ; [ DW_TAG_structure_type ] [UIMydata] [line 26, size 128, align 32, offset 0] [def] [from ] -!61 = !{!"0x29", !154} ; [ DW_TAG_file_type ] +!52 = !DIDerivedType(tag: DW_TAG_member, name: "__isa", size: 32, align: 32, file: !152, scope: !24, baseType: !32) +!53 = !DIDerivedType(tag: DW_TAG_member, name: "__forwarding", size: 32, align: 32, offset: 32, file: !152, scope: !24, baseType: !32) +!54 = !DIDerivedType(tag: DW_TAG_member, name: "__flags", size: 32, align: 32, offset: 64, file: !152, scope: !24, baseType: !34) +!55 = !DIDerivedType(tag: DW_TAG_member, name: "__size", size: 32, align: 32, offset: 96, file: !152, scope: !24, baseType: !34) +!56 = !DIDerivedType(tag: DW_TAG_member, name: "__copy_helper", size: 32, align: 32, offset: 128, file: !152, scope: !24, baseType: !32) +!57 = !DIDerivedType(tag: DW_TAG_member, name: "__destroy_helper", size: 32, align: 32, offset: 160, file: !152, scope: !24, baseType: !32) +!58 = !DIDerivedType(tag: DW_TAG_member, name: "mydata", size: 32, align: 32, offset: 192, file: !152, scope: !24, baseType: !59) +!59 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !60) +!60 = !DICompositeType(tag: DW_TAG_structure_type, name: "UIMydata", line: 26, size: 128, align: 32, runtimeLang: DW_LANG_ObjC, file: !154, scope: !24, elements: !62) +!61 = !DIFile(filename: "header11.h", directory: "/Volumes/Sandbox/llvm") !62 = !{!63, !71, !75, !79} -!63 = !{!"0x1c\00\000\000\000\000\000", !60, null, !64} ; [ DW_TAG_inheritance ] -!64 = !{!"0x13\00NSO\0066\0032\0032\000\000\0016", !155, !40, null, !66, null, null, null} ; [ DW_TAG_structure_type ] [NSO] [line 66, size 32, align 32, offset 0] [def] [from ] -!65 = !{!"0x29", !155} ; [ DW_TAG_file_type ] +!63 = !DIDerivedType(tag: DW_TAG_inheritance, file: !61, baseType: !64) +!64 = !DICompositeType(tag: DW_TAG_structure_type, name: "NSO", line: 66, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !155, scope: !40, elements: !66) +!65 = !DIFile(filename: "NSO.h", directory: "/Volumes/Sandbox/llvm") !66 = !{!67} -!67 = !{!"0xd\00isa\0067\0032\0032\000\002", !155, !65, !68, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!68 = !{!"0x16\00Class\00197\000\000\000\000", !153, !0, !69} ; [ DW_TAG_typedef ] -!69 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !70} ; [ DW_TAG_pointer_type ] -!70 = !{!"0x13\00objc_class\000\000\000\000\004\000", !153, !0, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [decl] [from ] -!71 = !{!"0xd\00_mydataRef\0028\0032\0032\0032\000", !154, !61, !72, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!72 = !{!"0x16\00CFTypeRef\00313\000\000\000\000", !152, !0, !73} ; [ DW_TAG_typedef ] -!73 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !74} ; [ DW_TAG_pointer_type ] -!74 = !{!"0x26\00\000\000\000\000\000", null, !0, null} ; [ DW_TAG_const_type ] -!75 = !{!"0xd\00_scale\0029\0032\0032\0064\000", !154, !61, !76, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!76 = !{!"0x16\00Float\0089\000\000\000\000", !156, !0, !78} ; [ DW_TAG_typedef ] -!77 = !{!"0x29", !156} ; [ DW_TAG_file_type ] -!78 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !0} ; [ DW_TAG_base_type ] -!79 = !{!"0xd\00_mydataFlags\0037\008\008\0096\000", !154, !61, !80, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!80 = !{!"0x13\00\0030\008\008\000\000\000", !154, !0, null, !81, null, null, null} ; [ DW_TAG_structure_type ] [line 30, size 8, align 8, offset 0] [def] [from ] +!67 = !DIDerivedType(tag: DW_TAG_member, name: "isa", line: 67, size: 32, align: 32, flags: DIFlagProtected, file: !155, scope: !65, baseType: !68, extraData: !"") +!68 = !DIDerivedType(tag: DW_TAG_typedef, name: "Class", line: 197, file: !153, scope: !0, baseType: !69) +!69 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !70) +!70 = !DICompositeType(tag: DW_TAG_structure_type, name: "objc_class", flags: DIFlagFwdDecl, file: !153, scope: !0) +!71 = !DIDerivedType(tag: DW_TAG_member, name: "_mydataRef", line: 28, size: 32, align: 32, offset: 32, file: !154, scope: !61, baseType: !72, extraData: !"") +!72 = !DIDerivedType(tag: DW_TAG_typedef, name: "CFTypeRef", line: 313, file: !152, scope: !0, baseType: !73) +!73 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !74) +!74 = !DIDerivedType(tag: DW_TAG_const_type, scope: !0, baseType: null) +!75 = !DIDerivedType(tag: DW_TAG_member, name: "_scale", line: 29, size: 32, align: 32, offset: 64, file: !154, scope: !61, baseType: !76, extraData: !"") +!76 = !DIDerivedType(tag: DW_TAG_typedef, name: "Float", line: 89, file: !156, scope: !0, baseType: !78) +!77 = !DIFile(filename: "header12.h", directory: "/Volumes/Sandbox/llvm") +!78 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) +!79 = !DIDerivedType(tag: DW_TAG_member, name: "_mydataFlags", line: 37, size: 8, align: 8, offset: 96, file: !154, scope: !61, baseType: !80, extraData: !"") +!80 = !DICompositeType(tag: DW_TAG_structure_type, line: 30, size: 8, align: 8, file: !154, scope: !0, elements: !81) !81 = !{!82, !84, !85, !86, !87, !88} -!82 = !{!"0xd\00named\0031\001\0032\000\000", !154, !61, !83} ; [ DW_TAG_member ] -!83 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] -!84 = !{!"0xd\00mydataO\0032\003\0032\001\000", !154, !61, !83} ; [ DW_TAG_member ] -!85 = !{!"0xd\00cached\0033\001\0032\004\000", !154, !61, !83} ; [ DW_TAG_member ] -!86 = !{!"0xd\00hasBeenCached\0034\001\0032\005\000", !154, !61, !83} ; [ DW_TAG_member ] -!87 = !{!"0xd\00hasPattern\0035\001\0032\006\000", !154, !61, !83} ; [ DW_TAG_member ] -!88 = !{!"0xd\00isCIMydata\0036\001\0032\007\000", !154, !61, !83} ; [ DW_TAG_member ] -!89 = !{!"0xd\00self\00609\0032\0032\00192\000", !152, !24, !90} ; [ DW_TAG_member ] -!90 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !91} ; [ DW_TAG_pointer_type ] -!91 = !{!"0x13\00MyWork\0036\00384\0032\000\000\0016", !152, !40, null, !92, null, null, null} ; [ DW_TAG_structure_type ] [MyWork] [line 36, size 384, align 32, offset 0] [def] [from ] +!82 = !DIDerivedType(tag: DW_TAG_member, name: "named", line: 31, size: 1, align: 32, file: !154, scope: !61, baseType: !83) +!83 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) +!84 = !DIDerivedType(tag: DW_TAG_member, name: "mydataO", line: 32, size: 3, align: 32, offset: 1, file: !154, scope: !61, baseType: !83) +!85 = !DIDerivedType(tag: DW_TAG_member, name: "cached", line: 33, size: 1, align: 32, offset: 4, file: !154, scope: !61, baseType: !83) +!86 = !DIDerivedType(tag: DW_TAG_member, name: "hasBeenCached", line: 34, size: 1, align: 32, offset: 5, file: !154, scope: !61, baseType: !83) +!87 = !DIDerivedType(tag: DW_TAG_member, name: "hasPattern", line: 35, size: 1, align: 32, offset: 6, file: !154, scope: !61, baseType: !83) +!88 = !DIDerivedType(tag: DW_TAG_member, name: "isCIMydata", line: 36, size: 1, align: 32, offset: 7, file: !154, scope: !61, baseType: !83) +!89 = !DIDerivedType(tag: DW_TAG_member, name: "self", line: 609, size: 32, align: 32, offset: 192, file: !152, scope: !24, baseType: !90) +!90 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !91) +!91 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyWork", line: 36, size: 384, align: 32, runtimeLang: DW_LANG_ObjC, file: !152, scope: !40, elements: !92) !92 = !{!93, !98, !101, !107, !123} -!93 = !{!"0x1c\00\000\000\000\000\000", !152, !91, !94} ; [ DW_TAG_inheritance ] -!94 = !{!"0x13\00twork\0043\0032\0032\000\000\0016", !157, !40, null, !96, null, null, null} ; [ DW_TAG_structure_type ] [twork] [line 43, size 32, align 32, offset 0] [def] [from ] -!95 = !{!"0x29", !157} ; [ DW_TAG_file_type ] +!93 = !DIDerivedType(tag: DW_TAG_inheritance, file: !152, scope: !91, baseType: !94) +!94 = !DICompositeType(tag: DW_TAG_structure_type, name: "twork", line: 43, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !157, scope: !40, elements: !96) +!95 = !DIFile(filename: "header13.h", directory: "/Volumes/Sandbox/llvm") !96 = !{!97} -!97 = !{!"0x1c\00\000\000\000\000\000", !94, null, !64} ; [ DW_TAG_inheritance ] -!98 = !{!"0xd\00_itemID\0038\0064\0032\0032\001", !152, !24, !99, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!99 = !{!"0x16\00uint64_t\0055\000\000\000\000", !153, !0, !100} ; [ DW_TAG_typedef ] -!100 = !{!"0x24\00long long unsigned int\000\0064\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] -!101 = !{!"0xd\00_library\0039\0032\0032\0096\001", !152, !24, !102, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!102 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !103} ; [ DW_TAG_pointer_type ] -!103 = !{!"0x13\00MyLibrary2\0022\0032\0032\000\000\0016", !158, !40, null, !105, null, null, null} ; [ DW_TAG_structure_type ] [MyLibrary2] [line 22, size 32, align 32, offset 0] [def] [from ] -!104 = !{!"0x29", !158} ; [ DW_TAG_file_type ] +!97 = !DIDerivedType(tag: DW_TAG_inheritance, file: !95, baseType: !64) +!98 = !DIDerivedType(tag: DW_TAG_member, name: "_itemID", line: 38, size: 64, align: 32, offset: 32, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !99, extraData: !"") +!99 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint64_t", line: 55, file: !153, scope: !0, baseType: !100) +!100 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 32, encoding: DW_ATE_unsigned) +!101 = !DIDerivedType(tag: DW_TAG_member, name: "_library", line: 39, size: 32, align: 32, offset: 96, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !102, extraData: !"") +!102 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !103) +!103 = !DICompositeType(tag: DW_TAG_structure_type, name: "MyLibrary2", line: 22, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !158, scope: !40, elements: !105) +!104 = !DIFile(filename: "header14.h", directory: "/Volumes/Sandbox/llvm") !105 = !{!106} -!106 = !{!"0x1c\00\000\000\000\000\000", !103, null, !64} ; [ DW_TAG_inheritance ] -!107 = !{!"0xd\00_bounds\0040\00128\0032\00128\001", !152, !24, !108, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!108 = !{!"0x16\00CR\0033\000\000\000\000", !153, !0, !109} ; [ DW_TAG_typedef ] -!109 = !{!"0x13\00CR\0029\00128\0032\000\000\000", !156, !0, null, !110, null, null, null} ; [ DW_TAG_structure_type ] [CR] [line 29, size 128, align 32, offset 0] [def] [from ] +!106 = !DIDerivedType(tag: DW_TAG_inheritance, file: !104, baseType: !64) +!107 = !DIDerivedType(tag: DW_TAG_member, name: "_bounds", line: 40, size: 128, align: 32, offset: 128, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !108, extraData: !"") +!108 = !DIDerivedType(tag: DW_TAG_typedef, name: "CR", line: 33, file: !153, scope: !0, baseType: !109) +!109 = !DICompositeType(tag: DW_TAG_structure_type, name: "CR", line: 29, size: 128, align: 32, file: !156, scope: !0, elements: !110) !110 = !{!111, !117} -!111 = !{!"0xd\00origin\0030\0064\0032\000\000", !156, !77, !112} ; [ DW_TAG_member ] -!112 = !{!"0x16\00CP\0017\000\000\000\000", !156, !0, !113} ; [ DW_TAG_typedef ] -!113 = !{!"0x13\00CP\0013\0064\0032\000\000\000", !156, !0, null, !114, null, null, null} ; [ DW_TAG_structure_type ] [CP] [line 13, size 64, align 32, offset 0] [def] [from ] +!111 = !DIDerivedType(tag: DW_TAG_member, name: "origin", line: 30, size: 64, align: 32, file: !156, scope: !77, baseType: !112) +!112 = !DIDerivedType(tag: DW_TAG_typedef, name: "CP", line: 17, file: !156, scope: !0, baseType: !113) +!113 = !DICompositeType(tag: DW_TAG_structure_type, name: "CP", line: 13, size: 64, align: 32, file: !156, scope: !0, elements: !114) !114 = !{!115, !116} -!115 = !{!"0xd\00x\0014\0032\0032\000\000", !156, !77, !76} ; [ DW_TAG_member ] -!116 = !{!"0xd\00y\0015\0032\0032\0032\000", !156, !77, !76} ; [ DW_TAG_member ] -!117 = !{!"0xd\00size\0031\0064\0032\0064\000", !156, !77, !118} ; [ DW_TAG_member ] -!118 = !{!"0x16\00Size\0025\000\000\000\000", !156, !0, !119} ; [ DW_TAG_typedef ] -!119 = !{!"0x13\00Size\0021\0064\0032\000\000\000", !156, !0, null, !120, null, null, null} ; [ DW_TAG_structure_type ] [Size] [line 21, size 64, align 32, offset 0] [def] [from ] +!115 = !DIDerivedType(tag: DW_TAG_member, name: "x", line: 14, size: 32, align: 32, file: !156, scope: !77, baseType: !76) +!116 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 15, size: 32, align: 32, offset: 32, file: !156, scope: !77, baseType: !76) +!117 = !DIDerivedType(tag: DW_TAG_member, name: "size", line: 31, size: 64, align: 32, offset: 64, file: !156, scope: !77, baseType: !118) +!118 = !DIDerivedType(tag: DW_TAG_typedef, name: "Size", line: 25, file: !156, scope: !0, baseType: !119) +!119 = !DICompositeType(tag: DW_TAG_structure_type, name: "Size", line: 21, size: 64, align: 32, file: !156, scope: !0, elements: !120) !120 = !{!121, !122} -!121 = !{!"0xd\00width\0022\0032\0032\000\000", !156, !77, !76} ; [ DW_TAG_member ] -!122 = !{!"0xd\00height\0023\0032\0032\0032\000", !156, !77, !76} ; [ DW_TAG_member ] -!123 = !{!"0xd\00_data\0040\00128\0032\00256\001", !152, !24, !108, !"", !"", !"", i32 0} ; [ DW_TAG_member ] -!124 = !{!"0xd\00semi\00609\0032\0032\00224\000", !152, !24, !125} ; [ DW_TAG_member ] -!125 = !{!"0x16\00d_t\0035\000\000\000\000", !152, !0, !126} ; [ DW_TAG_typedef ] -!126 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !127} ; [ DW_TAG_pointer_type ] -!127 = !{!"0x13\00my_struct\0049\000\000\000\004\000", !159, !0, null, null, null, null, null} ; [ DW_TAG_structure_type ] [my_struct] [line 49, size 0, align 0, offset 0] [decl] [from ] -!128 = !{!"0x29", !159} ; [ DW_TAG_file_type ] -!129 = !MDLocation(line: 609, column: 144, scope: !23) -!130 = !{!"0x101\00loadedMydata\0033555041\000", !23, !24, !59} ; [ DW_TAG_arg_variable ] -!131 = !MDLocation(line: 609, column: 155, scope: !23) -!132 = !{!"0x101\00bounds\0050332257\000", !23, !24, !108} ; [ DW_TAG_arg_variable ] -!133 = !MDLocation(line: 609, column: 175, scope: !23) -!134 = !{!"0x101\00data\0067109473\000", !23, !24, !108} ; [ DW_TAG_arg_variable ] -!135 = !MDLocation(line: 609, column: 190, scope: !23) -!136 = !{!"0x100\00mydata\00604\000", !23, !24, !50} ; [ DW_TAG_auto_variable ] -!137 = !MDLocation(line: 604, column: 49, scope: !23) -!138 = !{!"0x100\00self\00604\000", !23, !40, !90} ; [ DW_TAG_auto_variable ] -!139 = !{!"0x100\00semi\00607\000", !23, !24, !125} ; [ DW_TAG_auto_variable ] -!140 = !MDLocation(line: 607, column: 30, scope: !23) -!141 = !MDLocation(line: 610, column: 17, scope: !142) -!142 = !{!"0xb\00609\00200\0094", !152, !23} ; [ DW_TAG_lexical_block ] -!143 = !MDLocation(line: 611, column: 17, scope: !142) -!144 = !MDLocation(line: 612, column: 17, scope: !142) -!145 = !MDLocation(line: 613, column: 17, scope: !142) -!146 = !MDLocation(line: 615, column: 13, scope: !142) +!121 = !DIDerivedType(tag: DW_TAG_member, name: "width", line: 22, size: 32, align: 32, file: !156, scope: !77, baseType: !76) +!122 = !DIDerivedType(tag: DW_TAG_member, name: "height", line: 23, size: 32, align: 32, offset: 32, file: !156, scope: !77, baseType: !76) +!123 = !DIDerivedType(tag: DW_TAG_member, name: "_data", line: 40, size: 128, align: 32, offset: 256, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !108, extraData: !"") +!124 = !DIDerivedType(tag: DW_TAG_member, name: "semi", line: 609, size: 32, align: 32, offset: 224, file: !152, scope: !24, baseType: !125) +!125 = !DIDerivedType(tag: DW_TAG_typedef, name: "d_t", line: 35, file: !152, scope: !0, baseType: !126) +!126 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !127) +!127 = !DICompositeType(tag: DW_TAG_structure_type, name: "my_struct", line: 49, flags: DIFlagFwdDecl, file: !159, scope: !0) +!128 = !DIFile(filename: "header15.h", directory: "/Volumes/Sandbox/llvm") +!129 = !DILocation(line: 609, column: 144, scope: !23) +!130 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "loadedMydata", line: 609, arg: 2, scope: !23, file: !24, type: !59) +!131 = !DILocation(line: 609, column: 155, scope: !23) +!132 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bounds", line: 609, arg: 3, scope: !23, file: !24, type: !108) +!133 = !DILocation(line: 609, column: 175, scope: !23) +!134 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "data", line: 609, arg: 4, scope: !23, file: !24, type: !108) +!135 = !DILocation(line: 609, column: 190, scope: !23) +!136 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "mydata", line: 604, scope: !23, file: !24, type: !50) +!137 = !DILocation(line: 604, column: 49, scope: !23) +!138 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "self", line: 604, scope: !23, file: !40, type: !90) +!139 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "semi", line: 607, scope: !23, file: !24, type: !125) +!140 = !DILocation(line: 607, column: 30, scope: !23) +!141 = !DILocation(line: 610, column: 17, scope: !142) +!142 = distinct !DILexicalBlock(line: 609, column: 200, file: !152, scope: !23) +!143 = !DILocation(line: 611, column: 17, scope: !142) +!144 = !DILocation(line: 612, column: 17, scope: !142) +!145 = !DILocation(line: 613, column: 17, scope: !142) +!146 = !DILocation(line: 615, column: 13, scope: !142) !147 = !{!1, !1, !5, !5, !9, !14, !19, !19, !14, !14, !14, !19, !19, !19} !148 = !{!23} -!149 = !{!"header3.h", !"/Volumes/Sandbox/llvm"} -!150 = !{!"Private.h", !"/Volumes/Sandbox/llvm"} -!151 = !{!"header4.h", !"/Volumes/Sandbox/llvm"} -!152 = !{!"MyLibrary.m", !"/Volumes/Sandbox/llvm"} -!153 = !{!"MyLibrary.i", !"/Volumes/Sandbox/llvm"} -!154 = !{!"header11.h", !"/Volumes/Sandbox/llvm"} -!155 = !{!"NSO.h", !"/Volumes/Sandbox/llvm"} -!156 = !{!"header12.h", !"/Volumes/Sandbox/llvm"} -!157 = !{!"header13.h", !"/Volumes/Sandbox/llvm"} -!158 = !{!"header14.h", !"/Volumes/Sandbox/llvm"} -!159 = !{!"header15.h", !"/Volumes/Sandbox/llvm"} -!160 = !{!"header.h", !"/Volumes/Sandbox/llvm"} +!149 = !DIFile(filename: "header3.h", directory: "/Volumes/Sandbox/llvm") +!150 = !DIFile(filename: "Private.h", directory: "/Volumes/Sandbox/llvm") +!151 = !DIFile(filename: "header4.h", directory: "/Volumes/Sandbox/llvm") +!152 = !DIFile(filename: "MyLibrary.m", directory: "/Volumes/Sandbox/llvm") +!153 = !DIFile(filename: "MyLibrary.i", directory: "/Volumes/Sandbox/llvm") +!154 = !DIFile(filename: "header11.h", directory: "/Volumes/Sandbox/llvm") +!155 = !DIFile(filename: "NSO.h", directory: "/Volumes/Sandbox/llvm") +!156 = !DIFile(filename: "header12.h", directory: "/Volumes/Sandbox/llvm") +!157 = !DIFile(filename: "header13.h", directory: "/Volumes/Sandbox/llvm") +!158 = !DIFile(filename: "header14.h", directory: "/Volumes/Sandbox/llvm") +!159 = !DIFile(filename: "header15.h", directory: "/Volumes/Sandbox/llvm") +!160 = !DIFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm") !161 = !{!"header2.h", !"/Volumes/Sandbox/llvm"} -!162 = !{i32 1, !"Debug Info Version", i32 2} -!163 = !{!"0x102\0034\0020\006\0034\004\006\0034\0024"} ; [ DW_TAG_expression ] [DW_OP_plus 20 DW_OP_deref DW_OP_plus 4 DW_OP_deref DW_OP_plus 24] -!164 = !{!"0x102\0034\0024"} ; [ DW_TAG_expression ] [DW_OP_plus 24] -!165 = !{!"0x102\0034\0028"} ; [ DW_TAG_expression ] [DW_OP_plus 28] +!162 = !{i32 1, !"Debug Info Version", i32 3} +!163 = !DIExpression(DW_OP_plus, 20, DW_OP_deref, DW_OP_plus, 4, DW_OP_deref, DW_OP_plus, 24) +!164 = !DIExpression(DW_OP_deref, DW_OP_plus, 24) +!165 = !DIExpression(DW_OP_deref, DW_OP_plus, 28) diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index 94756953de0a..03b4d6b38151 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -20,18 +20,18 @@ entry: for.body9: ; preds = %for.body9, %entry %add19 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39 - tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !DIExpression()), !dbg !39 %add20 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39 - tail call void @llvm.dbg.value(metadata <4 x float> %add20, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata <4 x float> %add20, i64 0, metadata !28, metadata !DIExpression()), !dbg !39 br i1 %cond, label %for.end54, label %for.body9, !dbg !44 for.end54: ; preds = %for.body9 %tmp115 = extractelement <4 x float> %add19, i32 1 %conv6.i75 = fpext float %tmp115 to double, !dbg !45 - %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 + %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 %tmp116 = extractelement <4 x float> %add20, i32 1 %conv6.i76 = fpext float %tmp116 to double, !dbg !45 - %call.i83 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45 + %call.i83 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45 ret i32 0, !dbg !49 } @@ -42,60 +42,60 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.module.flags = !{!56} !llvm.dbg.cu = !{!2} -!0 = !{!"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\000", !54, null, !3, i32 0, <4 x float> (float)* @test0001, null, null, !51} ; [ DW_TAG_subprogram ] -!1 = !{!"0x29", !54} ; [ DW_TAG_file_type ] -!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !54, !17, !17, !50, null, null} ; [ DW_TAG_compile_unit ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, i32 0, !4, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !3, function: <4 x float> (float)* @test0001, variables: !51) +!1 = !DIFile(filename: "build2.c", directory: "/private/tmp") +!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) +!3 = !DISubroutineType(types: !4) !4 = !{!5} -!5 = !{!"0x16\00v4f32\0014\000\000\000\000", !54, !2, !6} ; [ DW_TAG_typedef ] -!6 = !{!"0x1\00\000\00128\00128\000\000", !54, !2, !7, !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] -!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ] +!5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) +!6 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 128, file: !54, scope: !2, baseType: !7, elements: !8) +!7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !8 = !{!9} -!9 = !{!"0x21\000\004"} ; [ DW_TAG_subrange_type ] -!10 = !{!"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\000", !54, null, !11, null, i32 (i32, i8**, i1)* @main, null, null, !52} ; [ DW_TAG_subprogram ] [line 59] [def] [scope 0] [main] -!11 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!9 = !DISubrange(count: 4) +!10 = !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !11, function: i32 (i32, i8**, i1)* @main, variables: !52) +!11 = !DISubroutineType(types: !12) !12 = !{!13} -!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ] -!14 = !{!"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\000", !55, null, !16, null, null, null, null, !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [scope 0] [printFV] -!15 = !{!"0x29", !55} ; [ DW_TAG_file_type ] -!16 = !{!"0x15\00\000\000\000\000\000\000", !55, !15, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!14 = !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !55, scope: null, type: !16, variables: !53) +!15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") +!16 = !DISubroutineType(types: !17) !17 = !{null} -!18 = !{!"0x101\00a\0016777219\000", !0, !1, !7} ; [ DW_TAG_arg_variable ] -!19 = !{!"0x101\00argc\0016777275\000", !10, !1, !13} ; [ DW_TAG_arg_variable ] -!20 = !{!"0x101\00argv\0033554491\000", !10, !1, !21} ; [ DW_TAG_arg_variable ] -!21 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !22} ; [ DW_TAG_pointer_type ] -!22 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !23} ; [ DW_TAG_pointer_type ] -!23 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ] -!24 = !{!"0x100\00i\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] -!25 = !{!"0xb\0059\0033\0014", !1, !10} ; [ DW_TAG_lexical_block ] -!26 = !{!"0x100\00j\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] -!27 = !{!"0x100\00x\0061\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] -!28 = !{!"0x100\00y\0062\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] -!29 = !{!"0x100\00z\0063\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] -!30 = !{!"0x101\00F\0016777257\000", !14, !15, !31} ; [ DW_TAG_arg_variable ] -!31 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !32} ; [ DW_TAG_pointer_type ] -!32 = !{!"0x16\00FV\0025\000\000\000\000", !55, !2, !33} ; [ DW_TAG_typedef ] -!33 = !{!"0x17\00\0022\00128\00128\000\000\000", !55, !2, i32 0, !34, null} ; [ DW_TAG_union_type ] +!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7) +!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13) +!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21) +!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !22) +!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !23) +!23 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) +!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 60, scope: !25, file: !1, type: !13) +!25 = distinct !DILexicalBlock(line: 59, column: 33, file: !1, scope: !10) +!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 60, scope: !25, file: !1, type: !13) +!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 61, scope: !25, file: !1, type: !5) +!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 62, scope: !25, file: !1, type: !5) +!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z", line: 63, scope: !25, file: !1, type: !5) +!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31) +!31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !32) +!32 = !DIDerivedType(tag: DW_TAG_typedef, name: "FV", line: 25, file: !55, scope: !2, baseType: !33) +!33 = !DICompositeType(tag: DW_TAG_union_type, line: 22, size: 128, align: 128, file: !55, scope: !2, elements: !34) !34 = !{!35, !37} -!35 = !{!"0xd\00V\0023\00128\00128\000\000", !55, !15, !36} ; [ DW_TAG_member ] -!36 = !{!"0x16\00v4sf\003\000\000\000\000", !55, !2, !6} ; [ DW_TAG_typedef ] -!37 = !{!"0xd\00A\0024\00128\0032\000\000", !55, !15, !38} ; [ DW_TAG_member ] -!38 = !{!"0x1\00\000\00128\0032\000\000", null, !2, !7, !8, i32 0, i32 0} ; [ DW_TAG_array_type ] -!39 = !MDLocation(line: 79, column: 7, scope: !40) -!40 = !{!"0xb\0075\0035\0018", !1, !41} ; [ DW_TAG_lexical_block ] -!41 = !{!"0xb\0075\005\0017", !1, !42} ; [ DW_TAG_lexical_block ] -!42 = !{!"0xb\0071\0032\0016", !1, !43} ; [ DW_TAG_lexical_block ] -!43 = !{!"0xb\0071\003\0015", !1, !25} ; [ DW_TAG_lexical_block ] -!44 = !MDLocation(line: 75, column: 5, scope: !42) -!45 = !MDLocation(line: 42, column: 2, scope: !46, inlinedAt: !48) -!46 = !{!"0xb\0042\002\0020", !15, !47} ; [ DW_TAG_lexical_block ] -!47 = !{!"0xb\0041\0028\0019", !15, !14} ; [ DW_TAG_lexical_block ] -!48 = !MDLocation(line: 95, column: 3, scope: !25) -!49 = !MDLocation(line: 99, column: 3, scope: !25) +!35 = !DIDerivedType(tag: DW_TAG_member, name: "V", line: 23, size: 128, align: 128, file: !55, scope: !15, baseType: !36) +!36 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4sf", line: 3, file: !55, scope: !2, baseType: !6) +!37 = !DIDerivedType(tag: DW_TAG_member, name: "A", line: 24, size: 128, align: 32, file: !55, scope: !15, baseType: !38) +!38 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, scope: !2, baseType: !7, elements: !8) +!39 = !DILocation(line: 79, column: 7, scope: !40) +!40 = distinct !DILexicalBlock(line: 75, column: 35, file: !1, scope: !41) +!41 = distinct !DILexicalBlock(line: 75, column: 5, file: !1, scope: !42) +!42 = distinct !DILexicalBlock(line: 71, column: 32, file: !1, scope: !43) +!43 = distinct !DILexicalBlock(line: 71, column: 3, file: !1, scope: !25) +!44 = !DILocation(line: 75, column: 5, scope: !42) +!45 = !DILocation(line: 42, column: 2, scope: !46, inlinedAt: !48) +!46 = distinct !DILexicalBlock(line: 42, column: 2, file: !15, scope: !47) +!47 = distinct !DILexicalBlock(line: 41, column: 28, file: !15, scope: !14) +!48 = !DILocation(line: 95, column: 3, scope: !25) +!49 = !DILocation(line: 99, column: 3, scope: !25) !50 = !{!0, !10, !14} !51 = !{!18} !52 = !{!19, !20, !24, !26, !27, !28, !29} !53 = !{!30} -!54 = !{!"build2.c", !"/private/tmp"} -!55 = !{!"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", !"/private/tmp"} -!56 = !{i32 1, !"Debug Info Version", i32 2} +!54 = !DIFile(filename: "build2.c", directory: "/private/tmp") +!55 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") +!56 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index 85b510f175ee..27bd3b8639c4 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -12,21 +12,21 @@ target triple = "thumbv7-apple-darwin10" define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !26 - tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !26 - tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !26 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !19, metadata !DIExpression()), !dbg !26 + tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !20, metadata !DIExpression()), !dbg !26 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !21, metadata !DIExpression()), !dbg !26 %0 = zext i8 %c to i32, !dbg !27 - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 + %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 ret i32 0, !dbg !29 } define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline { entry: - tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !30 - tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !30 - tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !16, metadata !DIExpression()), !dbg !30 + tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !17, metadata !DIExpression()), !dbg !30 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !18, metadata !DIExpression()), !dbg !30 %0 = zext i8 %c to i32, !dbg !31 - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 + %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 ret i32 0, !dbg !33 } @@ -36,20 +36,20 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !34 - tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !34 + tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !22, metadata !DIExpression()), !dbg !34 + tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !23, metadata !DIExpression()), !dbg !34 %0 = sitofp i32 %argc to double, !dbg !35 %1 = fadd double %0, 5.555552e+05, !dbg !35 - tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !35 - %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36 - %3 = getelementptr inbounds i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37 + tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !24, metadata !DIExpression()), !dbg !35 + %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36 + %3 = getelementptr inbounds i8, i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37 %4 = trunc i32 %argc to i8, !dbg !37 %5 = add i8 %4, 97, !dbg !37 - tail call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !19, metadata !{!"0x102"}) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !20, metadata !{!"0x102"}) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata i8 %5, i64 0, metadata !21, metadata !{!"0x102"}) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !49, metadata !DIExpression()) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !50, metadata !DIExpression()) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata i8 %5, i64 0, metadata !51, metadata !DIExpression()) nounwind, !dbg !38 %6 = zext i8 %5 to i32, !dbg !39 - %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 + %7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 %8 = tail call i32 @printer(i8* %3, double %1, i8 zeroext %5) nounwind, !dbg !40 ret i32 0, !dbg !41 } @@ -59,52 +59,57 @@ declare i32 @puts(i8* nocapture) nounwind !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!48} -!0 = !{!"0x2e\00printer\00printer\00printer\0012\000\001\000\006\00256\001\0012", !46, !1, !3, null, i32 (i8*, double, i8)* @printer, null, null, !43} ; [ DW_TAG_subprogram ] -!1 = !{!"0x29", !46} ; [ DW_TAG_file_type ] -!2 = !{!"0x11\001\00(LLVM build 00)\001\00\000\00\001", !46, !47, !47, !42, null, null} ; [ DW_TAG_compile_unit ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !46, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DISubprogram(name: "printer", linkageName: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !46, scope: !1, type: !3, function: i32 (i8*, double, i8)* @printer, variables: !43) +!1 = !DIFile(filename: "a.c", directory: "/tmp/") +!2 = !DICompileUnit(language: DW_LANG_C89, producer: "(LLVM build 00)", isOptimized: true, emissionKind: 1, file: !46, enums: !47, retainedTypes: !47, subprograms: !42, imports: null) +!3 = !DISubroutineType(types: !4) !4 = !{!5, !6, !7, !8} -!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !46, !1} ; [ DW_TAG_base_type ] -!6 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, null} ; [ DW_TAG_pointer_type ] -!7 = !{!"0x24\00double\000\0064\0032\000\000\004", !46, !1} ; [ DW_TAG_base_type ] -!8 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !46, !1} ; [ DW_TAG_base_type ] -!9 = !{!"0x2e\00inlineprinter\00inlineprinter\00inlineprinter\005\000\001\000\006\00256\001\005", !46, !1, !3, null, i32 (i8*, double, i8)* @inlineprinter, null, null, !44} ; [ DW_TAG_subprogram ] -!10 = !{!"0x2e\00main\00main\00main\0018\000\001\000\006\00256\001\0018", !46, !1, !11, null, i32 (i32, i8**)* @main, null, null, !45} ; [ DW_TAG_subprogram ] -!11 = !{!"0x15\00\000\000\000\000\000\000", !46, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: null) +!7 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 32, encoding: DW_ATE_float) +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) +!9 = !DISubprogram(name: "inlineprinter", linkageName: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !46, scope: !1, type: !3, function: i32 (i8*, double, i8)* @inlineprinter, variables: !44) +!10 = !DISubprogram(name: "main", linkageName: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !46, scope: !1, type: !11, function: i32 (i32, i8**)* @main, variables: !45) +!11 = !DISubroutineType(types: !12) !12 = !{!5, !5, !13} -!13 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, !14} ; [ DW_TAG_pointer_type ] -!14 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, !15} ; [ DW_TAG_pointer_type ] -!15 = !{!"0x24\00char\000\008\008\000\000\006", !46, !1} ; [ DW_TAG_base_type ] -!16 = !{!"0x101\00ptr\0011\000", !0, !1, !6} ; [ DW_TAG_arg_variable ] -!17 = !{!"0x101\00val\0011\000", !0, !1, !7} ; [ DW_TAG_arg_variable ] -!18 = !{!"0x101\00c\0011\000", !0, !1, !8} ; [ DW_TAG_arg_variable ] -!19 = !{!"0x101\00ptr\004\000", !9, !1, !6} ; [ DW_TAG_arg_variable ] -!20 = !{!"0x101\00val\004\000", !9, !1, !7} ; [ DW_TAG_arg_variable ] -!21 = !{!"0x101\00c\004\000", !9, !1, !8} ; [ DW_TAG_arg_variable ] -!22 = !{!"0x101\00argc\0017\000", !10, !1, !5} ; [ DW_TAG_arg_variable ] -!23 = !{!"0x101\00argv\0017\000", !10, !1, !13} ; [ DW_TAG_arg_variable ] -!24 = !{!"0x100\00dval\0019\000", !25, !1, !7} ; [ DW_TAG_auto_variable ] -!25 = !{!"0xb\0018\000\002", !46, !10} ; [ DW_TAG_lexical_block ] -!26 = !MDLocation(line: 4, scope: !9) -!27 = !MDLocation(line: 6, scope: !28) -!28 = !{!"0xb\005\000\001", !46, !9} ; [ DW_TAG_lexical_block ] -!29 = !MDLocation(line: 7, scope: !28) -!30 = !MDLocation(line: 11, scope: !0) -!31 = !MDLocation(line: 13, scope: !32) -!32 = !{!"0xb\0012\000\000", !46, !0} ; [ DW_TAG_lexical_block ] -!33 = !MDLocation(line: 14, scope: !32) -!34 = !MDLocation(line: 17, scope: !10) -!35 = !MDLocation(line: 19, scope: !25) -!36 = !MDLocation(line: 20, scope: !25) -!37 = !MDLocation(line: 21, scope: !25) -!38 = !MDLocation(line: 4, scope: !9, inlinedAt: !37) -!39 = !MDLocation(line: 6, scope: !28, inlinedAt: !37) -!40 = !MDLocation(line: 22, scope: !25) -!41 = !MDLocation(line: 23, scope: !25) +!13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !14) +!14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !15) +!15 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) +!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !0, file: !1, type: !6) +!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !0, file: !1, type: !7) +!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !0, file: !1, type: !8) +!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) +!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) +!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !9, file: !1, type: !8) + +!49 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) +!50 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) +!51 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 2, scope: !9, file: !1, type: !8) + +!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 17, arg: 0, scope: !10, file: !1, type: !5) +!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 17, arg: 0, scope: !10, file: !1, type: !13) +!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dval", line: 19, scope: !25, file: !1, type: !7) +!25 = distinct !DILexicalBlock(line: 18, column: 0, file: !46, scope: !10) +!26 = !DILocation(line: 4, scope: !9) +!27 = !DILocation(line: 6, scope: !28) +!28 = distinct !DILexicalBlock(line: 5, column: 0, file: !46, scope: !9) +!29 = !DILocation(line: 7, scope: !28) +!30 = !DILocation(line: 11, scope: !0) +!31 = !DILocation(line: 13, scope: !32) +!32 = distinct !DILexicalBlock(line: 12, column: 0, file: !46, scope: !0) +!33 = !DILocation(line: 14, scope: !32) +!34 = !DILocation(line: 17, scope: !10) +!35 = !DILocation(line: 19, scope: !25) +!36 = !DILocation(line: 20, scope: !25) +!37 = !DILocation(line: 21, scope: !25) +!38 = !DILocation(line: 4, scope: !9, inlinedAt: !37) +!39 = !DILocation(line: 6, scope: !28, inlinedAt: !37) +!40 = !DILocation(line: 22, scope: !25) +!41 = !DILocation(line: 23, scope: !25) !42 = !{!0, !9, !10} !43 = !{!16, !17, !18} !44 = !{!19, !20, !21} !45 = !{!22, !23, !24} -!46 = !{!"a.c", !"/tmp/"} -!47 = !{i32 0} -!48 = !{i32 1, !"Debug Info Version", i32 2} +!46 = !DIFile(filename: "a.c", directory: "/tmp/") +!47 = !{} +!48 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-no-frame.ll b/test/CodeGen/ARM/debug-info-no-frame.ll new file mode 100644 index 000000000000..e00563cc47c4 --- /dev/null +++ b/test/CodeGen/ARM/debug-info-no-frame.ll @@ -0,0 +1,36 @@ +; RUN: llc -mtriple=armv7-none-linux-gnueabihf < %s -o - | FileCheck %s + +; Function Attrs: nounwind +define void @need_cfi_def_cfa_offset() #0 { +; CHECK-LABEL: need_cfi_def_cfa_offset: +; CHECK: sub sp, sp, #4 +; CHECK: .cfi_def_cfa_offset 4 +entry: + %Depth = alloca i32, align 4 + call void @llvm.dbg.declare(metadata i32* %Depth, metadata !9, metadata !10), !dbg !11 + store i32 2, i32* %Depth, align 4, !dbg !11 + ret void, !dbg !12 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} + +!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false) +!1 = !DIFile(filename: "file.c", directory: "/dir") +!2 = !{} +!3 = !DISubprogram(name: "need_cfi_def_cfa_offset", scope: !1, file: !1, line: 1, type: !4, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @need_cfi_def_cfa_offset, variables: !2) +!4 = !DISubroutineType(types: !5) +!5 = !{null} +!6 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!7 = !{i32 2, !"Dwarf Version", i32 4} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Depth", scope: !3, file: !1, line: 3, type: !6) +!10 = !DIExpression() +!11 = !DILocation(line: 3, column: 9, scope: !3) +!12 = !DILocation(line: 7, column: 5, scope: !3) diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index c05df6ab3d51..665818fc0b2e 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -3,13 +3,13 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- target triple = "thumbv7-apple-macosx10.6.7" ;CHECK: sub-register DW_OP_regx -;CHECK-NEXT: ascii +;CHECK-NEXT: 256 ;CHECK-NEXT: DW_OP_piece -;CHECK-NEXT: byte 8 +;CHECK-NEXT: 8 ;CHECK-NEXT: sub-register DW_OP_regx -;CHECK-NEXT: ascii +;CHECK-NEXT: 257 ;CHECK-NEXT: DW_OP_piece -;CHECK-NEXT: byte 8 +;CHECK-NEXT: 8 @.str = external constant [13 x i8] @@ -24,10 +24,10 @@ for.body9: ; preds = %for.body9, %entry br i1 undef, label %for.end54, label %for.body9, !dbg !44 for.end54: ; preds = %for.body9 - tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !DIExpression()), !dbg !39 %tmp115 = extractelement <4 x float> %add19, i32 1 %conv6.i75 = fpext float %tmp115 to double, !dbg !45 - %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 + %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 ret i32 0, !dbg !49 } @@ -38,60 +38,60 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!56} -!0 = !{!"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\003", !54, !1, !3, null, <4 x float> (float)* @test0001, null, null, !51} ; [ DW_TAG_subprogram ] [line 3] [def] [test0001] -!1 = !{!"0x29", !54} ; [ DW_TAG_file_type ] -!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !54, !17, !17, !50, null, null} ; [ DW_TAG_compile_unit ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !54, scope: !1, type: !3, function: <4 x float> (float)* @test0001, variables: !51) +!1 = !DIFile(filename: "build2.c", directory: "/private/tmp") +!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) +!3 = !DISubroutineType(types: !4) !4 = !{!5} -!5 = !{!"0x16\00v4f32\0014\000\000\000\000", !54, !2, !6} ; [ DW_TAG_typedef ] -!6 = !{!"0x1\00\000\00128\00128\000\000", !2, null, !7, !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] -!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ] +!5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) +!6 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 128, file: !1, baseType: !7, elements: !8) +!7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !8 = !{!9} -!9 = !{!"0x21\000\004"} ; [ DW_TAG_subrange_type ] -!10 = !{!"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\0059", !54, !1, !11, null, i32 (i32, i8**)* @main, null, null, !52} ; [ DW_TAG_subprogram ] [line 59] [def] [main] -!11 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!9 = !DISubrange(count: 4) +!10 = !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 59, file: !54, scope: !1, type: !11, function: i32 (i32, i8**)* @main, variables: !52) +!11 = !DISubroutineType(types: !12) !12 = !{!13} -!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ] -!14 = !{!"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\0041", !55, !15, !16, null, null, null, null, !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [printFV] -!15 = !{!"0x29", !55} ; [ DW_TAG_file_type ] -!16 = !{!"0x15\00\000\000\000\000\000\000", !55, !15, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!14 = !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 41, file: !55, scope: !15, type: !16, variables: !53) +!15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") +!16 = !DISubroutineType(types: !17) !17 = !{null} -!18 = !{!"0x101\00a\0016777219\000", !0, !1, !7} ; [ DW_TAG_arg_variable ] -!19 = !{!"0x101\00argc\0016777275\000", !10, !1, !13} ; [ DW_TAG_arg_variable ] -!20 = !{!"0x101\00argv\0033554491\000", !10, !1, !21} ; [ DW_TAG_arg_variable ] -!21 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !22} ; [ DW_TAG_pointer_type ] -!22 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !23} ; [ DW_TAG_pointer_type ] -!23 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ] -!24 = !{!"0x100\00i\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] -!25 = !{!"0xb\0059\0033\0014", !54, !10} ; [ DW_TAG_lexical_block ] -!26 = !{!"0x100\00j\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] -!27 = !{!"0x100\00x\0061\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] -!28 = !{!"0x100\00y\0062\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] -!29 = !{!"0x100\00z\0063\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] -!30 = !{!"0x101\00F\0016777257\000", !14, !15, !31} ; [ DW_TAG_arg_variable ] -!31 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !32} ; [ DW_TAG_pointer_type ] -!32 = !{!"0x16\00FV\0025\000\000\000\000", !55, !2, !33} ; [ DW_TAG_typedef ] -!33 = !{!"0x17\00\0022\00128\00128\000\000\000", !55, !2, i32 0, !34, null} ; [ DW_TAG_union_type ] +!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7) +!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13) +!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21) +!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !22) +!22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !23) +!23 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) +!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 60, scope: !25, file: !1, type: !13) +!25 = distinct !DILexicalBlock(line: 59, column: 33, file: !54, scope: !10) +!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 60, scope: !25, file: !1, type: !13) +!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 61, scope: !25, file: !1, type: !5) +!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 62, scope: !25, file: !1, type: !5) +!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z", line: 63, scope: !25, file: !1, type: !5) +!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31) +!31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !32) +!32 = !DIDerivedType(tag: DW_TAG_typedef, name: "FV", line: 25, file: !55, scope: !2, baseType: !33) +!33 = !DICompositeType(tag: DW_TAG_union_type, line: 22, size: 128, align: 128, file: !55, scope: !2, elements: !34) !34 = !{!35, !37} -!35 = !{!"0xd\00V\0023\00128\00128\000\000", !55, !15, !36} ; [ DW_TAG_member ] -!36 = !{!"0x16\00v4sf\003\000\000\000\000", !55, !2, !6} ; [ DW_TAG_typedef ] -!37 = !{!"0xd\00A\0024\00128\0032\000\000", !55, !15, !38} ; [ DW_TAG_member ] -!38 = !{!"0x1\00\000\00128\0032\000\000", null, !2, !7, !8, i32 0, i32 0} ; [ DW_TAG_array_type ] -!39 = !MDLocation(line: 79, column: 7, scope: !40) -!40 = !{!"0xb\0075\0035\0018", !54, !41} ; [ DW_TAG_lexical_block ] -!41 = !{!"0xb\0075\005\0017", !54, !42} ; [ DW_TAG_lexical_block ] -!42 = !{!"0xb\0071\0032\0016", !54, !43} ; [ DW_TAG_lexical_block ] -!43 = !{!"0xb\0071\003\0015", !54, !25} ; [ DW_TAG_lexical_block ] -!44 = !MDLocation(line: 75, column: 5, scope: !42) -!45 = !MDLocation(line: 42, column: 2, scope: !46, inlinedAt: !48) -!46 = !{!"0xb\0042\002\0020", !55, !47} ; [ DW_TAG_lexical_block ] -!47 = !{!"0xb\0041\0028\0019", !55, !14} ; [ DW_TAG_lexical_block ] -!48 = !MDLocation(line: 95, column: 3, scope: !25) -!49 = !MDLocation(line: 99, column: 3, scope: !25) +!35 = !DIDerivedType(tag: DW_TAG_member, name: "V", line: 23, size: 128, align: 128, file: !55, scope: !15, baseType: !36) +!36 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4sf", line: 3, file: !55, scope: !2, baseType: !6) +!37 = !DIDerivedType(tag: DW_TAG_member, name: "A", line: 24, size: 128, align: 32, file: !55, scope: !15, baseType: !38) +!38 = !DICompositeType(tag: DW_TAG_array_type, size: 128, align: 32, scope: !2, baseType: !7, elements: !8) +!39 = !DILocation(line: 79, column: 7, scope: !40) +!40 = distinct !DILexicalBlock(line: 75, column: 35, file: !54, scope: !41) +!41 = distinct !DILexicalBlock(line: 75, column: 5, file: !54, scope: !42) +!42 = distinct !DILexicalBlock(line: 71, column: 32, file: !54, scope: !43) +!43 = distinct !DILexicalBlock(line: 71, column: 3, file: !54, scope: !25) +!44 = !DILocation(line: 75, column: 5, scope: !42) +!45 = !DILocation(line: 42, column: 2, scope: !46, inlinedAt: !48) +!46 = distinct !DILexicalBlock(line: 42, column: 2, file: !55, scope: !47) +!47 = distinct !DILexicalBlock(line: 41, column: 28, file: !55, scope: !14) +!48 = !DILocation(line: 95, column: 3, scope: !25) +!49 = !DILocation(line: 99, column: 3, scope: !25) !50 = !{!0, !10, !14} !51 = !{!18} !52 = !{!19, !20, !24, !26, !27, !28, !29} !53 = !{!30} -!54 = !{!"build2.c", !"/private/tmp"} -!55 = !{!"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", !"/private/tmp"} -!56 = !{i32 1, !"Debug Info Version", i32 2} +!54 = !DIFile(filename: "build2.c", directory: "/private/tmp") +!55 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") +!56 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index 9b303dde2e35..ec080f20db9c 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -2,7 +2,7 @@ ; Radar 9309221 ; Test dwarf reg no for s16 ;CHECK: super-register DW_OP_regx -;CHECK-NEXT: ascii +;CHECK-NEXT: 264 ;CHECK-NEXT: DW_OP_piece ;CHECK-NEXT: 4 @@ -14,12 +14,12 @@ target triple = "thumbv7-apple-macosx10.6.7" define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !24 - tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !25 - tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !26 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !8, metadata !DIExpression()), !dbg !24 + tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !10, metadata !DIExpression()), !dbg !25 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !12, metadata !DIExpression()), !dbg !26 %conv = fpext float %val to double, !dbg !27 %conv3 = zext i8 %c to i32, !dbg !27 - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 ret i32 0, !dbg !29 } @@ -27,33 +27,33 @@ declare i32 @printf(i8* nocapture, ...) nounwind optsize define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp { entry: - tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !30 - tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !31 - tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !32 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !14, metadata !DIExpression()), !dbg !30 + tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !15, metadata !DIExpression()), !dbg !31 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !16, metadata !DIExpression()), !dbg !32 %conv = fpext float %val to double, !dbg !33 %conv3 = zext i8 %c to i32, !dbg !33 - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 ret i32 0, !dbg !35 } define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !36 - tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !37 + tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !17, metadata !DIExpression()), !dbg !36 + tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !18, metadata !DIExpression()), !dbg !37 %conv = sitofp i32 %argc to double, !dbg !38 %add = fadd double %conv, 5.555552e+05, !dbg !38 %conv1 = fptrunc double %add to float, !dbg !38 - tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !38 - %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39 - %add.ptr = getelementptr i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40 + tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !22, metadata !DIExpression()), !dbg !38 + %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39 + %add.ptr = getelementptr i8, i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40 %add5 = add nsw i32 %argc, 97, !dbg !40 %conv6 = trunc i32 %add5 to i8, !dbg !40 - tail call void @llvm.dbg.value(metadata i8* %add.ptr, i64 0, metadata !8, metadata !{!"0x102"}) nounwind, !dbg !41 - tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !10, metadata !{!"0x102"}) nounwind, !dbg !42 - tail call void @llvm.dbg.value(metadata i8 %conv6, i64 0, metadata !12, metadata !{!"0x102"}) nounwind, !dbg !43 + tail call void @llvm.dbg.value(metadata i8* %add.ptr, i64 0, metadata !58, metadata !DIExpression()) nounwind, !dbg !41 + tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !60, metadata !DIExpression()) nounwind, !dbg !42 + tail call void @llvm.dbg.value(metadata i8 %conv6, i64 0, metadata !62, metadata !DIExpression()) nounwind, !dbg !43 %conv.i = fpext float %conv1 to double, !dbg !44 %conv3.i = and i32 %add5, 255, !dbg !44 - %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 + %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 %call14 = tail call i32 @printer(i8* %add.ptr, float %conv1, i8 zeroext %conv6) optsize, !dbg !45 ret i32 0, !dbg !46 } @@ -65,57 +65,62 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!53} -!0 = !{!"0x2e\00inlineprinter\00inlineprinter\00\005\000\001\000\006\00256\001\005", !51, !1, !3, null, i32 (i8*, float, i8)* @inlineprinter, null, null, !48} ; [ DW_TAG_subprogram ] [line 5] [def] [inlineprinter] -!1 = !{!"0x29", !51} ; [ DW_TAG_file_type ] -!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !51, !52, !52, !47, null, null} ; [ DW_TAG_compile_unit ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !51, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DISubprogram(name: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !51, scope: !1, type: !3, function: i32 (i8*, float, i8)* @inlineprinter, variables: !48) +!1 = !DIFile(filename: "a.c", directory: "/private/tmp") +!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !51, enums: !52, retainedTypes: !52, subprograms: !47, imports: null) +!3 = !DISubroutineType(types: !4) !4 = !{!5} -!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ] -!6 = !{!"0x2e\00printer\00printer\00\0012\000\001\000\006\00256\001\0012", !51, !1, !3, null, i32 (i8*, float, i8)* @printer, null, null, !49} ; [ DW_TAG_subprogram ] [line 12] [def] [printer] -!7 = !{!"0x2e\00main\00main\00\0018\000\001\000\006\00256\001\0018", !51, !1, !3, null, i32 (i32, i8**)* @main, null, null, !50} ; [ DW_TAG_subprogram ] [line 18] [def] [main] -!8 = !{!"0x101\00ptr\0016777220\000", !0, !1, !9} ; [ DW_TAG_arg_variable ] -!9 = !{!"0xf\00\000\0032\0032\000\000", null, !2, null} ; [ DW_TAG_pointer_type ] -!10 = !{!"0x101\00val\0033554436\000", !0, !1, !11} ; [ DW_TAG_arg_variable ] -!11 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ] -!12 = !{!"0x101\00c\0050331652\000", !0, !1, !13} ; [ DW_TAG_arg_variable ] -!13 = !{!"0x24\00unsigned char\000\008\008\000\000\008", null, !2} ; [ DW_TAG_base_type ] -!14 = !{!"0x101\00ptr\0016777227\000", !6, !1, !9} ; [ DW_TAG_arg_variable ] -!15 = !{!"0x101\00val\0033554443\000", !6, !1, !11} ; [ DW_TAG_arg_variable ] -!16 = !{!"0x101\00c\0050331659\000", !6, !1, !13} ; [ DW_TAG_arg_variable ] -!17 = !{!"0x101\00argc\0016777233\000", !7, !1, !5} ; [ DW_TAG_arg_variable ] -!18 = !{!"0x101\00argv\0033554449\000", !7, !1, !19} ; [ DW_TAG_arg_variable ] -!19 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !20} ; [ DW_TAG_pointer_type ] -!20 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !21} ; [ DW_TAG_pointer_type ] -!21 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ] -!22 = !{!"0x100\00dval\0019\000", !23, !1, !11} ; [ DW_TAG_auto_variable ] -!23 = !{!"0xb\0018\001\002", !51, !7} ; [ DW_TAG_lexical_block ] -!24 = !MDLocation(line: 4, column: 22, scope: !0) -!25 = !MDLocation(line: 4, column: 33, scope: !0) -!26 = !MDLocation(line: 4, column: 52, scope: !0) -!27 = !MDLocation(line: 6, column: 3, scope: !28) -!28 = !{!"0xb\005\001\000", !51, !0} ; [ DW_TAG_lexical_block ] -!29 = !MDLocation(line: 7, column: 3, scope: !28) -!30 = !MDLocation(line: 11, column: 42, scope: !6) -!31 = !MDLocation(line: 11, column: 53, scope: !6) -!32 = !MDLocation(line: 11, column: 72, scope: !6) -!33 = !MDLocation(line: 13, column: 3, scope: !34) -!34 = !{!"0xb\0012\001\001", !51, !6} ; [ DW_TAG_lexical_block ] -!35 = !MDLocation(line: 14, column: 3, scope: !34) -!36 = !MDLocation(line: 17, column: 15, scope: !7) -!37 = !MDLocation(line: 17, column: 28, scope: !7) -!38 = !MDLocation(line: 19, column: 31, scope: !23) -!39 = !MDLocation(line: 20, column: 3, scope: !23) -!40 = !MDLocation(line: 21, column: 3, scope: !23) -!41 = !MDLocation(line: 4, column: 22, scope: !0, inlinedAt: !40) -!42 = !MDLocation(line: 4, column: 33, scope: !0, inlinedAt: !40) -!43 = !MDLocation(line: 4, column: 52, scope: !0, inlinedAt: !40) -!44 = !MDLocation(line: 6, column: 3, scope: !28, inlinedAt: !40) -!45 = !MDLocation(line: 22, column: 3, scope: !23) -!46 = !MDLocation(line: 23, column: 1, scope: !23) +!5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!6 = !DISubprogram(name: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !51, scope: !1, type: !3, function: i32 (i8*, float, i8)* @printer, variables: !49) +!7 = !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !51, scope: !1, type: !3, function: i32 (i32, i8**)* @main, variables: !50) +!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: null) +!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) +!11 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) +!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) +!13 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) + +!58 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) +!60 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) +!62 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) + +!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !6, file: !1, type: !9) +!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !6, file: !1, type: !11) +!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !6, file: !1, type: !13) +!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 17, arg: 1, scope: !7, file: !1, type: !5) +!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 17, arg: 2, scope: !7, file: !1, type: !19) +!19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !20) +!20 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !21) +!21 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) +!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dval", line: 19, scope: !23, file: !1, type: !11) +!23 = distinct !DILexicalBlock(line: 18, column: 1, file: !51, scope: !7) +!24 = !DILocation(line: 4, column: 22, scope: !0) +!25 = !DILocation(line: 4, column: 33, scope: !0) +!26 = !DILocation(line: 4, column: 52, scope: !0) +!27 = !DILocation(line: 6, column: 3, scope: !28) +!28 = distinct !DILexicalBlock(line: 5, column: 1, file: !51, scope: !0) +!29 = !DILocation(line: 7, column: 3, scope: !28) +!30 = !DILocation(line: 11, column: 42, scope: !6) +!31 = !DILocation(line: 11, column: 53, scope: !6) +!32 = !DILocation(line: 11, column: 72, scope: !6) +!33 = !DILocation(line: 13, column: 3, scope: !34) +!34 = distinct !DILexicalBlock(line: 12, column: 1, file: !51, scope: !6) +!35 = !DILocation(line: 14, column: 3, scope: !34) +!36 = !DILocation(line: 17, column: 15, scope: !7) +!37 = !DILocation(line: 17, column: 28, scope: !7) +!38 = !DILocation(line: 19, column: 31, scope: !23) +!39 = !DILocation(line: 20, column: 3, scope: !23) +!40 = !DILocation(line: 21, column: 3, scope: !23) +!41 = !DILocation(line: 4, column: 22, scope: !0, inlinedAt: !40) +!42 = !DILocation(line: 4, column: 33, scope: !0, inlinedAt: !40) +!43 = !DILocation(line: 4, column: 52, scope: !0, inlinedAt: !40) +!44 = !DILocation(line: 6, column: 3, scope: !28, inlinedAt: !40) +!45 = !DILocation(line: 22, column: 3, scope: !23) +!46 = !DILocation(line: 23, column: 1, scope: !23) !47 = !{!0, !6, !7} !48 = !{!8, !10, !12} !49 = !{!14, !15, !16} !50 = !{!17, !18, !22} -!51 = !{!"a.c", !"/private/tmp"} -!52 = !{i32 0} -!53 = !{i32 1, !"Debug Info Version", i32 2} +!51 = !DIFile(filename: "a.c", directory: "/private/tmp") +!52 = !{} +!53 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index 977a6f27677c..f22559efad4d 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -15,7 +15,7 @@ target triple = "thumbv7-apple-macosx10.6.7" define void @_Z3foov() optsize ssp { entry: %call = tail call float @_Z3barv() optsize, !dbg !11 - tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !11 + tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !DIExpression()), !dbg !11 %call16 = tail call float @_Z2f2v() optsize, !dbg !12 %cmp7 = fcmp olt float %call, %call16, !dbg !12 br i1 %cmp7, label %for.body, label %for.end, !dbg !12 @@ -43,24 +43,24 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!20} -!0 = !{!"0x11\004\00clang version 3.0 (trunk 130845)\001\00\000\00\001", !18, !19, !19, !16, null, null} ; [ DW_TAG_compile_unit ] -!1 = !{!"0x2e\00foo\00foo\00_Z3foov\005\000\001\000\006\00256\001\005", !18, !2, !3, null, void ()* @_Z3foov, null, null, !17} ; [ DW_TAG_subprogram ] [line 5] [def] [foo] -!2 = !{!"0x29", !18} ; [ DW_TAG_file_type ] -!3 = !{!"0x15\00\000\000\000\000\000\000", !18, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130845)", isOptimized: true, emissionKind: 1, file: !18, enums: !19, retainedTypes: !19, subprograms: !16, imports: null) +!1 = !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !18, scope: !2, type: !3, function: void ()* @_Z3foov, variables: !17) +!2 = !DIFile(filename: "k.cc", directory: "/private/tmp") +!3 = !DISubroutineType(types: !4) !4 = !{null} -!5 = !{!"0x100\00k\006\000", !6, !2, !7} ; [ DW_TAG_auto_variable ] -!6 = !{!"0xb\005\0012\000", !18, !1} ; [ DW_TAG_lexical_block ] -!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !0} ; [ DW_TAG_base_type ] -!8 = !{!"0x100\00y\008\000", !9, !2, !7} ; [ DW_TAG_auto_variable ] -!9 = !{!"0xb\007\0025\002", !18, !10} ; [ DW_TAG_lexical_block ] -!10 = !{!"0xb\007\003\001", !18, !6} ; [ DW_TAG_lexical_block ] -!11 = !MDLocation(line: 6, column: 18, scope: !6) -!12 = !MDLocation(line: 7, column: 3, scope: !6) -!13 = !MDLocation(line: 8, column: 20, scope: !9) -!14 = !MDLocation(line: 7, column: 20, scope: !10) -!15 = !MDLocation(line: 10, column: 1, scope: !6) +!5 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 6, scope: !6, file: !2, type: !7) +!6 = distinct !DILexicalBlock(line: 5, column: 12, file: !18, scope: !1) +!7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) +!8 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 8, scope: !9, file: !2, type: !7) +!9 = distinct !DILexicalBlock(line: 7, column: 25, file: !18, scope: !10) +!10 = distinct !DILexicalBlock(line: 7, column: 3, file: !18, scope: !6) +!11 = !DILocation(line: 6, column: 18, scope: !6) +!12 = !DILocation(line: 7, column: 3, scope: !6) +!13 = !DILocation(line: 8, column: 20, scope: !9) +!14 = !DILocation(line: 7, column: 20, scope: !10) +!15 = !DILocation(line: 10, column: 1, scope: !6) !16 = !{!1} !17 = !{!5, !8} -!18 = !{!"k.cc", !"/private/tmp"} -!19 = !{i32 0} -!20 = !{i32 1, !"Debug Info Version", i32 2} +!18 = !DIFile(filename: "k.cc", directory: "/private/tmp") +!19 = !{} +!20 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-segmented-stacks.ll b/test/CodeGen/ARM/debug-segmented-stacks.ll index 7ea5665a7a9b..47d366e49ded 100644 --- a/test/CodeGen/ARM/debug-segmented-stacks.ll +++ b/test/CodeGen/ARM/debug-segmented-stacks.ll @@ -39,40 +39,40 @@ define void @test_basic() #0 { ; ARM-linux .cfi_same_value r5 } -!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99] -!1 = !{!"var.c", !"/tmp"} +!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!1 = !DIFile(filename: "var.c", directory: "/tmp") !2 = !{} !3 = !{!4} -!4 = !{!"0x2e\00test_basic\00test_basic\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, void ()* @test_basic, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum] -!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/var.c] -!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !DISubprogram(name: "test_basic", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: void ()* @test_basic, variables: !2) +!5 = !DIFile(filename: "var.c", directory: "/tmp") +!6 = !DISubroutineType(types: !7) !7 = !{!8, !8} -!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !9 = !{i32 2, !"Dwarf Version", i32 4} -!10 = !{i32 1, !"Debug Info Version", i32 2} +!10 = !{i32 1, !"Debug Info Version", i32 3} !11 = !{!"clang version 3.5 "} -!12 = !{!"0x101\00count\0016777221\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [count] [line 5] -!13 = !MDLocation(line: 5, scope: !4) -!14 = !{!"0x100\00vl\006\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [vl] [line 6] -!15 = !{!"0x16\00va_list\0030\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list] -!16 = !{!"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", !"/tmp"} -!17 = !{!"0x16\00__builtin_va_list\006\000\000\000\000", !1, null, !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list] -!18 = !{!"0x13\00__va_list\006\0032\0032\000\000\000", !1, null, null, !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ] +!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8) +!13 = !DILocation(line: 5, scope: !4) +!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vl", line: 6, scope: !4, file: !5, type: !15) +!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "va_list", line: 30, file: !16, baseType: !17) +!16 = !DIFile(filename: "/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", directory: "/tmp") +!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__builtin_va_list", line: 6, file: !1, baseType: !18) +!18 = !DICompositeType(tag: DW_TAG_structure_type, name: "__va_list", line: 6, size: 32, align: 32, file: !1, elements: !19) !19 = !{!20} -!20 = !{!"0xd\00__ap\006\0032\0032\000\000", !1, !18, !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ] -!21 = !{!"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ] -!22 = !MDLocation(line: 6, scope: !4) -!23 = !MDLocation(line: 7, scope: !4) -!24 = !{!"0x100\00test_basic\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [sum] [line 8] -!25 = !MDLocation(line: 8, scope: !4) -!26 = !{!"0x100\00i\009\000", !27, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 9] -!27 = !{!"0xb\009\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!28 = !MDLocation(line: 9, scope: !27) -!29 = !MDLocation(line: 10, scope: !30) -!30 = !{!"0xb\009\000\001", !1, !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!31 = !MDLocation(line: 11, scope: !30) -!32 = !MDLocation(line: 12, scope: !4) -!33 = !MDLocation(line: 13, scope: !4) +!20 = !DIDerivedType(tag: DW_TAG_member, name: "__ap", line: 6, size: 32, align: 32, file: !1, scope: !18, baseType: !21) +!21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: null) +!22 = !DILocation(line: 6, scope: !4) +!23 = !DILocation(line: 7, scope: !4) +!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "test_basic", line: 8, scope: !4, file: !5, type: !8) +!25 = !DILocation(line: 8, scope: !4) +!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 9, scope: !27, file: !5, type: !8) +!27 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !4) +!28 = !DILocation(line: 9, scope: !27) +!29 = !DILocation(line: 10, scope: !30) +!30 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !27) +!31 = !DILocation(line: 11, scope: !30) +!32 = !DILocation(line: 12, scope: !4) +!33 = !DILocation(line: 13, scope: !4) ; Just to prevent the alloca from being optimized away declare void @dummy_use(i32*, i32) diff --git a/test/CodeGen/ARM/disable-fp-elim.ll b/test/CodeGen/ARM/disable-fp-elim.ll new file mode 100644 index 000000000000..dafeda2ac762 --- /dev/null +++ b/test/CodeGen/ARM/disable-fp-elim.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -O1 | FileCheck %s --check-prefix=DISABLE-FP-ELIM +; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -disable-fp-elim -O1 | FileCheck %s --check-prefix=DISABLE-FP-ELIM +; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -disable-fp-elim=false -O1 | FileCheck %s --check-prefix=ENABLE-FP-ELIM +; RUN: llc < %s -mtriple armv7-none-linux-gnueabi -disable-fp-elim=false -O0 | FileCheck %s --check-prefix=DISABLE-FP-ELIM + +; Check that command line option "-disable-fp-elim" overrides function attribute +; "no-frame-pointer-elim". Also, check frame pointer elimination is disabled +; when fast-isel is used. + +; ENABLE-FP-ELIM-NOT: .setfp +; DISABLE-FP-ELIM: .setfp r11, sp + +define i32 @foo1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) #0 { +entry: + %call = tail call i32 @foo2(i32 %a) + %add = add i32 %c, %b + %add1 = add i32 %add, %d + %add2 = add i32 %add1, %e + %add3 = add i32 %add2, %call + ret i32 %add3 +} + +declare i32 @foo2(i32) + +attributes #0 = { nounwind "no-frame-pointer-elim"="true" } diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index a339c816c578..7b298fee42a5 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,11 +1,13 @@ -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV define i32 @f1(i32 %a, i32 %b) { entry: -; CHECK-ARM: f1 -; CHECK-ARM: __divsi3 +; CHECK-SWDIV: f1 +; CHECK-SWDIV: __divsi3 ; CHECK-HWDIV: f1 ; CHECK-HWDIV: sdiv @@ -15,8 +17,8 @@ entry: define i32 @f2(i32 %a, i32 %b) { entry: -; CHECK-ARM: f2 -; CHECK-ARM: __udivsi3 +; CHECK-SWDIV: f2 +; CHECK-SWDIV: __udivsi3 ; CHECK-HWDIV: f2 ; CHECK-HWDIV: udiv @@ -26,8 +28,8 @@ entry: define i32 @f3(i32 %a, i32 %b) { entry: -; CHECK-ARM: f3 -; CHECK-ARM: __modsi3 +; CHECK-SWDIV: f3 +; CHECK-SWDIV: __modsi3 ; CHECK-HWDIV: f3 ; CHECK-HWDIV: sdiv @@ -38,8 +40,8 @@ entry: define i32 @f4(i32 %a, i32 %b) { entry: -; CHECK-ARM: f4 -; CHECK-ARM: __umodsi3 +; CHECK-SWDIV: f4 +; CHECK-SWDIV: __umodsi3 ; CHECK-HWDIV: f4 ; CHECK-HWDIV: udiv diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll index 7be0c796bd21..9336d0c477d1 100644 --- a/test/CodeGen/ARM/divmod.ll +++ b/test/CodeGen/ARM/divmod.ll @@ -16,7 +16,7 @@ entry: %div = sdiv i32 %x, %y store i32 %div, i32* %P, align 4 %rem = srem i32 %x, %y - %arrayidx6 = getelementptr inbounds i32* %P, i32 1 + %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1 store i32 %rem, i32* %arrayidx6, align 4 ret void } @@ -34,7 +34,7 @@ entry: %div = udiv i32 %x, %y store i32 %div, i32* %P, align 4 %rem = urem i32 %x, %y - %arrayidx6 = getelementptr inbounds i32* %P, i32 1 + %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1 store i32 %rem, i32* %arrayidx6, align 4 ret void } @@ -47,7 +47,7 @@ define void @do_indent(i32 %cols) nounwind { entry: ; A8-LABEL: do_indent: ; SWIFT-LABEL: do_indent: - %0 = load i32* @flags, align 4 + %0 = load i32, i32* @flags, align 4 %1 = and i32 %0, 67108864 %2 = icmp eq i32 %1, 0 br i1 %2, label %bb1, label %bb @@ -57,7 +57,7 @@ bb: ; SWIFT: sdiv ; SWIFT: mls ; SWIFT-NOT: bl __divmodsi4 - %3 = load i32* @tabsize, align 4 + %3 = load i32, i32* @tabsize, align 4 %4 = srem i32 %cols, %3 %5 = sdiv i32 %cols, %3 %6 = tail call i32 @llvm.objectsize.i32.p0i8(i8* null, i1 false) @@ -66,7 +66,7 @@ bb: bb1: %line_indent_len.0 = phi i32 [ %4, %bb ], [ 0, %entry ] - %8 = getelementptr inbounds i8* null, i32 %line_indent_len.0 + %8 = getelementptr inbounds i8, i8* null, i32 %line_indent_len.0 store i8 0, i8* %8, align 1 ret void } diff --git a/test/CodeGen/ARM/dwarf-eh.ll b/test/CodeGen/ARM/dwarf-eh.ll index 0b8a072ec95c..c890206b3532 100644 --- a/test/CodeGen/ARM/dwarf-eh.ll +++ b/test/CodeGen/ARM/dwarf-eh.ll @@ -2,6 +2,10 @@ ; RUN: FileCheck %s ; RUN: llc -mtriple=arm-netbsd-eabi -o - -filetype=asm %s \ ; RUN: -relocation-model=pic | FileCheck -check-prefix=CHECK-PIC %s +; RUN: llc -mtriple=armv7-bitrig-gnueabihf -o - -filetype=asm %s | \ +; RUN: FileCheck %s +; RUN: llc -mtriple=armv7-bitrig-gnueabihf -o - -filetype=asm %s \ +; RUN: -relocation-model=pic | FileCheck -check-prefix=CHECK-PIC %s ; ModuleID = 'test.cc' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" @@ -11,7 +15,7 @@ target triple = "armv5e--netbsd-eabi" @_ZTVN10__cxxabiv117__class_type_infoE = external global i8* @_ZTS9exception = linkonce_odr constant [11 x i8] c"9exception\00" -@_ZTI9exception = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([11 x i8]* @_ZTS9exception, i32 0, i32 0) } +@_ZTI9exception = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i32 2) to i8*), i8* getelementptr inbounds ([11 x i8], [11 x i8]* @_ZTS9exception, i32 0, i32 0) } define void @f() uwtable { %1 = alloca i8* @@ -30,12 +34,12 @@ define void @f() uwtable { store i32 %7, i32* %2 br label %8 - %9 = load i32* %2 + %9 = load i32, i32* %2 %10 = call i32 @llvm.eh.typeid.for(i8* bitcast ({ i8*, i8* }* @_ZTI9exception to i8*)) nounwind %11 = icmp eq i32 %9, %10 br i1 %11, label %12, label %17 - %13 = load i8** %1 + %13 = load i8*, i8** %1 %14 = call i8* @__cxa_begin_catch(i8* %13) #3 %15 = bitcast i8* %14 to %struct.exception* store %struct.exception* %15, %struct.exception** %e @@ -44,8 +48,8 @@ define void @f() uwtable { ret void - %18 = load i8** %1 - %19 = load i32* %2 + %18 = load i8*, i8** %1 + %19 = load i32, i32* %2 %20 = insertvalue { i8*, i32 } undef, i8* %18, 0 %21 = insertvalue { i8*, i32 } %20, i32 %19, 1 resume { i8*, i32 } %21 diff --git a/test/CodeGen/ARM/dyn-stackalloc.ll b/test/CodeGen/ARM/dyn-stackalloc.ll index 4ac5b8a31e5f..5b963fd64dea 100644 --- a/test/CodeGen/ARM/dyn-stackalloc.ll +++ b/test/CodeGen/ARM/dyn-stackalloc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=arm-eabi %s -o /dev/null +; RUN: llc -mcpu=generic -mtriple=arm-eabi -verify-machineinstrs < %s | FileCheck %s %struct.comment = type { i8**, i32*, i32, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } @@ -7,7 +7,19 @@ @str215 = external global [2 x i8] define void @t1(%struct.state* %v) { - %tmp6 = load i32* null + +; Make sure we generate: +; sub sp, sp, r1 +; instead of: +; sub r1, sp, r1 +; mov sp, r1 + +; CHECK-LABEL: @t1 +; CHECK: bic [[REG1:r[0-9]+]], +; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]] +; CHECK: sub sp, sp, [[REG1]] + + %tmp6 = load i32, i32* null %tmp8 = alloca float, i32 %tmp6 store i32 1, i32* null br i1 false, label %bb123.preheader, label %return @@ -17,8 +29,8 @@ bb123.preheader: ; preds = %0 bb43: ; preds = %bb123.preheader call fastcc void @f1(float* %tmp8, float* null, i32 0) - %tmp70 = load i32* null - %tmp85 = getelementptr float* %tmp8, i32 0 + %tmp70 = load i32, i32* null + %tmp85 = getelementptr float, float* %tmp8, i32 0 call fastcc void @f2(float* null, float* null, float* %tmp85, i32 %tmp70) ret void @@ -38,8 +50,8 @@ define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) { %tmp6 = alloca i8, i32 %tmp5 %tmp9 = call i8* @strcpy(i8* %tmp6, i8* %tag) %tmp6.len = call i32 @strlen(i8* %tmp6) - %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len - call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false) + %tmp6.indexed = getelementptr i8, i8* %tmp6, i32 %tmp6.len + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false) %tmp15 = call i8* @strcat(i8* %tmp6, i8* %contents) call fastcc void @comment_add(%struct.comment* %vc, i8* %tmp6) ret void diff --git a/test/CodeGen/ARM/ehabi.ll b/test/CodeGen/ARM/ehabi.ll index ebf0c2a00330..088e48d2d793 100644 --- a/test/CodeGen/ARM/ehabi.ll +++ b/test/CodeGen/ARM/ehabi.ll @@ -146,8 +146,8 @@ declare void @_ZSt9terminatev() ; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP: .setfp r11, sp, #28 ; CHECK-FP: add r11, sp, #28 -; CHECK-FP: .pad #28 -; CHECK-FP: sub sp, sp, #28 +; CHECK-FP: .pad #44 +; CHECK-FP: sub sp, sp, #44 ; CHECK-FP: .personality __gxx_personality_v0 ; CHECK-FP: .handlerdata ; CHECK-FP: .fnend @@ -156,8 +156,8 @@ declare void @_ZSt9terminatev() ; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} -; CHECK-FP-ELIM: .pad #28 -; CHECK-FP-ELIM: sub sp, sp, #28 +; CHECK-FP-ELIM: .pad #36 +; CHECK-FP-ELIM: sub sp, sp, #36 ; CHECK-FP-ELIM: .personality __gxx_personality_v0 ; CHECK-FP-ELIM: .handlerdata ; CHECK-FP-ELIM: .fnend @@ -205,7 +205,7 @@ declare void @_ZSt9terminatev() ; DWARF-FP: .cfi_offset r4, -36 ; DWARF-FP: add r11, sp, #28 ; DWARF-FP: .cfi_def_cfa r11, 8 -; DWARF-FP: sub sp, sp, #28 +; DWARF-FP: sub sp, sp, #44 ; DWARF-FP: sub sp, r11, #28 ; DWARF-FP: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; DWARF-FP: mov pc, lr @@ -226,9 +226,9 @@ declare void @_ZSt9terminatev() ; DWARF-FP-ELIM: .cfi_offset r6, -28 ; DWARF-FP-ELIM: .cfi_offset r5, -32 ; DWARF-FP-ELIM: .cfi_offset r4, -36 -; DWARF-FP-ELIM: sub sp, sp, #28 -; DWARF-FP-ELIM: .cfi_def_cfa_offset 64 -; DWARF-FP-ELIM: add sp, sp, #28 +; DWARF-FP-ELIM: sub sp, sp, #36 +; DWARF-FP-ELIM: .cfi_def_cfa_offset 72 +; DWARF-FP-ELIM: add sp, sp, #36 ; DWARF-FP-ELIM: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; DWARF-FP-ELIM: mov pc, lr ; DWARF-FP-ELIM: .cfi_endproc diff --git a/test/CodeGen/ARM/emit-big-cst.ll b/test/CodeGen/ARM/emit-big-cst.ll index 01d789c492fe..7453e8caa946 100644 --- a/test/CodeGen/ARM/emit-big-cst.ll +++ b/test/CodeGen/ARM/emit-big-cst.ll @@ -11,7 +11,7 @@ define void @accessBig(i64* %storage) { %addr = bitcast i64* %storage to i82* - %bigLoadedCst = load volatile i82* @bigCst + %bigLoadedCst = load volatile i82, i82* @bigCst %tmp = add i82 %bigLoadedCst, 1 store i82 %tmp, i82* %addr ret void diff --git a/test/CodeGen/ARM/extload-knownzero.ll b/test/CodeGen/ARM/extload-knownzero.ll index f55b95104b86..da340f7a9431 100644 --- a/test/CodeGen/ARM/extload-knownzero.ll +++ b/test/CodeGen/ARM/extload-knownzero.ll @@ -8,7 +8,7 @@ entry: br i1 %tmp1, label %bb1, label %bb2 bb1: ; CHECK: ldrh - %tmp2 = load i16* %ptr, align 2 + %tmp2 = load i16, i16* %ptr, align 2 br label %bb2 bb2: ; CHECK-NOT: uxth diff --git a/test/CodeGen/ARM/extloadi1.ll b/test/CodeGen/ARM/extloadi1.ll index 2504c6c61e3e..a67859d60d19 100644 --- a/test/CodeGen/ARM/extloadi1.ll +++ b/test/CodeGen/ARM/extloadi1.ll @@ -4,7 +4,7 @@ define void @__mf_sigusr1_respond() { entry: - %tmp8.b = load i1* @handler_installed.6144.b ; <i1> [#uses=1] + %tmp8.b = load i1, i1* @handler_installed.6144.b ; <i1> [#uses=1] br i1 false, label %cond_true7, label %cond_next cond_next: ; preds = %entry diff --git a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll index 05a6bab99dbf..d759d2d52c36 100644 --- a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll +++ b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] } %struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] } @@ -14,10 +14,10 @@ entry: ; ARM: t1 ; THUMB: t1 %addr = alloca i32*, align 4 - store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4 + store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], [2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4 ; ARM: add r0, r0, #124 ; THUMB: adds r0, #124 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } @@ -26,11 +26,11 @@ entry: ; ARM: t2 ; THUMB: t2 %addr = alloca i32*, align 4 - store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4 + store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4 ; ARM: movw [[R:r[0-9]+]], #1148 ; ARM: add r0, r{{[0-9]+}}, [[R]] ; THUMB: addw r0, r0, #1148 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } @@ -39,10 +39,10 @@ entry: ; ARM: t3 ; THUMB: t3 %addr = alloca i32*, align 4 - store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4 + store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4 ; ARM: add r0, r0, #140 ; THUMB: adds r0, #140 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } @@ -51,7 +51,7 @@ entry: ; ARM: t4 ; THUMB: t4 %addr = alloca i32*, align 4 - store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4 + store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], [2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4 ; ARM-NOT: movw r{{[0-9]}}, #1060 ; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4 ; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #132 @@ -61,6 +61,6 @@ entry: ; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4 ; ARM: movw r{{[0-9]}}, #1284 ; THUMB: addw r{{[0-9]}}, r{{[0-9]}}, #1284 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } diff --git a/test/CodeGen/ARM/fast-isel-align.ll b/test/CodeGen/ARM/fast-isel-align.ll index 9c9a18858289..39085db95316 100644 --- a/test/CodeGen/ARM/fast-isel-align.ll +++ b/test/CodeGen/ARM/fast-isel-align.ll @@ -1,20 +1,20 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN -; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN +; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN @@ -34,8 +34,8 @@ entry: ; THUMB: str r1, [r0] %add = fadd float %x, %y - %0 = load %struct.anon** @a, align 4 - %x1 = getelementptr inbounds %struct.anon* %0, i32 0, i32 0 + %0 = load %struct.anon*, %struct.anon** @a, align 4 + %x1 = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 0, i32 0 store float %add, float* %x1, align 1 ret void } @@ -51,7 +51,7 @@ entry: ; ARM: @word_aligned_f64_store ; THUMB: @word_aligned_f64_store %add = fadd double %a, %b - store double %add, double* getelementptr inbounds (%struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4 + store double %add, double* getelementptr inbounds (%struct.anon.0, %struct.anon.0* @foo_unpacked, i32 0, i32 0), align 4 ; ARM: vstr d16, [r0] ; THUMB: vstr d16, [r0] ret void @@ -66,9 +66,9 @@ entry: ; THUMB: @unaligned_f32_load %0 = alloca %class.TAlignTest*, align 4 store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4 - %1 = load %class.TAlignTest** %0 - %2 = getelementptr inbounds %class.TAlignTest* %1, i32 0, i32 1 - %3 = load float* %2, align 1 + %1 = load %class.TAlignTest*, %class.TAlignTest** %0 + %2 = getelementptr inbounds %class.TAlignTest, %class.TAlignTest* %1, i32 0, i32 1 + %3 = load float, float* %2, align 1 %4 = fcmp une float %3, 0.000000e+00 ; ARM: ldr r[[R:[0-9]+]], [r0, #2] ; ARM: vmov s0, r[[R]] @@ -103,7 +103,7 @@ entry: ; THUMB-STRICT-ALIGN: ldrb ; THUMB-STRICT-ALIGN: ldrb - %0 = load i16* %x, align 1 + %0 = load i16, i16* %x, align 1 ret i16 %0 } @@ -139,6 +139,6 @@ entry: ; THUMB-STRICT-ALIGN: ldrb ; THUMB-STRICT-ALIGN: ldrb - %0 = load i32* %x, align 1 + %0 = load i32, i32* %x, align 1 ret i32 %0 } diff --git a/test/CodeGen/ARM/fast-isel-binary.ll b/test/CodeGen/ARM/fast-isel-binary.ll index e1a2a4f33835..3211fd6f2422 100644 --- a/test/CodeGen/ARM/fast-isel-binary.ll +++ b/test/CodeGen/ARM/fast-isel-binary.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Test add with non-legal types diff --git a/test/CodeGen/ARM/fast-isel-br-const.ll b/test/CodeGen/ARM/fast-isel-br-const.ll index 2e28b08fc8d6..988664b86b80 100644 --- a/test/CodeGen/ARM/fast-isel-br-const.ll +++ b/test/CodeGen/ARM/fast-isel-br-const.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { entry: diff --git a/test/CodeGen/ARM/fast-isel-br-phi.ll b/test/CodeGen/ARM/fast-isel-br-phi.ll index 3b9d4652b755..fb0f0153898b 100644 --- a/test/CodeGen/ARM/fast-isel-br-phi.ll +++ b/test/CodeGen/ARM/fast-isel-br-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios ; This test ensures HandlePHINodesInSuccessorBlocks() is able to promote basic ; non-legal integer types (i.e., i1, i8, i16). diff --git a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll index da829e929ef0..2c660179aa3c 100644 --- a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll +++ b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Fast-isel can't handle non-double multi-reg retvals. ; This test just check to make sure we don't hit the assert in FinishCall. diff --git a/test/CodeGen/ARM/fast-isel-call.ll b/test/CodeGen/ARM/fast-isel-call.ll index 74b31bd9e67f..bd170f30d979 100644 --- a/test/CodeGen/ARM/fast-isel-call.ll +++ b/test/CodeGen/ARM/fast-isel-call.ll @@ -1,12 +1,12 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP ; Note that some of these tests assume that relocations are either ; movw/movt or constant pool loads. Different platforms will select @@ -157,7 +157,7 @@ define void @foo3() uwtable { ; THUMB: blx r1 %fptr = alloca i32 (i32)*, align 8 store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8 - %1 = load i32 (i32)** %fptr, align 8 + %1 = load i32 (i32)*, i32 (i32)** %fptr, align 8 %call = call i32 %1(i32 0) ret void } diff --git a/test/CodeGen/ARM/fast-isel-cmp-imm.ll b/test/CodeGen/ARM/fast-isel-cmp-imm.ll index 55baf488a425..a9d7e4580638 100644 --- a/test/CodeGen/ARM/fast-isel-cmp-imm.ll +++ b/test/CodeGen/ARM/fast-isel-cmp-imm.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB define void @t1a(float %a) uwtable ssp { entry: diff --git a/test/CodeGen/ARM/fast-isel-conversion.ll b/test/CodeGen/ARM/fast-isel-conversion.ll index 5983493a818b..46b5e78fb662 100644 --- a/test/CodeGen/ARM/fast-isel-conversion.ll +++ b/test/CodeGen/ARM/fast-isel-conversion.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Test sitofp diff --git a/test/CodeGen/ARM/fast-isel-crash.ll b/test/CodeGen/ARM/fast-isel-crash.ll index ec9cf8d95019..885ca69834d3 100644 --- a/test/CodeGen/ARM/fast-isel-crash.ll +++ b/test/CodeGen/ARM/fast-isel-crash.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-apple-darwin +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-linux-gnueabi %union.anon = type { <16 x i32> } diff --git a/test/CodeGen/ARM/fast-isel-deadcode.ll b/test/CodeGen/ARM/fast-isel-deadcode.ll index c3eed30692b8..e584c54b48a2 100644 --- a/test/CodeGen/ARM/fast-isel-deadcode.ll +++ b/test/CodeGen/ARM/fast-isel-deadcode.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Target-specific selector can't properly handle the double because it isn't ; being passed via a register, so the materialized arguments become dead code. diff --git a/test/CodeGen/ARM/fast-isel-ext.ll b/test/CodeGen/ARM/fast-isel-ext.ll index de0dd1917eb7..b792f7a90738 100644 --- a/test/CodeGen/ARM/fast-isel-ext.ll +++ b/test/CodeGen/ARM/fast-isel-ext.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 +; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 +; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7 +; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports ; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always diff --git a/test/CodeGen/ARM/fast-isel-fold.ll b/test/CodeGen/ARM/fast-isel-fold.ll index e8ed8cbf34e9..37e93c0a7018 100644 --- a/test/CodeGen/ARM/fast-isel-fold.ll +++ b/test/CodeGen/ARM/fast-isel-fold.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB @a = global i8 1, align 1 @b = global i16 2, align 2 @@ -14,7 +14,7 @@ define void @t1() nounwind uwtable ssp { ; THUMB: ldrb ; THUMB-NOT: uxtb ; THUMB-NOT: and{{.*}}, #255 - %1 = load i8* @a, align 1 + %1 = load i8, i8* @a, align 1 call void @foo1(i8 zeroext %1) ret void } @@ -26,7 +26,7 @@ define void @t2() nounwind uwtable ssp { ; THUMB: t2 ; THUMB: ldrh ; THUMB-NOT: uxth - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 call void @foo2(i16 zeroext %1) ret void } @@ -43,7 +43,7 @@ define i32 @t3() nounwind uwtable ssp { ; THUMB: ldrb ; THUMB-NOT: uxtb ; THUMB-NOT: and{{.*}}, #255 - %1 = load i8* @a, align 1 + %1 = load i8, i8* @a, align 1 %2 = zext i8 %1 to i32 ret i32 %2 } @@ -55,7 +55,7 @@ define i32 @t4() nounwind uwtable ssp { ; THUMB: t4 ; THUMB: ldrh ; THUMB-NOT: uxth - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 %2 = zext i16 %1 to i32 ret i32 %2 } @@ -67,7 +67,7 @@ define i32 @t5() nounwind uwtable ssp { ; THUMB: t5 ; THUMB: ldrsh ; THUMB-NOT: sxth - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 %2 = sext i16 %1 to i32 ret i32 %2 } @@ -79,7 +79,7 @@ define i32 @t6() nounwind uwtable ssp { ; THUMB: t6 ; THUMB: ldrsb ; THUMB-NOT: sxtb - %1 = load i8* @a, align 2 + %1 = load i8, i8* @a, align 2 %2 = sext i8 %1 to i32 ret i32 %2 } diff --git a/test/CodeGen/ARM/fast-isel-frameaddr.ll b/test/CodeGen/ARM/fast-isel-frameaddr.ll index 93cdbbbbd86e..75d582f4ee3a 100644 --- a/test/CodeGen/ARM/fast-isel-frameaddr.ll +++ b/test/CodeGen/ARM/fast-isel-frameaddr.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=DARWIN-ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2 -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2 +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=DARWIN-ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=DARWIN-THUMB2 +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=LINUX-THUMB2 define i8* @frameaddr_index0() nounwind { entry: diff --git a/test/CodeGen/ARM/fast-isel-icmp.ll b/test/CodeGen/ARM/fast-isel-icmp.ll index 85f449e3d71d..bd7c2d096a8c 100644 --- a/test/CodeGen/ARM/fast-isel-icmp.ll +++ b/test/CodeGen/ARM/fast-isel-icmp.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind { entry: diff --git a/test/CodeGen/ARM/fast-isel-indirectbr.ll b/test/CodeGen/ARM/fast-isel-indirectbr.ll index 2456ef442040..91648d36a694 100644 --- a/test/CodeGen/ARM/fast-isel-indirectbr.ll +++ b/test/CodeGen/ARM/fast-isel-indirectbr.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define void @t1(i8* %x) { entry: diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll index b09931dc4e2f..6b434b74ca79 100644 --- a/test/CodeGen/ARM/fast-isel-intrinsic.ll +++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG ; Note that some of these tests assume that relocations are either ; movw/movt or constant pool loads. Different platforms will select @@ -39,7 +39,7 @@ define void @t1() nounwind ssp { ; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr ; THUMB-LONG: ldr r3, [r3] ; THUMB-LONG: blx r3 - call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i32 4, i1 false) + call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i32 4, i1 false) ret void } @@ -78,7 +78,7 @@ define void @t2() nounwind ssp { ; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr ; THUMB-LONG: ldr r3, [r3] ; THUMB-LONG: blx r3 - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 17, i32 4, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 17, i32 4, i1 false) ret void } @@ -115,7 +115,7 @@ define void @t3() nounwind ssp { ; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr ; THUMB-LONG: ldr r3, [r3] ; THUMB-LONG: blx r3 - call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false) + call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false) ret void } @@ -142,7 +142,7 @@ define void @t4() nounwind ssp { ; THUMB: ldrh r1, [r0, #24] ; THUMB: strh r1, [r0, #12] ; THUMB: bx lr - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 4, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 4, i1 false) ret void } @@ -179,7 +179,7 @@ define void @t5() nounwind ssp { ; THUMB: ldrh r1, [r0, #24] ; THUMB: strh r1, [r0, #12] ; THUMB: bx lr - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 2, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 2, i1 false) ret void } @@ -234,14 +234,14 @@ define void @t6() nounwind ssp { ; THUMB: ldrb r1, [r0, #25] ; THUMB: strb r1, [r0, #13] ; THUMB: bx lr - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false) ret void } ; rdar://13202135 define void @t7() nounwind ssp { ; Just make sure this doesn't assert when we have an odd length and an alignment of 2. - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 3, i32 2, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 3, i32 2, i1 false) ret void } diff --git a/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll b/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll index cf294bcfbece..cce914b094f7 100644 --- a/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll +++ b/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: ; ARM: t1 - %add.ptr = getelementptr inbounds i32* %ptr, i32 1 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 1 + %0 = load i32, i32* %add.ptr, align 4 ; ARM: ldr r{{[0-9]}}, [r0, #4] ret i32 %0 } @@ -12,8 +12,8 @@ entry: define i32 @t2(i32* nocapture %ptr) nounwind readonly { entry: ; ARM: t2 - %add.ptr = getelementptr inbounds i32* %ptr, i32 63 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 63 + %0 = load i32, i32* %add.ptr, align 4 ; ARM: ldr.w r{{[0-9]}}, [r0, #252] ret i32 %0 } @@ -21,8 +21,8 @@ entry: define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly { entry: ; ARM: t3 - %add.ptr = getelementptr inbounds i16* %ptr, i16 1 - %0 = load i16* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 1 + %0 = load i16, i16* %add.ptr, align 4 ; ARM: ldrh r{{[0-9]}}, [r0, #2] ret i16 %0 } @@ -30,8 +30,8 @@ entry: define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly { entry: ; ARM: t4 - %add.ptr = getelementptr inbounds i16* %ptr, i16 63 - %0 = load i16* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 63 + %0 = load i16, i16* %add.ptr, align 4 ; ARM: ldrh.w r{{[0-9]}}, [r0, #126] ret i16 %0 } @@ -39,8 +39,8 @@ entry: define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly { entry: ; ARM: t5 - %add.ptr = getelementptr inbounds i8* %ptr, i8 1 - %0 = load i8* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 1 + %0 = load i8, i8* %add.ptr, align 4 ; ARM: ldrb r{{[0-9]}}, [r0, #1] ret i8 %0 } @@ -48,8 +48,8 @@ entry: define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly { entry: ; ARM: t6 - %add.ptr = getelementptr inbounds i8* %ptr, i8 63 - %0 = load i8* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 63 + %0 = load i8, i8* %add.ptr, align 4 ; ARM: ldrb.w r{{[0-9]}}, [r0, #63] ret i8 %0 } diff --git a/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll b/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll index d9c9cc459c7e..f24100b36db9 100644 --- a/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll +++ b/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t1 - %add.ptr = getelementptr inbounds i32* %ptr, i32 -1 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1 + %0 = load i32, i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0, #-4] ret i32 %0 } @@ -12,8 +12,8 @@ entry: define i32 @t2(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t2 - %add.ptr = getelementptr inbounds i32* %ptr, i32 -63 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63 + %0 = load i32, i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0, #-252] ret i32 %0 } @@ -21,8 +21,8 @@ entry: define i32 @t3(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t3 - %add.ptr = getelementptr inbounds i32* %ptr, i32 -64 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64 + %0 = load i32, i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0] ret i32 %0 } @@ -30,8 +30,8 @@ entry: define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t4 - %add.ptr = getelementptr inbounds i16* %ptr, i32 -1 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1 + %0 = load i16, i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0, #-2] ret i16 %0 } @@ -39,8 +39,8 @@ entry: define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t5 - %add.ptr = getelementptr inbounds i16* %ptr, i32 -127 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127 + %0 = load i16, i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0, #-254] ret i16 %0 } @@ -48,8 +48,8 @@ entry: define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t6 - %add.ptr = getelementptr inbounds i16* %ptr, i32 -128 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128 + %0 = load i16, i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0] ret i16 %0 } @@ -57,8 +57,8 @@ entry: define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t7 - %add.ptr = getelementptr inbounds i8* %ptr, i32 -1 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1 + %0 = load i8, i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0, #-1] ret i8 %0 } @@ -66,8 +66,8 @@ entry: define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t8 - %add.ptr = getelementptr inbounds i8* %ptr, i32 -255 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255 + %0 = load i8, i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0, #-255] ret i8 %0 } @@ -75,8 +75,8 @@ entry: define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t9 - %add.ptr = getelementptr inbounds i8* %ptr, i32 -256 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256 + %0 = load i8, i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0] ret i8 %0 } @@ -84,7 +84,7 @@ entry: define void @t10(i32* nocapture %ptr) nounwind { entry: ; THUMB: t10 - %add.ptr = getelementptr inbounds i32* %ptr, i32 -1 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1 store i32 0, i32* %add.ptr, align 4 ; THUMB: str r{{[0-9]}}, [r0, #-4] ret void @@ -93,7 +93,7 @@ entry: define void @t11(i32* nocapture %ptr) nounwind { entry: ; THUMB: t11 - %add.ptr = getelementptr inbounds i32* %ptr, i32 -63 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63 store i32 0, i32* %add.ptr, align 4 ; THUMB: str r{{[0-9]}}, [r0, #-252] ret void @@ -102,7 +102,7 @@ entry: define void @t12(i32* nocapture %ptr) nounwind { entry: ; THUMB: t12 - %add.ptr = getelementptr inbounds i32* %ptr, i32 -64 + %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64 store i32 0, i32* %add.ptr, align 4 ; THUMB: str r{{[0-9]}}, [r0] ret void @@ -111,7 +111,7 @@ entry: define void @t13(i16* nocapture %ptr) nounwind { entry: ; THUMB: t13 - %add.ptr = getelementptr inbounds i16* %ptr, i32 -1 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1 store i16 0, i16* %add.ptr, align 2 ; THUMB: strh r{{[0-9]}}, [r0, #-2] ret void @@ -120,7 +120,7 @@ entry: define void @t14(i16* nocapture %ptr) nounwind { entry: ; THUMB: t14 - %add.ptr = getelementptr inbounds i16* %ptr, i32 -127 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127 store i16 0, i16* %add.ptr, align 2 ; THUMB: strh r{{[0-9]}}, [r0, #-254] ret void @@ -129,7 +129,7 @@ entry: define void @t15(i16* nocapture %ptr) nounwind { entry: ; THUMB: t15 - %add.ptr = getelementptr inbounds i16* %ptr, i32 -128 + %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128 store i16 0, i16* %add.ptr, align 2 ; THUMB: strh r{{[0-9]}}, [r0] ret void @@ -138,7 +138,7 @@ entry: define void @t16(i8* nocapture %ptr) nounwind { entry: ; THUMB: t16 - %add.ptr = getelementptr inbounds i8* %ptr, i32 -1 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1 store i8 0, i8* %add.ptr, align 1 ; THUMB: strb r{{[0-9]}}, [r0, #-1] ret void @@ -147,7 +147,7 @@ entry: define void @t17(i8* nocapture %ptr) nounwind { entry: ; THUMB: t17 - %add.ptr = getelementptr inbounds i8* %ptr, i32 -255 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255 store i8 0, i8* %add.ptr, align 1 ; THUMB: strb r{{[0-9]}}, [r0, #-255] ret void @@ -156,7 +156,7 @@ entry: define void @t18(i8* nocapture %ptr) nounwind { entry: ; THUMB: t18 - %add.ptr = getelementptr inbounds i8* %ptr, i32 -256 + %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256 store i8 0, i8* %add.ptr, align 1 ; THUMB: strb r{{[0-9]}}, [r0] ret void diff --git a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll index c05ea398d72e..ca512970c9cf 100644 --- a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll +++ b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll @@ -1,12 +1,12 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; rdar://10418009 define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t1 - %add.ptr = getelementptr inbounds i16* %a, i64 -8 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-16] ret i16 %0 } @@ -14,8 +14,8 @@ entry: define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t2 - %add.ptr = getelementptr inbounds i16* %a, i64 -16 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 -16 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-32] ret i16 %0 } @@ -23,8 +23,8 @@ entry: define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t3 - %add.ptr = getelementptr inbounds i16* %a, i64 -127 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 -127 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-254] ret i16 %0 } @@ -32,8 +32,8 @@ entry: define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t4 - %add.ptr = getelementptr inbounds i16* %a, i64 -128 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: mvn r{{[1-9]}}, #255 ; ARM: add r0, r0, r{{[1-9]}} ; ARM: ldrh r0, [r0] @@ -43,8 +43,8 @@ entry: define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t5 - %add.ptr = getelementptr inbounds i16* %a, i64 8 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 8 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #16] ret i16 %0 } @@ -52,8 +52,8 @@ entry: define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t6 - %add.ptr = getelementptr inbounds i16* %a, i64 16 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 16 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #32] ret i16 %0 } @@ -61,8 +61,8 @@ entry: define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t7 - %add.ptr = getelementptr inbounds i16* %a, i64 127 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 127 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #254] ret i16 %0 } @@ -70,8 +70,8 @@ entry: define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t8 - %add.ptr = getelementptr inbounds i16* %a, i64 128 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 128 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: add r0, r0, #256 ; ARM: ldrh r0, [r0] ret i16 %0 @@ -80,7 +80,7 @@ entry: define void @t9(i16* nocapture %a) nounwind uwtable ssp { entry: ; ARM: t9 - %add.ptr = getelementptr inbounds i16* %a, i64 -8 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8 store i16 0, i16* %add.ptr, align 2 ; ARM: strh r1, [r0, #-16] ret void @@ -91,7 +91,7 @@ entry: define void @t10(i16* nocapture %a) nounwind uwtable ssp { entry: ; ARM: t10 - %add.ptr = getelementptr inbounds i16* %a, i64 -128 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128 store i16 0, i16* %add.ptr, align 2 ; ARM: mvn r{{[1-9]}}, #255 ; ARM: add r0, r0, r{{[1-9]}} @@ -102,7 +102,7 @@ entry: define void @t11(i16* nocapture %a) nounwind uwtable ssp { entry: ; ARM: t11 - %add.ptr = getelementptr inbounds i16* %a, i64 8 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 8 store i16 0, i16* %add.ptr, align 2 ; ARM: strh r{{[1-9]}}, [r0, #16] ret void @@ -113,7 +113,7 @@ entry: define void @t12(i16* nocapture %a) nounwind uwtable ssp { entry: ; ARM: t12 - %add.ptr = getelementptr inbounds i16* %a, i64 128 + %add.ptr = getelementptr inbounds i16, i16* %a, i64 128 store i16 0, i16* %add.ptr, align 2 ; ARM: add r0, r0, #256 ; ARM: strh r{{[1-9]}}, [r0] @@ -123,8 +123,8 @@ entry: define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t13 - %add.ptr = getelementptr inbounds i8* %a, i64 -8 - %0 = load i8* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8 + %0 = load i8, i8* %add.ptr, align 2 ; ARM: ldrsb r0, [r0, #-8] ret i8 %0 } @@ -132,8 +132,8 @@ entry: define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t14 - %add.ptr = getelementptr inbounds i8* %a, i64 -255 - %0 = load i8* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i8, i8* %a, i64 -255 + %0 = load i8, i8* %add.ptr, align 2 ; ARM: ldrsb r0, [r0, #-255] ret i8 %0 } @@ -141,8 +141,8 @@ entry: define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t15 - %add.ptr = getelementptr inbounds i8* %a, i64 -256 - %0 = load i8* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i8, i8* %a, i64 -256 + %0 = load i8, i8* %add.ptr, align 2 ; ARM: mvn r{{[1-9]}}, #255 ; ARM: add r0, r0, r{{[1-9]}} ; ARM: ldrsb r0, [r0] diff --git a/test/CodeGen/ARM/fast-isel-load-store-verify.ll b/test/CodeGen/ARM/fast-isel-load-store-verify.ll index 710d88b3158c..acf10c8b719e 100644 --- a/test/CodeGen/ARM/fast-isel-load-store-verify.ll +++ b/test/CodeGen/ARM/fast-isel-load-store-verify.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL ; FIXME Add tests for thumbv7, they currently fail MI verification because ; of a mismatch in register classes in uses. @@ -17,7 +17,7 @@ define i8 @t1() nounwind uwtable ssp { ; ALL: @t1 ; ALL: ldrb ; ALL: add - %1 = load i8* @a, align 1 + %1 = load i8, i8* @a, align 1 %2 = add nsw i8 %1, 1 ret i8 %2 } @@ -26,7 +26,7 @@ define i16 @t2() nounwind uwtable ssp { ; ALL: @t2 ; ALL: ldrh ; ALL: add - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 %2 = add nsw i16 %1, 1 ret i16 %2 } @@ -35,7 +35,7 @@ define i32 @t3() nounwind uwtable ssp { ; ALL: @t3 ; ALL: ldr ; ALL: add - %1 = load i32* @c, align 4 + %1 = load i32, i32* @c, align 4 %2 = add nsw i32 %1, 1 ret i32 %2 } diff --git a/test/CodeGen/ARM/fast-isel-mvn.ll b/test/CodeGen/ARM/fast-isel-mvn.ll index 886f2daa21dd..89b7c05158cd 100644 --- a/test/CodeGen/ARM/fast-isel-mvn.ll +++ b/test/CodeGen/ARM/fast-isel-mvn.ll @@ -1,8 +1,8 @@ -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=MOVT +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=MOVT ; rdar://10412592 define void @t1() nounwind { diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll index 838c103e7c09..70e15daaca62 100644 --- a/test/CodeGen/ARM/fast-isel-pic.ll +++ b/test/CodeGen/ARM/fast-isel-pic.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF @g = global i32 0, align 4 @@ -29,7 +29,7 @@ entry: ; ARMv7-ELF-NEXT: add r[[reg2]], pc ; ARMv7-ELF: ldr r[[reg3:[0-9]+]], ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]] - %tmp = load i32* @g + %tmp = load i32, i32* @g ret i32 %tmp } @@ -60,6 +60,6 @@ entry: ; ARMv7-ELF-NEXT: add r[[reg5]], pc ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]] - %tmp = load i32* @i + %tmp = load i32, i32* @i ret i32 %tmp } diff --git a/test/CodeGen/ARM/fast-isel-pred.ll b/test/CodeGen/ARM/fast-isel-pred.ll index 48f93225b6b8..ae8b67d7157b 100644 --- a/test/CodeGen/ARM/fast-isel-pred.ll +++ b/test/CodeGen/ARM/fast-isel-pred.ll @@ -7,9 +7,9 @@ entry: %X = alloca <4 x i32>, align 16 %Y = alloca <4 x float>, align 16 store i32 0, i32* %retval - %tmp = load <4 x i32>* %X, align 16 + %tmp = load <4 x i32>, <4 x i32>* %X, align 16 call void @__aa(<4 x i32> %tmp, i8* null, i32 3, <4 x float>* %Y) - %0 = load i32* %retval + %0 = load i32, i32* %retval ret i32 %0 } @@ -24,15 +24,15 @@ entry: store i8* %p, i8** %p.addr, align 4 store i32 %offset, i32* %offset.addr, align 4 store <4 x float>* %constants, <4 x float>** %constants.addr, align 4 - %tmp = load <4 x i32>* %v.addr, align 16 + %tmp = load <4 x i32>, <4 x i32>* %v.addr, align 16 store <4 x i32> %tmp, <4 x i32>* %__a.addr.i, align 16 - %tmp.i = load <4 x i32>* %__a.addr.i, align 16 + %tmp.i = load <4 x i32>, <4 x i32>* %__a.addr.i, align 16 %0 = bitcast <4 x i32> %tmp.i to <16 x i8> %1 = bitcast <16 x i8> %0 to <4 x i32> %vcvt.i = sitofp <4 x i32> %1 to <4 x float> - %tmp1 = load i8** %p.addr, align 4 - %tmp2 = load i32* %offset.addr, align 4 - %tmp3 = load <4 x float>** %constants.addr, align 4 + %tmp1 = load i8*, i8** %p.addr, align 4 + %tmp2 = load i32, i32* %offset.addr, align 4 + %tmp3 = load <4 x float>*, <4 x float>** %constants.addr, align 4 call void @__bb(<4 x float> %vcvt.i, i8* %tmp1, i32 %tmp2, <4 x float>* %tmp3) ret void } @@ -48,12 +48,12 @@ entry: store i8* %p, i8** %p.addr, align 4 store i32 %offset, i32* %offset.addr, align 4 store <4 x float>* %constants, <4 x float>** %constants.addr, align 4 - %tmp = load i64* %data, align 4 - %tmp1 = load i8** %p.addr, align 4 - %tmp2 = load i32* %offset.addr, align 4 - %add.ptr = getelementptr i8* %tmp1, i32 %tmp2 + %tmp = load i64, i64* %data, align 4 + %tmp1 = load i8*, i8** %p.addr, align 4 + %tmp2 = load i32, i32* %offset.addr, align 4 + %add.ptr = getelementptr i8, i8* %tmp1, i32 %tmp2 %0 = bitcast i8* %add.ptr to i64* - %arrayidx = getelementptr inbounds i64* %0, i32 0 + %arrayidx = getelementptr inbounds i64, i64* %0, i32 0 store i64 %tmp, i64* %arrayidx ret void } diff --git a/test/CodeGen/ARM/fast-isel-redefinition.ll b/test/CodeGen/ARM/fast-isel-redefinition.ll index ee150facac96..a1c8657cb811 100644 --- a/test/CodeGen/ARM/fast-isel-redefinition.ll +++ b/test/CodeGen/ARM/fast-isel-redefinition.ll @@ -1,11 +1,11 @@ -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic < %s +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -optimize-regalloc -regalloc=basic < %s ; This isn't exactly a useful set of command-line options, but check that it ; doesn't crash. (It was crashing because a register was getting redefined.) target triple = "thumbv7-apple-macosx10.6.7" define i32 @f(i32* %x) nounwind ssp { - %y = getelementptr inbounds i32* %x, i32 5000 - %tmp103 = load i32* %y, align 4 + %y = getelementptr inbounds i32, i32* %x, i32 5000 + %tmp103 = load i32, i32* %y, align 4 ret i32 %tmp103 } diff --git a/test/CodeGen/ARM/fast-isel-remat-same-constant.ll b/test/CodeGen/ARM/fast-isel-remat-same-constant.ll new file mode 100644 index 000000000000..d64cf8022ed4 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-remat-same-constant.ll @@ -0,0 +1,29 @@ +; RUN: llc %s -o - -fast-isel=true -O0 -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-apple-ios8.0.0" + +; This test failed with verify machine instrs due to incorrect kill flags on the add instructions +; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which should +; be correct. However, the second add is also a constant expression and the local value save area grows +; down. This meant the next use of the vreg for #6680 was after the first which had killed it. + +; CHECK: #6680 + +%struct.RD_8x8DATA = type { i32, [16 x [16 x i32]], [16 x [16 x i32]], [16 x [16 x i32]], [3 x [16 x [16 x i32]]], [4 x i16], [4 x i8], [4 x i8], [4 x i8], [16 x [16 x i16]], [16 x [16 x i16]], [16 x [16 x i32]] } + +@tr8x8 = external global %struct.RD_8x8DATA, align 4 +@tr4x4 = external global %struct.RD_8x8DATA, align 4 + +; Function Attrs: noreturn +declare void @foo(i16*, i16*) #0 + +; Function Attrs: minsize +define i32 @test() #1 { +bb: + call void @foo(i16* getelementptr inbounds (%struct.RD_8x8DATA, %struct.RD_8x8DATA* @tr8x8, i32 0, i32 10, i32 0, i32 0), i16* getelementptr inbounds (%struct.RD_8x8DATA, %struct.RD_8x8DATA* @tr4x4, i32 0, i32 10, i32 0, i32 0)) + unreachable +} + +attributes #0 = { noreturn } +attributes #1 = { minsize } diff --git a/test/CodeGen/ARM/fast-isel-ret.ll b/test/CodeGen/ARM/fast-isel-ret.ll index 8a68309dc831..f66479c2cfa3 100644 --- a/test/CodeGen/ARM/fast-isel-ret.ll +++ b/test/CodeGen/ARM/fast-isel-ret.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s ; Sign-extend of i1 currently not supported by fast-isel ;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp { diff --git a/test/CodeGen/ARM/fast-isel-select.ll b/test/CodeGen/ARM/fast-isel-select.ll index 549c97e24dcd..4eef1d6bb988 100644 --- a/test/CodeGen/ARM/fast-isel-select.ll +++ b/test/CodeGen/ARM/fast-isel-select.ll @@ -1,18 +1,18 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i1 %c) nounwind readnone { entry: ; ARM: t1 ; ARM: movw r{{[1-9]}}, #10 -; ARM: cmp r0, #0 +; ARM: tst r0, #1 ; ARM: moveq r{{[1-9]}}, #20 ; ARM: mov r0, r{{[1-9]}} ; THUMB: t1 ; THUMB: movs r{{[1-9]}}, #10 -; THUMB: cmp r0, #0 +; THUMB: tst.w r0, #1 ; THUMB: it eq ; THUMB: moveq r{{[1-9]}}, #20 ; THUMB: mov r0, r{{[1-9]}} @@ -23,11 +23,11 @@ entry: define i32 @t2(i1 %c, i32 %a) nounwind readnone { entry: ; ARM: t2 -; ARM: cmp r0, #0 +; ARM: tst r0, #1 ; ARM: moveq r{{[1-9]}}, #20 ; ARM: mov r0, r{{[1-9]}} ; THUMB: t2 -; THUMB: cmp r0, #0 +; THUMB: tst.w r0, #1 ; THUMB: it eq ; THUMB: moveq r{{[1-9]}}, #20 ; THUMB: mov r0, r{{[1-9]}} @@ -38,11 +38,11 @@ entry: define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone { entry: ; ARM: t3 -; ARM: cmp r0, #0 +; ARM: tst r0, #1 ; ARM: movne r2, r1 ; ARM: add r0, r2, r1 ; THUMB: t3 -; THUMB: cmp r0, #0 +; THUMB: tst.w r0, #1 ; THUMB: it ne ; THUMB: movne r2, r1 ; THUMB: add.w r0, r2, r1 @@ -55,12 +55,12 @@ define i32 @t4(i1 %c) nounwind readnone { entry: ; ARM: t4 ; ARM: mvn r{{[1-9]}}, #9 -; ARM: cmp r0, #0 +; ARM: tst r0, #1 ; ARM: mvneq r{{[1-9]}}, #0 ; ARM: mov r0, r{{[1-9]}} ; THUMB-LABEL: t4 ; THUMB: mvn [[REG:r[1-9]+]], #9 -; THUMB: cmp r0, #0 +; THUMB: tst.w r0, #1 ; THUMB: it eq ; THUMB: mvneq [[REG]], #0 ; THUMB: mov r0, [[REG]] @@ -71,11 +71,11 @@ entry: define i32 @t5(i1 %c, i32 %a) nounwind readnone { entry: ; ARM: t5 -; ARM: cmp r0, #0 +; ARM: tst r0, #1 ; ARM: mvneq r{{[1-9]}}, #1 ; ARM: mov r0, r{{[1-9]}} ; THUMB: t5 -; THUMB: cmp r0, #0 +; THUMB: tst.w r0, #1 ; THUMB: it eq ; THUMB: mvneq r{{[1-9]}}, #1 ; THUMB: mov r0, r{{[1-9]}} @@ -87,11 +87,11 @@ entry: define i32 @t6(i1 %c, i32 %a) nounwind readnone { entry: ; ARM: t6 -; ARM: cmp r0, #0 +; ARM: tst r0, #1 ; ARM: mvneq r{{[1-9]}}, #978944 ; ARM: mov r0, r{{[1-9]}} ; THUMB: t6 -; THUMB: cmp r0, #0 +; THUMB: tst.w r0, #1 ; THUMB: it eq ; THUMB: mvneq r{{[1-9]}}, #978944 ; THUMB: mov r0, r{{[1-9]}} diff --git a/test/CodeGen/ARM/fast-isel-shift-materialize.ll b/test/CodeGen/ARM/fast-isel-shift-materialize.ll new file mode 100644 index 000000000000..ab36a979d71b --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-shift-materialize.ll @@ -0,0 +1,25 @@ +; RUN: llc %s -o - -verify-machineinstrs -fast-isel=true | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-apple-ios8.0.0" + +; When materializing the '2' for the shifts below, the second shift kills the vreg +; we materialize in to. However, the first shift was also killing that vreg. +; This fails the machine verifier because the second use then thinks its reading an +; undefined register. + +; CHECK: lsr.w +; CHECK: lsr.w + +declare void @foo(i32, i32) + +; Function Attrs: minsize +define i32 @test(i32 %tmp3, i32 %tmp9) #0 { +bb: + %tmp4 = lshr i32 %tmp3, 2 + %tmp10 = lshr i32 %tmp9, 2 + call void @foo(i32 %tmp10, i32 %tmp4) + unreachable +} + +attributes #0 = { minsize } diff --git a/test/CodeGen/ARM/fast-isel-shifter.ll b/test/CodeGen/ARM/fast-isel-shifter.ll index eb4b2b2ce0ae..87b861f35396 100644 --- a/test/CodeGen/ARM/fast-isel-shifter.ll +++ b/test/CodeGen/ARM/fast-isel-shifter.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM define i32 @shl() nounwind ssp { entry: diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll index 9bd0a51e7120..c3980cb51f67 100644 --- a/test/CodeGen/ARM/fast-isel-static.ll +++ b/test/CodeGen/ARM/fast-isel-static.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s -; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s -; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s -; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s define void @myadd(float* %sum, float* %addend) nounwind { entry: @@ -9,12 +9,12 @@ entry: %addend.addr = alloca float*, align 4 store float* %sum, float** %sum.addr, align 4 store float* %addend, float** %addend.addr, align 4 - %tmp = load float** %sum.addr, align 4 - %tmp1 = load float* %tmp - %tmp2 = load float** %addend.addr, align 4 - %tmp3 = load float* %tmp2 + %tmp = load float*, float** %sum.addr, align 4 + %tmp1 = load float, float* %tmp + %tmp2 = load float*, float** %addend.addr, align 4 + %tmp3 = load float, float* %tmp2 %add = fadd float %tmp1, %tmp3 - %tmp4 = load float** %sum.addr, align 4 + %tmp4 = load float*, float** %sum.addr, align 4 store float %add, float* %tmp4 ret void } diff --git a/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll b/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll new file mode 100644 index 000000000000..18d60fee189f --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll @@ -0,0 +1,24 @@ +; RUN: llc %s -o - -fast-isel=true -O0 -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-apple-ios8.0.0" + +; This test ensures that when fast-isel rewrites uses of the vreg for %tmp29, it also +; updates kill flags on the shift instruction generated as part of the gep. +; This was failing instruction verification. + +; CHECK-LABEL: @test + +%struct.node = type opaque + +declare void @foo([4 x i32], %struct.node*) + +define void @test([4 x i32] %xpic.coerce, %struct.node* %t) { +bb: + %tmp29 = extractvalue [4 x i32] %xpic.coerce, 0 + %tmp40 = bitcast %struct.node* %t to [8 x %struct.node*]* + %tmp41 = getelementptr inbounds [8 x %struct.node*], [8 x %struct.node*]* %tmp40, i32 0, i32 %tmp29 + %tmp42 = load %struct.node*, %struct.node** %tmp41, align 4 + call void @foo([4 x i32] %xpic.coerce, %struct.node* %tmp42) + ret void +} diff --git a/test/CodeGen/ARM/fast-isel-vaddd.ll b/test/CodeGen/ARM/fast-isel-vaddd.ll new file mode 100644 index 000000000000..2aa269a9774d --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-vaddd.ll @@ -0,0 +1,33 @@ +; RUN: llc %s -o - -verify-machineinstrs -fast-isel=true -mattr=+vfp4 -mattr=+neon | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +%union.DV = type { <2 x double> } + +; Fast-ISel was incorrectly trying to codegen <2 x double> adds and returning only a single vadds +; Check that we generate the 2 vaddd's we expect + +; CHECK: vadd.f64 +; CHECK: vadd.f64 + +define i32 @main(i32 %argc, i8** nocapture readnone %Argv, <2 x double> %tmp31) { +bb: + %Ad = alloca %union.DV, align 16 + %tmp32 = getelementptr inbounds %union.DV, %union.DV* %Ad, i32 0, i32 0 + %tmp33 = fadd <2 x double> %tmp31, %tmp31 + br label %bb37 + +bb37: ; preds = %bb37, %bb + %i.02 = phi i32 [ 0, %bb ], [ %tmp38, %bb37 ] + store <2 x double> %tmp33, <2 x double>* %tmp32, align 16 + %tmp38 = add nuw nsw i32 %i.02, 1 + %exitcond = icmp eq i32 %tmp38, 500000 + br i1 %exitcond, label %bb39, label %bb37 + +bb39: ; preds = %bb37 + call fastcc void @printDV(%union.DV* %Ad) + ret i32 0 +} + +declare hidden fastcc void @printDV(%union.DV* nocapture readonly) diff --git a/test/CodeGen/ARM/fast-isel-vararg.ll b/test/CodeGen/ARM/fast-isel-vararg.ll index 3ff2b151ab5f..35442eea1005 100644 --- a/test/CodeGen/ARM/fast-isel-vararg.ll +++ b/test/CodeGen/ARM/fast-isel-vararg.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @VarArg() nounwind { entry: @@ -10,11 +10,11 @@ entry: %m = alloca i32, align 4 %n = alloca i32, align 4 %tmp = alloca i32, align 4 - %0 = load i32* %i, align 4 - %1 = load i32* %j, align 4 - %2 = load i32* %k, align 4 - %3 = load i32* %m, align 4 - %4 = load i32* %n, align 4 + %0 = load i32, i32* %i, align 4 + %1 = load i32, i32* %j, align 4 + %2 = load i32, i32* %k, align 4 + %3 = load i32, i32* %m, align 4 + %4 = load i32, i32* %n, align 4 ; ARM: VarArg ; ARM: mov [[FP:r[0-9]+]], sp ; ARM: sub sp, sp, #32 @@ -37,9 +37,9 @@ entry: ; THUMB: str.w {{[a-z0-9]+}}, [sp] ; THUMB: str.w {{[a-z0-9]+}}, [sp, #4] ; THUMB: bl {{_?}}CallVariadic - %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) + %call = call i32 (i32, ...) @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) store i32 %call, i32* %tmp, align 4 - %5 = load i32* %tmp, align 4 + %5 = load i32, i32* %tmp, align 4 ret i32 %5 } diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 5981cab7dcb1..49460220c47c 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; Very basic fast-isel functionality. define i32 @test0(i32 %a, i32 %b) nounwind { @@ -9,8 +9,8 @@ entry: %b.addr = alloca i32, align 4 store i32 %a, i32* %a.addr store i32 %b, i32* %b.addr - %tmp = load i32* %a.addr - %tmp1 = load i32* %b.addr + %tmp = load i32, i32* %a.addr + %tmp1 = load i32, i32* %b.addr %add = add nsw i32 %tmp, %tmp1 ret i32 %add } @@ -110,9 +110,9 @@ bb2: ; ARM: sxth bb3: - %c1 = load i8* %ptr3 - %c2 = load i16* %ptr2 - %c3 = load i32* %ptr1 + %c1 = load i8, i8* %ptr3 + %c2 = load i16, i16* %ptr2 + %c3 = load i32, i32* %ptr1 %c4 = zext i8 %c1 to i32 %c5 = sext i16 %c2 to i32 %c6 = add i32 %c4, %c5 @@ -138,7 +138,7 @@ bb3: @test4g = external global i32 define void @test4() { - %a = load i32* @test4g + %a = load i32, i32* @test4g %b = add i32 %a, 1 store i32 %b, i32* @test4g ret void diff --git a/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll b/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll index a32ab6d09317..232ab50c3ee5 100644 --- a/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll +++ b/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll @@ -6,13 +6,13 @@ define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp { entry: %ptr.addr = alloca i8*, align 8 %add = add i8 64, 64 ; 0x40 + 0x40 - %0 = load i8** %ptr.addr, align 8 + %0 = load i8*, i8** %ptr.addr, align 8 ; CHECK-LABEL: _gep_promotion: ; CHECK: ldrb {{r[0-9]+}}, {{\[r[0-9]+\]}} - %arrayidx = getelementptr inbounds i8* %0, i8 %add + %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add - %1 = load i8* %arrayidx, align 1 + %1 = load i8, i8* %arrayidx, align 1 ret i8 %1 } diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index 1de057208ce3..d013fbf8c15a 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -48,7 +48,7 @@ entry: ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32 ; SOFT: vbsl [[REG6]], [[REG7]], - %0 = tail call double (...)* @bar() nounwind + %0 = tail call double (...) @bar() nounwind %1 = fptrunc double %0 to float %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone %3 = fadd float %1, %2 diff --git a/test/CodeGen/ARM/flag-crash.ll b/test/CodeGen/ARM/flag-crash.ll index 9c61944a2154..66eb8a51c18a 100644 --- a/test/CodeGen/ARM/flag-crash.ll +++ b/test/CodeGen/ARM/flag-crash.ll @@ -5,13 +5,13 @@ define fastcc void @func(%struct.gs_matrix* nocapture %pm1) nounwind { entry: - %0 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 6 - %1 = load float* %0, align 4 - %2 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 8 - %3 = load float* %2, align 4 - %4 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 2 + %0 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 6 + %1 = load float, float* %0, align 4 + %2 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 8 + %3 = load float, float* %2, align 4 + %4 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 2 %5 = bitcast float* %4 to i32* - %6 = load i32* %5, align 4 + %6 = load i32, i32* %5, align 4 %7 = or i32 0, %6 %.mask = and i32 %7, 2147483647 %8 = icmp eq i32 %.mask, 0 diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll index 65fe9e36fa1d..3a4767e9173f 100644 --- a/test/CodeGen/ARM/fnegs.ll +++ b/test/CodeGen/ARM/fnegs.ll @@ -21,7 +21,7 @@ define float @test1(float* %a) { entry: - %0 = load float* %a, align 4 ; <float> [#uses=2] + %0 = load float, float* %a, align 4 ; <float> [#uses=2] %1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2] %2 = fpext float %1 to double ; <double> [#uses=1] %3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1] @@ -48,7 +48,7 @@ entry: define float @test2(float* %a) { entry: - %0 = load float* %a, align 4 ; <float> [#uses=2] + %0 = load float, float* %a, align 4 ; <float> [#uses=2] %1 = fmul float -1.000000e+00, %0 ; <float> [#uses=2] %2 = fpext float %1 to double ; <double> [#uses=1] %3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll index c5ff82eaf830..1fd9bd9e47a3 100644 --- a/test/CodeGen/ARM/fold-stack-adjust.ll +++ b/test/CodeGen/ARM/fold-stack-adjust.ll @@ -12,11 +12,11 @@ declare void @bar(i8*) define void @check_simple() minsize { ; CHECK-LABEL: check_simple: -; CHECK: push.w {r7, r8, r9, r10, r11, lr} +; CHECK: push {r3, r4, r5, r6, r7, lr} ; CHECK-NOT: sub sp, sp, ; ... ; CHECK-NOT: add sp, sp, -; CHECK: pop.w {r0, r1, r2, r3, r11, pc} +; CHECK: pop {r0, r1, r2, r3, r7, pc} ; CHECK-T1-LABEL: check_simple: ; CHECK-T1: push {r3, r4, r5, r6, r7, lr} @@ -44,11 +44,11 @@ define void @check_simple() minsize { define void @check_simple_too_big() minsize { ; CHECK-LABEL: check_simple_too_big: -; CHECK: push.w {r11, lr} +; CHECK: push {r7, lr} ; CHECK: sub sp, ; ... ; CHECK: add sp, -; CHECK: pop.w {r11, pc} +; CHECK: pop {r7, pc} %var = alloca i8, i32 64 call void @bar(i8* %var) ret void @@ -82,7 +82,7 @@ define void @check_vfp_fold() minsize { %var = alloca i8, i32 16 - %tmp = load %bigVec* @var + %tmp = load %bigVec, %bigVec* @var call void @bar(i8* %var) store %bigVec %tmp, %bigVec* @var @@ -93,11 +93,11 @@ define void @check_vfp_fold() minsize { ; folded in except that doing so would clobber the value being returned. define i64 @check_no_return_clobber() minsize { ; CHECK-LABEL: check_no_return_clobber: -; CHECK: push.w {r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr} ; CHECK-NOT: sub sp, ; ... ; CHECK: add sp, #24 -; CHECK: pop.w {r11, pc} +; CHECK: pop {r7, pc} ; Just to keep iOS FileCheck within previous function: ; CHECK-IOS-LABEL: check_no_return_clobber: @@ -119,7 +119,7 @@ define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize { %var = alloca i8, i32 64 - %tmp = load %bigVec* @var + %tmp = load %bigVec, %bigVec* @var call void @bar(i8* %var) store %bigVec %tmp, %bigVec* @var @@ -152,7 +152,7 @@ define void @test_fold_point(i1 %tst) minsize { ; We want a long-lived floating register so that a callee-saved dN is used and ; there's both a vpop and a pop. - %live_val = load double* @dbl + %live_val = load double, double* @dbl br i1 %tst, label %true, label %end true: call void @bar(i8* %var) @@ -176,9 +176,9 @@ define void @test_varsize(...) minsize { ; CHECK-LABEL: test_varsize: ; CHECK: sub sp, #16 -; CHECK: push.w {r9, r10, r11, lr} +; CHECK: push {r5, r6, r7, lr} ; ... -; CHECK: pop.w {r2, r3, r11, lr} +; CHECK: pop.w {r2, r3, r7, lr} ; CHECK: add sp, #16 ; CHECK: bx lr diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll index 7e1f000e88d9..cc47e3baddad 100644 --- a/test/CodeGen/ARM/fp.ll +++ b/test/CodeGen/ARM/fp.ll @@ -45,7 +45,7 @@ define double @h(double* %v) { ;CHECK: vldr ;CHECK-NEXT: vmov entry: - %tmp = load double* %v ; <double> [#uses=1] + %tmp = load double, double* %v ; <double> [#uses=1] ret double %tmp } diff --git a/test/CodeGen/ARM/fp16-promote.ll b/test/CodeGen/ARM/fp16-promote.ll new file mode 100644 index 000000000000..e691c2bb8a97 --- /dev/null +++ b/test/CodeGen/ARM/fp16-promote.ll @@ -0,0 +1,903 @@ +; RUN: llc -asm-verbose=false < %s -mattr=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 -check-prefix=CHECK-ALL +; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=CHECK-LIBCALL -check-prefix=CHECK-ALL + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv7-eabihf" + +; CHECK-FP16-LABEL: test_fadd: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vadd.f32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fadd: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vadd.f32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fadd(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = fadd half %a, %b + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fsub: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vsub.f32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fsub: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vsub.f32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fsub(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = fsub half %a, %b + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fmul: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vmul.f32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fmul +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vmul.f32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fmul(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = fmul half %a, %b + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fdiv: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vdiv.f32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fdiv +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vdiv.f32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fdiv(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = fdiv half %a, %b + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_frem: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl fmodf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_frem +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl fmodf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_frem(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = frem half %a, %b + store half %r, half* %p + ret void +} + +; CHECK-ALL-LABEL: test_load_store: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: ldrh r0, [r0] +; CHECK-ALL-NEXT: strh r0, [r1] +; CHECK-ALL-NEXT: bx lr +define void @test_load_store(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + store half %a, half* %q + ret void +} + +; Testing only successfull compilation of function calls. In ARM ABI, half +; args and returns are handled as f32. + +declare half @test_callee(half %a, half %b) #0 + +; CHECK-ALL-LABEL: test_call: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: push {r11, lr} +; CHECK-ALL-NEXT: bl test_callee +; CHECK-ALL-NEXT: pop {r11, pc} +define half @test_call(half %a, half %b) #0 { + %r = call half @test_callee(half %a, half %b) + ret half %r +} + +; CHECK-ALL-LABEL: test_call_flipped: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: push {r11, lr} +; CHECK-ALL-NEXT: mov r2, r0 +; CHECK-ALL-NEXT: mov r0, r1 +; CHECK-ALL-NEXT: mov r1, r2 +; CHECK-ALL-NEXT: bl test_callee +; CHECK-ALL-NEXT: pop {r11, pc} +define half @test_call_flipped(half %a, half %b) #0 { + %r = call half @test_callee(half %b, half %a) + ret half %r +} + +; CHECK-ALL-LABEL: test_tailcall_flipped: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: mov r2, r0 +; CHECK-ALL-NEXT: mov r0, r1 +; CHECK-ALL-NEXT: mov r1, r2 +; CHECK-ALL-NEXT: b test_callee +define half @test_tailcall_flipped(half %a, half %b) #0 { + %r = tail call half @test_callee(half %b, half %a) + ret half %r +} + +; Optimizer picks %p or %q based on %c and only loads that value +; No conversion is needed +; CHECK-ALL-LABEL: test_select: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: cmp r2, #0 +; CHECK-ALL-NEXT: movne r1, r0 +; CHECK-ALL-NEXT: ldrh r1, [r1] +; CHECK-ALL-NEXT: strh r1, [r0] +; CHECK-ALL-NEXT: bx lr +define void @test_select(half* %p, half* %q, i1 zeroext %c) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = select i1 %c, half %a, half %b + store half %r, half* %p + ret void +} + +; Test only two variants of fcmp. These get translated to f32 vcmpe +; instructions anyway. +; CHECK-FP16-LABEL: test_fcmp_une: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcmpe.f32 +; CHECK-FP16: vmrs APSR_nzcv, fpscr +; CHECK-FP16: movwne +; CHECK-LIBCALL-LABEL: test_fcmp_une: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vcmpe.f32 +; CHECK-LIBCALL: movwne +define i1 @test_fcmp_une(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = fcmp une half %a, %b + ret i1 %r +} + +; CHECK-FP16-LABEL: test_fcmp_ueq: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcmpe.f32 +; CHECK-FP16: vmrs APSR_nzcv, fpscr +; CHECK-FP16: movweq +; CHECK-FP16: movwvs +; CHECK-LIBCALL-LABEL: test_fcmp_ueq: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vcmpe.f32 +; CHECK-LIBCALL: movweq +define i1 @test_fcmp_ueq(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = fcmp ueq half %a, %b + ret i1 %r +} + +; CHECK-FP16-LABEL: test_br_cc: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcmpe.f32 +; CHECK-FP16: vmrs APSR_nzcv, fpscr +; CHECK-FP16: strmi +; CHECK-FP16: strpl +; CHECK-LIBCALL-LABEL: test_br_cc: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vcmpe.f32 +; CHECK-LIBCALL: strmi +; CHECK-LIBCALL: strpl +define void @test_br_cc(half* %p, half* %q, i32* %p1, i32* %p2) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %c = fcmp uge half %a, %b + br i1 %c, label %then, label %else +then: + store i32 0, i32* %p1 + ret void +else: + store i32 0, i32* %p2 + ret void +} + +declare i1 @test_dummy(half* %p) #0 +; CHECK-FP16-LABEL: test_phi: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: [[LOOP:.LBB[1-9_]+]]: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl test_dummy +; CHECK-FP16: bne [[LOOP]] +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_phi: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: [[LOOP:.LBB[1-9_]+]]: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl test_dummy +; CHECK-LIBCALL: bne [[LOOP]] +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_phi(half* %p) #0 { +entry: + %a = load half, half* %p + br label %loop +loop: + %r = phi half [%a, %entry], [%b, %loop] + %b = load half, half* %p + %c = call i1 @test_dummy(half* %p) + br i1 %c, label %loop, label %return +return: + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fptosi_i32: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvt.s32.f32 +; CHECK-LIBCALL-LABEL: test_fptosi_i32: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vcvt.s32.f32 +define i32 @test_fptosi_i32(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = fptosi half %a to i32 + ret i32 %r +} + +; CHECK-FP16-LABEL: test_fptosi_i64: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl __aeabi_f2lz +; CHECK-LIBCALL-LABEL: test_fptosi_i64: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_f2lz +define i64 @test_fptosi_i64(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = fptosi half %a to i64 + ret i64 %r +} + +; CHECK-FP16-LABEL: test_fptoui_i32: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvt.u32.f32 +; CHECK-LIBCALL-LABEL: test_fptoui_i32: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vcvt.u32.f32 +define i32 @test_fptoui_i32(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = fptoui half %a to i32 + ret i32 %r +} + +; CHECK-FP16-LABEL: test_fptoui_i64: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl __aeabi_f2ulz +; CHECK-LIBCALL-LABEL: test_fptoui_i64: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_f2ulz +define i64 @test_fptoui_i64(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = fptoui half %a to i64 + ret i64 %r +} + +; CHECK-FP16-LABEL: test_sitofp_i32: +; CHECK-FP16: vcvt.f32.s32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_sitofp_i32: +; CHECK-LIBCALL: vcvt.f32.s32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_sitofp_i32(i32 %a, half* %p) #0 { + %r = sitofp i32 %a to half + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_uitofp_i32: +; CHECK-FP16: vcvt.f32.u32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_uitofp_i32: +; CHECK-LIBCALL: vcvt.f32.u32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_uitofp_i32(i32 %a, half* %p) #0 { + %r = uitofp i32 %a to half + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_sitofp_i64: +; CHECK-FP16: bl __aeabi_l2f +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_sitofp_i64: +; CHECK-LIBCALL: bl __aeabi_l2f +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_sitofp_i64(i64 %a, half* %p) #0 { + %r = sitofp i64 %a to half + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_uitofp_i64: +; CHECK-FP16: bl __aeabi_ul2f +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_uitofp_i64: +; CHECK-LIBCALL: bl __aeabi_ul2f +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_uitofp_i64(i64 %a, half* %p) #0 { + %r = uitofp i64 %a to half + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fptrunc_float: +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fptrunc_float: +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fptrunc_float(float %f, half* %p) #0 { + %a = fptrunc float %f to half + store half %a, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fptrunc_double: +; CHECK-FP16: bl __aeabi_d2h +; CHECK-LIBCALL-LABEL: test_fptrunc_double: +; CHECK-LIBCALL: bl __aeabi_d2h +define void @test_fptrunc_double(double %d, half* %p) #0 { + %a = fptrunc double %d to half + store half %a, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fpextend_float: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-LIBCALL-LABEL: test_fpextend_float: +; CHECK-LIBCALL: b __gnu_h2f_ieee +define float @test_fpextend_float(half* %p) { + %a = load half, half* %p, align 2 + %r = fpext half %a to float + ret float %r +} + +; CHECK-FP16-LABEL: test_fpextend_double: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvt.f64.f32 +; CHECK-LIBCALL-LABEL: test_fpextend_double: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vcvt.f64.f32 +define double @test_fpextend_double(half* %p) { + %a = load half, half* %p, align 2 + %r = fpext half %a to double + ret double %r +} + +; CHECK-ALL-LABEL: test_bitcast_halftoi16: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: ldrh r0, [r0] +; CHECK-ALL-NEXT: bx lr +define i16 @test_bitcast_halftoi16(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = bitcast half %a to i16 + ret i16 %r +} + +; CHECK-ALL-LABEL: test_bitcast_i16tohalf: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: strh r0, [r1] +; CHECK-ALL-NEXT: bx lr +define void @test_bitcast_i16tohalf(i16 %a, half* %p) #0 { + %r = bitcast i16 %a to half + store half %r, half* %p + ret void +} + +declare half @llvm.sqrt.f16(half %a) #0 +declare half @llvm.powi.f16(half %a, i32 %b) #0 +declare half @llvm.sin.f16(half %a) #0 +declare half @llvm.cos.f16(half %a) #0 +declare half @llvm.pow.f16(half %a, half %b) #0 +declare half @llvm.exp.f16(half %a) #0 +declare half @llvm.exp2.f16(half %a) #0 +declare half @llvm.log.f16(half %a) #0 +declare half @llvm.log10.f16(half %a) #0 +declare half @llvm.log2.f16(half %a) #0 +declare half @llvm.fma.f16(half %a, half %b, half %c) #0 +declare half @llvm.fabs.f16(half %a) #0 +declare half @llvm.minnum.f16(half %a, half %b) #0 +declare half @llvm.maxnum.f16(half %a, half %b) #0 +declare half @llvm.copysign.f16(half %a, half %b) #0 +declare half @llvm.floor.f16(half %a) #0 +declare half @llvm.ceil.f16(half %a) #0 +declare half @llvm.trunc.f16(half %a) #0 +declare half @llvm.rint.f16(half %a) #0 +declare half @llvm.nearbyint.f16(half %a) #0 +declare half @llvm.round.f16(half %a) #0 +declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0 + +; CHECK-FP16-LABEL: test_sqrt: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vsqrt.f32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_sqrt: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vsqrt.f32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_sqrt(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.sqrt.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fpowi: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl __powisf2 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fpowi: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __powisf2 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fpowi(half* %p, i32 %b) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.powi.f16(half %a, i32 %b) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_sin: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl sinf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_sin: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl sinf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_sin(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.sin.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_cos: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl cosf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_cos: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl cosf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_cos(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.cos.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_pow: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl powf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_pow: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl powf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_pow(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = call half @llvm.pow.f16(half %a, half %b) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_exp: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl expf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_exp: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl expf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_exp(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.exp.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_exp2: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl exp2f +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_exp2: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl exp2f +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_exp2(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.exp2.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_log: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl logf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_log: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl logf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_log(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.log.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_log10: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl log10f +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_log10: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl log10f +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_log10(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.log10.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_log2: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl log2f +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_log2: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl log2f +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_log2(half* %p) #0 { + %a = load half, half* %p, align 2 + %r = call half @llvm.log2.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fma: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl fmaf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fma: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl fmaf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fma(half* %p, half* %q, half* %r) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %c = load half, half* %r, align 2 + %v = call half @llvm.fma.f16(half %a, half %b, half %c) + store half %v, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fabs: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vabs.f32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fabs: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bfc +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fabs(half* %p) { + %a = load half, half* %p, align 2 + %r = call half @llvm.fabs.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_minnum: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl fminf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_minnum: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl fminf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_minnum(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = call half @llvm.minnum.f16(half %a, half %b) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_maxnum: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl fmaxf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_maxnum: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl fmaxf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_maxnum(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = call half @llvm.maxnum.f16(half %a, half %b) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_copysign: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vbsl +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_copysign: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vbsl +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_copysign(half* %p, half* %q) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %r = call half @llvm.copysign.f16(half %a, half %b) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_floor: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl floorf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_floor: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl floorf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_floor(half* %p) { + %a = load half, half* %p, align 2 + %r = call half @llvm.floor.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_ceil: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl ceilf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_ceil: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl ceilf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_ceil(half* %p) { + %a = load half, half* %p, align 2 + %r = call half @llvm.ceil.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_trunc: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl truncf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_trunc: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl truncf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_trunc(half* %p) { + %a = load half, half* %p, align 2 + %r = call half @llvm.trunc.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_rint: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl rintf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_rint: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl rintf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_rint(half* %p) { + %a = load half, half* %p, align 2 + %r = call half @llvm.rint.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_nearbyint: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl nearbyintf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_nearbyint: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl nearbyintf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_nearbyint(half* %p) { + %a = load half, half* %p, align 2 + %r = call half @llvm.nearbyint.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_round: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: bl roundf +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_round: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl roundf +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_round(half* %p) { + %a = load half, half* %p, align 2 + %r = call half @llvm.round.f16(half %a) + store half %r, half* %p + ret void +} + +; CHECK-FP16-LABEL: test_fmuladd: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vmla.f32 +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL-LABEL: test_fmuladd: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: vmla.f32 +; CHECK-LIBCALL: bl __gnu_f2h_ieee +define void @test_fmuladd(half* %p, half* %q, half* %r) #0 { + %a = load half, half* %p, align 2 + %b = load half, half* %q, align 2 + %c = load half, half* %r, align 2 + %v = call half @llvm.fmuladd.f16(half %a, half %b, half %c) + store half %v, half* %p + ret void +} + +; f16 vectors are not legal in the backend. Vector elements are not assigned +; to the register, but are stored in the stack instead. Hence insertelement +; and extractelement have these extra loads and stores. + +; CHECK-ALL-LABEL: test_insertelement: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: sub sp, sp, #8 +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: mov +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: add +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: add sp, sp, #8 +; CHECK-ALL-NEXT: bx lr +define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 { + %a = load half, half* %p, align 2 + %b = load <4 x half>, <4 x half>* %q, align 8 + %c = insertelement <4 x half> %b, half %a, i32 %i + store <4 x half> %c, <4 x half>* %q + ret void +} + +; CHECK-ALL-LABEL: test_extractelement: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: sub sp, sp, #8 +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: orr +; CHECK-ALL-NEXT: str +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: orr +; CHECK-ALL-NEXT: str +; CHECK-ALL-NEXT: mov +; CHECK-ALL-NEXT: add +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: add sp, sp, #8 +; CHECK-ALL-NEXT: bx lr +define void @test_extractelement(half* %p, <4 x half>* %q, i32 %i) #0 { + %a = load <4 x half>, <4 x half>* %q, align 8 + %b = extractelement <4 x half> %a, i32 %i + store half %b, half* %p + ret void +} + +; test struct operations + +%struct.dummy = type { i32, half } + +; CHECK-ALL-LABEL: test_insertvalue: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: ldr +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: str +; CHECK-ALL-NEXT: bx lr +define void @test_insertvalue(%struct.dummy* %p, half* %q) { + %a = load %struct.dummy, %struct.dummy* %p + %b = load half, half* %q + %c = insertvalue %struct.dummy %a, half %b, 1 + store %struct.dummy %c, %struct.dummy* %p + ret void +} + +; CHECK-ALL-LABEL: test_extractvalue: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: ldrh +; CHECK-ALL-NEXT: strh +; CHECK-ALL-NEXT: bx lr +define void @test_extractvalue(%struct.dummy* %p, half* %q) { + %a = load %struct.dummy, %struct.dummy* %p + %b = extractvalue %struct.dummy %a, 1 + store half %b, half* %q + ret void +} + +; CHECK-FP16-LABEL: test_struct_return: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-LIBCALL-LABEL: test_struct_return: +; CHECK-LIBCALL: bl __gnu_h2f_ieee +define %struct.dummy @test_struct_return(%struct.dummy* %p) { + %a = load %struct.dummy, %struct.dummy* %p + ret %struct.dummy %a +} + +; CHECK-ALL-LABEL: test_struct_arg: +; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: mov r0, r1 +; CHECK-ALL-NEXT: bx lr +define half @test_struct_arg(%struct.dummy %p) { + %a = extractvalue %struct.dummy %p, 1 + ret half %a +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll index 5a926acc5430..25fbf9070cb6 100644 --- a/test/CodeGen/ARM/fp16.ll +++ b/test/CodeGen/ARM/fp16.ll @@ -16,8 +16,8 @@ define void @foo() nounwind { ; CHECK-ARMV8-LABEL: foo: ; CHECK-SOFTFLOAT-LABEL: foo: entry: - %0 = load i16* @x, align 2 - %1 = load i16* @y, align 2 + %0 = load i16, i16* @x, align 2 + %1 = load i16, i16* @y, align 2 %2 = tail call float @llvm.convert.from.fp16.f32(i16 %0) ; CHECK: __gnu_h2f_ieee ; CHECK-FP16: vcvtb.f32.f16 diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll index eab5988e3eb4..45bb6d2f702d 100644 --- a/test/CodeGen/ARM/fpcmp-opt.ll +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -13,8 +13,8 @@ entry: ; CHECK: vcmpe.f32 [[S1]], [[S0]] ; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: beq - %0 = load float* %a - %1 = load float* %b + %0 = load float, float* %a + %1 = load float, float* %b %2 = fcmp une float %0, %1 br i1 %2, label %bb1, label %bb2 @@ -41,7 +41,7 @@ entry: ; CHECK-NOT: vcmpe.f32 ; CHECK-NOT: vmrs ; CHECK: bne - %0 = load double* %a + %0 = load double, double* %a %1 = fcmp oeq double %0, 0.000000e+00 br i1 %1, label %bb1, label %bb2 @@ -64,7 +64,7 @@ entry: ; CHECK-NOT: vcmpe.f32 ; CHECK-NOT: vmrs ; CHECK: bne - %0 = load float* %a + %0 = load float, float* %a %1 = fcmp oeq float %0, 0.000000e+00 br i1 %1, label %bb1, label %bb2 diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll index 3a454ed9631c..23fbea911e5e 100644 --- a/test/CodeGen/ARM/fpmem.ll +++ b/test/CodeGen/ARM/fpmem.ll @@ -9,7 +9,7 @@ define float @f1(float %a) { define float @f2(float* %v, float %u) { ; CHECK-LABEL: f2: ; CHECK: vldr{{.*}}[ - %tmp = load float* %v ; <float> [#uses=1] + %tmp = load float, float* %v ; <float> [#uses=1] %tmp1 = fadd float %tmp, %u ; <float> [#uses=1] ret float %tmp1 } @@ -17,8 +17,8 @@ define float @f2(float* %v, float %u) { define float @f2offset(float* %v, float %u) { ; CHECK-LABEL: f2offset: ; CHECK: vldr{{.*}}, #4] - %addr = getelementptr float* %v, i32 1 - %tmp = load float* %addr + %addr = getelementptr float, float* %v, i32 1 + %tmp = load float, float* %addr %tmp1 = fadd float %tmp, %u ret float %tmp1 } @@ -26,8 +26,8 @@ define float @f2offset(float* %v, float %u) { define float @f2noffset(float* %v, float %u) { ; CHECK-LABEL: f2noffset: ; CHECK: vldr{{.*}}, #-4] - %addr = getelementptr float* %v, i32 -1 - %tmp = load float* %addr + %addr = getelementptr float, float* %v, i32 -1 + %tmp = load float, float* %addr %tmp1 = fadd float %tmp, %u ret float %tmp1 } diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll index f50d0b96fe99..6cbb30b23fbe 100644 --- a/test/CodeGen/ARM/fptoint.ll +++ b/test/CodeGen/ARM/fptoint.ll @@ -4,13 +4,13 @@ @u = weak global i32 0 ; <i32*> [#uses=2] define i32 @foo1(float *%x) { - %tmp1 = load float* %x + %tmp1 = load float, float* %x %tmp2 = bitcast float %tmp1 to i32 ret i32 %tmp2 } define i64 @foo2(double *%x) { - %tmp1 = load double* %x + %tmp1 = load double, double* %x %tmp2 = bitcast double %tmp1 to i64 ret i64 %tmp2 } diff --git a/test/CodeGen/ARM/frame-register.ll b/test/CodeGen/ARM/frame-register.ll index e6a55bddaf1c..0cc5005ec488 100644 --- a/test/CodeGen/ARM/frame-register.ll +++ b/test/CodeGen/ARM/frame-register.ll @@ -17,12 +17,12 @@ entry: %i.addr = alloca i32, align 4 %j = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 %add = add nsw i32 %0, 1 store i32 %add, i32* %j, align 4 - %1 = load i32* %j, align 4 + %1 = load i32, i32* %j, align 4 call void @callee(i32 %1) - %2 = load i32* %j, align 4 + %2 = load i32, i32* %j, align 4 %add1 = add nsw i32 %2, 1 ret i32 %add1 } @@ -30,9 +30,9 @@ entry: ; CHECK-ARM: push {r11, lr} ; CHECK-ARM: mov r11, sp -; CHECK-THUMB: push {r4, r6, r7, lr} -; CHECK-THUMB: add r7, sp, #8 +; CHECK-THUMB: push {r7, lr} +; CHECK-THUMB: add r7, sp, #0 ; CHECK-DARWIN-ARM: push {r7, lr} -; CHECK-DARWIN-THUMB: push {r4, r7, lr} +; CHECK-DARWIN-THUMB: push {r7, lr} diff --git a/test/CodeGen/ARM/fusedMAC.ll b/test/CodeGen/ARM/fusedMAC.ll index e29f291dc2c5..6f6cdc11491e 100644 --- a/test/CodeGen/ARM/fusedMAC.ll +++ b/test/CodeGen/ARM/fusedMAC.ll @@ -144,7 +144,7 @@ entry: define float @test_fnms_f32(float %a, float %b, float* %c) nounwind readnone ssp { ; CHECK: test_fnms_f32 ; CHECK: vfnms.f32 - %tmp1 = load float* %c, align 4 + %tmp1 = load float, float* %c, align 4 %tmp2 = fsub float -0.0, %tmp1 %tmp3 = tail call float @llvm.fma.f32(float %a, float %b, float %tmp2) nounwind readnone ret float %tmp3 diff --git a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll index 623b4220c21f..f34f8f1a66c1 100644 --- a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll +++ b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll @@ -15,7 +15,7 @@ define ghccc void @test_direct_tail() { define ghccc void @test_indirect_tail() { ; CHECK-LABEL: test_indirect_tail: ; CHECK: bx {{r[0-9]+}} - %func = load void()** @ind_func - tail call ghccc void()* %func() + %func = load void()*, void()** @ind_func + tail call ghccc void() %func() ret void } diff --git a/test/CodeGen/ARM/global-merge-1.ll b/test/CodeGen/ARM/global-merge-1.ll index e5d4def938df..d4d9b0f9d1f3 100644 --- a/test/CodeGen/ARM/global-merge-1.ll +++ b/test/CodeGen/ARM/global-merge-1.ll @@ -1,9 +1,12 @@ ; RUN: llc %s -O0 -o - | FileCheck -check-prefix=NO-MERGE %s -; RUN: llc %s -O0 -o - -enable-global-merge=false | FileCheck -check-prefix=NO-MERGE %s -; RUN: llc %s -O0 -o - -enable-global-merge=true | FileCheck -check-prefix=NO-MERGE %s -; RUN: llc %s -O1 -o - | FileCheck -check-prefix=MERGE %s -; RUN: llc %s -O1 -o - -enable-global-merge=false | FileCheck -check-prefix=NO-MERGE %s -; RUN: llc %s -O1 -o - -enable-global-merge=true | FileCheck -check-prefix=MERGE %s +; RUN: llc %s -O0 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O0 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s +; RUN: llc %s -O1 -o - | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O1 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O1 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s +; RUN: llc %s -O3 -o - | FileCheck -check-prefix=MERGE %s +; RUN: llc %s -O3 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O3 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s ; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2 ; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2 @@ -29,25 +32,25 @@ target triple = "thumbv7-apple-ios3.0.0" ; Function Attrs: nounwind ssp define internal void @initialize() #0 { %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %1, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 0), align 4, !tbaa !1 + store i32 %1, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 0), align 4, !tbaa !1 %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %2, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 0), align 4, !tbaa !1 + store i32 %2, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 0), align 4, !tbaa !1 %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %3, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 1), align 4, !tbaa !1 + store i32 %3, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 1), align 4, !tbaa !1 %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %4, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 1), align 4, !tbaa !1 + store i32 %4, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 1), align 4, !tbaa !1 %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %5, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 2), align 4, !tbaa !1 + store i32 %5, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 2), align 4, !tbaa !1 %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %6, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 2), align 4, !tbaa !1 + store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 2), align 4, !tbaa !1 %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %7, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 3), align 4, !tbaa !1 + store i32 %7, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 3), align 4, !tbaa !1 %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %8, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 3), align 4, !tbaa !1 + store i32 %8, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 3), align 4, !tbaa !1 %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %9, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1 + store i32 %9, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1 %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3 - store i32 %10, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1 + store i32 %10, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1 ret void } @@ -55,20 +58,20 @@ declare i32 @calc(...) #1 ; Function Attrs: nounwind ssp define internal void @calculate() #0 { - %1 = load <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4 - %2 = load <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4 + %1 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4 + %2 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4 %3 = mul <4 x i32> %2, %1 store <4 x i32> %3, <4 x i32>* bitcast ([5 x i32]* @foo to <4 x i32>*), align 4 - %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1 - %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1 + %4 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1 + %5 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1 %6 = mul nsw i32 %5, %4 - store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i32 0, i32 4), align 4, !tbaa !1 + store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i32 0, i32 4), align 4, !tbaa !1 ret void } ; Function Attrs: nounwind readnone ssp define internal i32* @returnFoo() #2 { - ret i32* getelementptr inbounds ([5 x i32]* @foo, i32 0, i32 0) + ret i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i32 0, i32 0) } attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/global-merge-addrspace.ll b/test/CodeGen/ARM/global-merge-addrspace.ll index 0efa690bde28..8f40a4c28a76 100644 --- a/test/CodeGen/ARM/global-merge-addrspace.ll +++ b/test/CodeGen/ARM/global-merge-addrspace.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumb-apple-darwin -arm-global-merge -global-merge-group-by-use=false | FileCheck %s ; Test the GlobalMerge pass. Check that the pass does not crash when using ; multiple address spaces. @@ -7,6 +7,6 @@ @g2 = internal addrspace(1) global i32 2 -; CHECK: _MergedGlobals1: +; CHECK: _MergedGlobals.1: @g3 = internal addrspace(2) global i32 3 @g4 = internal addrspace(2) global i32 4 diff --git a/test/CodeGen/ARM/global-merge.ll b/test/CodeGen/ARM/global-merge.ll index f88e92796196..e8c8289098a7 100644 --- a/test/CodeGen/ARM/global-merge.ll +++ b/test/CodeGen/ARM/global-merge.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumb-apple-darwin -global-merge-on-const=true | FileCheck %s +; RUN: llc < %s -mtriple=thumb-apple-darwin -arm-global-merge -global-merge-group-by-use=false -global-merge-on-const=true | FileCheck %s ; Test the ARMGlobalMerge pass. Use -march=thumb because it has a small ; value for the maximum offset (127). @@ -59,16 +59,16 @@ declare void @__cxa_end_catch() ; Make sure that the complete variable fits within the range of the maximum ; offset. Having the starting offset in range is not sufficient. ; When this works properly, @g3 is placed in a separate chunk of merged globals. -; CHECK: _MergedGlobals1: +; CHECK: _MergedGlobals.1: @g3 = internal global [30 x i32] [ i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ], align 4 ; Global variables that can be placed in BSS should be kept together in a ; separate pool of merged globals. -; CHECK: _MergedGlobals2 +; CHECK: _MergedGlobals.2 @g4 = internal global i32 0 @g5 = internal global i32 0 ; Global variables that are constant can be merged together -; CHECK: _MergedGlobals3 +; CHECK: _MergedGlobals.3 @g6 = internal constant [12 x i32] zeroinitializer, align 4 @g7 = internal constant [12 x i32] zeroinitializer, align 4 diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index 2c599bf011a7..bab96dadce55 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -6,7 +6,7 @@ @G = external global i32 define i32 @test1() { - %tmp = load i32* @G + %tmp = load i32, i32* @G ret i32 %tmp } diff --git a/test/CodeGen/ARM/gv-stubs-crash.ll b/test/CodeGen/ARM/gv-stubs-crash.ll index c4c4180a6200..6e82afeacf88 100644 --- a/test/CodeGen/ARM/gv-stubs-crash.ll +++ b/test/CodeGen/ARM/gv-stubs-crash.ll @@ -4,7 +4,7 @@ @Exn = external hidden unnamed_addr constant { i8*, i8* } define hidden void @func(i32* %this, i32* %e) optsize align 2 { - %e.ld = load i32* %e, align 4 + %e.ld = load i32, i32* %e, align 4 %inv = invoke zeroext i1 @func2(i32* %this, i32 %e.ld) optsize to label %ret unwind label %lpad diff --git a/test/CodeGen/ARM/half.ll b/test/CodeGen/ARM/half.ll index 10cebb38c565..b40eaf638519 100644 --- a/test/CodeGen/ARM/half.ll +++ b/test/CodeGen/ARM/half.ll @@ -6,7 +6,7 @@ define void @test_load_store(half* %in, half* %out) { ; CHECK-LABEL: test_load_store: ; CHECK: ldrh [[TMP:r[0-9]+]], [r0] ; CHECK: strh [[TMP]], [r1] - %val = load half* %in + %val = load half, half* %in store half %val, half* %out ret void } @@ -14,7 +14,7 @@ define void @test_load_store(half* %in, half* %out) { define i16 @test_bitcast_from_half(half* %addr) { ; CHECK-LABEL: test_bitcast_from_half: ; CHECK: ldrh r0, [r0] - %val = load half* %addr + %val = load half, half* %addr %val_int = bitcast half %val to i16 ret i16 %val_int } @@ -30,10 +30,10 @@ define void @test_bitcast_to_half(half* %addr, i16 %in) { define float @test_extend32(half* %addr) { ; CHECK-LABEL: test_extend32: -; CHECK-OLD: b.w ___gnu_h2f_ieee +; CHECK-OLD: b.w ___extendhfsf2 ; CHECK-F16: vcvtb.f32.f16 ; CHECK-V8: vcvtb.f32.f16 - %val16 = load half* %addr + %val16 = load half, half* %addr %val32 = fpext half %val16 to float ret float %val32 } @@ -41,12 +41,12 @@ define float @test_extend32(half* %addr) { define double @test_extend64(half* %addr) { ; CHECK-LABEL: test_extend64: -; CHECK-OLD: blx ___gnu_h2f_ieee +; CHECK-OLD: blx ___extendhfsf2 ; CHECK-OLD: vcvt.f64.f32 ; CHECK-F16: vcvtb.f32.f16 ; CHECK-F16: vcvt.f64.f32 ; CHECK-V8: vcvtb.f64.f16 - %val16 = load half* %addr + %val16 = load half, half* %addr %val32 = fpext half %val16 to double ret double %val32 } @@ -54,7 +54,7 @@ define double @test_extend64(half* %addr) { define void @test_trunc32(float %in, half* %addr) { ; CHECK-LABEL: test_trunc32: -; CHECK-OLD: blx ___gnu_f2h_ieee +; CHECK-OLD: blx ___truncsfhf2 ; CHECK-F16: vcvtb.f16.f32 ; CHECK-V8: vcvtb.f16.f32 %val16 = fptrunc float %in to half diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll index d2685854dba0..08e6104bbcf6 100644 --- a/test/CodeGen/ARM/hello.ll +++ b/test/CodeGen/ARM/hello.ll @@ -10,7 +10,7 @@ @str = internal constant [12 x i8] c"Hello World\00" define i32 @main() { - %tmp = call i32 @puts( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) ) ; <i32> [#uses=0] + %tmp = call i32 @puts( i8* getelementptr ([12 x i8], [12 x i8]* @str, i32 0, i64 0) ) ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/hidden-vis-2.ll b/test/CodeGen/ARM/hidden-vis-2.ll index 18d38d40072c..a104f354295d 100644 --- a/test/CodeGen/ARM/hidden-vis-2.ll +++ b/test/CodeGen/ARM/hidden-vis-2.ll @@ -7,6 +7,6 @@ entry: ; CHECK-LABEL: t: ; CHECK: ldr ; CHECK-NEXT: ldr - %0 = load i32* @x, align 4 ; <i32> [#uses=1] + %0 = load i32, i32* @x, align 4 ; <i32> [#uses=1] ret i32 %0 } diff --git a/test/CodeGen/ARM/hidden-vis-3.ll b/test/CodeGen/ARM/hidden-vis-3.ll index 3bc3312e9c4e..0cf2f779704d 100644 --- a/test/CodeGen/ARM/hidden-vis-3.ll +++ b/test/CodeGen/ARM/hidden-vis-3.ll @@ -10,8 +10,8 @@ entry: ; CHECK: LCPI0_1: ; CHECK-NEXT: .long _y - %0 = load i32* @x, align 4 ; <i32> [#uses=1] - %1 = load i32* @y, align 4 ; <i32> [#uses=1] + %0 = load i32, i32* @x, align 4 ; <i32> [#uses=1] + %1 = load i32, i32* @y, align 4 ; <i32> [#uses=1] %2 = add i32 %1, %0 ; <i32> [#uses=1] ret i32 %2 } diff --git a/test/CodeGen/ARM/ifconv-kills.ll b/test/CodeGen/ARM/ifconv-kills.ll index de80c927cea5..3a458e481936 100644 --- a/test/CodeGen/ARM/ifconv-kills.ll +++ b/test/CodeGen/ARM/ifconv-kills.ll @@ -10,15 +10,15 @@ entry: ; present something which can be easily if-converted if.then: ; %R0 should be killed here - %valt = load i32* %ptr, align 4 + %valt = load i32, i32* %ptr, align 4 br label %return if.else: ; %R0 should be killed here, however after if-conversion the %R0 kill ; has to be removed because if.then will follow after this and still ; read it. - %addr = getelementptr inbounds i32* %ptr, i32 4 - %vale = load i32* %addr, align 4 + %addr = getelementptr inbounds i32, i32* %ptr, i32 4 + %vale = load i32, i32* %addr, align 4 br label %return return: diff --git a/test/CodeGen/ARM/ifconv-regmask.ll b/test/CodeGen/ARM/ifconv-regmask.ll index d45f65f9567f..2144ca6e4074 100644 --- a/test/CodeGen/ARM/ifconv-regmask.ll +++ b/test/CodeGen/ARM/ifconv-regmask.ll @@ -7,7 +7,7 @@ ; Function Attrs: nounwind ssp define i32 @sfu() { entry: - %bf.load = load i32* getelementptr inbounds (%union.opcode* @opcode, i32 0, i32 0), align 4 + %bf.load = load i32, i32* getelementptr inbounds (%union.opcode, %union.opcode* @opcode, i32 0, i32 0), align 4 %bf.lshr = lshr i32 %bf.load, 26 %bf.clear = and i32 %bf.lshr, 7 switch i32 %bf.clear, label %return [ diff --git a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll index f76fd302774b..4e6924fe5b6b 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll @@ -50,7 +50,7 @@ if.else.i.i: br label %_ZN1M6spliceEv.exit _ZN1M6spliceEv.exit: - %LIS = getelementptr inbounds %classK* %this, i32 0, i32 1 + %LIS = getelementptr inbounds %classK, %classK* %this, i32 0, i32 1 call void @_ZN1F10handleMoveEb(%classF* %LIS, i1 zeroext false) unreachable } diff --git a/test/CodeGen/ARM/ifcvt-branch-weight.ll b/test/CodeGen/ARM/ifcvt-branch-weight.ll index 2d12a899f4b3..41d78e53acc7 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight.ll @@ -3,16 +3,16 @@ %struct.S = type { i8* (i8*)*, [1 x i8] } define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { entry: - %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0 - %1 = load i8* %0, align 1 + %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0 + %1 = load i8, i8* %0, align 1 %2 = zext i8 %1 to i32 %3 = and i32 %2, 112 %4 = icmp eq i32 %3, 0 br i1 %4, label %return, label %bb bb: - %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0 - %6 = load i8* %5, align 1 + %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0 + %6 = load i8, i8* %5, align 1 %7 = zext i8 %6 to i32 %8 = and i32 %7, 112 %9 = icmp eq i32 %8, 0 diff --git a/test/CodeGen/ARM/ifcvt-dead-def.ll b/test/CodeGen/ARM/ifcvt-dead-def.ll new file mode 100644 index 000000000000..77a3f5c0961f --- /dev/null +++ b/test/CodeGen/ARM/ifcvt-dead-def.ll @@ -0,0 +1,55 @@ +; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-unknown-unknown" + +%struct.ref_s = type { %union.v, i16, i16 } +%union.v = type { i32 } +%struct.gs_color_s = type { i16, i16, i16, i16, i8, i8 } + +; In this case, the if converter was cloning the return instruction so that we had +; r2<def> = ... +; return [pred] r2<dead,def> +; ldr <r2, kill> +; return +; The problem here was that the dead def on the first return was making the machine verifier +; think that the load read from an undefined register. We need to remove the dead flag from +; the return, and also add an implicit use of the prior value of r2. + +; CHECK: ldrh + +; Function Attrs: minsize nounwind optsize ssp +define i32 @test(%struct.ref_s* %pref1, %struct.ref_s* %pref2, %struct.gs_color_s** %tmp152) #0 { +bb: + %nref = alloca %struct.ref_s, align 4 + %tmp46 = call %struct.ref_s* @name_string_ref(%struct.ref_s* %pref1, %struct.ref_s* %nref) #2 + %tmp153 = load %struct.gs_color_s*, %struct.gs_color_s** %tmp152, align 4 + %tmp154 = bitcast %struct.ref_s* %pref2 to %struct.gs_color_s** + %tmp155 = load %struct.gs_color_s*, %struct.gs_color_s** %tmp154, align 4 + %tmp162 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp153, i32 0, i32 1 + %tmp163 = load i16, i16* %tmp162, align 2 + %tmp164 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp155, i32 0, i32 1 + %tmp165 = load i16, i16* %tmp164, align 2 + %tmp166 = icmp eq i16 %tmp163, %tmp165 + br i1 %tmp166, label %bb167, label %bb173 + +bb167: ; preds = %bb + %tmp168 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp153, i32 0, i32 2 + %tmp169 = load i16, i16* %tmp168, align 2 + %tmp170 = getelementptr inbounds %struct.gs_color_s, %struct.gs_color_s* %tmp155, i32 0, i32 2 + %tmp171 = load i16, i16* %tmp170, align 2 + %tmp172 = icmp eq i16 %tmp169, %tmp171 + br label %bb173 + +bb173: ; preds = %bb167, %bb + %tmp174 = phi i1 [ false, %bb ], [ %tmp172, %bb167 ] + %tmp175 = zext i1 %tmp174 to i32 + ret i32 %tmp175 +} + +; Function Attrs: minsize optsize +declare %struct.ref_s* @name_string_ref(%struct.ref_s*, %struct.ref_s*) #1 + +attributes #0 = { minsize nounwind optsize } +attributes #1 = { minsize optsize } +attributes #2 = { minsize nounwind optsize } diff --git a/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/test/CodeGen/ARM/ifcvt-iter-indbr.ll new file mode 100644 index 000000000000..75e9d77d7920 --- /dev/null +++ b/test/CodeGen/ARM/ifcvt-iter-indbr.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s + +declare i32 @foo(i32) +declare i8* @bar(i32, i8*, i8*) + +; Verify that we don't try to iteratively re-ifconvert a block with a +; (predicated) indirectbr terminator. +; If we do, we would ignore its fallthrough successor. + + +; CHECK-LABEL: test: +; CHECK: cmp {{.*}}, #21 +; CHECK-NEXT: itt eq +; CHECK-NEXT: streq.w +; CHECK-NEXT: moveq pc +; CHECK-NEXT: LBB{{[0-9_]+}}: +; CHECK-NEXT: cmp {{.*}}, #42 +; CHECK-NEXT: itt ne +; CHECK-NEXT: strne.w +; CHECK-NEXT: movne pc +; CHECK-NEXT: Ltmp +; CHECK-NEXT: LBB0_2: +; CHECK-NEXT: movw r0, #1234 +; CHECK-NEXT: b [[FOOCALL:LBB[0-9_]+]] +; CHECK-NEXT: Ltmp +; CHECK-NEXT: LBB{{[0-9_]+}}: +; CHECK-NEXT: movw r0, #4567 +; CHECK-NEXT: [[FOOCALL]]: +; CHECK-NEXT: blx _foo + +define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) { +entry: + %dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2)) + %dst2 = call i8* @bar(i32 2, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2)) + %dst3 = call i8* @bar(i32 3, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2)) + %cc1 = icmp eq i32 %a, 21 + br i1 %cc1, label %cc1t, label %cc1f + +cc1t: + store i32 %a, i32* %p + indirectbr i8* %dst3, [label %bb1, label %bb2] + +cc1f: + %cc2 = icmp ne i32 %a2, 42 + br i1 %cc2, label %cc2t, label %bb1 +cc2t: + store i32 %a, i32* %p2 + indirectbr i8* %dst1, [label %bb1, label %bb2] + +bb1: + %ret_bb1 = call i32 @foo(i32 1234) + ret i32 %ret_bb1 +bb2: + %ret_bb2 = call i32 @foo(i32 4567) + ret i32 %ret_bb2 +} diff --git a/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll b/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll new file mode 100644 index 000000000000..cf04fc90504a --- /dev/null +++ b/test/CodeGen/ARM/ifcvt-regmask-noreturn.ll @@ -0,0 +1,45 @@ +; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +@debw = external global i8*, align 4 + +; This test ensures that the stack_chk call correctly puts implicit uses/defs for the regsiters +; live across it when if converting. This will be R0 which is passed to the call to free at the end +; of the function. +; Prior to this change, the stack_chk call (which does not return) would clobber R0 in its regmask, +; leading to verifier errors because the later use of R0 in free() is not live. + +; CHECK-LABEL: @test +; CHECK: stack_chk_fail + +; Function Attrs: ssp +define void @test(i32 %argc, i8** nocapture readonly %argv, i32* %ptr, i32 %val) #0 { +entry: + %count.i = alloca [256 x i32], align 4 + %cmp284.i = icmp eq i32 %val, 0 + br i1 %cmp284.i, label %for.end31.i, label %for.body21.i + +for.body21.i: ; preds = %entry + %arrayidx23.i = getelementptr inbounds [256 x i32], [256 x i32]* %count.i, i32 0, i32 1 + %tmp20 = load i32, i32* %arrayidx23.i, align 4, !tbaa !0 + store i32 %tmp20, i32* %ptr, align 4, !tbaa !0 + br label %for.end31.i + +for.end31.i: ; preds = %for.body21.i, %entry + %tmp21 = load i8*, i8** @debw, align 4, !tbaa !4 + tail call void @free(i8* %tmp21) + ret void +} + +declare void @free(i8* nocapture) + +attributes #0 = { ssp "stack-protector-buffer-size"="8" } + +!0 = !{!1, !1, i64 0} +!1 = !{!"int", !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} +!4 = !{!5, !5, i64 0} +!5 = !{!"any pointer", !2, i64 0} diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll index dba8a3f1a6af..eae41e21c610 100644 --- a/test/CodeGen/ARM/ifcvt11.ll +++ b/test/CodeGen/ARM/ifcvt11.ll @@ -21,10 +21,10 @@ bb: ; preds = %bb4, %bb.nph ; CHECK: vmrs APSR_nzcv, fpscr %r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ] %n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ] - %scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0 - %scevgep11 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 1 - %3 = load double* %scevgep10, align 4 - %4 = load double* %scevgep11, align 4 + %scevgep10 = getelementptr inbounds %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 0 + %scevgep11 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 1 + %3 = load double, double* %scevgep10, align 4 + %4 = load double, double* %scevgep11, align 4 %5 = fcmp uge double %3, %4 br i1 %5, label %bb3, label %bb1 @@ -34,8 +34,8 @@ bb1: ; preds = %bb ; CHECK-NOT: vmrsmi ; CHECK: vcmpe.f64 ; CHECK: vmrs APSR_nzcv, fpscr - %scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2 - %6 = load double* %scevgep12, align 4 + %scevgep12 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 2 + %6 = load double, double* %scevgep12, align 4 %7 = fcmp uge double %3, %6 br i1 %7, label %bb3, label %bb2 diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll index 5da63dc5f022..e53d989ad529 100644 --- a/test/CodeGen/ARM/ifcvt3.ll +++ b/test/CodeGen/ARM/ifcvt3.ll @@ -4,8 +4,8 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: t1: -; CHECK: cmp r2, #1 -; CHECK: cmpne r2, #7 +; CHECK: cmp r2, #7 +; CHECK: cmpne r2, #1 switch i32 %c, label %cond_next [ i32 1, label %cond_true i32 7, label %cond_true diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index 31e3e00c468e..3aa2139cc03a 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -6,7 +6,7 @@ define void @foo(i32 %a) { entry: - %tmp = load i32** @x ; <i32*> [#uses=1] + %tmp = load i32*, i32** @x ; <i32*> [#uses=1] store i32 %a, i32* %tmp ret void } diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index a00dedaee670..78901930e4b2 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -10,7 +10,7 @@ entry: br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp10 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp10 = call i32 (...) @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/ARM/ifcvt7.ll b/test/CodeGen/ARM/ifcvt7.ll index 476ed4d47c64..e0d2b7cffb44 100644 --- a/test/CodeGen/ARM/ifcvt7.ll +++ b/test/CodeGen/ARM/ifcvt7.ll @@ -11,9 +11,9 @@ entry: br label %tailrecurse tailrecurse: ; preds = %bb, %entry - %tmp6 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] - %tmp9 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2] - %tmp12 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] + %tmp6 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] + %tmp9 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2] + %tmp12 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] %tmp14 = icmp eq %struct.quad_struct* null, null ; <i1> [#uses=1] %tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; <i1> [#uses=1] %tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/illegal-vector-bitcast.ll b/test/CodeGen/ARM/illegal-vector-bitcast.ll index 7208fffbcc85..766b3d7ca433 100644 --- a/test/CodeGen/ARM/illegal-vector-bitcast.ll +++ b/test/CodeGen/ARM/illegal-vector-bitcast.ll @@ -3,10 +3,10 @@ define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y) { - %h = load <8 x float>* %f + %h = load <8 x float>, <8 x float>* %f %i = fmul <8 x float> %h, <float 0x3FF19999A0000000, float 0x400A666660000000, float 0x40119999A0000000, float 0x40159999A0000000, float 0.5, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000> %m = bitcast <8 x float> %i to <4 x i64> - %z = load <4 x i64>* %y + %z = load <4 x i64>, <4 x i64>* %y %n = mul <4 x i64> %z, %m %p = bitcast <4 x i64> %n to <8 x float> store <8 x float> %p, <8 x float>* %g diff --git a/test/CodeGen/ARM/indirect-reg-input.ll b/test/CodeGen/ARM/indirect-reg-input.ll index 17f6a9c96f68..e82e1dee9428 100644 --- a/test/CodeGen/ARM/indirect-reg-input.ll +++ b/test/CodeGen/ARM/indirect-reg-input.ll @@ -8,7 +8,7 @@ define void @switch_to_stack(%struct.my_stack* %stack) nounwind { entry: - %regs = getelementptr inbounds %struct.my_stack* %stack, i32 0, i32 0 + %regs = getelementptr inbounds %struct.my_stack, %struct.my_stack* %stack, i32 0, i32 0 tail call void asm "\0A", "=*r,*0"(%struct.myjmp_buf* %regs, %struct.myjmp_buf* %regs) ret void } diff --git a/test/CodeGen/ARM/indirectbr-2.ll b/test/CodeGen/ARM/indirectbr-2.ll index 0c41da658009..ca068db1db0e 100644 --- a/test/CodeGen/ARM/indirectbr-2.ll +++ b/test/CodeGen/ARM/indirectbr-2.ll @@ -15,7 +15,7 @@ define i32 @func() nounwind ssp { %1 = alloca i32, align 4 - %2 = load i32* @foo, align 4 + %2 = load i32, i32* @foo, align 4 %3 = icmp eq i32 %2, 34879 br label %4 @@ -23,17 +23,17 @@ define i32 @func() nounwind ssp { %5 = zext i1 %3 to i32 %6 = mul i32 %5, 287 %7 = add i32 %6, 2 - %8 = getelementptr [2 x i32]* @DWJumpTable2808, i32 0, i32 %5 - %9 = load i32* %8 + %8 = getelementptr [2 x i32], [2 x i32]* @DWJumpTable2808, i32 0, i32 %5 + %9 = load i32, i32* %8 %10 = add i32 %9, ptrtoint (i8* blockaddress(@func, %4) to i32) %11 = inttoptr i32 %10 to i8* - %12 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([45 x i8]* @0, i32 0, i32 0)) + %12 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @0, i32 0, i32 0)) indirectbr i8* %11, [label %13, label %14] ; <label>:13 ; preds = %4 %tmp14 = phi i32 [ %7, %4 ] store i32 23958, i32* @foo, align 4 - %tmp15 = load i32* %1, align 4 + %tmp15 = load i32, i32* %1, align 4 %tmp16 = icmp eq i32 %tmp15, 0 %tmp17 = zext i1 %tmp16 to i32 %tmp21 = add i32 %tmp17, %tmp14 diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index 7c49cb310f39..d15ef14b4493 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -16,7 +16,7 @@ entry: ; THUMB: [[NEXTADDR_PCBASE:LPC0_[0-9]]]: ; THUMB: add r[[NEXTADDR_REG]], pc - %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2] + %0 = load i8*, i8** @nextaddr, align 4 ; <i8*> [#uses=2] %1 = icmp eq i8* %0, null ; <i1> [#uses=1] ; indirect branch gets duplicated here ; ARM: bx @@ -31,8 +31,8 @@ bb2: ; preds = %entry, %bb3 indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] bb3: ; preds = %entry - %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1] - %gotovar.4.0.pre = load i8** %2, align 4 ; <i8*> [#uses=1] + %2 = getelementptr inbounds [5 x i8*], [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1] + %gotovar.4.0.pre = load i8*, i8** %2, align 4 ; <i8*> [#uses=1] br label %bb2 L5: ; preds = %bb2 diff --git a/test/CodeGen/ARM/inline-diagnostics.ll b/test/CodeGen/ARM/inline-diagnostics.ll index 0276abf2f5fa..3f5b73c5a211 100644 --- a/test/CodeGen/ARM/inline-diagnostics.ll +++ b/test/CodeGen/ARM/inline-diagnostics.ll @@ -8,8 +8,8 @@ define float @inline_func(float %f1, float %f2) #0 { %c2 = alloca %struct.float4, align 4 %c3 = alloca %struct.float4, align 4 call void asm sideeffect "vmul.f32 ${2:q}, ${0:q}, ${1:q}", "=*r,=*r,*w"(%struct.float4* %c1, %struct.float4* %c2, %struct.float4* %c3) #1, !srcloc !1 - %x = getelementptr inbounds %struct.float4* %c3, i32 0, i32 0 - %1 = load float* %x, align 4 + %x = getelementptr inbounds %struct.float4, %struct.float4* %c3, i32 0, i32 0 + %1 = load float, float* %x, align 4 ret float %1 } diff --git a/test/CodeGen/ARM/inlineasm-64bit.ll b/test/CodeGen/ARM/inlineasm-64bit.ll index d098a4383bc6..8e747c5eb650 100644 --- a/test/CodeGen/ARM/inlineasm-64bit.ll +++ b/test/CodeGen/ARM/inlineasm-64bit.ll @@ -35,7 +35,7 @@ entry: ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind - %incdec.ptr = getelementptr inbounds i64* %p, i32 1 + %incdec.ptr = getelementptr inbounds i64, i64* %p, i32 1 tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind ret void diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll index c6da09d156b7..43bd5815a558 100644 --- a/test/CodeGen/ARM/interrupt-attr.ll +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -35,7 +35,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to ; appropriate sentinel so no special return needed). ; CHECK-M-LABEL: irq_fn: -; CHECK-M: push.w {r4, r10, r11, lr} +; CHECK-M: push.w {r4, r7, r11, lr} ; CHECK-M: add.w r11, sp, #8 ; CHECK-M: mov r4, sp ; CHECK-M: bfc r4, #0, #3 @@ -43,7 +43,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-M: bl _bar ; CHECK-M: sub.w r4, r11, #8 ; CHECK-M: mov sp, r4 -; CHECK-M: pop.w {r4, r10, r11, pc} +; CHECK-M: pop.w {r4, r7, r11, pc} call arm_aapcscc void @bar() ret void @@ -65,7 +65,7 @@ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" { ; CHECK-A-THUMB-LABEL: fiq_fn: ; CHECK-M-LABEL: fiq_fn: - %val = load volatile [16 x i32]* @bigvar + %val = load volatile [16 x i32], [16 x i32]* @bigvar store volatile [16 x i32] %val, [16 x i32]* @bigvar ret void } @@ -81,7 +81,7 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { ; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #0 - %val = load volatile [16 x i32]* @bigvar + %val = load volatile [16 x i32], [16 x i32]* @bigvar store volatile [16 x i32] %val, [16 x i32]* @bigvar ret void } @@ -126,8 +126,8 @@ define arm_aapcscc void @floating_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-A-NOT: vstr ; CHECK-A-NOT: vstm ; CHECK-A: vadd.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} - %lhs = load volatile double* @var - %rhs = load volatile double* @var + %lhs = load volatile double, double* @var + %rhs = load volatile double, double* @var %sum = fadd double %lhs, %rhs store double %sum, double* @var ret void diff --git a/test/CodeGen/ARM/intrinsics-crypto.ll b/test/CodeGen/ARM/intrinsics-crypto.ll index 96413d341e4c..6e5efd85a347 100644 --- a/test/CodeGen/ARM/intrinsics-crypto.ll +++ b/test/CodeGen/ARM/intrinsics-crypto.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) { - %tmp = load <16 x i8>* %a - %tmp2 = load <16 x i8>* %b + %tmp = load <16 x i8>, <16 x i8>* %a + %tmp2 = load <16 x i8>, <16 x i8>* %b %tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2) ; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}} %tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2) @@ -15,9 +15,9 @@ define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) { } define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) { - %tmp = load <4 x i32>* %a - %tmp2 = load <4 x i32>* %b - %tmp3 = load <4 x i32>* %c + %tmp = load <4 x i32>, <4 x i32>* %a + %tmp2 = load <4 x i32>, <4 x i32>* %b + %tmp3 = load <4 x i32>, <4 x i32>* %c %scalar = extractelement <4 x i32> %tmp, i32 0 %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar) %res1 = insertelement <4 x i32> undef, i32 %resscalar, i32 0 diff --git a/test/CodeGen/ARM/intrinsics-memory-barrier.ll b/test/CodeGen/ARM/intrinsics-memory-barrier.ll index 5ee0b3e59902..5626d38aae4b 100644 --- a/test/CodeGen/ARM/intrinsics-memory-barrier.ll +++ b/test/CodeGen/ARM/intrinsics-memory-barrier.ll @@ -18,7 +18,7 @@ define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) { call void @llvm.arm.dmb(i32 15) ; CHECK: dmb sy - %d1 = getelementptr i32* %d, i32 1 + %d1 = getelementptr i32, i32* %d, i32 1 store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4] ret void @@ -31,7 +31,7 @@ define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) { call void @llvm.arm.dsb(i32 15) ; CHECK: dsb sy - %d1 = getelementptr i32* %d, i32 1 + %d1 = getelementptr i32, i32* %d, i32 1 store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4] ret void @@ -44,7 +44,7 @@ define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) { call void @llvm.arm.isb(i32 15) ; CHECK: isb sy - %d1 = getelementptr i32* %d, i32 1 + %d1 = getelementptr i32, i32* %d, i32 1 store i32 %b, i32* %d1 ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4] ret void diff --git a/test/CodeGen/ARM/invoke-donothing-assert.ll b/test/CodeGen/ARM/invoke-donothing-assert.ll index 0b607f7edf38..aab3556c5477 100644 --- a/test/CodeGen/ARM/invoke-donothing-assert.ll +++ b/test/CodeGen/ARM/invoke-donothing-assert.ll @@ -46,7 +46,7 @@ new.notnull.i.i: br label %cleanup cleanup: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %inc294 = add nsw i32 %0, 4 store i32 %inc294, i32* %a, align 4 br i1 false, label %_ZN3lol5ArrayIivvvvvvvED1Ev.exit, label %delete.notnull.i.i.i1409 diff --git a/test/CodeGen/ARM/isel-v8i32-crash.ll b/test/CodeGen/ARM/isel-v8i32-crash.ll index 0116fe8de7cc..f1745bd47279 100644 --- a/test/CodeGen/ARM/isel-v8i32-crash.ll +++ b/test/CodeGen/ARM/isel-v8i32-crash.ll @@ -15,7 +15,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" define void @func(i16* nocapture %pb, float* nocapture readonly %pf) #0 { entry: %0 = bitcast float* %pf to <8 x float>* - %1 = load <8 x float>* %0, align 4 + %1 = load <8 x float>, <8 x float>* %0, align 4 %2 = fmul <8 x float> %1, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00> %3 = fptosi <8 x float> %2 to <8 x i16> %4 = bitcast i16* %pb to <8 x i16>* diff --git a/test/CodeGen/ARM/krait-cpu-div-attribute.ll b/test/CodeGen/ARM/krait-cpu-div-attribute.ll new file mode 100644 index 000000000000..222664a904ca --- /dev/null +++ b/test/CodeGen/ARM/krait-cpu-div-attribute.ll @@ -0,0 +1,36 @@ +; Tests the genration of ".arch_extension" attribute for hardware +; division on krait CPU. For now, krait is recognized as "cortex-a9" + hwdiv +; Also, tests for the hwdiv instruction on krait CPU + +; check for arch_extension/cpu directive +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait | FileCheck %s --check-prefix=DIV_EXTENSION +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait | FileCheck %s --check-prefix=DIV_EXTENSION +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=NODIV_KRAIT +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=NODIV_KRAIT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -mattr=-hwdiv,-hwdiv-arm | FileCheck %s --check-prefix=NODIV_KRAIT + +; check if correct instruction is emitted by integrated assembler +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple armv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple thumbv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV + +; arch_extension attribute +; DIV_EXTENSION: .cpu cortex-a9 +; DIV_EXTENSION: .arch_extension idiv +; NODIV_KRAIT-NOT: .arch_extension idiv +; HWDIV: sdiv + +define i32 @main() #0 { +entry: + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %b = alloca i32, align 4 + %c = alloca i32, align 4 + store i32 0, i32* %retval + store volatile i32 100, i32* %b, align 4 + store volatile i32 32, i32* %c, align 4 + %0 = load volatile i32, i32* %b, align 4 + %1 = load volatile i32, i32* %c, align 4 + %div = sdiv i32 %0, %1 + store volatile i32 %div, i32* %a, align 4 + ret i32 0 +} diff --git a/test/CodeGen/ARM/large-stack.ll b/test/CodeGen/ARM/large-stack.ll index 1a9a1fadeebe..e2d4de341ec2 100644 --- a/test/CodeGen/ARM/large-stack.ll +++ b/test/CodeGen/ARM/large-stack.ll @@ -15,6 +15,6 @@ define i32 @test3() { %tmp = alloca i32, align 4 %a = alloca [805306369 x i8], align 16 store i32 0, i32* %tmp - %tmp1 = load i32* %tmp + %tmp1 = load i32, i32* %tmp ret i32 %tmp1 } diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 3977da6da9cb..65e972f4e1b4 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -8,8 +8,8 @@ define i32 @t1() { ; CHECK: pop ; V4T-LABEL: t1: ; V4T: pop - %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1] - %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] + %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1] + %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1] ret i32 %tmp4 } @@ -19,9 +19,9 @@ define i32 @t2() { ; CHECK: pop ; V4T-LABEL: t2: ; V4T: pop - %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] - %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] - %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1] + %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] + %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] + %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1] %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] ret i32 %tmp6 } @@ -34,9 +34,9 @@ define i32 @t3() { ; V4T: ldmib ; V4T: pop ; V4T-NEXT: bx lr - %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] - %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] - %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] + %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] + %tmp3 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] + %tmp5 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] ret i32 %tmp6 } diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll index 57e9977ff872..bd4de5de669c 100644 --- a/test/CodeGen/ARM/ldr.ll +++ b/test/CodeGen/ARM/ldr.ll @@ -4,7 +4,7 @@ define i32 @f1(i32* %v) { ; CHECK-LABEL: f1: ; CHECK: ldr r0 entry: - %tmp = load i32* %v + %tmp = load i32, i32* %v ret i32 %tmp } @@ -12,8 +12,8 @@ define i32 @f2(i32* %v) { ; CHECK-LABEL: f2: ; CHECK: ldr r0 entry: - %tmp2 = getelementptr i32* %v, i32 1023 - %tmp = load i32* %tmp2 + %tmp2 = getelementptr i32, i32* %v, i32 1023 + %tmp = load i32, i32* %tmp2 ret i32 %tmp } @@ -22,8 +22,8 @@ define i32 @f3(i32* %v) { ; CHECK: mov ; CHECK: ldr r0 entry: - %tmp2 = getelementptr i32* %v, i32 1024 - %tmp = load i32* %tmp2 + %tmp2 = getelementptr i32, i32* %v, i32 1024 + %tmp = load i32, i32* %tmp2 ret i32 %tmp } @@ -34,7 +34,7 @@ define i32 @f4(i32 %base) { entry: %tmp1 = sub i32 %base, 128 %tmp2 = inttoptr i32 %tmp1 to i32* - %tmp3 = load i32* %tmp2 + %tmp3 = load i32, i32* %tmp2 ret i32 %tmp3 } @@ -44,7 +44,7 @@ define i32 @f5(i32 %base, i32 %offset) { entry: %tmp1 = add i32 %base, %offset %tmp2 = inttoptr i32 %tmp1 to i32* - %tmp3 = load i32* %tmp2 + %tmp3 = load i32, i32* %tmp2 ret i32 %tmp3 } @@ -55,7 +55,7 @@ entry: %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 %tmp3 = inttoptr i32 %tmp2 to i32* - %tmp4 = load i32* %tmp3 + %tmp4 = load i32, i32* %tmp3 ret i32 %tmp4 } @@ -66,6 +66,6 @@ entry: %tmp1 = lshr i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 %tmp3 = inttoptr i32 %tmp2 to i32* - %tmp4 = load i32* %tmp3 + %tmp4 = load i32, i32* %tmp3 ret i32 %tmp4 } diff --git a/test/CodeGen/ARM/ldr_ext.ll b/test/CodeGen/ARM/ldr_ext.ll index 31aaba5c3c21..15efb50c9a9a 100644 --- a/test/CodeGen/ARM/ldr_ext.ll +++ b/test/CodeGen/ARM/ldr_ext.ll @@ -2,28 +2,28 @@ define i32 @test1(i8* %t1) nounwind { ; CHECK: ldrb - %tmp.u = load i8* %t1 + %tmp.u = load i8, i8* %t1 %tmp1.s = zext i8 %tmp.u to i32 ret i32 %tmp1.s } define i32 @test2(i16* %t1) nounwind { ; CHECK: ldrh - %tmp.u = load i16* %t1 + %tmp.u = load i16, i16* %t1 %tmp1.s = zext i16 %tmp.u to i32 ret i32 %tmp1.s } define i32 @test3(i8* %t0) nounwind { ; CHECK: ldrsb - %tmp.s = load i8* %t0 + %tmp.s = load i8, i8* %t0 %tmp1.s = sext i8 %tmp.s to i32 ret i32 %tmp1.s } define i32 @test4(i16* %t0) nounwind { ; CHECK: ldrsh - %tmp.s = load i16* %t0 + %tmp.s = load i16, i16* %t0 %tmp1.s = sext i16 %tmp.s to i32 ret i32 %tmp1.s } @@ -31,7 +31,7 @@ define i32 @test4(i16* %t0) nounwind { define i32 @test5() nounwind { ; CHECK: mov r0, #0 ; CHECK: ldrsh - %tmp.s = load i16* null + %tmp.s = load i16, i16* null %tmp1.s = sext i16 %tmp.s to i32 ret i32 %tmp1.s } diff --git a/test/CodeGen/ARM/ldr_frame.ll b/test/CodeGen/ARM/ldr_frame.ll index ed964ecd3f83..01b18bccc337 100644 --- a/test/CodeGen/ARM/ldr_frame.ll +++ b/test/CodeGen/ARM/ldr_frame.ll @@ -2,30 +2,30 @@ define i32 @f1() { %buf = alloca [32 x i32], align 4 - %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0 - %tmp1 = load i32* %tmp + %tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 0 + %tmp1 = load i32, i32* %tmp ret i32 %tmp1 } define i32 @f2() { %buf = alloca [32 x i8], align 4 - %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 0 - %tmp1 = load i8* %tmp + %tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 0 + %tmp1 = load i8, i8* %tmp %tmp2 = zext i8 %tmp1 to i32 ret i32 %tmp2 } define i32 @f3() { %buf = alloca [32 x i32], align 4 - %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32 - %tmp1 = load i32* %tmp + %tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 32 + %tmp1 = load i32, i32* %tmp ret i32 %tmp1 } define i32 @f4() { %buf = alloca [32 x i8], align 4 - %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 2 - %tmp1 = load i8* %tmp + %tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 2 + %tmp1 = load i8, i8* %tmp %tmp2 = zext i8 %tmp1 to i32 ret i32 %tmp2 } diff --git a/test/CodeGen/ARM/ldr_post.ll b/test/CodeGen/ARM/ldr_post.ll index 2558b16f3d3c..139c6f45e520 100644 --- a/test/CodeGen/ARM/ldr_post.ll +++ b/test/CodeGen/ARM/ldr_post.ll @@ -7,7 +7,7 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b ; <i32> [#uses=2] %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1] - %tmp3 = load i32* %tmp2 ; <i32> [#uses=1] + %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1] %tmp4 = sub i32 %tmp1, %c ; <i32> [#uses=1] %tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1] ret i32 %tmp5 @@ -19,7 +19,7 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) { define i32 @test2(i32 %a, i32 %b) { %tmp1 = mul i32 %a, %b ; <i32> [#uses=2] %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1] - %tmp3 = load i32* %tmp2 ; <i32> [#uses=1] + %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1] %tmp4 = sub i32 %tmp1, 16 ; <i32> [#uses=1] %tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1] ret i32 %tmp5 diff --git a/test/CodeGen/ARM/ldr_pre.ll b/test/CodeGen/ARM/ldr_pre.ll index a97927a20ab1..c6c76e222836 100644 --- a/test/CodeGen/ARM/ldr_pre.ll +++ b/test/CodeGen/ARM/ldr_pre.ll @@ -5,8 +5,8 @@ ; CHECK: ldr {{.*!}} ; CHECK-NOT: ldr define i32* @test1(i32* %X, i32* %dest) { - %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] - %A = load i32* %Y ; <i32> [#uses=1] + %Y = getelementptr i32, i32* %X, i32 4 ; <i32*> [#uses=2] + %A = load i32, i32* %Y ; <i32> [#uses=1] store i32 %A, i32* %dest ret i32* %Y } @@ -17,7 +17,7 @@ define i32* @test1(i32* %X, i32* %dest) { define i32 @test2(i32 %a, i32 %b, i32 %c) { %tmp1 = sub i32 %a, %b ; <i32> [#uses=2] %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1] - %tmp3 = load i32* %tmp2 ; <i32> [#uses=1] + %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1] %tmp4 = sub i32 %tmp1, %c ; <i32> [#uses=1] %tmp5 = add i32 %tmp4, %tmp3 ; <i32> [#uses=1] ret i32 %tmp5 diff --git a/test/CodeGen/ARM/ldrd-memoper.ll b/test/CodeGen/ARM/ldrd-memoper.ll index f1a1121f6aa4..744fbd5efb86 100644 --- a/test/CodeGen/ARM/ldrd-memoper.ll +++ b/test/CodeGen/ARM/ldrd-memoper.ll @@ -8,8 +8,8 @@ ; CHECK: Formed {{.*}} t2LDRD{{.*}} mem:LD4[%0] LD4[%0+4] define i64 @t(i64 %a) nounwind readonly { entry: - %0 = load i64** @b, align 4 - %1 = load i64* %0, align 4 + %0 = load i64*, i64** @b, align 4 + %1 = load i64, i64* %0, align 4 %2 = mul i64 %1, %a ret i64 %2 } diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index caef2e78bbfa..7ce846844e05 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -19,8 +19,8 @@ entry: ; M3-LABEL: t: ; M3-NOT: ldrd - %0 = load i64** @b, align 4 - %1 = load i64* %0, align 4 + %0 = load i64*, i64** @b, align 4 + %1 = load i64, i64* %0, align 4 %2 = mul i64 %1, %a ret i64 %2 } @@ -53,12 +53,12 @@ entry: bb: ; preds = %bb, %entry %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3] - %scevgep = getelementptr i32* %a, i32 %i.03 ; <i32*> [#uses=1] - %scevgep4 = getelementptr i32* %b, i32 %i.03 ; <i32*> [#uses=1] + %scevgep = getelementptr i32, i32* %a, i32 %i.03 ; <i32*> [#uses=1] + %scevgep4 = getelementptr i32, i32* %b, i32 %i.03 ; <i32*> [#uses=1] %tmp = add i32 %i.03, 1 ; <i32> [#uses=3] - %scevgep5 = getelementptr i32* %a, i32 %tmp ; <i32*> [#uses=1] - %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1] - %3 = load i32* %scevgep5, align 4 ; <i32> [#uses=1] + %scevgep5 = getelementptr i32, i32* %a, i32 %tmp ; <i32*> [#uses=1] + %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1] + %3 = load i32, i32* %scevgep5, align 4 ; <i32> [#uses=1] %4 = add nsw i32 %3, %2 ; <i32> [#uses=1] store i32 %4, i32* %scevgep4, align 4 %exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1] @@ -84,10 +84,10 @@ entry: ; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}} %orig_blocks = alloca [256 x i16], align 2 %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind - %tmp1 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 1), align 4 - %tmp2 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 2), align 4 + %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4 + %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4 %add = add nsw i32 %tmp2, %tmp1 - store i32 %add, i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 0), align 4 + store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4 call void @llvm.lifetime.end(i64 512, i8* %0) nounwind ret void } diff --git a/test/CodeGen/ARM/ldst-f32-2-i32.ll b/test/CodeGen/ARM/ldst-f32-2-i32.ll index 61c459c7435e..d00f44e8e885 100644 --- a/test/CodeGen/ARM/ldst-f32-2-i32.ll +++ b/test/CodeGen/ARM/ldst-f32-2-i32.ll @@ -14,10 +14,10 @@ bb: ; CHECK: str [[REGISTER]], [{{r[0-9]+}}], #4 %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] %tmp = mul i32 %j.05, %index - %uglygep = getelementptr i8* %src6, i32 %tmp + %uglygep = getelementptr i8, i8* %src6, i32 %tmp %src_addr.04 = bitcast i8* %uglygep to float* - %dst_addr.03 = getelementptr float* %dst, i32 %j.05 - %1 = load float* %src_addr.04, align 4 + %dst_addr.03 = getelementptr float, float* %dst, i32 %j.05 + %1 = load float, float* %src_addr.04, align 4 store float %1, float* %dst_addr.03, align 4 %2 = add i32 %j.05, 1 %exitcond = icmp eq i32 %2, %width diff --git a/test/CodeGen/ARM/ldstrex-m.ll b/test/CodeGen/ARM/ldstrex-m.ll index b50699f4cde6..3d83a9d78e35 100644 --- a/test/CodeGen/ARM/ldstrex-m.ll +++ b/test/CodeGen/ARM/ldstrex-m.ll @@ -4,7 +4,7 @@ ; CHECK-NOT: ldrexd define i64 @f0(i64* %p) nounwind readonly { entry: - %0 = load atomic i64* %p seq_cst, align 8 + %0 = load atomic i64, i64* %p seq_cst, align 8 ret i64 %0 } @@ -29,7 +29,7 @@ entry: ; CHECK: ldr define i32 @f3(i32* %p) nounwind readonly { entry: - %0 = load atomic i32* %p seq_cst, align 4 + %0 = load atomic i32, i32* %p seq_cst, align 4 ret i32 %0 } @@ -37,7 +37,7 @@ entry: ; CHECK: ldrb define i8 @f4(i8* %p) nounwind readonly { entry: - %0 = load atomic i8* %p seq_cst, align 4 + %0 = load atomic i8, i8* %p seq_cst, align 4 ret i8 %0 } diff --git a/test/CodeGen/ARM/ldstrex.ll b/test/CodeGen/ARM/ldstrex.ll index a40e255e83ea..59349f72a8fe 100644 --- a/test/CodeGen/ARM/ldstrex.ll +++ b/test/CodeGen/ARM/ldstrex.ll @@ -106,24 +106,24 @@ declare void @llvm.arm.clrex() nounwind define void @excl_addrmode() { ; CHECK-T2ADDRMODE-LABEL: excl_addrmode: - %base1020 = load i32** @base - %offset1020 = getelementptr i32* %base1020, i32 255 + %base1020 = load i32*, i32** @base + %offset1020 = getelementptr i32, i32* %base1020, i32 255 call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020) call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1020) ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020] - %base1024 = load i32** @base - %offset1024 = getelementptr i32* %base1024, i32 256 + %base1024 = load i32*, i32** @base + %offset1024 = getelementptr i32, i32* %base1024, i32 256 call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024) call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1024) ; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024 ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] - %base1 = load i32** @base + %base1 = load i32*, i32** @base %addr8 = bitcast i32* %base1 to i8* - %offset1_8 = getelementptr i8* %addr8, i32 1 + %offset1_8 = getelementptr i8, i8* %addr8, i32 1 %offset1 = bitcast i8* %offset1_8 to i32* call i32 @llvm.arm.ldrex.p0i32(i32* %offset1) call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1) diff --git a/test/CodeGen/ARM/load-global.ll b/test/CodeGen/ARM/load-global.ll index 00ca2e8b1b75..34748bc848bd 100644 --- a/test/CodeGen/ARM/load-global.ll +++ b/test/CodeGen/ARM/load-global.ll @@ -45,6 +45,6 @@ define i32 @test1() { ; LINUX: ldr r0, [r1, r0] ; LINUX: ldr r0, [r0] ; LINUX: .long G(GOT) - %tmp = load i32* @G + %tmp = load i32, i32* @G ret i32 %tmp } diff --git a/test/CodeGen/ARM/load.ll b/test/CodeGen/ARM/load.ll index ca16adc00822..3b2d637cb26e 100644 --- a/test/CodeGen/ARM/load.ll +++ b/test/CodeGen/ARM/load.ll @@ -2,28 +2,28 @@ define i32 @f1(i8* %p) { entry: - %tmp = load i8* %p ; <i8> [#uses=1] + %tmp = load i8, i8* %p ; <i8> [#uses=1] %tmp1 = sext i8 %tmp to i32 ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f2(i8* %p) { entry: - %tmp = load i8* %p ; <i8> [#uses=1] + %tmp = load i8, i8* %p ; <i8> [#uses=1] %tmp2 = zext i8 %tmp to i32 ; <i32> [#uses=1] ret i32 %tmp2 } define i32 @f3(i16* %p) { entry: - %tmp = load i16* %p ; <i16> [#uses=1] + %tmp = load i16, i16* %p ; <i16> [#uses=1] %tmp3 = sext i16 %tmp to i32 ; <i32> [#uses=1] ret i32 %tmp3 } define i32 @f4(i16* %p) { entry: - %tmp = load i16* %p ; <i16> [#uses=1] + %tmp = load i16, i16* %p ; <i16> [#uses=1] %tmp4 = zext i16 %tmp to i32 ; <i32> [#uses=1] ret i32 %tmp4 } diff --git a/test/CodeGen/ARM/load_i1_select.ll b/test/CodeGen/ARM/load_i1_select.ll index 7a208ea41752..48cd4eae58fa 100644 --- a/test/CodeGen/ARM/load_i1_select.ll +++ b/test/CodeGen/ARM/load_i1_select.ll @@ -11,7 +11,7 @@ target triple = "thumbv7-apple-ios0.0.0" ; CHECK: tst.w r[[R0]], #1 define void @foo(i8* %call, double* %p) nounwind { entry: - %tmp2 = load i8* %call + %tmp2 = load i8, i8* %call %tmp3 = trunc i8 %tmp2 to i1 %cond = select i1 %tmp3, double 2.000000e+00, double 1.000000e+00 store double %cond, double* %p diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index d0bff4a906e0..1807813d9305 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -85,6 +85,6 @@ define i64 @f10() { ; CHECK-LABEL: f10: entry: %a = alloca i64, align 8 ; <i64*> [#uses=1] - %retval = load i64* %a ; <i64> [#uses=1] + %retval = load i64, i64* %a ; <i64> [#uses=1] ret i64 %retval } diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll index fed6ec02f32d..3f30fd40b7e7 100644 --- a/test/CodeGen/ARM/longMAC.ll +++ b/test/CodeGen/ARM/longMAC.ll @@ -75,3 +75,44 @@ define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) { %add = add i64 %mul, %c ret i64 %add } + +define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) { +;CHECK-LABEL: MACLongTest6: +;CHECK: smull r12, lr, r1, r0 +;CHECK: smlal r12, lr, r3, r2 + %conv = sext i32 %a to i64 + %conv1 = sext i32 %b to i64 + %mul = mul nsw i64 %conv1, %conv + %conv2 = sext i32 %c to i64 + %conv3 = sext i32 %d to i64 + %mul4 = mul nsw i64 %conv3, %conv2 + %add = add nsw i64 %mul4, %mul + ret i64 %add +} + +define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) { +;CHECK-LABEL: MACLongTest7: +;CHECK-NOT: smlal + %conv = sext i32 %lhs to i64 + %conv1 = sext i32 %rhs to i64 + %mul = mul nsw i64 %conv1, %conv + %shl = shl i64 %mul, 32 + %shr = lshr i64 %mul, 32 + %or = or i64 %shl, %shr + %add = add i64 %or, %acc + ret i64 %add +} + +define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) { +;CHECK-LABEL: MACLongTest8: +;CHECK-NOT: smlal + %conv = zext i32 %lhs to i64 + %conv1 = zext i32 %rhs to i64 + %mul = mul nuw i64 %conv1, %conv + %and = and i64 %mul, 4294967295 + %shl = shl i64 %mul, 32 + %or = or i64 %and, %shl + %add = add i64 %or, %acc + ret i64 %add +} + diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index 153fd8fe34e4..aa2b2d26d121 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -22,17 +22,17 @@ entry: bb: ; preds = %cond_next59, %entry %indvar = phi i32 [ 0, %entry ], [ %k.069.0, %cond_next59 ] ; <i32> [#uses=6] %k.069.0 = add i32 %indvar, 1 ; <i32> [#uses=3] - %tmp3 = getelementptr i32* %mpp, i32 %indvar ; <i32*> [#uses=1] - %tmp4 = load i32* %tmp3 ; <i32> [#uses=1] - %tmp8 = getelementptr i32* %tpmm, i32 %indvar ; <i32*> [#uses=1] - %tmp9 = load i32* %tmp8 ; <i32> [#uses=1] + %tmp3 = getelementptr i32, i32* %mpp, i32 %indvar ; <i32*> [#uses=1] + %tmp4 = load i32, i32* %tmp3 ; <i32> [#uses=1] + %tmp8 = getelementptr i32, i32* %tpmm, i32 %indvar ; <i32*> [#uses=1] + %tmp9 = load i32, i32* %tmp8 ; <i32> [#uses=1] %tmp10 = add i32 %tmp9, %tmp4 ; <i32> [#uses=2] - %tmp13 = getelementptr i32* %mc, i32 %k.069.0 ; <i32*> [#uses=5] + %tmp13 = getelementptr i32, i32* %mc, i32 %k.069.0 ; <i32*> [#uses=5] store i32 %tmp10, i32* %tmp13 - %tmp17 = getelementptr i32* %ip, i32 %indvar ; <i32*> [#uses=1] - %tmp18 = load i32* %tmp17 ; <i32> [#uses=1] - %tmp22 = getelementptr i32* %tpim, i32 %indvar ; <i32*> [#uses=1] - %tmp23 = load i32* %tmp22 ; <i32> [#uses=1] + %tmp17 = getelementptr i32, i32* %ip, i32 %indvar ; <i32*> [#uses=1] + %tmp18 = load i32, i32* %tmp17 ; <i32> [#uses=1] + %tmp22 = getelementptr i32, i32* %tpim, i32 %indvar ; <i32*> [#uses=1] + %tmp23 = load i32, i32* %tmp22 ; <i32> [#uses=1] %tmp24 = add i32 %tmp23, %tmp18 ; <i32> [#uses=2] %tmp30 = icmp sgt i32 %tmp24, %tmp10 ; <i1> [#uses=1] br i1 %tmp30, label %cond_true, label %cond_next @@ -42,9 +42,9 @@ cond_true: ; preds = %bb br label %cond_next cond_next: ; preds = %cond_true, %bb - %tmp39 = load i32* %tmp13 ; <i32> [#uses=1] - %tmp42 = getelementptr i32* %ms, i32 %k.069.0 ; <i32*> [#uses=1] - %tmp43 = load i32* %tmp42 ; <i32> [#uses=1] + %tmp39 = load i32, i32* %tmp13 ; <i32> [#uses=1] + %tmp42 = getelementptr i32, i32* %ms, i32 %k.069.0 ; <i32*> [#uses=1] + %tmp43 = load i32, i32* %tmp42 ; <i32> [#uses=1] %tmp44 = add i32 %tmp43, %tmp39 ; <i32> [#uses=2] store i32 %tmp44, i32* %tmp13 %tmp52 = icmp slt i32 %tmp44, -987654321 ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/lsr-icmp-imm.ll b/test/CodeGen/ARM/lsr-icmp-imm.ll index 103642b8b72f..ef98727344e5 100644 --- a/test/CodeGen/ARM/lsr-icmp-imm.ll +++ b/test/CodeGen/ARM/lsr-icmp-imm.ll @@ -18,8 +18,8 @@ for.body: ; preds = %entry, %for.body %bi.06 = phi i32 [ %i.addr.0.bi.0, %for.body ], [ 0, %entry ] %i.addr.05 = phi i32 [ %sub, %for.body ], [ %i, %entry ] %b.04 = phi i32 [ %.b.0, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds i32* %a, i32 %i.addr.05 - %0 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.addr.05 + %0 = load i32, i32* %arrayidx, align 4 %cmp1 = icmp sgt i32 %0, %b.04 %.b.0 = select i1 %cmp1, i32 %0, i32 %b.04 %i.addr.0.bi.0 = select i1 %cmp1, i32 %i.addr.05, i32 %bi.06 diff --git a/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/test/CodeGen/ARM/lsr-scale-addr-mode.ll index 948024163ba7..063ef76d95c9 100644 --- a/test/CodeGen/ARM/lsr-scale-addr-mode.ll +++ b/test/CodeGen/ARM/lsr-scale-addr-mode.ll @@ -9,7 +9,7 @@ entry: cond_next: ; preds = %cond_next, %entry %indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ] ; <i32> [#uses=1] %tmp25 = add i32 %indvar, 1 ; <i32> [#uses=3] - %tmp36 = getelementptr i32* %a, i32 %tmp25 ; <i32*> [#uses=1] + %tmp36 = getelementptr i32, i32* %a, i32 %tmp25 ; <i32*> [#uses=1] store i32 0, i32* %tmp36 icmp eq i32 %tmp25, -1 ; <i1>:0 [#uses=1] br i1 %0, label %return, label %cond_next diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll index 3ad60d47b53b..17292cfe2896 100644 --- a/test/CodeGen/ARM/lsr-unfolded-offset.ll +++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll @@ -23,10 +23,10 @@ entry: outer.loop: ; preds = %for.inc69, %entry %overlap.081 = phi i32 [ %overlap.4, %for.inc69 ], [ 0, %entry ] %0 = phi i32 [ %inc71, %for.inc69 ], [ 0, %entry ] - %offset = getelementptr %struct.partition_entry* %part, i32 %0, i32 2 - %len = getelementptr %struct.partition_entry* %part, i32 %0, i32 3 - %tmp5 = load i64* %offset, align 4 - %tmp15 = load i64* %len, align 4 + %offset = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %0, i32 2 + %len = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %0, i32 3 + %tmp5 = load i64, i64* %offset, align 4 + %tmp15 = load i64, i64* %len, align 4 %add = add nsw i64 %tmp15, %tmp5 br label %inner.loop @@ -37,10 +37,10 @@ inner.loop: ; preds = %for.inc, %outer.loo br i1 %cmp23, label %for.inc, label %if.end if.end: ; preds = %inner.loop - %len39 = getelementptr %struct.partition_entry* %part, i32 %1, i32 3 - %offset28 = getelementptr %struct.partition_entry* %part, i32 %1, i32 2 - %tmp29 = load i64* %offset28, align 4 - %tmp40 = load i64* %len39, align 4 + %len39 = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %1, i32 3 + %offset28 = getelementptr %struct.partition_entry, %struct.partition_entry* %part, i32 %1, i32 2 + %tmp29 = load i64, i64* %offset28, align 4 + %tmp40 = load i64, i64* %len39, align 4 %add41 = add nsw i64 %tmp40, %tmp29 %cmp44 = icmp sge i64 %tmp29, %tmp5 %cmp47 = icmp slt i64 %tmp29, %add diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll index 7e4b309fd9d1..1f92ff4e1192 100644 --- a/test/CodeGen/ARM/machine-cse-cmp.ll +++ b/test/CodeGen/ARM/machine-cse-cmp.ll @@ -30,14 +30,14 @@ entry: ; CHECK: poplt ; CHECK-NOT: cmp ; CHECK: movle - %0 = load i32* @foo, align 4 + %0 = load i32, i32* @foo, align 4 %cmp28 = icmp sgt i32 %0, 0 br i1 %cmp28, label %for.body.lr.ph, label %for.cond1.preheader for.body.lr.ph: ; preds = %entry %1 = icmp sgt i32 %0, 1 %smax = select i1 %1, i32 %0, i32 1 - call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([250 x i8]* @bar, i32 0, i32 0), i8 0, i32 %smax, i32 1, i1 false) + call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([250 x i8], [250 x i8]* @bar, i32 0, i32 0), i8 0, i32 %smax, i32 1, i1 false) unreachable for.cond1.preheader: ; preds = %entry @@ -53,7 +53,7 @@ entry: ; CHECK-NOT: sub ; CHECK: cmp ; CHECK: blt -%0 = load i32* %offset, align 4 +%0 = load i32, i32* %offset, align 4 %cmp = icmp slt i32 %0, %size %s = sub nsw i32 %0, %size %size2 = sub nsw i32 %size, 0 @@ -70,7 +70,7 @@ if.end: ; CHECK-NOT: sub ; CHECK: str store i32 %s3, i32* %offset, align 4 -%add.ptr = getelementptr inbounds i8* %base, i32 %sub +%add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub br label %return return: diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll index ca6550178f92..a1eec78e453f 100644 --- a/test/CodeGen/ARM/machine-licm.ll +++ b/test/CodeGen/ARM/machine-licm.ll @@ -39,14 +39,14 @@ bb.nph: ; preds = %entry ; THUMB: LCPI0_0: ; THUMB-NOT: LCPI0_1: ; THUMB: .section - %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] + %.pre = load i32, i32* @GV, align 4 ; <i32> [#uses=1] br label %bb bb: ; preds = %bb, %bb.nph %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1] %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2] - %scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1] - %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1] + %scevgep = getelementptr i32, i32* %vals, i32 %i.03 ; <i32*> [#uses=1] + %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1] %3 = add nsw i32 %1, %2 ; <i32> [#uses=2] store i32 %3, i32* @GV, align 4 %4 = add i32 %i.03, 1 ; <i32> [#uses=2] diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index 84ce4a7f0e79..4ea26e1c59a3 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -23,20 +23,20 @@ entry: ; CHECK-T1: strb [[TREG1]], ; CHECK-T1: ldrh [[TREG2:r[0-9]]], ; CHECK-T1: strh [[TREG2]] - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false) ret i32 0 } define void @t1(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t1: -; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] +; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] ; CHECK: adds r0, #15 ; CHECK: adds r1, #15 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false) ret void } @@ -46,35 +46,32 @@ entry: ; CHECK: movw [[REG2:r[0-9]+]], #16716 ; CHECK: movt [[REG2:r[0-9]+]], #72 ; CHECK: str [[REG2]], [r0, #32] -; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] -; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] -; CHECK: adds r0, #16 -; CHECK: adds r1, #16 -; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] +; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]! +; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]! +; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false) ret void } define void @t3(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t3: -; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] -; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] -; CHECK: adds r0, #16 -; CHECK: adds r1, #16 -; CHECK: vld1.8 {d{{[0-9]+}}}, [r1] +; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]! +; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]! +; CHECK: vldr d{{[0-9]+}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}}, [r0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false) ret void } define void @t4(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t4: -; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1] -; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false) +; CHECK: vld1.64 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1] +; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]! +; CHECK: strh [[REG5:r[0-9]+]], [r0] + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false) ret void } @@ -93,25 +90,25 @@ entry: ; CHECK-T1: strb [[TREG3]], ; CHECK-T1: movs [[TREG4:r[0-9]]], ; CHECK-T1: strb [[TREG4]], - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false) ret void } define void @t6() nounwind { entry: ; CHECK-LABEL: t6: -; CHECK: vld1.8 {[[REG9:d[0-9]+]]}, [r0] +; CHECK: vldr [[REG9:d[0-9]+]], [r0] ; CHECK: vstr [[REG9]], [r1] ; CHECK: adds r1, #6 ; CHECK: adds r0, #6 -; CHECK: vld1.8 +; CHECK: vld1.16 ; CHECK: vst1.16 ; CHECK-T1-LABEL: t6: ; CHECK-T1: movs [[TREG5:r[0-9]]], ; CHECK-T1: strh [[TREG5]], ; CHECK-T1: ldr [[TREG6:r[0-9]]], ; CHECK-T1: str [[TREG6]] - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false) ret void } diff --git a/test/CodeGen/ARM/memfunc.ll b/test/CodeGen/ARM/memfunc.ll index 8d3800b43c14..5223983a7f30 100644 --- a/test/CodeGen/ARM/memfunc.ll +++ b/test/CodeGen/ARM/memfunc.ll @@ -1,33 +1,375 @@ -; RUN: llc < %s -mtriple=armv7-apple-ios -o - | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7m-none-macho -o - | FileCheck %s --check-prefix=DARWIN -; RUN: llc < %s -mtriple=arm-none-eabi -o - | FileCheck --check-prefix=EABI %s -; RUN: llc < %s -mtriple=arm-none-eabihf -o - | FileCheck --check-prefix=EABI %s +; RUN: llc < %s -mtriple=armv7-apple-ios -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-IOS --check-prefix=CHECK +; RUN: llc < %s -mtriple=thumbv7m-none-macho -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-DARWIN --check-prefix=CHECK +; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK +; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK -@from = common global [500 x i32] zeroinitializer, align 4 -@to = common global [500 x i32] zeroinitializer, align 4 +define void @f1(i8* %dest, i8* %src) { +entry: + ; CHECK-LABEL: f1 + + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false) + + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false) + + ; EABI memset swaps arguments + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 0, i1 false) + + ; EABI uses memclr if value set to 0 + ; CHECK-IOS: mov r1, #0 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #0 + ; CHECK-DARWIN: memset + ; CHECK-EABI: __aeabi_memclr + call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 0, i1 false) + + ; EABI uses aligned function variants if possible + + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove4 + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 4, i1 false) + + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy4 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 4, i1 false) + + ; CHECK-IOS: memset + ; CHECK-DARWIN: memset + ; CHECK-EABI: __aeabi_memset4 + call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 4, i1 false) + + ; CHECK-IOS: memset + ; CHECK-DARWIN: memset + ; CHECK-EABI: __aeabi_memclr4 + call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 4, i1 false) + + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove8 + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 8, i1 false) + + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy8 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 8, i1 false) + + ; CHECK-IOS: memset + ; CHECK-DARWIN: memset + ; CHECK-EABI: __aeabi_memset8 + call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 8, i1 false) + + ; CHECK-IOS: memset + ; CHECK-DARWIN: memset + ; CHECK-EABI: __aeabi_memclr8 + call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 8, i1 false) + + unreachable +} + +; Check that alloca arguments to memory intrinsics are automatically aligned if at least 8 bytes in size +define void @f2(i8* %dest, i32 %n) { +entry: + ; CHECK-LABEL: f2 + + ; IOS (ARMv7) should 8-byte align, others should 4-byte align + ; CHECK-IOS: add r1, sp, #32 + ; CHECK-IOS: memmove + ; CHECK-DARWIN: add r1, sp, #28 + ; CHECK-DARWIN: memmove + ; CHECK-EABI: add r1, sp, #28 + ; CHECK-EABI: __aeabi_memmove + %arr0 = alloca [9 x i8], align 1 + %0 = bitcast [9 x i8]* %arr0 to i8* + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) + + ; CHECK: add r1, sp, #16 + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + %arr1 = alloca [9 x i8], align 1 + %1 = bitcast [9 x i8]* %arr1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) + + ; CHECK-IOS: mov r0, sp + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: add r0, sp, #4 + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: add r0, sp, #4 + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + %arr2 = alloca [9 x i8], align 1 + %2 = bitcast [9 x i8]* %arr2 to i8* + call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) + + unreachable +} + +; Check that alloca arguments are not aligned if less than 8 bytes in size +define void @f3(i8* %dest, i32 %n) { +entry: + ; CHECK-LABEL: f3 -define void @f() { + ; CHECK: {{add(.w)? r1, sp, #17|sub(.w)? r1, r7, #15}} + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove + %arr0 = alloca [7 x i8], align 1 + %0 = bitcast [7 x i8]* %arr0 to i8* + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r1, sp, #10}} + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + %arr1 = alloca [7 x i8], align 1 + %1 = bitcast [7 x i8]* %arr1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r0, sp, #3}} + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + %arr2 = alloca [7 x i8], align 1 + %2 = bitcast [7 x i8]* %arr2 to i8* + call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) + + unreachable +} + +; Check that alloca arguments are not aligned if size+offset is less than 8 bytes +define void @f4(i8* %dest, i32 %n) { entry: + ; CHECK-LABEL: f4 + + ; CHECK: {{add(.w)? r., sp, #23|sub(.w)? r., r7, #17}} + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove + %arr0 = alloca [9 x i8], align 1 + %0 = getelementptr inbounds [9 x i8], [9 x i8]* %arr0, i32 0, i32 4 + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) - ; CHECK: memmove - ; EABI: __aeabi_memmove - call void @llvm.memmove.p0i8.p0i8.i32(i8* bitcast ([500 x i32]* @from to i8*), i8* bitcast ([500 x i32]* @to to i8*), i32 500, i32 0, i1 false) + ; CHECK: {{add(.w)? r., sp, #(10|14)}} + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + %arr1 = alloca [9 x i8], align 1 + %1 = getelementptr inbounds [9 x i8], [9 x i8]* %arr1, i32 0, i32 4 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) - ; CHECK: memcpy - ; EABI: __aeabi_memcpy - call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([500 x i32]* @from to i8*), i8* bitcast ([500 x i32]* @to to i8*), i32 500, i32 0, i1 false) + ; CHECK: {{add(.w)? r., sp, #(1|5)}} + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + %arr2 = alloca [9 x i8], align 1 + %2 = getelementptr inbounds [9 x i8], [9 x i8]* %arr2, i32 0, i32 4 + call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) - ; EABI memset swaps arguments - ; CHECK: mov r1, #0 - ; CHECK: memset - ; DARWIN: movs r1, #0 - ; DARWIN: memset - ; EABI: mov r2, #0 - ; EABI: __aeabi_memset - call void @llvm.memset.p0i8.i32(i8* bitcast ([500 x i32]* @from to i8*), i8 0, i32 500, i32 0, i1 false) - unreachable + unreachable } +; Check that alloca arguments are not aligned if the offset is not a multiple of 4 +define void @f5(i8* %dest, i32 %n) { +entry: + ; CHECK-LABEL: f5 + + ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}} + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove + %arr0 = alloca [13 x i8], align 1 + %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 1 + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(10|14)}} + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + %arr1 = alloca [13 x i8], align 1 + %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 1 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(1|5)}} + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + %arr2 = alloca [13 x i8], align 1 + %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 1 + call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) + + unreachable +} + +; Check that alloca arguments are not aligned if the offset is unknown +define void @f6(i8* %dest, i32 %n, i32 %i) { +entry: + ; CHECK-LABEL: f6 + + ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #25}} + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove + %arr0 = alloca [13 x i8], align 1 + %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 %i + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(10|14)}} + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + %arr1 = alloca [13 x i8], align 1 + %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 %i + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(1|5)}} + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + %arr2 = alloca [13 x i8], align 1 + %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 %i + call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) + + unreachable +} + +; Check that alloca arguments are not aligned if the GEP is not inbounds +define void @f7(i8* %dest, i32 %n) { +entry: + ; CHECK-LABEL: f7 + + ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}} + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove + %arr0 = alloca [13 x i8], align 1 + %0 = getelementptr [13 x i8], [13 x i8]* %arr0, i32 0, i32 4 + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(10|14)}} + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + %arr1 = alloca [13 x i8], align 1 + %1 = getelementptr [13 x i8], [13 x i8]* %arr1, i32 0, i32 4 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(1|5)}} + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + %arr2 = alloca [13 x i8], align 1 + %2 = getelementptr [13 x i8], [13 x i8]* %arr2, i32 0, i32 4 + call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) + + unreachable +} + +; Check that alloca arguments are not aligned when the offset is past the end of the allocation +define void @f8(i8* %dest, i32 %n) { +entry: + ; CHECK-LABEL: f8 + + ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}} + ; CHECK-IOS: memmove + ; CHECK-DARWIN: memmove + ; CHECK-EABI: __aeabi_memmove + %arr0 = alloca [13 x i8], align 1 + %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 16 + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(10|14)}} + ; CHECK-IOS: memcpy + ; CHECK-DARWIN: memcpy + ; CHECK-EABI: __aeabi_memcpy + %arr1 = alloca [13 x i8], align 1 + %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 16 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) + + ; CHECK: {{add(.w)? r., sp, #(1|5)}} + ; CHECK-IOS: mov r1, #1 + ; CHECK-IOS: memset + ; CHECK-DARWIN: movs r1, #1 + ; CHECK-DARWIN: memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: __aeabi_memset + %arr2 = alloca [13 x i8], align 1 + %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 16 + call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) + + unreachable +} + +; Check that global variables are aligned if they are large enough, but only if +; they are defined in this object and don't have an explicit section. +@arr1 = global [7 x i8] c"\01\02\03\04\05\06\07", align 1 +@arr2 = global [8 x i8] c"\01\02\03\04\05\06\07\08", align 1 +@arr3 = global [7 x i8] c"\01\02\03\04\05\06\07", section "foo,bar", align 1 +@arr4 = global [8 x i8] c"\01\02\03\04\05\06\07\08", section "foo,bar", align 1 +@arr5 = weak global [7 x i8] c"\01\02\03\04\05\06\07", align 1 +@arr6 = weak_odr global [7 x i8] c"\01\02\03\04\05\06\07", align 1 +@arr7 = external global [7 x i8], align 1 +define void @f9(i8* %dest, i32 %n) { +entry: + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr1, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr2, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr3, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @arr4, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr5, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr6, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr7, i32 0, i32 0), i32 %n, i32 1, i1 false) + + unreachable +} + +; CHECK: {{\.data|\.section.+data}} +; CHECK-NOT: .align +; CHECK: arr1: +; CHECK-IOS: .align 3 +; CHECK-DARWIN: .align 2 +; CHECK-EABI: .align 2 +; CHECK: arr2: +; CHECK: {{\.section.+foo,bar}} +; CHECK-NOT: .align +; CHECK: arr3: +; CHECK-NOT: .align +; CHECK: arr4: +; CHECK: {{\.data|\.section.+data}} +; CHECK-NOT: .align +; CHECK: arr5: +; CHECK-NOT: .align +; CHECK: arr6: +; CHECK-NOT: arr7: + declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind diff --git a/test/CodeGen/ARM/memset-inline.ll b/test/CodeGen/ARM/memset-inline.ll index 4e86d05b0a1c..191db1e20a25 100644 --- a/test/CodeGen/ARM/memset-inline.ll +++ b/test/CodeGen/ARM/memset-inline.ll @@ -17,9 +17,9 @@ entry: ; CHECK: add.w r1, r0, #10 ; CHECK: vmov.i32 {{q[0-9]+}}, #0x0 ; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] -; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] +; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] %buf = alloca [26 x i8], align 1 - %0 = getelementptr inbounds [26 x i8]* %buf, i32 0, i32 0 + %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false) call void @something(i8* %0) nounwind ret void diff --git a/test/CodeGen/ARM/minsize-litpools.ll b/test/CodeGen/ARM/minsize-litpools.ll index d5cd2a9b72e1..d5452ed0f909 100644 --- a/test/CodeGen/ARM/minsize-litpools.ll +++ b/test/CodeGen/ARM/minsize-litpools.ll @@ -12,7 +12,7 @@ define i32 @small_global() minsize { ; CHECK: ldr r[[GLOBDEST:[0-9]+]], {{.?LCPI0_0}} ; CHECK: ldr r0, [r[[GLOBDEST]]] - %val = load i32* @var + %val = load i32, i32* @var ret i32 %val } @@ -21,6 +21,6 @@ define i32 @big_global() { ; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var ; CHECK: movt [[GLOBDEST]], :upper16:var - %val = load i32* @var + %val = load i32, i32* @var ret i32 %val } diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll index bb2d42ca9ede..330252a90d7c 100644 --- a/test/CodeGen/ARM/misched-copy-arm.ll +++ b/test/CodeGen/ARM/misched-copy-arm.ll @@ -18,8 +18,8 @@ for.body: ; preds = %entry, %for.body %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ] %indvars.iv.next = add i32 %indvars.iv, %s - %arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv - %0 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, i32* %d, i32 %indvars.iv + %0 = load i32, i32* %arrayidx, align 4 %mul = mul nsw i32 %0, %s.05 %exitcond = icmp eq i32 %indvars.iv.next, %a br i1 %exitcond, label %for.end, label %for.body @@ -63,9 +63,9 @@ if.then24: ; preds = %while.cond if.end28: ; preds = %if.then24, %while.cond, %while.cond %dst.1 = phi %struct.rtx_def* [ undef, %if.then24 ], [ %dst.0, %while.cond ], [ %dst.0, %while.cond ] - %arrayidx30 = getelementptr inbounds %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0 + %arrayidx30 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0 %rtx31 = bitcast %union.rtunion_def* %arrayidx30 to %struct.rtx_def** - %0 = load %struct.rtx_def** %rtx31, align 4 + %0 = load %struct.rtx_def*, %struct.rtx_def** %rtx31, align 4 br label %while.cond if.then46: ; preds = %while.cond diff --git a/test/CodeGen/ARM/movcc-double.ll b/test/CodeGen/ARM/movcc-double.ll new file mode 100644 index 000000000000..9ce708d9bd36 --- /dev/null +++ b/test/CodeGen/ARM/movcc-double.ll @@ -0,0 +1,50 @@ +; RUN: llc -o - %s | FileCheck %s +target triple = "arm-unknown-unknown" + +; select with and i1/or i1 condition should be implemented as a series of 2 +; cmovs, not by producing two conditions and using and on them. + +define i32 @select_and(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) { +; CHECK-LABEL: select_and +; CHECK-NOT: tst +; CHECK-NOT: movne +; CHECK: mov{{lo|hs}} +; CHECK: mov{{lo|hs}} + %cmp0 = icmp ult i32 %a0, %a1 + %cmp1 = icmp ult i32 %a2, %a3 + %and = and i1 %cmp0, %cmp1 + %res = select i1 %and, i32 %a4, i32 %a5 + ret i32 %res +} + +define i32 @select_or(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) { +; select with and i1 condition should be implemented as a series of 2 cmovs, not +; by producing two conditions and using and on them. +; CHECK-LABEL: select_or +; CHECK-NOT: orss +; CHECK-NOT: tst +; CHECK: mov{{lo|hs}} +; CHECK: mov{{lo|hs}} + %cmp0 = icmp ult i32 %a0, %a1 + %cmp1 = icmp ult i32 %a2, %a3 + %and = or i1 %cmp0, %cmp1 + %res = select i1 %and, i32 %a4, i32 %a5 + ret i32 %res +} + +; If one of the conditions is materialized as a 0/1 value anyway, then the +; sequence of 2 cmovs should not be used. + +@var32 = global i32 0 +define i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) { +; CHECK-LABEL: select_noopt +; CHECK: orrs +; CHECK: movne + %cmp0 = icmp ult i32 %a0, %a1 + %cmp1 = icmp ult i32 %a1, %a2 + %or = or i1 %cmp0, %cmp1 + %zero_one = zext i1 %or to i32 + store volatile i32 %zero_one, i32* @var32 + %res = select i1 %or, i32 %a3, i32 %a4 + ret i32 %res +} diff --git a/test/CodeGen/ARM/mult-alt-generic-arm.ll b/test/CodeGen/ARM/mult-alt-generic-arm.ll index 05e9b0facd6c..208b05475870 100644 --- a/test/CodeGen/ARM/mult-alt-generic-arm.ll +++ b/test/CodeGen/ARM/mult-alt-generic-arm.ll @@ -33,10 +33,10 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r,<r"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* %in1, align 4 + %tmp1 = load i32, i32* %in1, align 4 %1 = call i32 asm "foo $1,$0", "=r,r<"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 ret void @@ -48,10 +48,10 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r,>r"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* %in1, align 4 + %tmp1 = load i32, i32* %in1, align 4 %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 ret void @@ -63,7 +63,7 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 ret void @@ -120,10 +120,10 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* @min1, align 4 + %tmp1 = load i32, i32* @min1, align 4 %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind @@ -137,15 +137,15 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* @min1, align 4 + %tmp1 = load i32, i32* @min1, align 4 %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind store i32 %2, i32* %out0, align 4 - %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind store i32 %3, i32* %out0, align 4 ; No lowering support. ; %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind @@ -159,14 +159,14 @@ define arm_aapcscc void @single_p() nounwind { entry: %out0 = alloca i32, align 4 store i32 0, i32* %out0, align 4 - %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind store i32 %0, i32* %out0, align 4 ret void } define arm_aapcscc void @multi_m() nounwind { entry: - %tmp = load i32* @min1, align 4 + %tmp = load i32, i32* @min1, align 4 call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind ret void } @@ -191,10 +191,10 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r|r,r|<r"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* %in1, align 4 + %tmp1 = load i32, i32* %in1, align 4 %1 = call i32 asm "foo $1,$0", "=r|r,r|r<"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 ret void @@ -206,10 +206,10 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r|r,r|>r"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* %in1, align 4 + %tmp1 = load i32, i32* %in1, align 4 %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 ret void @@ -221,7 +221,7 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 ret void @@ -278,10 +278,10 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* @min1, align 4 + %tmp1 = load i32, i32* @min1, align 4 %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind @@ -295,15 +295,15 @@ entry: %in1 = alloca i32, align 4 store i32 0, i32* %out0, align 4 store i32 1, i32* %in1, align 4 - %tmp = load i32* %in1, align 4 + %tmp = load i32, i32* %in1, align 4 %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind store i32 %0, i32* %out0, align 4 - %tmp1 = load i32* @min1, align 4 + %tmp1 = load i32, i32* @min1, align 4 %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind store i32 %1, i32* %out0, align 4 %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind store i32 %2, i32* %out0, align 4 - %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind store i32 %3, i32* %out0, align 4 ; No lowering support. ; %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind @@ -317,7 +317,7 @@ define arm_aapcscc void @multi_p() nounwind { entry: %out0 = alloca i32, align 4 store i32 0, i32* %out0, align 4 - %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32], [2 x i32]* @marray, i32 0, i32 0)) nounwind store i32 %0, i32* %out0, align 4 ret void } diff --git a/test/CodeGen/ARM/negative-offset.ll b/test/CodeGen/ARM/negative-offset.ll index 7b949fd71fe1..bafc9645471c 100644 --- a/test/CodeGen/ARM/negative-offset.ll +++ b/test/CodeGen/ARM/negative-offset.ll @@ -7,10 +7,10 @@ entry: ;CHECK-NOT: sub ;CHECK: ldr r{{.*}}, [r0, #-16] ;CHECK: ldr r{{.*}}, [r0, #-8] - %arrayidx = getelementptr inbounds i32* %p, i32 -4 - %0 = load i32* %arrayidx, align 4 - %arrayidx1 = getelementptr inbounds i32* %p, i32 -2 - %1 = load i32* %arrayidx1, align 4 + %arrayidx = getelementptr inbounds i32, i32* %p, i32 -4 + %0 = load i32, i32* %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %p, i32 -2 + %1 = load i32, i32* %arrayidx1, align 4 %add = add nsw i32 %1, %0 ret i32 %add } diff --git a/test/CodeGen/ARM/neon-spfp.ll b/test/CodeGen/ARM/neon-spfp.ll index dd2e67fe7753..4eeaa8abfab2 100644 --- a/test/CodeGen/ARM/neon-spfp.ll +++ b/test/CodeGen/ARM/neon-spfp.ll @@ -64,7 +64,7 @@ for.body: ; preds = %for.body, %entry ; CHECK-DARWINA15: vmul.f32 s{{[0-9]*}} ; CHECK-DARWINSWIFT: vmul.f32 d{{[0-9]*}} %conv = fpext float %mul to double - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %conv) #1 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %conv) #1 %inc = add nsw i32 %i.04, 1 %exitcond = icmp eq i32 %inc, 16000 br i1 %exitcond, label %for.end, label %for.body diff --git a/test/CodeGen/ARM/neon-v8.1a.ll b/test/CodeGen/ARM/neon-v8.1a.ll new file mode 100644 index 000000000000..91259139d446 --- /dev/null +++ b/test/CodeGen/ARM/neon-v8.1a.ll @@ -0,0 +1,166 @@ +; RUN: llc < %s -mtriple=armv8 -mattr=+v8.1a | FileCheck %s + +;----------------------------------------------------------------------------- +; RDMA Vector + +declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>) +declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) +declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) +declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) + +declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>) +declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>) +declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>) +declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>) + +declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) +declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) +declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) +declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) + +define <4 x i16> @test_vqrdmlah_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) { +; CHECK-LABEL: test_vqrdmlah_v4i16: + %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs) + %retval = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK: vqrdmlah.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret <4 x i16> %retval +} + +define <8 x i16> @test_vqrdmlah_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) { +; CHECK-LABEL: test_vqrdmlah_v8i16: + %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs) + %retval = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK: vqrdmlah.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} + ret <8 x i16> %retval +} + +define <2 x i32> @test_vqrdmlah_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) { +; CHECK-LABEL: test_vqrdmlah_v2i32: + %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs) + %retval = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK: vqrdmlah.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret <2 x i32> %retval +} + +define <4 x i32> @test_vqrdmlah_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) { +; CHECK-LABEL: test_vqrdmlah_v4i32: + %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs) + %retval = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK: vqrdmlah.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} + ret <4 x i32> %retval +} + +define <4 x i16> @test_vqrdmlsh_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) { +; CHECK-LABEL: test_vqrdmlsh_v4i16: + %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs) + %retval = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK: vqrdmlsh.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret <4 x i16> %retval +} + +define <8 x i16> @test_vqrdmlsh_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) { +; CHECK-LABEL: test_vqrdmlsh_v8i16: + %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs) + %retval = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK: vqrdmlsh.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} + ret <8 x i16> %retval +} + +define <2 x i32> @test_vqrdmlsh_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) { +; CHECK-LABEL: test_vqrdmlsh_v2i32: + %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs) + %retval = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK: vqrdmlsh.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + ret <2 x i32> %retval +} + +define <4 x i32> @test_vqrdmlsh_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) { +; CHECK-LABEL: test_vqrdmlsh_v4i32: + %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs) + %retval = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK: vqrdmlsh.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} + ret <4 x i32> %retval +} + +;----------------------------------------------------------------------------- +; RDMA Scalar + +define <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_vqrdmlah_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> + %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle) + %retval = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK: vqrdmlah.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[3] + ret <4 x i16> %retval +} + +define <8 x i16> @test_vqrdmlahq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_vqrdmlahq_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2> + %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle) + %retval = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK: vqrdmlah.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[2] + ret <8 x i16> %retval +} + +define <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_vqrdmlah_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1> + %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle) + %retval = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK: vqrdmlah.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[1] + ret <2 x i32> %retval +} + +define <4 x i32> @test_vqrdmlahq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_vqrdmlahq_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer + %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle) + %retval = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK: vqrdmlah.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[0] + ret <4 x i32> %retval +} + +define <4 x i16> @test_vqrdmlsh_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_vqrdmlsh_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> + %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle) + %retval = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK: vqrdmlsh.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[3] + ret <4 x i16> %retval +} + +define <8 x i16> @test_vqrdmlshq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_vqrdmlshq_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2> + %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle) + %retval = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK: vqrdmlsh.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[2] + ret <8 x i16> %retval +} + +define <2 x i32> @test_vqrdmlsh_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_vqrdmlsh_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1> + %prod = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle) + %retval = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK: vqrdmlsh.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}[1] + ret <2 x i32> %retval +} + +define <4 x i32> @test_vqrdmlshq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_vqrdmlshq_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <4 x i32> zeroinitializer + %prod = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle) + %retval = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK: vqrdmlsh.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{d[0-9]+}}[0] + ret <4 x i32> %retval +} diff --git a/test/CodeGen/ARM/neon_cmp.ll b/test/CodeGen/ARM/neon_cmp.ll index e1662c43c647..fcf4486fa46d 100644 --- a/test/CodeGen/ARM/neon_cmp.ll +++ b/test/CodeGen/ARM/neon_cmp.ll @@ -4,8 +4,8 @@ ; radar://13191881 ; CHECK: vfcmp define void @vfcmp(<2 x double>* %a, <2 x double>* %b) { - %wide.load = load <2 x double>* %a, align 4 - %wide.load2 = load <2 x double>* %b, align 4 + %wide.load = load <2 x double>, <2 x double>* %a, align 4 + %wide.load2 = load <2 x double>, <2 x double>* %b, align 4 ; CHECK-NOT: vdup.32 ; CHECK-NOT: vmovn.i64 %v1 = fcmp olt <2 x double> %wide.load, %wide.load2 diff --git a/test/CodeGen/ARM/neon_div.ll b/test/CodeGen/ARM/neon_div.ll index 4f1607ed5baf..e185c2a8afbc 100644 --- a/test/CodeGen/ARM/neon_div.ll +++ b/test/CodeGen/ARM/neon_div.ll @@ -7,8 +7,8 @@ define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vrecpe.f32 ;CHECK: vmovn.i32 ;CHECK: vmovn.i16 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sdiv <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -21,8 +21,8 @@ define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vrecps.f32 ;CHECK: vmovn.i32 ;CHECK: vqmovun.s16 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = udiv <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -31,8 +31,8 @@ define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: vrecpe.f32 ;CHECK: vrecps.f32 ;CHECK: vmovn.i32 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sdiv <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -42,8 +42,8 @@ define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: vrecps.f32 ;CHECK: vrecps.f32 ;CHECK: vmovn.i32 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = udiv <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } diff --git a/test/CodeGen/ARM/neon_fpconv.ll b/test/CodeGen/ARM/neon_fpconv.ll index 8e37ce778182..61ac4098a6dd 100644 --- a/test/CodeGen/ARM/neon_fpconv.ll +++ b/test/CodeGen/ARM/neon_fpconv.ll @@ -19,7 +19,7 @@ define <2 x double> @vextend(<2 x float> %a) { ; CHECK: vsitofp_double define void @vsitofp_double(<2 x i32>* %loadaddr, <2 x double>* %storeaddr) { - %v0 = load <2 x i32>* %loadaddr + %v0 = load <2 x i32>, <2 x i32>* %loadaddr ; CHECK: vldr ; CHECK-NEXT: vcvt.f64.s32 ; CHECK-NEXT: vcvt.f64.s32 @@ -31,7 +31,7 @@ define void @vsitofp_double(<2 x i32>* %loadaddr, ; CHECK: vuitofp_double define void @vuitofp_double(<2 x i32>* %loadaddr, <2 x double>* %storeaddr) { - %v0 = load <2 x i32>* %loadaddr + %v0 = load <2 x i32>, <2 x i32>* %loadaddr ; CHECK: vldr ; CHECK-NEXT: vcvt.f64.u32 ; CHECK-NEXT: vcvt.f64.u32 diff --git a/test/CodeGen/ARM/neon_ld1.ll b/test/CodeGen/ARM/neon_ld1.ll index 9fd3fc5f341a..f4d601905537 100644 --- a/test/CodeGen/ARM/neon_ld1.ll +++ b/test/CodeGen/ARM/neon_ld1.ll @@ -7,8 +7,8 @@ ; CHECK: vstr d define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind { entry: - %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] - %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] + %0 = load <4 x i16>, <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] + %1 = load <4 x i16>, <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] %2 = add <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1] %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1] store <2 x i32> %3, <2 x i32>* %r, align 8 @@ -22,8 +22,8 @@ entry: ; CHECK: vmov r0, r1, d define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly { entry: - %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] - %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] + %0 = load <4 x i16>, <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1] + %1 = load <4 x i16>, <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1] %2 = sub <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1] %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1] ret <2 x i32> %3 diff --git a/test/CodeGen/ARM/neon_ld2.ll b/test/CodeGen/ARM/neon_ld2.ll index 571a16a061df..5bd6ae6d2a98 100644 --- a/test/CodeGen/ARM/neon_ld2.ll +++ b/test/CodeGen/ARM/neon_ld2.ll @@ -13,8 +13,8 @@ ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}} define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind { entry: - %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] - %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] + %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] + %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] %2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] store <4 x i32> %3, <4 x i32>* %r, align 16 @@ -35,8 +35,8 @@ entry: ; SWIFT: vmov r2, r3, d define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly { entry: - %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] - %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] + %0 = load <2 x i64>, <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1] + %1 = load <2 x i64>, <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1] %2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1] %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1] ret <4 x i32> %3 @@ -50,8 +50,8 @@ entry: ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+}} define void @t3(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind { entry: - %0 = load <2 x i64>* %a, align 8 - %1 = load <2 x i64>* %b, align 8 + %0 = load <2 x i64>, <2 x i64>* %a, align 8 + %1 = load <2 x i64>, <2 x i64>* %b, align 8 %2 = add <2 x i64> %0, %1 %3 = bitcast <2 x i64> %2 to <4 x i32> store <4 x i32> %3, <4 x i32>* %r, align 8 diff --git a/test/CodeGen/ARM/neon_spill.ll b/test/CodeGen/ARM/neon_spill.ll index d286d16486c1..04f08f43840f 100644 --- a/test/CodeGen/ARM/neon_spill.ll +++ b/test/CodeGen/ARM/neon_spill.ll @@ -24,7 +24,7 @@ declare arm_aapcs_vfpcc %2** @func4() define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 { call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind %2 = call arm_aapcs_vfpcc %0** @func2() nounwind - %3 = load %0** %2, align 4 + %3 = load %0*, %0** %2, align 4 store float 0.000000e+00, float* undef, align 4 %4 = call arm_aapcs_vfpcc %2* @func3(%2* undef, %2* undef, i32 2956) nounwind call arm_aapcs_vfpcc void @func1(%0* %3, float* undef, float* undef, %2* undef) diff --git a/test/CodeGen/ARM/no-fpu.ll b/test/CodeGen/ARM/no-fpu.ll index fff4bccb80e9..c5d1f1951d7c 100644 --- a/test/CodeGen/ARM/no-fpu.ll +++ b/test/CodeGen/ARM/no-fpu.ll @@ -6,7 +6,7 @@ ; Check no NEON instructions are selected when feature is disabled. define void @neonop(i64* nocapture readonly %a, i64* nocapture %b) #0 { %1 = bitcast i64* %a to <2 x i64>* - %wide.load = load <2 x i64>* %1, align 8 + %wide.load = load <2 x i64>, <2 x i64>* %1, align 8 ; NONEON-NOVFP-NOT: vld1.64 ; NONEON-NOT: vld1.64 %add = add <2 x i64> %wide.load, %wide.load diff --git a/test/CodeGen/ARM/no-tail-call.ll b/test/CodeGen/ARM/no-tail-call.ll index 3a8cb21bee92..5a5d43c28714 100644 --- a/test/CodeGen/ARM/no-tail-call.ll +++ b/test/CodeGen/ARM/no-tail-call.ll @@ -17,28 +17,28 @@ entry: %0 = alloca %foo, align 4 %1 = alloca %foo, align 4 %2 = alloca %foo, align 4 - %.native = getelementptr inbounds %foo* %0, i32 0, i32 0 - %.native.value = getelementptr inbounds %Sf* %.native, i32 0, i32 0 + %.native = getelementptr inbounds %foo, %foo* %0, i32 0, i32 0 + %.native.value = getelementptr inbounds %Sf, %Sf* %.native, i32 0, i32 0 store float 0.000000e+00, float* %.native.value, align 4 - %.native1 = getelementptr inbounds %foo* %1, i32 0, i32 0 - %.native1.value = getelementptr inbounds %Sf* %.native1, i32 0, i32 0 + %.native1 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0 + %.native1.value = getelementptr inbounds %Sf, %Sf* %.native1, i32 0, i32 0 store float 1.000000e+00, float* %.native1.value, align 4 - %.native2 = getelementptr inbounds %foo* %2, i32 0, i32 0 - %.native2.value = getelementptr inbounds %Sf* %.native2, i32 0, i32 0 + %.native2 = getelementptr inbounds %foo, %foo* %2, i32 0, i32 0 + %.native2.value = getelementptr inbounds %Sf, %Sf* %.native2, i32 0, i32 0 store float 5.000000e+00, float* %.native2.value, align 4 br i1 true, label %3, label %4 ; <label>:3 ; preds = %entry - %.native4 = getelementptr inbounds %foo* %1, i32 0, i32 0 - %.native4.value = getelementptr inbounds %Sf* %.native4, i32 0, i32 0 + %.native4 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0 + %.native4.value = getelementptr inbounds %Sf, %Sf* %.native4, i32 0, i32 0 store float 2.000000e+00, float* %.native4.value, align 4 br label %4 ; <label>:4 ; preds = %3, %entry %5 = call float @llvm.ceil.f32(float 5.000000e+00) - %.native3 = getelementptr inbounds %foo* %1, i32 0, i32 0 - %.native3.value = getelementptr inbounds %Sf* %.native3, i32 0, i32 0 - %6 = load float* %.native3.value, align 4 + %.native3 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0 + %.native3.value = getelementptr inbounds %Sf, %Sf* %.native3, i32 0, i32 0 + %6 = load float, float* %.native3.value, align 4 %7 = call float @llvm.ceil.f32(float %6) %8 = insertvalue { float, float, float } { float 0.000000e+00, float undef, float undef }, float %5, 1 %9 = insertvalue { float, float, float } %8, float %7, 2 @@ -55,28 +55,28 @@ entry: %0 = alloca %foo, align 4 %1 = alloca %foo, align 4 %2 = alloca %foo, align 4 - %.native = getelementptr inbounds %foo* %0, i32 0, i32 0 - %.native.value = getelementptr inbounds %Sf* %.native, i32 0, i32 0 + %.native = getelementptr inbounds %foo, %foo* %0, i32 0, i32 0 + %.native.value = getelementptr inbounds %Sf, %Sf* %.native, i32 0, i32 0 store float 0.000000e+00, float* %.native.value, align 4 - %.native1 = getelementptr inbounds %foo* %1, i32 0, i32 0 - %.native1.value = getelementptr inbounds %Sf* %.native1, i32 0, i32 0 + %.native1 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0 + %.native1.value = getelementptr inbounds %Sf, %Sf* %.native1, i32 0, i32 0 store float 1.000000e+00, float* %.native1.value, align 4 - %.native2 = getelementptr inbounds %foo* %2, i32 0, i32 0 - %.native2.value = getelementptr inbounds %Sf* %.native2, i32 0, i32 0 + %.native2 = getelementptr inbounds %foo, %foo* %2, i32 0, i32 0 + %.native2.value = getelementptr inbounds %Sf, %Sf* %.native2, i32 0, i32 0 store float 5.000000e+00, float* %.native2.value, align 4 br i1 true, label %3, label %4 ; <label>:3 ; preds = %entry - %.native4 = getelementptr inbounds %foo* %1, i32 0, i32 0 - %.native4.value = getelementptr inbounds %Sf* %.native4, i32 0, i32 0 + %.native4 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0 + %.native4.value = getelementptr inbounds %Sf, %Sf* %.native4, i32 0, i32 0 store float 2.000000e+00, float* %.native4.value, align 4 br label %4 ; <label>:4 ; preds = %3, %entry %5 = call float @llvm.ceil.f32(float 5.000000e+00) - %.native3 = getelementptr inbounds %foo* %1, i32 0, i32 0 - %.native3.value = getelementptr inbounds %Sf* %.native3, i32 0, i32 0 - %6 = load float* %.native3.value, align 4 + %.native3 = getelementptr inbounds %foo, %foo* %1, i32 0, i32 0 + %.native3.value = getelementptr inbounds %Sf, %Sf* %.native3, i32 0, i32 0 + %6 = load float, float* %.native3.value, align 4 %7 = call float @llvm.ceil.f32(float %6) %8 = insertvalue { float, float } { float 0.000000e+00, float undef }, float %7, 1 ret { float, float } %8 diff --git a/test/CodeGen/ARM/none-macho.ll b/test/CodeGen/ARM/none-macho.ll index 2a7878fee300..733ba4ba2d2c 100644 --- a/test/CodeGen/ARM/none-macho.ll +++ b/test/CodeGen/ARM/none-macho.ll @@ -2,16 +2,11 @@ ; RUN: llc -mtriple=thumbv7m-none-macho -O0 %s -o - -relocation-model=pic -disable-fp-elim | FileCheck %s ; RUN: llc -mtriple=thumbv7m-none-macho -filetype=obj %s -o /dev/null - ; Bare-metal should probably "declare" segments just like normal MachO -; CHECK: __picsymbolstub4 -; CHECK: __StaticInit -; CHECK: __text - @var = external global i32 define i32 @test_litpool() minsize { ; CHECK-LABEL: test_litpool: - %val = load i32* @var + %val = load i32, i32* @var ret i32 %val ; Lit-pool entries need to produce a "$non_lazy_ptr" version of the symbol. @@ -21,7 +16,7 @@ define i32 @test_litpool() minsize { define i32 @test_movw_movt() { ; CHECK-LABEL: test_movw_movt: - %val = load i32* @var + %val = load i32, i32* @var ret i32 %val ; movw/movt should also address their symbols MachO-style @@ -56,7 +51,7 @@ define i32 @test_frame_ptr() { %big_arr = type [8 x i32] define void @test_two_areas(%big_arr* %addr) { ; CHECK-LABEL: test_two_areas: - %val = load %big_arr* %addr + %val = load %big_arr, %big_arr* %addr call void @test_trap() store %big_arr %val, %big_arr* %addr diff --git a/test/CodeGen/ARM/noopt-dmb-v7.ll b/test/CodeGen/ARM/noopt-dmb-v7.ll new file mode 100644 index 000000000000..56a29c8a17e8 --- /dev/null +++ b/test/CodeGen/ARM/noopt-dmb-v7.ll @@ -0,0 +1,15 @@ +; Ensure that adjacent duplicated barriers are not removed at -O0. +; RUN: llc -O0 < %s -mtriple=armv7 -mattr=+db | FileCheck %s + +define i32 @t1() { +entry: + fence seq_cst + fence seq_cst + fence seq_cst + ret i32 0 +} + +; CHECK: @ BB#0: @ %entry +; CHECK-NEXT: dmb ish +; CHECK-NEXT: dmb ish +; CHECK-NEXT: dmb ish diff --git a/test/CodeGen/ARM/nop_concat_vectors.ll b/test/CodeGen/ARM/nop_concat_vectors.ll index c81090095a99..fa0e892f9e24 100644 --- a/test/CodeGen/ARM/nop_concat_vectors.ll +++ b/test/CodeGen/ARM/nop_concat_vectors.ll @@ -5,7 +5,7 @@ ;CHECK-NOT: vst1.32 ;CHECK: bx define void @foo(<16 x i8>* %J) { - %A = load <16 x i8>* %J + %A = load <16 x i8>, <16 x i8>* %J %T1 = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %T2 = shufflevector <8 x i8> %T1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> store <16 x i8> %T2, <16 x i8>* %J diff --git a/test/CodeGen/ARM/null-streamer.ll b/test/CodeGen/ARM/null-streamer.ll index 350c45e5bebe..19ad22a4bdb8 100644 --- a/test/CodeGen/ARM/null-streamer.ll +++ b/test/CodeGen/ARM/null-streamer.ll @@ -5,3 +5,5 @@ define i32 @main() { entry: ret i32 0 } + +module asm ".fnstart" diff --git a/test/CodeGen/ARM/odr_comdat.ll b/test/CodeGen/ARM/odr_comdat.ll deleted file mode 100644 index e28b5788ef6d..000000000000 --- a/test/CodeGen/ARM/odr_comdat.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ARMGNUEABI - -; Checking that a comdat group gets generated correctly for a static member -; of instantiated C++ templates. -; see http://sourcery.mentor.com/public/cxx-abi/abi.html#vague-itemplate -; section 5.2.6 Instantiated templates -; "Any static member data object is emitted in a COMDAT identified by its mangled -; name, in any object file with a reference to its name symbol." - -; Case 1: variable is not explicitly initialized, and ends up in a .bss section -; ARMGNUEABI: .section .bss._ZN1CIiE1iE,"aGw",%nobits,_ZN1CIiE1iE,comdat -@_ZN1CIiE1iE = weak_odr global i32 0, align 4 - -; Case 2: variable is explicitly initialized, and ends up in a .data section -; ARMGNUEABI: .section .data._ZN1CIiE1jE,"aGw",%progbits,_ZN1CIiE1jE,comdat -@_ZN1CIiE1jE = weak_odr global i32 12, align 4 diff --git a/test/CodeGen/ARM/optimize-dmbs-v7.ll b/test/CodeGen/ARM/optimize-dmbs-v7.ll index 64f5e202d36a..34a55aa718a3 100644 --- a/test/CodeGen/ARM/optimize-dmbs-v7.ll +++ b/test/CodeGen/ARM/optimize-dmbs-v7.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv7 -mattr=+db | FileCheck %s +; RUN: llc -O1 < %s -mtriple=armv7 -mattr=+db | FileCheck %s @x1 = global i32 0, align 4 @x2 = global i32 0, align 4 diff --git a/test/CodeGen/ARM/optselect-regclass.ll b/test/CodeGen/ARM/optselect-regclass.ll index 0acb2f2f0ecc..4c5d44c352b2 100644 --- a/test/CodeGen/ARM/optselect-regclass.ll +++ b/test/CodeGen/ARM/optselect-regclass.ll @@ -9,7 +9,7 @@ ; Function Attrs: nounwind ssp define void @xfr() { entry: - %bf.load4 = load i32* getelementptr inbounds (%union.opcode.0.2.5.8.15.28* @opcode, i32 0, i32 0), align 4 + %bf.load4 = load i32, i32* getelementptr inbounds (%union.opcode.0.2.5.8.15.28, %union.opcode.0.2.5.8.15.28* @opcode, i32 0, i32 0), align 4 %bf.clear10 = and i32 %bf.load4, 65535 %and11 = and i32 %bf.load4, 32768 %tobool12 = icmp ne i32 %and11, 0 @@ -17,7 +17,7 @@ entry: %or = or i32 %cond13, %bf.clear10 %shl = shl nuw i32 %or, 2 %add = add i32 0, %shl - tail call void (i8*, i32, i32, i8*, ...)* @__sprintf_chk(i8* getelementptr inbounds ([50 x i8]* @operands, i32 0, i32 0), i32 0, i32 50, i8* getelementptr inbounds ([13 x i8]* @.str86, i32 0, i32 0), i32 undef, i32 undef, i32 %add) + tail call void (i8*, i32, i32, i8*, ...) @__sprintf_chk(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @operands, i32 0, i32 0), i32 0, i32 50, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str86, i32 0, i32 0), i32 undef, i32 undef, i32 %add) ret void } diff --git a/test/CodeGen/ARM/phi.ll b/test/CodeGen/ARM/phi.ll index 5a8f623e6f50..ff85052175c8 100644 --- a/test/CodeGen/ARM/phi.ll +++ b/test/CodeGen/ARM/phi.ll @@ -9,17 +9,17 @@ entry: br i1 %a, label %lblock, label %rblock lblock: - %lbranch = getelementptr i32* %b, i32 1 + %lbranch = getelementptr i32, i32* %b, i32 1 br label %end rblock: - %rbranch = getelementptr i32* %b, i32 1 + %rbranch = getelementptr i32, i32* %b, i32 1 br label %end end: ; CHECK: ldr r0, [r1, #4] %gep = phi i32* [%lbranch, %lblock], [%rbranch, %rblock] - %r = load i32* %gep + %r = load i32, i32* %gep ; CHECK-NEXT: bx lr ret i32 %r } diff --git a/test/CodeGen/ARM/popcnt.ll b/test/CodeGen/ARM/popcnt.ll index 7ace640c6b61..74f90640ca6e 100644 --- a/test/CodeGen/ARM/popcnt.ll +++ b/test/CodeGen/ARM/popcnt.ll @@ -4,7 +4,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vcnt8: ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -12,7 +12,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vcntQ8: ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -24,7 +24,7 @@ define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind { ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vuzp.8 {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp2 } @@ -36,7 +36,7 @@ define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind { ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vuzp.8 {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp2 } @@ -51,7 +51,7 @@ define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind { ; CHECK: vrev32.16 {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vuzp.16 {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -66,7 +66,7 @@ define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind { ; CHECK: vrev32.16 {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vuzp.16 {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } @@ -81,7 +81,7 @@ declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclz8: ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0) ret <8 x i8> %tmp2 } @@ -89,7 +89,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vclz16: ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0) ret <4 x i16> %tmp2 } @@ -97,7 +97,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vclz32: ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0) ret <2 x i32> %tmp2 } @@ -105,7 +105,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vclzQ8: ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0) ret <16 x i8> %tmp2 } @@ -113,7 +113,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vclzQ16: ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0) ret <8 x i16> %tmp2 } @@ -121,7 +121,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vclzQ32: ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0) ret <4 x i32> %tmp2 } @@ -137,7 +137,7 @@ declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclss8: ;CHECK: vcls.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -145,7 +145,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vclss16: ;CHECK: vcls.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp2 } @@ -153,7 +153,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vclss32: ;CHECK: vcls.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -161,7 +161,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vclsQs8: ;CHECK: vcls.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -169,7 +169,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vclsQs16: ;CHECK: vcls.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp2 } @@ -177,7 +177,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vclsQs32: ;CHECK: vcls.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } diff --git a/test/CodeGen/ARM/pr13249.ll b/test/CodeGen/ARM/pr13249.ll index 4bc881035497..cede6007ba16 100644 --- a/test/CodeGen/ARM/pr13249.ll +++ b/test/CodeGen/ARM/pr13249.ll @@ -6,19 +6,19 @@ bb: bb3: ; preds = %bb3, %bb %tmp = phi i8* [ %tmp5, %bb3 ], [ %arg, %bb ] - %tmp4 = load i8* %tmp, align 1 - %tmp5 = getelementptr inbounds i8* %tmp, i32 1 + %tmp4 = load i8, i8* %tmp, align 1 + %tmp5 = getelementptr inbounds i8, i8* %tmp, i32 1 br i1 undef, label %bb3, label %bb7 bb7: ; preds = %bb13, %bb3 %tmp8 = phi i8 [ %tmp14, %bb13 ], [ %tmp4, %bb3 ] %tmp9 = phi i8* [ %tmp12, %bb13 ], [ %tmp, %bb3 ] %tmp10 = icmp ne i8 %tmp8, %arg1 - %tmp12 = getelementptr inbounds i8* %tmp9, i32 1 + %tmp12 = getelementptr inbounds i8, i8* %tmp9, i32 1 br i1 %tmp10, label %bb13, label %bb15 bb13: ; preds = %bb7 - %tmp14 = load i8* %tmp12, align 1 + %tmp14 = load i8, i8* %tmp12, align 1 br label %bb7 bb15: ; preds = %bb7 diff --git a/test/CodeGen/ARM/pr18364-movw.ll b/test/CodeGen/ARM/pr18364-movw.ll index fdcf15485f1c..b783522c42b8 100644 --- a/test/CodeGen/ARM/pr18364-movw.ll +++ b/test/CodeGen/ARM/pr18364-movw.ll @@ -14,8 +14,8 @@ entry: %z = alloca i64, align 8 store i64 1, i64* %y, align 8 store i64 11579764786944, i64* %z, align 8 - %0 = load i64* %y, align 8 - %1 = load i64* %z, align 8 + %0 = load i64, i64* %y, align 8 + %1 = load i64, i64* %z, align 8 %sub = sub i64 %0, %1 ret i64 %sub } diff --git a/test/CodeGen/ARM/pr3502.ll b/test/CodeGen/ARM/pr3502.ll index 606d9698b977..4ec982ebea2b 100644 --- a/test/CodeGen/ARM/pr3502.ll +++ b/test/CodeGen/ARM/pr3502.ll @@ -11,7 +11,7 @@ define void @SomeCall(i32 %num) nounwind { entry: tail call void asm sideeffect "mcr p15, 0, $0, c7, c10, 4 \0A\09", "r,~{memory}"(i32 0) nounwind tail call void asm sideeffect "mcr p15,0,$0,c7,c14,0", "r,~{memory}"(i32 0) nounwind - %0 = load %struct.SHARED_AREA** null, align 4 ; <%struct.SHARED_AREA*> [#uses=1] + %0 = load %struct.SHARED_AREA*, %struct.SHARED_AREA** null, align 4 ; <%struct.SHARED_AREA*> [#uses=1] %1 = ptrtoint %struct.SHARED_AREA* %0 to i32 ; <i32> [#uses=1] %2 = lshr i32 %1, 20 ; <i32> [#uses=1] %3 = tail call i32 @SetCurrEntry(i32 %2, i32 0) nounwind ; <i32> [#uses=0] diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 7fdc5b65c70e..447411d510e9 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -31,7 +31,7 @@ entry: ; THUMB2-LABEL: t2: ; THUMB2: pld [r0, #1023] - %tmp = getelementptr i8* %ptr, i32 1023 + %tmp = getelementptr i8, i8* %ptr, i32 1023 tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 ) ret void } @@ -89,8 +89,8 @@ entry: ;THUMB2: pld [sp, #50] %red = alloca [100 x i8], align 1 -%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0 -%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50 +%0 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 0 +%1 = getelementptr inbounds [100 x i8], [100 x i8]* %red, i32 0, i32 50 call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1) call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) ret void diff --git a/test/CodeGen/ARM/print-memb-operand.ll b/test/CodeGen/ARM/print-memb-operand.ll new file mode 100644 index 000000000000..7748efb3a08a --- /dev/null +++ b/test/CodeGen/ARM/print-memb-operand.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s + +; CHECK: dmb ld + +define void @test2() #0 { + call void @llvm.arm.dmb(i32 13) + ret void +} + +declare void @llvm.arm.dmb(i32) + +attributes #0 = { "target-cpu"="cyclone" } diff --git a/test/CodeGen/ARM/private.ll b/test/CodeGen/ARM/private.ll index e48c292db466..fab8f37f989a 100644 --- a/test/CodeGen/ARM/private.ll +++ b/test/CodeGen/ARM/private.ll @@ -15,7 +15,7 @@ define private void @foo() { define i32 @bar() { call void @foo() - %1 = load i32* @baz, align 4 + %1 = load i32, i32* @baz, align 4 ret i32 %1 } diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index feed5ad2830a..507ee48cafc2 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -19,10 +19,10 @@ entry: ; CHECK: vshrn.i32 ; CHECK-NOT: vmov d ; CHECK-NEXT: vst1.16 - %0 = getelementptr inbounds %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] - %1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] - %2 = getelementptr inbounds %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] - %3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] + %0 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %1 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %2 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %3 = load <4 x i32>, <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] %6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2] @@ -55,20 +55,20 @@ entry: ; CHECK-NOT: vmov ; CHECK: vst1.16 ; CHECK: vst1.16 - %0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] - %1 = load <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] - %2 = getelementptr inbounds %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] - %3 = load <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] + %0 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %1 = load <8 x i16>, <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] + %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %3 = load <8 x i16>, <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] - %6 = getelementptr inbounds i16* %i_ptr, i32 8 ; <i16*> [#uses=1] + %6 = getelementptr inbounds i16, i16* %i_ptr, i32 8 ; <i16*> [#uses=1] %7 = bitcast i16* %6 to i8* ; <i8*> [#uses=1] %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7, i32 1) ; <<8 x i16>> [#uses=1] %9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1] %10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1] %11 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1] tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9, i32 1) - %12 = getelementptr inbounds i16* %o_ptr, i32 8 ; <i16*> [#uses=1] + %12 = getelementptr inbounds i16, i16* %o_ptr, i32 8 ; <i16*> [#uses=1] %13 = bitcast i16* %12 to i8* ; <i8*> [#uses=1] tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10, i32 1) ret void @@ -102,7 +102,7 @@ entry: ; CHECK: bne %tmp1 = bitcast i32* %in to i8* ; <i8*> [#uses=1] %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] - %tmp3 = getelementptr inbounds i32* %in, i32 8 ; <i32*> [#uses=1] + %tmp3 = getelementptr inbounds i32, i32* %in, i32 8 ; <i32*> [#uses=1] %tmp4 = bitcast i32* %tmp3 to i8* ; <i8*> [#uses=1] %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] %tmp8 = bitcast i32* %out to i8* ; <i8*> [#uses=1] @@ -146,7 +146,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK-NOT: vmov ; CHECK: vadd.i16 %tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1] - %tmp1 = load <8 x i16>* %B ; <<8 x i16>> [#uses=2] + %tmp1 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=2] %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1] @@ -159,7 +159,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ; CHECK: vldr ; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} - %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] + %tmp1 = load <8 x i8>, <8 x i8>* %B ; <<8 x i8>> [#uses=2] %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1] diff --git a/test/CodeGen/ARM/regpair_hint_phys.ll b/test/CodeGen/ARM/regpair_hint_phys.ll new file mode 100644 index 000000000000..8585a4c207c1 --- /dev/null +++ b/test/CodeGen/ARM/regpair_hint_phys.ll @@ -0,0 +1,22 @@ +; RUN: llc -o - %s +; ARM target used to fail an assertion if RegPair{Odd|Even} hint pointed to a +; physreg. +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-apple-tvos8.3.0" + +declare i8* @llvm.frameaddress(i32) #1 +declare i8* @llvm.returnaddress(i32) #1 + +@somevar = global [2 x i32] [i32 0, i32 0] + +define void @__ubsan_handle_shift_out_of_bounds() #0 { +entry: + %0 = tail call i8* @llvm.frameaddress(i32 0) + %1 = ptrtoint i8* %0 to i32 + %2 = tail call i8* @llvm.returnaddress(i32 0) + %3 = ptrtoint i8* %2 to i32 + %val0 = insertvalue [2 x i32] [i32 undef, i32 undef], i32 %3, 0 + %val1 = insertvalue [2 x i32] %val0, i32 %1, 1 + store [2 x i32] %val1, [2 x i32]* @somevar, align 8 + ret void +} diff --git a/test/CodeGen/ARM/saxpy10-a9.ll b/test/CodeGen/ARM/saxpy10-a9.ll index f8f5e18fcf5e..91610f1a232d 100644 --- a/test/CodeGen/ARM/saxpy10-a9.ll +++ b/test/CodeGen/ARM/saxpy10-a9.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -misched-bench -scheditins=false | FileCheck %s +; RUN: llc < %s -march=arm -mtriple=thumbv7-apple-ios7.0.0 -float-abi=hard -mcpu=cortex-a9 -misched-postra -enable-misched -pre-RA-sched=source -scheditins=false | FileCheck %s ; ; Test MI-Sched suppory latency based stalls on in in-order pipeline ; using the new machine model. @@ -14,15 +14,12 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK: vldr ; CHECK: vldr ; CHECK: vldr -; CHECK: vldr +; CHECK-NEXT: vldr +; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vldr -; CHECK-NEXT: vldr -; CHECK-NEXT: vadd -; CHECK-NEXT: vmul -; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd ; CHECK-NEXT: vmul @@ -31,6 +28,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul +; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vadd @@ -48,6 +46,8 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vadd +; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr @@ -63,72 +63,72 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; This accumulates a sum rather than storing each result. define float @saxpy10(float* nocapture readonly %data1, float* nocapture readonly %data2, float %a) { entry: - %0 = load float* %data1, align 4 + %0 = load float, float* %data1, align 4 %mul = fmul float %0, %a - %1 = load float* %data2, align 4 + %1 = load float, float* %data2, align 4 %add = fadd float %mul, %1 %add2 = fadd float %add, 0.000000e+00 - %arrayidx.1 = getelementptr inbounds float* %data1, i32 1 - %2 = load float* %arrayidx.1, align 4 + %arrayidx.1 = getelementptr inbounds float, float* %data1, i32 1 + %2 = load float, float* %arrayidx.1, align 4 %mul.1 = fmul float %2, %a - %arrayidx1.1 = getelementptr inbounds float* %data2, i32 1 - %3 = load float* %arrayidx1.1, align 4 + %arrayidx1.1 = getelementptr inbounds float, float* %data2, i32 1 + %3 = load float, float* %arrayidx1.1, align 4 %add.1 = fadd float %mul.1, %3 %add2.1 = fadd float %add2, %add.1 - %arrayidx.2 = getelementptr inbounds float* %data1, i32 2 - %4 = load float* %arrayidx.2, align 4 + %arrayidx.2 = getelementptr inbounds float, float* %data1, i32 2 + %4 = load float, float* %arrayidx.2, align 4 %mul.2 = fmul float %4, %a - %arrayidx1.2 = getelementptr inbounds float* %data2, i32 2 - %5 = load float* %arrayidx1.2, align 4 + %arrayidx1.2 = getelementptr inbounds float, float* %data2, i32 2 + %5 = load float, float* %arrayidx1.2, align 4 %add.2 = fadd float %mul.2, %5 %add2.2 = fadd float %add2.1, %add.2 - %arrayidx.3 = getelementptr inbounds float* %data1, i32 3 - %6 = load float* %arrayidx.3, align 4 + %arrayidx.3 = getelementptr inbounds float, float* %data1, i32 3 + %6 = load float, float* %arrayidx.3, align 4 %mul.3 = fmul float %6, %a - %arrayidx1.3 = getelementptr inbounds float* %data2, i32 3 - %7 = load float* %arrayidx1.3, align 4 + %arrayidx1.3 = getelementptr inbounds float, float* %data2, i32 3 + %7 = load float, float* %arrayidx1.3, align 4 %add.3 = fadd float %mul.3, %7 %add2.3 = fadd float %add2.2, %add.3 - %arrayidx.4 = getelementptr inbounds float* %data1, i32 4 - %8 = load float* %arrayidx.4, align 4 + %arrayidx.4 = getelementptr inbounds float, float* %data1, i32 4 + %8 = load float, float* %arrayidx.4, align 4 %mul.4 = fmul float %8, %a - %arrayidx1.4 = getelementptr inbounds float* %data2, i32 4 - %9 = load float* %arrayidx1.4, align 4 + %arrayidx1.4 = getelementptr inbounds float, float* %data2, i32 4 + %9 = load float, float* %arrayidx1.4, align 4 %add.4 = fadd float %mul.4, %9 %add2.4 = fadd float %add2.3, %add.4 - %arrayidx.5 = getelementptr inbounds float* %data1, i32 5 - %10 = load float* %arrayidx.5, align 4 + %arrayidx.5 = getelementptr inbounds float, float* %data1, i32 5 + %10 = load float, float* %arrayidx.5, align 4 %mul.5 = fmul float %10, %a - %arrayidx1.5 = getelementptr inbounds float* %data2, i32 5 - %11 = load float* %arrayidx1.5, align 4 + %arrayidx1.5 = getelementptr inbounds float, float* %data2, i32 5 + %11 = load float, float* %arrayidx1.5, align 4 %add.5 = fadd float %mul.5, %11 %add2.5 = fadd float %add2.4, %add.5 - %arrayidx.6 = getelementptr inbounds float* %data1, i32 6 - %12 = load float* %arrayidx.6, align 4 + %arrayidx.6 = getelementptr inbounds float, float* %data1, i32 6 + %12 = load float, float* %arrayidx.6, align 4 %mul.6 = fmul float %12, %a - %arrayidx1.6 = getelementptr inbounds float* %data2, i32 6 - %13 = load float* %arrayidx1.6, align 4 + %arrayidx1.6 = getelementptr inbounds float, float* %data2, i32 6 + %13 = load float, float* %arrayidx1.6, align 4 %add.6 = fadd float %mul.6, %13 %add2.6 = fadd float %add2.5, %add.6 - %arrayidx.7 = getelementptr inbounds float* %data1, i32 7 - %14 = load float* %arrayidx.7, align 4 + %arrayidx.7 = getelementptr inbounds float, float* %data1, i32 7 + %14 = load float, float* %arrayidx.7, align 4 %mul.7 = fmul float %14, %a - %arrayidx1.7 = getelementptr inbounds float* %data2, i32 7 - %15 = load float* %arrayidx1.7, align 4 + %arrayidx1.7 = getelementptr inbounds float, float* %data2, i32 7 + %15 = load float, float* %arrayidx1.7, align 4 %add.7 = fadd float %mul.7, %15 %add2.7 = fadd float %add2.6, %add.7 - %arrayidx.8 = getelementptr inbounds float* %data1, i32 8 - %16 = load float* %arrayidx.8, align 4 + %arrayidx.8 = getelementptr inbounds float, float* %data1, i32 8 + %16 = load float, float* %arrayidx.8, align 4 %mul.8 = fmul float %16, %a - %arrayidx1.8 = getelementptr inbounds float* %data2, i32 8 - %17 = load float* %arrayidx1.8, align 4 + %arrayidx1.8 = getelementptr inbounds float, float* %data2, i32 8 + %17 = load float, float* %arrayidx1.8, align 4 %add.8 = fadd float %mul.8, %17 %add2.8 = fadd float %add2.7, %add.8 - %arrayidx.9 = getelementptr inbounds float* %data1, i32 9 - %18 = load float* %arrayidx.9, align 4 + %arrayidx.9 = getelementptr inbounds float, float* %data1, i32 9 + %18 = load float, float* %arrayidx.9, align 4 %mul.9 = fmul float %18, %a - %arrayidx1.9 = getelementptr inbounds float* %data2, i32 9 - %19 = load float* %arrayidx1.9, align 4 + %arrayidx1.9 = getelementptr inbounds float, float* %data2, i32 9 + %19 = load float, float* %arrayidx1.9, align 4 %add.9 = fadd float %mul.9, %19 %add2.9 = fadd float %add2.8, %add.9 ret float %add2.9 diff --git a/test/CodeGen/ARM/sched-it-debug-nodes.ll b/test/CodeGen/ARM/sched-it-debug-nodes.ll new file mode 100644 index 000000000000..7906e7c7581e --- /dev/null +++ b/test/CodeGen/ARM/sched-it-debug-nodes.ll @@ -0,0 +1,88 @@ +; RUN: llc -mtriple thumbv7 -print-before=post-RA-sched -print-after=post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s + +; ModuleID = '<stdin>' +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv7" + +%struct.s = type opaque + +; Function Attrs: nounwind +define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 { +entry: + tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !19, metadata !28), !dbg !29 + tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !20, metadata !28), !dbg !29 + tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !21, metadata !28), !dbg !29 + tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !22, metadata !28), !dbg !29 + %cmp = icmp ult i32 %n, 4, !dbg !30 + br i1 %cmp, label %return, label %if.end, !dbg !32 + +if.end: ; preds = %entry + tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !33 + br label %return, !dbg !34 + +return: ; preds = %entry, %if.end + %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] + ret i32 %retval.0, !dbg !35 +} + +; NOTE: This is checking that the register in the DEBUG_VALUE node is not +; accidentally being marked as KILL. The DBG_VALUE node gets introduced in +; If-Conversion, and gets bundled into the IT block. The Post RA Scheduler +; attempts to schedule the Machine Instr, and tries to tag the register in the +; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or +; hopefully, triggering an assert). + +; CHECK: BUNDLE %ITSTATE<imp-def,dead> +; CHECK: * DBG_VALUE %R1, %noreg, !"u" +; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u" + +declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind readnone } +attributes #3 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!23, !24, !25, !26} +!llvm.ident = !{!27} + +!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") +!2 = !{} +!3 = !{!4} +!4 = !DISubprogram(name: "f", scope: !5, file: !5, line: 9, type: !6, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, function: i32 (%struct.s*, i32, i8*, i32)* @f, variables: !18) +!5 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") +!6 = !DISubroutineType(types: !7) +!7 = !{!8, !9, !12, !13, !17} +!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 32, align: 32) +!10 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !5, line: 5, baseType: !11) +!11 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !5, line: 5, flags: DIFlagFwdDecl) +!12 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) +!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 32, align: 32) +!14 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !15) +!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !5, line: 2, baseType: !16) +!16 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) +!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !5, line: 3, baseType: !12) +!18 = !{!19, !20, !21, !22} +!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", arg: 1, scope: !4, file: !5, line: 9, type: !9) +!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "u", arg: 2, scope: !4, file: !5, line: 9, type: !12) +!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", arg: 3, scope: !4, file: !5, line: 9, type: !13) +!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "n", arg: 4, scope: !4, file: !5, line: 9, type: !17) +!23 = !{i32 2, !"Dwarf Version", i32 4} +!24 = !{i32 2, !"Debug Info Version", i32 3} +!25 = !{i32 1, !"wchar_size", i32 4} +!26 = !{i32 1, !"min_enum_size", i32 4} +!27 = !{!"clang version 3.7.0 (llvm/trunk 237059)"} +!28 = !DIExpression() +!29 = !DILocation(line: 9, scope: !4) +!30 = !DILocation(line: 10, scope: !31) +!31 = distinct !DILexicalBlock(scope: !4, file: !5, line: 10) +!32 = !DILocation(line: 10, scope: !4) +!33 = !DILocation(line: 13, scope: !4) +!34 = !DILocation(line: 14, scope: !4) +!35 = !DILocation(line: 15, scope: !4) diff --git a/test/CodeGen/ARM/section-name.ll b/test/CodeGen/ARM/section-name.ll index a0aad4733bc8..a4c6054197f3 100644 --- a/test/CodeGen/ARM/section-name.ll +++ b/test/CodeGen/ARM/section-name.ll @@ -16,7 +16,7 @@ entry: ret void } -; CHECK: .section .text.test3,"axG",%progbits,test3,comdat +; CHECK: .text ; CHECK: .weak test3 ; CHECK: .type test3,%function define linkonce_odr void @test3() { diff --git a/test/CodeGen/ARM/segmented-stacks.ll b/test/CodeGen/ARM/segmented-stacks.ll index 9873bf332948..cbb124de11c3 100644 --- a/test/CodeGen/ARM/segmented-stacks.ll +++ b/test/CodeGen/ARM/segmented-stacks.ll @@ -55,7 +55,7 @@ define void @test_basic() #0 { } define i32 @test_nested(i32 * nest %closure, i32 %other) #0 { - %addend = load i32 * %closure + %addend = load i32 , i32 * %closure %result = add i32 %other, %addend %mem = alloca i32, i32 10 call void @dummy_use (i32* %mem, i32 10) diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index 326eb512d858..460ca8f18405 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -183,7 +183,7 @@ define i32 @t12(i32 %a, i32 %b) nounwind { ; Handle frame index operands. define void @pr13628() nounwind uwtable align 2 { %x3 = alloca i8, i32 256, align 8 - %x4 = load i8* undef, align 1 + %x4 = load i8, i8* undef, align 1 %x5 = icmp ne i8 %x4, 0 %x6 = select i1 %x5, i8* %x3, i8* null call void @bar(i8* %x6) nounwind diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index f14adcae663c..6f5c0e8279a9 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -43,8 +43,8 @@ entry: %tmp3 = inttoptr i32 %tmp2 to i32* %tmp4 = add i32 %base2, %tmp1 %tmp5 = inttoptr i32 %tmp4 to i32* - %tmp6 = load i32* %tmp3 - %tmp7 = load i32* %tmp5 + %tmp6 = load i32, i32* %tmp3 + %tmp7 = load i32, i32* %tmp5 %tmp8 = add i32 %tmp7, %tmp6 ret i32 %tmp8 } @@ -64,11 +64,11 @@ entry: ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! ; A9: str [[REG]], [r0, r1, lsl #2] ; A9-NOT: str [[REG]], [r0] - %0 = tail call i8* (...)* @malloc(i32 undef) nounwind + %0 = tail call i8* (...) @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 - %3 = getelementptr inbounds i32* %1, i32 %2 - %4 = load i32* %3, align 4 + %3 = getelementptr inbounds i32, i32* %1, i32 %2 + %4 = load i32, i32* %3, align 4 %5 = add nsw i32 %4, 1 store i32 %5, i32* %3, align 4 ret void diff --git a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll index d8241d0dc380..f85203e381b9 100644 --- a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll +++ b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O1 -mtriple thumbv7-apple-ios6 +; RUN: llc < %s -O1 -mtriple thumbv7-apple-ios6 | FileCheck %s ; Just make sure no one tries to make the assumption that the normal edge of an ; invoke is never a critical edge. Previously, this code would assert. @@ -65,3 +65,129 @@ declare i32 @__gxx_personality_sj0(...) declare void @release(i8*) declare void @terminatev() + +; Make sure that the instruction DemoteRegToStack inserts to reload +; %call.i.i.i14.i.i follows the instruction that saves the value to the stack in +; basic block %entry.do.body.i.i.i_crit_edge. +; Previously, DemoteRegToStack would insert a load instruction into the entry +; block to reload %call.i.i.i14.i.i before the phi instruction (%0) in block +; %do.body.i.i.i. + +; CHECK-LABEL: __Z4foo1c: +; CHECK: blx __Znwm +; CHECK: {{.*}}@ %entry.do.body.i.i.i_crit_edge +; CHECK: str r0, [sp, [[OFFSET:#[0-9]+]]] +; CHECK: ldr [[R0:r[0-9]+]], [sp, [[OFFSET]]] +; CHECK: {{.*}}@ %do.body.i.i.i +; CHECK: cbz [[R0]] + +%"class.std::__1::basic_string" = type { %"class.std::__1::__compressed_pair" } +%"class.std::__1::__compressed_pair" = type { %"class.std::__1::__libcpp_compressed_pair_imp" } +%"class.std::__1::__libcpp_compressed_pair_imp" = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep" } +%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep" = type { %union.anon } +%union.anon = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long" } +%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long" = type { i32, i32, i8* } + +@.str = private unnamed_addr constant [12 x i8] c"some_string\00", align 1 + +define void @_Z4foo1c(i8 signext %a) { +entry: + %s1 = alloca %"class.std::__1::basic_string", align 4 + call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"* %s1, i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), i32 11) + %call.i.i.i14.i.i = invoke noalias i8* @_Znwm(i32 1024) + to label %do.body.i.i.i unwind label %lpad.body + +do.body.i.i.i: ; preds = %entry, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i + %lsr.iv = phi i32 [ %lsr.iv.next, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ -1024, %entry ] + %0 = phi i8* [ %incdec.ptr.i.i.i, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ %call.i.i.i14.i.i, %entry ] + %new.isnull.i.i.i.i = icmp eq i8* %0, null + br i1 %new.isnull.i.i.i.i, label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i, label %new.notnull.i.i.i.i + +new.notnull.i.i.i.i: ; preds = %do.body.i.i.i + store i8 %a, i8* %0, align 1 + br label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i + +_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i: ; preds = %new.notnull.i.i.i.i, %do.body.i.i.i + %1 = phi i8* [ null, %do.body.i.i.i ], [ %0, %new.notnull.i.i.i.i ] + %incdec.ptr.i.i.i = getelementptr inbounds i8, i8* %1, i32 1 + %lsr.iv.next = add i32 %lsr.iv, 1 + %cmp.i16.i.i = icmp eq i32 %lsr.iv.next, 0 + br i1 %cmp.i16.i.i, label %invoke.cont, label %do.body.i.i.i + +invoke.cont: ; preds = %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i + invoke void @_Z4foo2Pci(i8* %call.i.i.i14.i.i, i32 1024) + to label %invoke.cont5 unwind label %lpad2 + +invoke.cont5: ; preds = %invoke.cont + %cmp.i.i.i15 = icmp eq i8* %call.i.i.i14.i.i, null + br i1 %cmp.i.i.i15, label %invoke.cont6, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19 + +_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19: ; preds = %invoke.cont5 + call void @_ZdlPv(i8* %call.i.i.i14.i.i) + br label %invoke.cont6 + +invoke.cont6: ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19, %invoke.cont5 + %call10 = call %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1) + ret void + +lpad.body: ; preds = %entry + %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %3 = extractvalue { i8*, i32 } %2, 0 + %4 = extractvalue { i8*, i32 } %2, 1 + br label %ehcleanup + +lpad2: ; preds = %invoke.cont + %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %6 = extractvalue { i8*, i32 } %5, 0 + %7 = extractvalue { i8*, i32 } %5, 1 + %cmp.i.i.i21 = icmp eq i8* %call.i.i.i14.i.i, null + br i1 %cmp.i.i.i21, label %ehcleanup, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 + +_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26: ; preds = %lpad2 + call void @_ZdlPv(i8* %call.i.i.i14.i.i) + br label %ehcleanup + +ehcleanup: ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26, %lpad2, %lpad.body + %exn.slot.0 = phi i8* [ %3, %lpad.body ], [ %6, %lpad2 ], [ %6, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ] + %ehselector.slot.0 = phi i32 [ %4, %lpad.body ], [ %7, %lpad2 ], [ %7, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ] + %call12 = invoke %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1) + to label %eh.resume unwind label %terminate.lpad + +eh.resume: ; preds = %ehcleanup + %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.0, 0 + %lpad.val13 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.0, 1 + resume { i8*, i32 } %lpad.val13 + +terminate.lpad: ; preds = %ehcleanup + %8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null + %9 = extractvalue { i8*, i32 } %8, 0 + call void @__clang_call_terminate(i8* %9) + unreachable +} + +declare void @_Z4foo2Pci(i8*, i32) + +define linkonce_odr hidden void @__clang_call_terminate(i8*) { + %2 = tail call i8* @__cxa_begin_catch(i8* %0) + tail call void @_ZSt9terminatev() + unreachable +} + +declare i8* @__cxa_begin_catch(i8*) +declare void @_ZSt9terminatev() +declare %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* returned) +declare void @_ZdlPv(i8*) #3 +declare noalias i8* @_Znwm(i32) +declare void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"*, i8*, i32) +declare void @_Unwind_SjLj_Register({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*) +declare void @_Unwind_SjLj_Unregister({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*) +declare i8* @llvm.frameaddress(i32) +declare i8* @llvm.stacksave() +declare void @llvm.stackrestore(i8*) +declare i32 @llvm.eh.sjlj.setjmp(i8*) +declare i8* @llvm.eh.sjlj.lsda() +declare void @llvm.eh.sjlj.callsite(i32) +declare void @llvm.eh.sjlj.functioncontext(i8*) diff --git a/test/CodeGen/ARM/smul.ll b/test/CodeGen/ARM/smul.ll index b7ddd10a5682..13873f511e1f 100644 --- a/test/CodeGen/ARM/smul.ll +++ b/test/CodeGen/ARM/smul.ll @@ -7,7 +7,7 @@ define i32 @f1(i32 %y) { ; CHECK: f1 ; CHECK: smulbt - %tmp = load i16* @x ; <i16> [#uses=1] + %tmp = load i16, i16* @x ; <i16> [#uses=1] %tmp1 = add i16 %tmp, 2 ; <i16> [#uses=1] %tmp2 = sext i16 %tmp1 to i32 ; <i32> [#uses=1] %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/space-directive.ll b/test/CodeGen/ARM/space-directive.ll index 55be1991fe82..24f0d0aadf60 100644 --- a/test/CodeGen/ARM/space-directive.ll +++ b/test/CodeGen/ARM/space-directive.ll @@ -11,7 +11,7 @@ define i32 @test_space() minsize { ; CHECK: [[PAST_CP]]: ; CHECK: .zero 10000 %addr = inttoptr i32 12345678 to i32* - %val = load i32* %addr + %val = load i32, i32* %addr call i32 @llvm.arm.space(i32 10000, i32 undef) ret i32 %val } diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 425fc12755cd..1a102e3d971f 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -43,7 +43,7 @@ entry: store float 0.000000e+00, float* undef, align 4 %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %val173 = load <4 x float>* undef ; <<4 x float>> [#uses=1] + %val173 = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1] br label %bb4 bb4: ; preds = %bb193, %entry diff --git a/test/CodeGen/ARM/ssp-data-layout.ll b/test/CodeGen/ARM/ssp-data-layout.ll index e7dafac7020d..92fa0809ed2d 100644 --- a/test/CodeGen/ARM/ssp-data-layout.ll +++ b/test/CodeGen/ARM/ssp-data-layout.ll @@ -21,13 +21,13 @@ define void @layout_ssp() ssp { entry: ; Expected stack layout for ssp is -; 180 large_char . Group 1, nested arrays, arrays >= ssp-buffer-size -; 172 struct_large_char . -; 168 scalar1 | Everything else -; 164 scalar2 -; 160 scalar3 -; 156 addr-of -; 152 small_nonchar (84+68) +; 176 large_char . Group 1, nested arrays, arrays >= ssp-buffer-size +; 168 struct_large_char . +; 164 scalar1 | Everything else +; 160 scalar2 +; 156 scalar3 +; 152 addr-of +; 148 small_nonchar ; 112 large_nonchar ; 110 small_char ; 108 struct_small_char @@ -35,27 +35,25 @@ entry: ; 68 struct_small_nonchar ; CHECK: layout_ssp: -; r[[SP]] is used as an offset into the stack later -; CHECK: add r[[SP:[0-9]+]], sp, #68 ; CHECK: bl get_scalar1 -; CHECK: str r0, [sp, #168] +; CHECK: str r0, [sp, #164] ; CHECK: bl end_scalar1 ; CHECK: bl get_scalar2 -; CHECK: str r0, [sp, #164] +; CHECK: str r0, [sp, #160] ; CHECK: bl end_scalar2 ; CHECK: bl get_scalar3 -; CHECK: str r0, [sp, #160] +; CHECK: str r0, [sp, #156] ; CHECK: bl end_scalar3 ; CHECK: bl get_addrof -; CHECK: str r0, [sp, #156] +; CHECK: str r0, [sp, #152] ; CHECK: bl end_addrof ; CHECK: get_small_nonchar -; CHECK: strh r0, [r[[SP]], #84] +; CHECK: strh r0, [sp, #148] ; CHECK: bl end_small_nonchar ; CHECK: bl get_large_nonchar @@ -67,11 +65,11 @@ entry: ; CHECK: bl end_small_char ; CHECK: bl get_large_char -; CHECK: strb r0, [sp, #180] +; CHECK: strb r0, [sp, #176] ; CHECK: bl end_large_char ; CHECK: bl get_struct_large_char -; CHECK: strb r0, [sp, #172] +; CHECK: strb r0, [sp, #168] ; CHECK: bl end_struct_large_char ; CHECK: bl get_struct_small_char @@ -83,7 +81,7 @@ entry: ; CHECK: bl end_struct_large_nonchar ; CHECK: bl get_struct_small_nonchar -; CHECK: strh r0, [r[[SP]]] +; CHECK: strh r0, [sp, #68] ; CHECK: bl end_struct_small_nonchar %x = alloca i32, align 4 %y = alloca i32, align 4 @@ -110,58 +108,58 @@ entry: store i32 %call3, i32* %ptr, align 4 call void @end_addrof() %call4 = call signext i16 @get_small_nonchar() - %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0 + %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0 store i16 %call4, i16* %arrayidx, align 2 call void @end_small_nonchar() %call5 = call i32 @get_large_nonchar() - %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0 + %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0 store i32 %call5, i32* %arrayidx6, align 4 call void @end_large_nonchar() %call7 = call signext i8 @get_small_char() - %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0 + %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0 store i8 %call7, i8* %arrayidx8, align 1 call void @end_small_char() %call9 = call signext i8 @get_large_char() - %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0 + %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0 store i8 %call9, i8* %arrayidx10, align 1 call void @end_large_char() %call11 = call signext i8 @get_struct_large_char() - %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0 - %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0 + %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0 + %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0 store i8 %call11, i8* %arrayidx12, align 1 call void @end_struct_large_char() %call13 = call signext i8 @get_struct_small_char() - %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0 - %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0 + %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0 + %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0 store i8 %call13, i8* %arrayidx15, align 1 call void @end_struct_small_char() %call16 = call i32 @get_struct_large_nonchar() - %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0 - %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0 + %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0 + %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0 store i32 %call16, i32* %arrayidx18, align 4 call void @end_struct_large_nonchar() %call19 = call signext i16 @get_struct_small_nonchar() - %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0 - %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0 + %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 + %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0 store i16 %call19, i16* %arrayidx21, align 2 call void @end_struct_small_nonchar() - %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0 - %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0 - %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0 - %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0 - %0 = load i32* %x, align 4 - %1 = load i32* %y, align 4 - %2 = load i32* %z, align 4 - %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0 + %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0 + %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0 + %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0 + %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0 + %0 = load i32, i32* %x, align 4 + %1 = load i32, i32* %y, align 4 + %2 = load i32, i32* %z, align 4 + %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0 %3 = bitcast [8 x i8]* %coerce.dive to i64* - %4 = load i64* %3, align 1 - %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0 + %4 = load i64, i64* %3, align 1 + %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0 %5 = bitcast [2 x i8]* %coerce.dive25 to i16* - %6 = load i16* %5, align 1 - %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0 + %6 = load i16, i16* %5, align 1 + %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* - %8 = load i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + %8 = load i32, i32* %7, align 1 + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -182,8 +180,6 @@ entry: ; 68 scalar3 + ; ; CHECK: layout_sspstrong: -; r[[SP]] is used as an offset into the stack later -; CHECK: add r[[SP:[0-9]+]], sp, #84 ; CHECK: bl get_scalar1 ; CHECK: str r0, [sp, #76] @@ -202,7 +198,7 @@ entry: ; CHECK: bl end_addrof ; CHECK: get_small_nonchar -; CHECK: strh r0, [r[[SP]], #8] +; CHECK: strh r0, [sp, #92] ; CHECK: bl end_small_nonchar ; CHECK: bl get_large_nonchar @@ -230,7 +226,7 @@ entry: ; CHECK: bl end_struct_large_nonchar ; CHECK: bl get_struct_small_nonchar -; CHECK: strh r0, [r[[SP]]] +; CHECK: strh r0, [sp, #84] ; CHECK: bl end_struct_small_nonchar %x = alloca i32, align 4 %y = alloca i32, align 4 @@ -257,58 +253,58 @@ entry: store i32 %call3, i32* %ptr, align 4 call void @end_addrof() %call4 = call signext i16 @get_small_nonchar() - %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0 + %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0 store i16 %call4, i16* %arrayidx, align 2 call void @end_small_nonchar() %call5 = call i32 @get_large_nonchar() - %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0 + %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0 store i32 %call5, i32* %arrayidx6, align 4 call void @end_large_nonchar() %call7 = call signext i8 @get_small_char() - %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0 + %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0 store i8 %call7, i8* %arrayidx8, align 1 call void @end_small_char() %call9 = call signext i8 @get_large_char() - %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0 + %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0 store i8 %call9, i8* %arrayidx10, align 1 call void @end_large_char() %call11 = call signext i8 @get_struct_large_char() - %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0 - %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0 + %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0 + %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0 store i8 %call11, i8* %arrayidx12, align 1 call void @end_struct_large_char() %call13 = call signext i8 @get_struct_small_char() - %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0 - %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0 + %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0 + %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0 store i8 %call13, i8* %arrayidx15, align 1 call void @end_struct_small_char() %call16 = call i32 @get_struct_large_nonchar() - %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0 - %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0 + %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0 + %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0 store i32 %call16, i32* %arrayidx18, align 4 call void @end_struct_large_nonchar() %call19 = call signext i16 @get_struct_small_nonchar() - %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0 - %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0 + %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 + %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0 store i16 %call19, i16* %arrayidx21, align 2 call void @end_struct_small_nonchar() - %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0 - %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0 - %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0 - %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0 - %0 = load i32* %x, align 4 - %1 = load i32* %y, align 4 - %2 = load i32* %z, align 4 - %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0 + %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0 + %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0 + %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0 + %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0 + %0 = load i32, i32* %x, align 4 + %1 = load i32, i32* %y, align 4 + %2 = load i32, i32* %z, align 4 + %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0 %3 = bitcast [8 x i8]* %coerce.dive to i64* - %4 = load i64* %3, align 1 - %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0 + %4 = load i64, i64* %3, align 1 + %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0 %5 = bitcast [2 x i8]* %coerce.dive25 to i16* - %6 = load i16* %5, align 1 - %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0 + %6 = load i16, i16* %5, align 1 + %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* - %8 = load i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + %8 = load i32, i32* %7, align 1 + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -317,8 +313,6 @@ entry: ; Expected stack layout for sspreq is the same as sspstrong ; ; CHECK: layout_sspreq: -; r[[SP]] is used as an offset into the stack later -; CHECK: add r[[SP:[0-9]+]], sp, #84 ; CHECK: bl get_scalar1 ; CHECK: str r0, [sp, #76] @@ -337,7 +331,7 @@ entry: ; CHECK: bl end_addrof ; CHECK: get_small_nonchar -; CHECK: strh r0, [r[[SP]], #8] +; CHECK: strh r0, [sp, #92] ; CHECK: bl end_small_nonchar ; CHECK: bl get_large_nonchar @@ -365,7 +359,7 @@ entry: ; CHECK: bl end_struct_large_nonchar ; CHECK: bl get_struct_small_nonchar -; CHECK: strh r0, [r[[SP]]] +; CHECK: strh r0, [sp, #84] ; CHECK: bl end_struct_small_nonchar %x = alloca i32, align 4 %y = alloca i32, align 4 @@ -392,58 +386,58 @@ entry: store i32 %call3, i32* %ptr, align 4 call void @end_addrof() %call4 = call signext i16 @get_small_nonchar() - %arrayidx = getelementptr inbounds [2 x i16]* %small2, i32 0, i64 0 + %arrayidx = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i64 0 store i16 %call4, i16* %arrayidx, align 2 call void @end_small_nonchar() %call5 = call i32 @get_large_nonchar() - %arrayidx6 = getelementptr inbounds [8 x i32]* %large2, i32 0, i64 0 + %arrayidx6 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i64 0 store i32 %call5, i32* %arrayidx6, align 4 call void @end_large_nonchar() %call7 = call signext i8 @get_small_char() - %arrayidx8 = getelementptr inbounds [2 x i8]* %small, i32 0, i64 0 + %arrayidx8 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i64 0 store i8 %call7, i8* %arrayidx8, align 1 call void @end_small_char() %call9 = call signext i8 @get_large_char() - %arrayidx10 = getelementptr inbounds [8 x i8]* %large, i32 0, i64 0 + %arrayidx10 = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i64 0 store i8 %call9, i8* %arrayidx10, align 1 call void @end_large_char() %call11 = call signext i8 @get_struct_large_char() - %foo = getelementptr inbounds %struct.struct_large_char* %a, i32 0, i32 0 - %arrayidx12 = getelementptr inbounds [8 x i8]* %foo, i32 0, i64 0 + %foo = getelementptr inbounds %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0 + %arrayidx12 = getelementptr inbounds [8 x i8], [8 x i8]* %foo, i32 0, i64 0 store i8 %call11, i8* %arrayidx12, align 1 call void @end_struct_large_char() %call13 = call signext i8 @get_struct_small_char() - %foo14 = getelementptr inbounds %struct.struct_small_char* %b, i32 0, i32 0 - %arrayidx15 = getelementptr inbounds [2 x i8]* %foo14, i32 0, i64 0 + %foo14 = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0 + %arrayidx15 = getelementptr inbounds [2 x i8], [2 x i8]* %foo14, i32 0, i64 0 store i8 %call13, i8* %arrayidx15, align 1 call void @end_struct_small_char() %call16 = call i32 @get_struct_large_nonchar() - %foo17 = getelementptr inbounds %struct.struct_large_nonchar* %c, i32 0, i32 0 - %arrayidx18 = getelementptr inbounds [8 x i32]* %foo17, i32 0, i64 0 + %foo17 = getelementptr inbounds %struct.struct_large_nonchar, %struct.struct_large_nonchar* %c, i32 0, i32 0 + %arrayidx18 = getelementptr inbounds [8 x i32], [8 x i32]* %foo17, i32 0, i64 0 store i32 %call16, i32* %arrayidx18, align 4 call void @end_struct_large_nonchar() %call19 = call signext i16 @get_struct_small_nonchar() - %foo20 = getelementptr inbounds %struct.struct_small_nonchar* %d, i32 0, i32 0 - %arrayidx21 = getelementptr inbounds [2 x i16]* %foo20, i32 0, i64 0 + %foo20 = getelementptr inbounds %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 + %arrayidx21 = getelementptr inbounds [2 x i16], [2 x i16]* %foo20, i32 0, i64 0 store i16 %call19, i16* %arrayidx21, align 2 call void @end_struct_small_nonchar() - %arraydecay = getelementptr inbounds [8 x i8]* %large, i32 0, i32 0 - %arraydecay22 = getelementptr inbounds [2 x i8]* %small, i32 0, i32 0 - %arraydecay23 = getelementptr inbounds [8 x i32]* %large2, i32 0, i32 0 - %arraydecay24 = getelementptr inbounds [2 x i16]* %small2, i32 0, i32 0 - %0 = load i32* %x, align 4 - %1 = load i32* %y, align 4 - %2 = load i32* %z, align 4 - %coerce.dive = getelementptr %struct.struct_large_char* %a, i32 0, i32 0 + %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %large, i32 0, i32 0 + %arraydecay22 = getelementptr inbounds [2 x i8], [2 x i8]* %small, i32 0, i32 0 + %arraydecay23 = getelementptr inbounds [8 x i32], [8 x i32]* %large2, i32 0, i32 0 + %arraydecay24 = getelementptr inbounds [2 x i16], [2 x i16]* %small2, i32 0, i32 0 + %0 = load i32, i32* %x, align 4 + %1 = load i32, i32* %y, align 4 + %2 = load i32, i32* %z, align 4 + %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %a, i32 0, i32 0 %3 = bitcast [8 x i8]* %coerce.dive to i64* - %4 = load i64* %3, align 1 - %coerce.dive25 = getelementptr %struct.struct_small_char* %b, i32 0, i32 0 + %4 = load i64, i64* %3, align 1 + %coerce.dive25 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %b, i32 0, i32 0 %5 = bitcast [2 x i8]* %coerce.dive25 to i16* - %6 = load i16* %5, align 1 - %coerce.dive26 = getelementptr %struct.struct_small_nonchar* %d, i32 0, i32 0 + %6 = load i16, i16* %5, align 1 + %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* - %8 = load i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + %8 = load i32, i32* %7, align 1 + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -463,26 +457,26 @@ entry: %d1 = alloca %struct.struct_large_nonchar, align 8 %d2 = alloca %struct.struct_small_nonchar, align 2 %call = call signext i8 @get_struct_small_char() - %foo = getelementptr inbounds %struct.struct_small_char* %a, i32 0, i32 0 - %arrayidx = getelementptr inbounds [2 x i8]* %foo, i32 0, i64 0 + %foo = getelementptr inbounds %struct.struct_small_char, %struct.struct_small_char* %a, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %foo, i32 0, i64 0 store i8 %call, i8* %arrayidx, align 1 call void @end_struct_small_char() %call1 = call signext i8 @get_struct_large_char2() - %foo2 = getelementptr inbounds %struct.struct_large_char2* %b, i32 0, i32 1 - %arrayidx3 = getelementptr inbounds [8 x i8]* %foo2, i32 0, i64 0 + %foo2 = getelementptr inbounds %struct.struct_large_char2, %struct.struct_large_char2* %b, i32 0, i32 1 + %arrayidx3 = getelementptr inbounds [8 x i8], [8 x i8]* %foo2, i32 0, i64 0 store i8 %call1, i8* %arrayidx3, align 1 call void @end_struct_large_char2() %0 = bitcast %struct.struct_large_char2* %b to %struct.struct_large_char* - %coerce.dive = getelementptr %struct.struct_large_char* %0, i32 0, i32 0 + %coerce.dive = getelementptr %struct.struct_large_char, %struct.struct_large_char* %0, i32 0, i32 0 %1 = bitcast [8 x i8]* %coerce.dive to i64* - %2 = load i64* %1, align 1 - %coerce.dive4 = getelementptr %struct.struct_small_char* %a, i32 0, i32 0 + %2 = load i64, i64* %1, align 1 + %coerce.dive4 = getelementptr %struct.struct_small_char, %struct.struct_small_char* %a, i32 0, i32 0 %3 = bitcast [2 x i8]* %coerce.dive4 to i16* - %4 = load i16* %3, align 1 - %coerce.dive5 = getelementptr %struct.struct_small_nonchar* %d2, i32 0, i32 0 + %4 = load i16, i16* %3, align 1 + %coerce.dive5 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d2, i32 0, i32 0 %5 = bitcast [2 x i16]* %coerce.dive5 to i32* - %6 = load i32* %5, align 1 - call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval align 8 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0) + %6 = load i32, i32* %5, align 1 + call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0) ret void } diff --git a/test/CodeGen/ARM/stack-alignment.ll b/test/CodeGen/ARM/stack-alignment.ll index 153f92e25f62..ac14a5959d1f 100644 --- a/test/CodeGen/ARM/stack-alignment.ll +++ b/test/CodeGen/ARM/stack-alignment.ll @@ -40,65 +40,65 @@ entry: ; CHECK-THUMB2: bfc r4, #0, #12 ; CHECK-THUMB2-NEXT: mov sp, r4 %a = alloca i8, align 4096 - %0 = load double* %d, align 4 - %arrayidx1 = getelementptr inbounds double* %d, i32 1 - %1 = load double* %arrayidx1, align 4 - %arrayidx2 = getelementptr inbounds double* %d, i32 2 - %2 = load double* %arrayidx2, align 4 - %arrayidx3 = getelementptr inbounds double* %d, i32 3 - %3 = load double* %arrayidx3, align 4 - %arrayidx4 = getelementptr inbounds double* %d, i32 4 - %4 = load double* %arrayidx4, align 4 - %arrayidx5 = getelementptr inbounds double* %d, i32 5 - %5 = load double* %arrayidx5, align 4 - %arrayidx6 = getelementptr inbounds double* %d, i32 6 - %6 = load double* %arrayidx6, align 4 - %arrayidx7 = getelementptr inbounds double* %d, i32 7 - %7 = load double* %arrayidx7, align 4 - %arrayidx8 = getelementptr inbounds double* %d, i32 8 - %8 = load double* %arrayidx8, align 4 - %arrayidx9 = getelementptr inbounds double* %d, i32 9 - %9 = load double* %arrayidx9, align 4 - %arrayidx10 = getelementptr inbounds double* %d, i32 10 - %10 = load double* %arrayidx10, align 4 - %arrayidx11 = getelementptr inbounds double* %d, i32 11 - %11 = load double* %arrayidx11, align 4 - %arrayidx12 = getelementptr inbounds double* %d, i32 12 - %12 = load double* %arrayidx12, align 4 - %arrayidx13 = getelementptr inbounds double* %d, i32 13 - %13 = load double* %arrayidx13, align 4 - %arrayidx14 = getelementptr inbounds double* %d, i32 14 - %14 = load double* %arrayidx14, align 4 - %arrayidx15 = getelementptr inbounds double* %d, i32 15 - %15 = load double* %arrayidx15, align 4 - %arrayidx16 = getelementptr inbounds double* %d, i32 16 - %16 = load double* %arrayidx16, align 4 - %arrayidx17 = getelementptr inbounds double* %d, i32 17 - %17 = load double* %arrayidx17, align 4 - %arrayidx18 = getelementptr inbounds double* %d, i32 18 - %18 = load double* %arrayidx18, align 4 - %arrayidx19 = getelementptr inbounds double* %d, i32 19 - %19 = load double* %arrayidx19, align 4 - %arrayidx20 = getelementptr inbounds double* %d, i32 20 - %20 = load double* %arrayidx20, align 4 - %arrayidx21 = getelementptr inbounds double* %d, i32 21 - %21 = load double* %arrayidx21, align 4 - %arrayidx22 = getelementptr inbounds double* %d, i32 22 - %22 = load double* %arrayidx22, align 4 - %arrayidx23 = getelementptr inbounds double* %d, i32 23 - %23 = load double* %arrayidx23, align 4 - %arrayidx24 = getelementptr inbounds double* %d, i32 24 - %24 = load double* %arrayidx24, align 4 - %arrayidx25 = getelementptr inbounds double* %d, i32 25 - %25 = load double* %arrayidx25, align 4 - %arrayidx26 = getelementptr inbounds double* %d, i32 26 - %26 = load double* %arrayidx26, align 4 - %arrayidx27 = getelementptr inbounds double* %d, i32 27 - %27 = load double* %arrayidx27, align 4 - %arrayidx28 = getelementptr inbounds double* %d, i32 28 - %28 = load double* %arrayidx28, align 4 - %arrayidx29 = getelementptr inbounds double* %d, i32 29 - %29 = load double* %arrayidx29, align 4 + %0 = load double, double* %d, align 4 + %arrayidx1 = getelementptr inbounds double, double* %d, i32 1 + %1 = load double, double* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds double, double* %d, i32 2 + %2 = load double, double* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds double, double* %d, i32 3 + %3 = load double, double* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds double, double* %d, i32 4 + %4 = load double, double* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds double, double* %d, i32 5 + %5 = load double, double* %arrayidx5, align 4 + %arrayidx6 = getelementptr inbounds double, double* %d, i32 6 + %6 = load double, double* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds double, double* %d, i32 7 + %7 = load double, double* %arrayidx7, align 4 + %arrayidx8 = getelementptr inbounds double, double* %d, i32 8 + %8 = load double, double* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds double, double* %d, i32 9 + %9 = load double, double* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds double, double* %d, i32 10 + %10 = load double, double* %arrayidx10, align 4 + %arrayidx11 = getelementptr inbounds double, double* %d, i32 11 + %11 = load double, double* %arrayidx11, align 4 + %arrayidx12 = getelementptr inbounds double, double* %d, i32 12 + %12 = load double, double* %arrayidx12, align 4 + %arrayidx13 = getelementptr inbounds double, double* %d, i32 13 + %13 = load double, double* %arrayidx13, align 4 + %arrayidx14 = getelementptr inbounds double, double* %d, i32 14 + %14 = load double, double* %arrayidx14, align 4 + %arrayidx15 = getelementptr inbounds double, double* %d, i32 15 + %15 = load double, double* %arrayidx15, align 4 + %arrayidx16 = getelementptr inbounds double, double* %d, i32 16 + %16 = load double, double* %arrayidx16, align 4 + %arrayidx17 = getelementptr inbounds double, double* %d, i32 17 + %17 = load double, double* %arrayidx17, align 4 + %arrayidx18 = getelementptr inbounds double, double* %d, i32 18 + %18 = load double, double* %arrayidx18, align 4 + %arrayidx19 = getelementptr inbounds double, double* %d, i32 19 + %19 = load double, double* %arrayidx19, align 4 + %arrayidx20 = getelementptr inbounds double, double* %d, i32 20 + %20 = load double, double* %arrayidx20, align 4 + %arrayidx21 = getelementptr inbounds double, double* %d, i32 21 + %21 = load double, double* %arrayidx21, align 4 + %arrayidx22 = getelementptr inbounds double, double* %d, i32 22 + %22 = load double, double* %arrayidx22, align 4 + %arrayidx23 = getelementptr inbounds double, double* %d, i32 23 + %23 = load double, double* %arrayidx23, align 4 + %arrayidx24 = getelementptr inbounds double, double* %d, i32 24 + %24 = load double, double* %arrayidx24, align 4 + %arrayidx25 = getelementptr inbounds double, double* %d, i32 25 + %25 = load double, double* %arrayidx25, align 4 + %arrayidx26 = getelementptr inbounds double, double* %d, i32 26 + %26 = load double, double* %arrayidx26, align 4 + %arrayidx27 = getelementptr inbounds double, double* %d, i32 27 + %27 = load double, double* %arrayidx27, align 4 + %arrayidx28 = getelementptr inbounds double, double* %d, i32 28 + %28 = load double, double* %arrayidx28, align 4 + %arrayidx29 = getelementptr inbounds double, double* %d, i32 29 + %29 = load double, double* %arrayidx29, align 4 %div = fdiv double %29, %28 %div30 = fdiv double %div, %27 %div31 = fdiv double %div30, %26 @@ -159,6 +159,6 @@ entry: %div86 = fdiv double %div85, %29 %mul = fmul double %div57, %div86 %conv = fptosi double %mul to i32 - %add.ptr = getelementptr inbounds i8* %a, i32 %conv + %add.ptr = getelementptr inbounds i8, i8* %a, i32 %conv ret i8* %add.ptr } diff --git a/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll b/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll index f5cda14861af..2a7a82da8f69 100644 --- a/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll +++ b/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll @@ -14,9 +14,9 @@ target triple = "armv7s-apple-ios6.0.0" define i32 @main() #0 { entry: %title = alloca [15 x i8], align 1 - %0 = getelementptr inbounds [15 x i8]* %title, i32 0, i32 0 - call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* getelementptr inbounds ([15 x i8]* @main.title, i32 0, i32 0), i32 15, i32 1, i1 false) - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i8* %0) #3 + %0 = getelementptr inbounds [15 x i8], [15 x i8]* %title, i32 0, i32 0 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* getelementptr inbounds ([15 x i8], [15 x i8]* @main.title, i32 0, i32 0), i32 15, i32 1, i1 false) + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i8* %0) #3 ret i32 0 } diff --git a/test/CodeGen/ARM/stack_guard_remat.ll b/test/CodeGen/ARM/stack_guard_remat.ll index 7c89b99b8f97..99d499498450 100644 --- a/test/CodeGen/ARM/stack_guard_remat.ll +++ b/test/CodeGen/ARM/stack_guard_remat.ll @@ -52,7 +52,7 @@ define i32 @test_stack_guard_remat() #0 { %a1 = alloca [256 x i32], align 4 %1 = bitcast [256 x i32]* %a1 to i8* call void @llvm.lifetime.start(i64 1024, i8* %1) - %2 = getelementptr inbounds [256 x i32]* %a1, i32 0, i32 0 + %2 = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i32 0, i32 0 call void @foo3(i32* %2) #3 call void asm sideeffect "foo2", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{sp},~{lr}"() call void @llvm.lifetime.end(i64 1024, i8* %1) diff --git a/test/CodeGen/ARM/stm.ll b/test/CodeGen/ARM/stm.ll index 82dc14d14646..88207e6be105 100644 --- a/test/CodeGen/ARM/stm.ll +++ b/test/CodeGen/ARM/stm.ll @@ -10,7 +10,7 @@ entry: ; CHECK: main ; CHECK: push ; CHECK: stm - %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; <i32> [#uses=0] - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; <i32> [#uses=0] + %0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([26 x i8], [26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; <i32> [#uses=0] + %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([32 x i8], [32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/str_post.ll b/test/CodeGen/ARM/str_post.ll index a4f864065d5e..0933e15dab4e 100644 --- a/test/CodeGen/ARM/str_post.ll +++ b/test/CodeGen/ARM/str_post.ll @@ -3,7 +3,7 @@ define i16 @test1(i32* %X, i16* %A) { ; CHECK-LABEL: test1: ; CHECK: strh {{.*}}[{{.*}}], #-4 - %Y = load i32* %X ; <i32> [#uses=1] + %Y = load i32, i32* %X ; <i32> [#uses=1] %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1] store i16 %tmp1, i16* %A %tmp2 = ptrtoint i16* %A to i16 ; <i16> [#uses=1] @@ -14,7 +14,7 @@ define i16 @test1(i32* %X, i16* %A) { define i32 @test2(i32* %X, i32* %A) { ; CHECK-LABEL: test2: ; CHECK: str {{.*}}[{{.*}}], - %Y = load i32* %X ; <i32> [#uses=1] + %Y = load i32, i32* %X ; <i32> [#uses=1] store i32 %Y, i32* %A %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1] %tmp2 = sub i32 %tmp1, 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll index 5ce2bcecb476..4b8b4c6bca72 100644 --- a/test/CodeGen/ARM/str_pre-2.ll +++ b/test/CodeGen/ARM/str_pre-2.ll @@ -7,8 +7,8 @@ entry: ; CHECK: push {r4, r5, lr} ; CHECK: pop {r4, r5, pc} call void asm sideeffect "", "~{r4},~{r5}"() nounwind - %0 = load i64** @b, align 4 - %1 = load i64* %0, align 4 + %0 = load i64*, i64** @b, align 4 + %1 = load i64, i64* %0, align 4 %2 = mul i64 %1, %a ret i64 %2 } diff --git a/test/CodeGen/ARM/str_pre.ll b/test/CodeGen/ARM/str_pre.ll index 60e6e9ecfeb3..848261f83e31 100644 --- a/test/CodeGen/ARM/str_pre.ll +++ b/test/CodeGen/ARM/str_pre.ll @@ -1,16 +1,16 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define void @test1(i32* %X, i32* %A, i32** %dest) { - %B = load i32* %A ; <i32> [#uses=1] - %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] + %B = load i32, i32* %A ; <i32> [#uses=1] + %Y = getelementptr i32, i32* %X, i32 4 ; <i32*> [#uses=2] store i32 %B, i32* %Y store i32* %Y, i32** %dest ret void } define i16* @test2(i16* %X, i32* %A) { - %B = load i32* %A ; <i32> [#uses=1] - %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] + %B = load i32, i32* %A ; <i32> [#uses=1] + %Y = getelementptr i16, i16* %X, i32 4 ; <i16*> [#uses=2] %tmp = trunc i32 %B to i16 ; <i16> [#uses=1] store i16 %tmp, i16* %Y ret i16* %Y diff --git a/test/CodeGen/ARM/struct-byval-frame-index.ll b/test/CodeGen/ARM/struct-byval-frame-index.ll index 0fd55ec6c943..52f70fe1e0f8 100644 --- a/test/CodeGen/ARM/struct-byval-frame-index.ll +++ b/test/CodeGen/ARM/struct-byval-frame-index.ll @@ -72,10 +72,10 @@ declare void @SetMotionVectorsMB(%structK* nocapture, i32) #1 ; Function Attrs: nounwind define void @set_stored_macroblock_parameters() #1 { entry: - %0 = load %structB** @img, align 4 - %1 = load i32* undef, align 4 - %mb_data = getelementptr inbounds %structB* %0, i32 0, i32 61 - %2 = load %structK** %mb_data, align 4 + %0 = load %structB*, %structB** @img, align 4 + %1 = load i32, i32* undef, align 4 + %mb_data = getelementptr inbounds %structB, %structB* %0, i32 0, i32 61 + %2 = load %structK*, %structK** %mb_data, align 4 br label %for.body for.body: ; preds = %for.body, %entry @@ -110,7 +110,7 @@ for.body119: ; preds = %for.body119, %for.c if.end164: ; preds = %for.body119, %for.cond47.preheader, %if.end43 store i32*** null, i32**** @cofDC, align 4 - %mb_type = getelementptr inbounds %structK* %2, i32 %1, i32 8 + %mb_type = getelementptr inbounds %structK, %structK* %2, i32 %1, i32 8 br i1 undef, label %if.end230, label %if.then169 if.then169: ; preds = %if.end164 @@ -124,7 +124,7 @@ for.cond210.preheader: ; preds = %if.then169 if.end230: ; preds = %if.end164 tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* bitcast ([4 x i32]* @b8mode to i8*), i32 16, i32 4, i1 false) - %b8pdir = getelementptr inbounds %structK* %2, i32 %1, i32 15 + %b8pdir = getelementptr inbounds %structK, %structK* %2, i32 %1, i32 15 %3 = bitcast [4 x i32]* %b8pdir to i8* tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %3, i8* bitcast ([4 x i32]* @b8pdir to i8*), i32 16, i32 4, i1 false) br i1 undef, label %if.end236, label %if.then233 @@ -134,7 +134,7 @@ if.then233: ; preds = %if.end230 if.end236: ; preds = %if.end230 %cmp242 = icmp ne i16 undef, 8 - %4 = load i32* @luma_transform_size_8x8_flag, align 4 + %4 = load i32, i32* @luma_transform_size_8x8_flag, align 4 %tobool245 = icmp ne i32 %4, 0 %or.cond812 = or i1 %cmp242, %tobool245 br i1 %or.cond812, label %if.end249, label %land.lhs.true246 @@ -150,51 +150,51 @@ if.then248: ; preds = %land.lhs.true246 br label %if.end249 if.end249: ; preds = %if.then248, %land.lhs.true246, %if.end236 - %5 = load i32* @luma_transform_size_8x8_flag, align 4 - %6 = load %structA** @rdopt, align 4 - %luma_transform_size_8x8_flag264 = getelementptr inbounds %structA* %6, i32 0, i32 21 + %5 = load i32, i32* @luma_transform_size_8x8_flag, align 4 + %6 = load %structA*, %structA** @rdopt, align 4 + %luma_transform_size_8x8_flag264 = getelementptr inbounds %structA, %structA* %6, i32 0, i32 21 store i32 %5, i32* %luma_transform_size_8x8_flag264, align 4 - %7 = load i32* undef, align 4 + %7 = load i32, i32* undef, align 4 %add281 = add nsw i32 %7, 0 br label %for.body285 for.body285: ; preds = %for.inc503, %if.end249 %8 = phi %structB* [ undef, %if.end249 ], [ %.pre1155, %for.inc503 ] %i.21103 = phi i32 [ 0, %if.end249 ], [ %inc504, %for.inc503 ] - %block_x286 = getelementptr inbounds %structB* %8, i32 0, i32 37 - %9 = load i32* %block_x286, align 4 + %block_x286 = getelementptr inbounds %structB, %structB* %8, i32 0, i32 37 + %9 = load i32, i32* %block_x286, align 4 %add287 = add nsw i32 %9, %i.21103 %shr289 = ashr i32 %i.21103, 1 %add290 = add nsw i32 %shr289, 0 - %arrayidx292 = getelementptr inbounds %structK* %2, i32 %1, i32 15, i32 %add290 - %10 = load %structM** @enc_picture, align 4 - %ref_idx = getelementptr inbounds %structM* %10, i32 0, i32 35 - %11 = load i8**** %ref_idx, align 4 - %12 = load i8*** %11, align 4 - %arrayidx313 = getelementptr inbounds i8** %12, i32 %add281 - %13 = load i8** %arrayidx313, align 4 - %arrayidx314 = getelementptr inbounds i8* %13, i32 %add287 + %arrayidx292 = getelementptr inbounds %structK, %structK* %2, i32 %1, i32 15, i32 %add290 + %10 = load %structM*, %structM** @enc_picture, align 4 + %ref_idx = getelementptr inbounds %structM, %structM* %10, i32 0, i32 35 + %11 = load i8***, i8**** %ref_idx, align 4 + %12 = load i8**, i8*** %11, align 4 + %arrayidx313 = getelementptr inbounds i8*, i8** %12, i32 %add281 + %13 = load i8*, i8** %arrayidx313, align 4 + %arrayidx314 = getelementptr inbounds i8, i8* %13, i32 %add287 store i8 -1, i8* %arrayidx314, align 1 - %14 = load %structB** @img, align 4 - %MbaffFrameFlag327 = getelementptr inbounds %structB* %14, i32 0, i32 100 - %15 = load i32* %MbaffFrameFlag327, align 4 + %14 = load %structB*, %structB** @img, align 4 + %MbaffFrameFlag327 = getelementptr inbounds %structB, %structB* %14, i32 0, i32 100 + %15 = load i32, i32* %MbaffFrameFlag327, align 4 %tobool328 = icmp eq i32 %15, 0 br i1 %tobool328, label %if.end454, label %if.then329 if.then329: ; preds = %for.body285 - %16 = load %structA** @rdopt, align 4 + %16 = load %structA*, %structA** @rdopt, align 4 br label %if.end454 if.end454: ; preds = %if.then329, %for.body285 - %17 = load i32* %arrayidx292, align 4 + %17 = load i32, i32* %arrayidx292, align 4 %cmp457 = icmp eq i32 %17, 0 br i1 %cmp457, label %if.then475, label %lor.lhs.false459 lor.lhs.false459: ; preds = %if.end454 - %18 = load i32* %mb_type, align 4 + %18 = load i32, i32* %mb_type, align 4 switch i32 %18, label %for.inc503 [ i32 9, label %if.then475 - i32 10, label %if.then475 + i32 11, label %if.then475 i32 13, label %if.then475 i32 14, label %if.then475 ] @@ -205,7 +205,7 @@ if.then475: ; preds = %lor.lhs.false459, % for.inc503: ; preds = %if.then475, %lor.lhs.false459 %inc504 = add nsw i32 %i.21103, 1 - %.pre1155 = load %structB** @img, align 4 + %.pre1155 = load %structB*, %structB** @img, align 4 br label %for.body285 } diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll index 130925a0c237..d7b9b477ec1e 100644 --- a/test/CodeGen/ARM/struct_byval.ll +++ b/test/CodeGen/ARM/struct_byval.ll @@ -1,5 +1,9 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL +; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT + +; NOMOVT-NOT: movt ; rdar://9877866 %struct.SmallStruct = type { i32, [8 x i32], [37 x i8] } @@ -33,6 +37,14 @@ entry: ; THUMB: sub ; THUMB: str ; THUMB: bne +; NACL-LABEL: g: +; Ensure that use movw instead of constpool for the loop trip count. But don't +; match the __stack_chk_guard movw +; NACL: movw r{{[1-9]}}, # +; NACL: ldr +; NACL: sub +; NACL: str +; NACL: bne %st = alloca %struct.LargeStruct, align 4 %call = call i32 @e2(%struct.LargeStruct* byval %st) ret i32 0 @@ -51,6 +63,11 @@ entry: ; THUMB: sub ; THUMB: vst1 ; THUMB: bne +; NACL: movw r{{[1-9]}}, # +; NACL: vld1 +; NACL: sub +; NACL: vst1 +; NACL: bne %st = alloca %struct.LargeStruct, align 16 %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st) ret i32 0 @@ -80,7 +97,7 @@ define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize { ; THUMB-LABEL: f4 ; THUMB: blx _consumestruct entry: - %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0 + %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0 %0 = bitcast i32* %addr to i8* tail call void @consumestruct(i8* %0, i32 80) optsize ret void @@ -104,7 +121,7 @@ define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture b ; THUMB-LABEL: f6 ; THUMB: b.w _consumestruct entry: - %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0 + %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0 %0 = bitcast i32* %addr to i8* tail call void @consumestruct(i8* %0, i32 80) optsize ret void diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll index f7328dc580ef..32038883469b 100644 --- a/test/CodeGen/ARM/sub-cmp-peephole.ll +++ b/test/CodeGen/ARM/sub-cmp-peephole.ll @@ -169,7 +169,7 @@ entry: ; CHECK: sub ; CHECK: cmp ; CHECK: bge - %load = load i32* @t, align 4 + %load = load i32, i32* @t, align 4 %sub = sub i32 %load, 17 %cmp = icmp slt i32 %sub, 0 br i1 %cmp, label %if.then, label %if.else @@ -191,7 +191,7 @@ entry: ; CHECK: sub ; CHECK: cmp ; CHECK: bhs - %load = load i32* @t, align 4 + %load = load i32, i32* @t, align 4 %sub = sub i32 %load, 17 %cmp = icmp ult i32 %sub, 0 br i1 %cmp, label %if.then, label %if.else diff --git a/test/CodeGen/ARM/swift-atomics.ll b/test/CodeGen/ARM/swift-atomics.ll index 8b100f1f41f2..ca7e7fb299bf 100644 --- a/test/CodeGen/ARM/swift-atomics.ll +++ b/test/CodeGen/ARM/swift-atomics.ll @@ -33,7 +33,7 @@ define i32 @test_seq_cst(i32* %p, i32 %v) { ; CHECK-STRICT-ATOMIC: dmb {{ish$}} store atomic i32 %v, i32* %p seq_cst, align 4 - %val = load atomic i32* %p seq_cst, align 4 + %val = load atomic i32, i32* %p seq_cst, align 4 ret i32 %val } @@ -46,6 +46,6 @@ define i32 @test_acq(i32* %addr) { ; CHECK-STRICT-ATOMIC-LABEL: test_acq: ; CHECK-STRICT-ATOMIC: dmb {{ish$}} - %val = load atomic i32* %addr acquire, align 4 + %val = load atomic i32, i32* %addr acquire, align 4 ret i32 %val } diff --git a/test/CodeGen/ARM/swift-vldm.ll b/test/CodeGen/ARM/swift-vldm.ll index 67ae00ad7db8..9e507279fa09 100644 --- a/test/CodeGen/ARM/swift-vldm.ll +++ b/test/CodeGen/ARM/swift-vldm.ll @@ -12,14 +12,14 @@ declare fastcc void @force_register(double %d0, double %d1, double %d2, double % define void @test_vldm(double* %x, double * %y) { entry: - %addr1 = getelementptr double * %x, i32 1 - %addr2 = getelementptr double * %x, i32 2 - %addr3 = getelementptr double * %x, i32 3 - %d0 = load double * %y - %d1 = load double * %x - %d2 = load double * %addr1 - %d3 = load double * %addr2 - %d4 = load double * %addr3 + %addr1 = getelementptr double, double * %x, i32 1 + %addr2 = getelementptr double, double * %x, i32 2 + %addr3 = getelementptr double, double * %x, i32 3 + %d0 = load double , double * %y + %d1 = load double , double * %x + %d2 = load double , double * %addr1 + %d3 = load double , double * %addr2 + %d4 = load double , double * %addr3 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we ; don't form a "vldmia rX, {d1, d2, d3, d4}". ; We are relying on the calling convention and that register allocation diff --git a/test/CodeGen/ARM/t2abs-killflags.ll b/test/CodeGen/ARM/t2abs-killflags.ll new file mode 100644 index 000000000000..eed8f6719aec --- /dev/null +++ b/test/CodeGen/ARM/t2abs-killflags.ll @@ -0,0 +1,23 @@ +; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-unknown-unknown" + +; Test that we don't crash the machine verifier when expanding t2ABS. +; It was applying the kill flag to its source, even if the original t2ABS didn't +; kill the operand prior to pseudo expansion. + +; Function Attrs: noreturn +declare void @foo(i32, i32) #0 + +; CHECK-LABEL: @test +; CHECK: rsbmi +define void @test(i32 %arg) { + %cmp58 = icmp slt i32 %arg, 0 + %sub62 = sub nsw i32 0, %arg + %l.1 = select i1 %cmp58, i32 %sub62, i32 %arg + call void @foo(i32 %l.1, i32 %arg) #0 + unreachable +} + +attributes #0 = { noreturn } diff --git a/test/CodeGen/ARM/tail-dup-kill-flags.ll b/test/CodeGen/ARM/tail-dup-kill-flags.ll new file mode 100644 index 000000000000..bce6cdc4e28d --- /dev/null +++ b/test/CodeGen/ARM/tail-dup-kill-flags.ll @@ -0,0 +1,54 @@ +; RUN: llc %s -o - -fast-isel=true -O1 -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-apple-ios8.0.0" + +; Tail duplication was incorrectly leaving kill flags on the duplicated instructions. +; The machine verifier is able to spot this error, so this test should pass if it passes verification. + +; CHECK-LABEL: @test + +%struct.cdiff_ctx = type { i8*, %struct.cdiff_node*, %struct.cdiff_node*, %struct.cdiff_node*, %struct.cdiff_node* } +%struct.cdiff_node = type { i32, i8*, i8*, %struct.cdiff_node* } + +declare i32 @logg(i32) + +define hidden i32 @test(%struct.cdiff_ctx* nocapture %ctx, %struct.cdiff_node* %tmp10) { +bb: + br label %.outer + +bb33: ; preds = %bb92, %.outer + %lines.0 = phi i32 [ %tmp37, %bb92 ], [ %lines.0.ph, %.outer ] + %tmp37 = add i32 %lines.0, 1 + %tmp39 = load i32, i32* %tmp57, align 4 + %tmp40 = icmp eq i32 %tmp39, %tmp37 + br i1 %tmp40, label %bb41, label %bb92 + +bb41: ; preds = %bb33 + %tmp45 = call i32 @strncmp() + %tmp46 = icmp eq i32 %tmp45, 0 + br i1 %tmp46, label %bb53, label %bb47 + +bb47: ; preds = %bb41 + %tmp52 = call i32 @logg(i32 %tmp37) + ret i32 -1 + +bb53: ; preds = %bb41 + %tmp54 = getelementptr inbounds %struct.cdiff_node, %struct.cdiff_node* %del.0.ph, i32 0, i32 3 + %tmp55 = load %struct.cdiff_node*, %struct.cdiff_node** %tmp54, align 4 + br label %.outer + +.outer: ; preds = %bb53, %bb + %del.0.ph = phi %struct.cdiff_node* [ %tmp55, %bb53 ], [ null, %bb ] + %lines.0.ph = phi i32 [ 1, %bb53 ], [ 0, %bb ] + %tmp57 = getelementptr inbounds %struct.cdiff_node, %struct.cdiff_node* %del.0.ph, i32 0, i32 0 + br label %bb33 + +bb92: ; preds = %bb33 + %tmp93 = call i32 @puts() + br label %bb33 +} + +declare i32 @strncmp() + +declare i32 @puts() diff --git a/test/CodeGen/ARM/tail-dup.ll b/test/CodeGen/ARM/tail-dup.ll index d654056eaf3d..407bdf7524b1 100644 --- a/test/CodeGen/ARM/tail-dup.ll +++ b/test/CodeGen/ARM/tail-dup.ll @@ -11,28 +11,28 @@ define i32 @fn(i32* nocapture %opcodes) nounwind readonly ssp { entry: - %0 = load i32* %opcodes, align 4 - %arrayidx = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %0 + %0 = load i32, i32* %opcodes, align 4 + %arrayidx = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %0 br label %indirectgoto INCREMENT: ; preds = %indirectgoto %inc = add nsw i32 %result.0, 1 - %1 = load i32* %opcodes.addr.0, align 4 - %arrayidx2 = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %1 + %1 = load i32, i32* %opcodes.addr.0, align 4 + %arrayidx2 = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %1 br label %indirectgoto DECREMENT: ; preds = %indirectgoto %dec = add nsw i32 %result.0, -1 - %2 = load i32* %opcodes.addr.0, align 4 - %arrayidx4 = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %2 + %2 = load i32, i32* %opcodes.addr.0, align 4 + %arrayidx4 = getelementptr inbounds [3 x i8*], [3 x i8*]* @fn.codetable, i32 0, i32 %2 br label %indirectgoto indirectgoto: ; preds = %DECREMENT, %INCREMENT, %entry %result.0 = phi i32 [ 0, %entry ], [ %dec, %DECREMENT ], [ %inc, %INCREMENT ] %opcodes.pn = phi i32* [ %opcodes, %entry ], [ %opcodes.addr.0, %DECREMENT ], [ %opcodes.addr.0, %INCREMENT ] %indirect.goto.dest.in = phi i8** [ %arrayidx, %entry ], [ %arrayidx4, %DECREMENT ], [ %arrayidx2, %INCREMENT ] - %opcodes.addr.0 = getelementptr inbounds i32* %opcodes.pn, i32 1 - %indirect.goto.dest = load i8** %indirect.goto.dest.in, align 4 + %opcodes.addr.0 = getelementptr inbounds i32, i32* %opcodes.pn, i32 1 + %indirect.goto.dest = load i8*, i8** %indirect.goto.dest.in, align 4 indirectbr i8* %indirect.goto.dest, [label %RETURN, label %INCREMENT, label %DECREMENT] RETURN: ; preds = %indirectgoto diff --git a/test/CodeGen/ARM/test-sharedidx.ll b/test/CodeGen/ARM/test-sharedidx.ll index 9203f166ffa9..377996c4c3c8 100644 --- a/test/CodeGen/ARM/test-sharedidx.ll +++ b/test/CodeGen/ARM/test-sharedidx.ll @@ -23,15 +23,15 @@ for.body: ; preds = %entry, %for.body.3 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! %i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ] - %arrayidx = getelementptr inbounds i8* %a, i32 %i.09 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09 + %0 = load i8, i8* %arrayidx, align 1 %conv6 = zext i8 %0 to i32 - %arrayidx1 = getelementptr inbounds i8* %b, i32 %i.09 - %1 = load i8* %arrayidx1, align 1 + %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.09 + %1 = load i8, i8* %arrayidx1, align 1 %conv27 = zext i8 %1 to i32 %add = add nsw i32 %conv27, %conv6 %conv3 = trunc i32 %add to i8 - %arrayidx4 = getelementptr inbounds i8* %c, i32 %i.09 + %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.09 store i8 %conv3, i8* %arrayidx4, align 1 %add5 = add i32 %i.09, %s %cmp = icmp ult i32 %add5, %len @@ -44,15 +44,15 @@ for.body.1: ; preds = %for.body ; CHECK: %for.body.1 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! - %arrayidx.1 = getelementptr inbounds i8* %a, i32 %add5 - %2 = load i8* %arrayidx.1, align 1 + %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5 + %2 = load i8, i8* %arrayidx.1, align 1 %conv6.1 = zext i8 %2 to i32 - %arrayidx1.1 = getelementptr inbounds i8* %b, i32 %add5 - %3 = load i8* %arrayidx1.1, align 1 + %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %add5 + %3 = load i8, i8* %arrayidx1.1, align 1 %conv27.1 = zext i8 %3 to i32 %add.1 = add nsw i32 %conv27.1, %conv6.1 %conv3.1 = trunc i32 %add.1 to i8 - %arrayidx4.1 = getelementptr inbounds i8* %c, i32 %add5 + %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %add5 store i8 %conv3.1, i8* %arrayidx4.1, align 1 %add5.1 = add i32 %add5, %s %cmp.1 = icmp ult i32 %add5.1, %len @@ -62,15 +62,15 @@ for.body.2: ; preds = %for.body.1 ; CHECK: %for.body.2 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! - %arrayidx.2 = getelementptr inbounds i8* %a, i32 %add5.1 - %4 = load i8* %arrayidx.2, align 1 + %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1 + %4 = load i8, i8* %arrayidx.2, align 1 %conv6.2 = zext i8 %4 to i32 - %arrayidx1.2 = getelementptr inbounds i8* %b, i32 %add5.1 - %5 = load i8* %arrayidx1.2, align 1 + %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %add5.1 + %5 = load i8, i8* %arrayidx1.2, align 1 %conv27.2 = zext i8 %5 to i32 %add.2 = add nsw i32 %conv27.2, %conv6.2 %conv3.2 = trunc i32 %add.2 to i8 - %arrayidx4.2 = getelementptr inbounds i8* %c, i32 %add5.1 + %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %add5.1 store i8 %conv3.2, i8* %arrayidx4.2, align 1 %add5.2 = add i32 %add5.1, %s %cmp.2 = icmp ult i32 %add5.2, %len @@ -80,15 +80,15 @@ for.body.3: ; preds = %for.body.2 ; CHECK: %for.body.3 ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! - %arrayidx.3 = getelementptr inbounds i8* %a, i32 %add5.2 - %6 = load i8* %arrayidx.3, align 1 + %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2 + %6 = load i8, i8* %arrayidx.3, align 1 %conv6.3 = zext i8 %6 to i32 - %arrayidx1.3 = getelementptr inbounds i8* %b, i32 %add5.2 - %7 = load i8* %arrayidx1.3, align 1 + %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %add5.2 + %7 = load i8, i8* %arrayidx1.3, align 1 %conv27.3 = zext i8 %7 to i32 %add.3 = add nsw i32 %conv27.3, %conv6.3 %conv3.3 = trunc i32 %add.3 to i8 - %arrayidx4.3 = getelementptr inbounds i8* %c, i32 %add5.2 + %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %add5.2 store i8 %conv3.3, i8* %arrayidx4.3, align 1 %add5.3 = add i32 %add5.2, %s %cmp.3 = icmp ult i32 %add5.3, %len diff --git a/test/CodeGen/ARM/this-return.ll b/test/CodeGen/ARM/this-return.ll index c681a1c80958..802f880c1380 100644 --- a/test/CodeGen/ARM/this-return.ll +++ b/test/CodeGen/ARM/this-return.ll @@ -29,7 +29,7 @@ entry: ; CHECKT2D: b.w _B_ctor_base %0 = bitcast %struct.C* %this to %struct.A* %call = tail call %struct.A* @A_ctor_base(%struct.A* %0) - %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0 + %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0 %call2 = tail call %struct.B* @B_ctor_base(%struct.B* %1, i32 %x) ret %struct.C* %this } @@ -48,7 +48,7 @@ entry: ; CHECKT2D-NOT: b.w _B_ctor_base_nothisret %0 = bitcast %struct.C* %this to %struct.A* %call = tail call %struct.A* @A_ctor_base_nothisret(%struct.A* %0) - %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0 + %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0 %call2 = tail call %struct.B* @B_ctor_base_nothisret(%struct.B* %1, i32 %x) ret %struct.C* %this } @@ -85,7 +85,7 @@ entry: ; CHECKT2D: blx _B_ctor_complete ; CHECKT2D-NOT: mov r0, {{r[0-9]+}} ; CHECKT2D: b.w _B_ctor_complete - %b = getelementptr inbounds %struct.D* %this, i32 0, i32 0 + %b = getelementptr inbounds %struct.D, %struct.D* %this, i32 0, i32 0 %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) ret %struct.D* %this @@ -97,9 +97,9 @@ entry: ; CHECKELF-NOT: b B_ctor_complete ; CHECKT2D-LABEL: E_ctor_base: ; CHECKT2D-NOT: b.w _B_ctor_complete - %b = getelementptr inbounds %struct.E* %this, i32 0, i32 0 + %b = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 0 %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) - %b2 = getelementptr inbounds %struct.E* %this, i32 0, i32 1 + %b2 = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 1 %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b2, i32 %x) ret %struct.E* %this } diff --git a/test/CodeGen/ARM/thumb-alignment.ll b/test/CodeGen/ARM/thumb-alignment.ll new file mode 100644 index 000000000000..c11d4b6da3c9 --- /dev/null +++ b/test/CodeGen/ARM/thumb-alignment.ll @@ -0,0 +1,54 @@ +; RUN: llc -relocation-model=pic -mtriple=thumbv7-unknown-linux -o - %s | FileCheck %s + +@x = external global i32 + +; CHECK: .globl foo +; CHECK-NEXT: .align 2 +define i32* @foo() { + ret i32* @x +} + +; CHECK: .globl bar +; CHECK-NEXT: .align 1 +define i32* @bar() { + ret i32* zeroinitializer +} + +@a = external global i32 +@b = external global i32 +@c = external global i32 +@d = external global i32 + +; Create a Thumb-2 jump table, which should force alignment to 4 bytes. + +; CHECK: .globl baz +; CHECK-NEXT: .align 2 +; CHECK: adr.w +define i32 @baz() { + %1 = load i32, i32* @c, align 4 + switch i32 %1, label %7 [ + i32 1, label %2 + i32 4, label %5 + i32 9, label %5 + i32 3, label %8 + ] + +; <label>:2 + %3 = load i32, i32* @a, align 4 + %4 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32 (...)*, i32, i32)*)(i32 (...)* bitcast (i32 ()* @baz to i32 (...)*), i32 0, i32 %3) #2 + br label %8 + +; <label>:5 + %6 = load i32, i32* @d, align 4 + store i32 %6, i32* @b, align 4 + br label %8 + +; <label>:7 + br label %8 + +; <label>:8 + %e.0 = phi i32 [ 1, %7 ], [ 1, %2 ], [ 0, %0 ], [ 0, %5 ] + ret i32 %e.0 +} + +declare i32 @fn2(...) diff --git a/test/CodeGen/ARM/thumb-big-stack.ll b/test/CodeGen/ARM/thumb-big-stack.ll new file mode 100644 index 000000000000..e5cbb9747a7e --- /dev/null +++ b/test/CodeGen/ARM/thumb-big-stack.ll @@ -0,0 +1,6844 @@ +; RUN: llc %s -O0 -verify-machineinstrs -o - | FileCheck %s +; This file uses to trigger a machine verifier error because we +; were generating a stack adjustement with SP as second argument, +; which is unpredictable behavior for t2ADDrr. +; This file has been generated from the constpool test of the test-suite. +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios" + +@.str = external unnamed_addr constant [21 x i8], align 1 + +; CHECK-LABEL: f: +; CHECK: movw [[ADDR:(r[0-9]+|lr)]], # +; CHECK-NEXT: add [[ADDR]], sp +; CHECK-NEXT: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, {{\[}}[[ADDR]]:128] +define <4 x float> @f(<4 x float> %x) { +entry: + %.compoundliteral7837 = alloca <4 x float>, align 16 + %.compoundliteral7865 = alloca <4 x float>, align 16 + %.compoundliteral7991 = alloca <4 x float>, align 16 + %.compoundliteral8019 = alloca <4 x float>, align 16 + %.compoundliteral8061 = alloca <4 x float>, align 16 + %.compoundliteral8075 = alloca <4 x float>, align 16 + %.compoundliteral8089 = alloca <4 x float>, align 16 + %.compoundliteral8103 = alloca <4 x float>, align 16 + %.compoundliteral8117 = alloca <4 x float>, align 16 + %.compoundliteral8145 = alloca <4 x float>, align 16 + %.compoundliteral8243 = alloca <4 x float>, align 16 + %.compoundliteral8285 = alloca <4 x float>, align 16 + %.compoundliteral8299 = alloca <4 x float>, align 16 + %.compoundliteral8313 = alloca <4 x float>, align 16 + %.compoundliteral8327 = alloca <4 x float>, align 16 + %.compoundliteral9601 = alloca <4 x float>, align 16 + %.compoundliteral9615 = alloca <4 x float>, align 16 + %.compoundliteral9629 = alloca <4 x float>, align 16 + %.compoundliteral9657 = alloca <4 x float>, align 16 + %.compoundliteral9755 = alloca <4 x float>, align 16 + %.compoundliteral9769 = alloca <4 x float>, align 16 + %.compoundliteral9853 = alloca <4 x float>, align 16 + %.compoundliteral9867 = alloca <4 x float>, align 16 + %.compoundliteral9895 = alloca <4 x float>, align 16 + %.compoundliteral9909 = alloca <4 x float>, align 16 + %.compoundliteral9923 = alloca <4 x float>, align 16 + %.compoundliteral9937 = alloca <4 x float>, align 16 + %.compoundliteral9951 = alloca <4 x float>, align 16 + %.compoundliteral9979 = alloca <4 x float>, align 16 + %.compoundliteral10021 = alloca <4 x float>, align 16 + %.compoundliteral10049 = alloca <4 x float>, align 16 + %.compoundliteral10063 = alloca <4 x float>, align 16 + %.compoundliteral10077 = alloca <4 x float>, align 16 + %.compoundliteral10091 = alloca <4 x float>, align 16 + %.compoundliteral10119 = alloca <4 x float>, align 16 + %.compoundliteral10133 = alloca <4 x float>, align 16 + %.compoundliteral10147 = alloca <4 x float>, align 16 + %.compoundliteral10161 = alloca <4 x float>, align 16 + %.compoundliteral10203 = alloca <4 x float>, align 16 + %.compoundliteral10231 = alloca <4 x float>, align 16 + %.compoundliteral10385 = alloca <4 x float>, align 16 + %.compoundliteral10399 = alloca <4 x float>, align 16 + %.compoundliteral10413 = alloca <4 x float>, align 16 + %.compoundliteral10539 = alloca <4 x float>, align 16 + %.compoundliteral10553 = alloca <4 x float>, align 16 + %.compoundliteral10567 = alloca <4 x float>, align 16 + %.compoundliteral10581 = alloca <4 x float>, align 16 + %.compoundliteral10595 = alloca <4 x float>, align 16 + %.compoundliteral10609 = alloca <4 x float>, align 16 + %.compoundliteral10623 = alloca <4 x float>, align 16 + %.compoundliteral10637 = alloca <4 x float>, align 16 + %.compoundliteral10665 = alloca <4 x float>, align 16 + %.compoundliteral10693 = alloca <4 x float>, align 16 + %.compoundliteral10707 = alloca <4 x float>, align 16 + %.compoundliteral10721 = alloca <4 x float>, align 16 + %.compoundliteral10735 = alloca <4 x float>, align 16 + %.compoundliteral10749 = alloca <4 x float>, align 16 + %.compoundliteral10763 = alloca <4 x float>, align 16 + %.compoundliteral10945 = alloca <4 x float>, align 16 + %.compoundliteral10959 = alloca <4 x float>, align 16 + %.compoundliteral10987 = alloca <4 x float>, align 16 + %.compoundliteral11001 = alloca <4 x float>, align 16 + %.compoundliteral11015 = alloca <4 x float>, align 16 + %.compoundliteral11197 = alloca <4 x float>, align 16 + %.compoundliteral11421 = alloca <4 x float>, align 16 + %.compoundliteral11435 = alloca <4 x float>, align 16 + %.compoundliteral11463 = alloca <4 x float>, align 16 + %.compoundliteral11477 = alloca <4 x float>, align 16 + %.compoundliteral11491 = alloca <4 x float>, align 16 + %.compoundliteral11519 = alloca <4 x float>, align 16 + %.compoundliteral11533 = alloca <4 x float>, align 16 + %.compoundliteral11547 = alloca <4 x float>, align 16 + %.compoundliteral11631 = alloca <4 x float>, align 16 + %.compoundliteral11645 = alloca <4 x float>, align 16 + %.compoundliteral11659 = alloca <4 x float>, align 16 + %.compoundliteral11701 = alloca <4 x float>, align 16 + %.compoundliteral11743 = alloca <4 x float>, align 16 + %.compoundliteral11757 = alloca <4 x float>, align 16 + %.compoundliteral11771 = alloca <4 x float>, align 16 + %.compoundliteral11785 = alloca <4 x float>, align 16 + %.compoundliteral11799 = alloca <4 x float>, align 16 + %.compoundliteral11827 = alloca <4 x float>, align 16 + %.compoundliteral11841 = alloca <4 x float>, align 16 + %.compoundliteral11855 = alloca <4 x float>, align 16 + %.compoundliteral11869 = alloca <4 x float>, align 16 + %.compoundliteral11939 = alloca <4 x float>, align 16 + %.compoundliteral11953 = alloca <4 x float>, align 16 + %.compoundliteral11967 = alloca <4 x float>, align 16 + %.compoundliteral11981 = alloca <4 x float>, align 16 + %.compoundliteral11995 = alloca <4 x float>, align 16 + %.compoundliteral12023 = alloca <4 x float>, align 16 + %.compoundliteral12051 = alloca <4 x float>, align 16 + %.compoundliteral12065 = alloca <4 x float>, align 16 + %.compoundliteral12247 = alloca <4 x float>, align 16 + %.compoundliteral12261 = alloca <4 x float>, align 16 + %.compoundliteral12275 = alloca <4 x float>, align 16 + %.compoundliteral12499 = alloca <4 x float>, align 16 + %.compoundliteral12541 = alloca <4 x float>, align 16 + %.compoundliteral12555 = alloca <4 x float>, align 16 + %.compoundliteral12751 = alloca <4 x float>, align 16 + %.compoundliteral12891 = alloca <4 x float>, align 16 + %.compoundliteral12905 = alloca <4 x float>, align 16 + %.compoundliteral12919 = alloca <4 x float>, align 16 + %.compoundliteral12933 = alloca <4 x float>, align 16 + %.compoundliteral12947 = alloca <4 x float>, align 16 + %.compoundliteral12961 = alloca <4 x float>, align 16 + %.compoundliteral12975 = alloca <4 x float>, align 16 + %.compoundliteral12989 = alloca <4 x float>, align 16 + %.compoundliteral13003 = alloca <4 x float>, align 16 + %.compoundliteral13017 = alloca <4 x float>, align 16 + %.compoundliteral13031 = alloca <4 x float>, align 16 + %.compoundliteral13423 = alloca <4 x float>, align 16 + %.compoundliteral13437 = alloca <4 x float>, align 16 + %.compoundliteral13493 = alloca <4 x float>, align 16 + %.compoundliteral13535 = alloca <4 x float>, align 16 + %.compoundliteral13549 = alloca <4 x float>, align 16 + %.compoundliteral13647 = alloca <4 x float>, align 16 + %.compoundliteral13675 = alloca <4 x float>, align 16 + %.compoundliteral13689 = alloca <4 x float>, align 16 + %.compoundliteral13703 = alloca <4 x float>, align 16 + %.compoundliteral13717 = alloca <4 x float>, align 16 + %.compoundliteral13745 = alloca <4 x float>, align 16 + %.compoundliteral13759 = alloca <4 x float>, align 16 + %.compoundliteral13773 = alloca <4 x float>, align 16 + %.compoundliteral13787 = alloca <4 x float>, align 16 + %.compoundliteral13941 = alloca <4 x float>, align 16 + %.compoundliteral13969 = alloca <4 x float>, align 16 + %.compoundliteral13983 = alloca <4 x float>, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40746999A0000000, float 0xC0719B3340000000, float 0xC070B66660000000, float 0xC07404CCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40701B3340000000, float 0x405B866660000000, float 0xC0763999A0000000, float 4.895000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp1 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add68 = fadd <4 x float> %tmp1, %tmp + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add68, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp2 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add76 = fadd float undef, 0x4074C999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp3 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins77 = insertelement <4 x float> %tmp3, float %add76, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins77, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp4 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext78 = extractelement <4 x float> %tmp4, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add79 = fadd float %vecext78, 0x40776E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp5 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins80 = insertelement <4 x float> %tmp5, float %add79, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins80, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40678CCCC0000000, float 0xC03E4CCCC0000000, float -4.170000e+02, float -1.220000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp6 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add82 = fadd <4 x float> undef, %tmp6 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add82, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp7 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext83 = extractelement <4 x float> %tmp7, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add84 = fadd float %vecext83, 1.300000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp8 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins85 = insertelement <4 x float> %tmp8, float %add84, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins85, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp9 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext86 = extractelement <4 x float> %tmp9, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add93 = fadd float undef, 0xC076C66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp10 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins94 = insertelement <4 x float> %tmp10, float %add93, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x406C2999A0000000, float 8.050000e+01, float 0xC0794999A0000000, float 0xC073E4CCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp11 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp12 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add96 = fadd <4 x float> %tmp12, %tmp11 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp13 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext97 = extractelement <4 x float> %tmp13, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add98 = fadd float %vecext97, 0x4079E66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp14 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins102 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins102, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp15 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add104 = fadd float undef, 0x406AB999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp16 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC0531999A0000000, float 0xC0737999A0000000, float 0x407CB33340000000, float 0xC06DCCCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext579 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add580 = fadd float %vecext579, 0xC07424CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp17 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins581 = insertelement <4 x float> %tmp17, float %add580, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins581, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp18 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext582 = extractelement <4 x float> %tmp18, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add583 = fadd float %vecext582, 0x40444CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp19 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext590 = extractelement <4 x float> %tmp19, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add591 = fadd float %vecext590, 1.725000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins592 = insertelement <4 x float> undef, float %add591, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins592, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp20 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add594 = fadd float undef, 0xC05B466660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add605 = fadd float undef, 0x407164CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp21 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add616 = fadd float undef, 1.885000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp22 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp23 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins620 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins620, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext621 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add622 = fadd float %vecext621, 0x40709B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins623 = insertelement <4 x float> undef, float %add622, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins623, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp24 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext624 = extractelement <4 x float> %tmp24, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add625 = fadd float %vecext624, 0xC064033340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp25 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins626 = insertelement <4 x float> %tmp25, float %add625, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins626, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x404D0CCCC0000000, float 3.955000e+02, float 0xC0334CCCC0000000, float 0x40754E6660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp26 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp27 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add628 = fadd <4 x float> %tmp27, %tmp26 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add628, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp28 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext629 = extractelement <4 x float> %tmp28, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add630 = fadd float %vecext629, 0x40730CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp29 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins631 = insertelement <4 x float> %tmp29, float %add630, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins631, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp30 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext632 = extractelement <4 x float> %tmp30, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add633 = fadd float %vecext632, 0xC0630999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp31 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins634 = insertelement <4 x float> %tmp31, float %add633, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins634, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp32 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext635 = extractelement <4 x float> %tmp32, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add636 = fadd float %vecext635, 0xC078833340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp33 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp34 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp35 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add658 = fadd float undef, 0xC04A4CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext663 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp36 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins665 = insertelement <4 x float> %tmp36, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext694 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add695 = fadd float %vecext694, 0xC03CCCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp37 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins696 = insertelement <4 x float> %tmp37, float %add695, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins696, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC069FCCCC0000000, float 0xC07C6E6660000000, float 0x4067E33340000000, float 0x4078DB3340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp38 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext699 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add703 = fadd float undef, 0x4068F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins704 = insertelement <4 x float> undef, float %add703, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins704, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp39 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp40 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins710 = insertelement <4 x float> %tmp40, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins710, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC05D9999A0000000, float 0x405D6CCCC0000000, float 0x40765CCCC0000000, float 0xC07C64CCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp41 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp42 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add712 = fadd <4 x float> %tmp42, %tmp41 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add712, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp43 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext713 = extractelement <4 x float> %tmp43, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp44 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins715 = insertelement <4 x float> %tmp44, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp45 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext716 = extractelement <4 x float> %tmp45, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add717 = fadd float %vecext716, -4.315000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp46 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins718 = insertelement <4 x float> %tmp46, float %add717, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins718, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp47 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext719 = extractelement <4 x float> %tmp47, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add723 = fadd float undef, 0xC06A6CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins724 = insertelement <4 x float> undef, float %add723, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add726 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext730 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add731 = fadd float %vecext730, 0xC0759CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp48 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins732 = insertelement <4 x float> %tmp48, float %add731, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins732, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp49 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext733 = extractelement <4 x float> %tmp49, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp50 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins738 = insertelement <4 x float> %tmp50, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x406E6CCCC0000000, float 0xC07A766660000000, float 0xC0608CCCC0000000, float 0xC063333340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp51 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add740 = fadd <4 x float> undef, %tmp51 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp52 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext741 = extractelement <4 x float> %tmp52, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add742 = fadd float %vecext741, 0xC07984CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp53 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins743 = insertelement <4 x float> %tmp53, float %add742, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins743, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp54 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp55 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add754 = fadd <4 x float> %tmp55, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add754, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp56 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext755 = extractelement <4 x float> %tmp56, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add756 = fadd float %vecext755, 0xC070ACCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp57 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins757 = insertelement <4 x float> %tmp57, float %add756, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add765 = fadd float undef, 0x405BA66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp58 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins766 = insertelement <4 x float> %tmp58, float %add765, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp59 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext769 = extractelement <4 x float> %tmp59, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add770 = fadd float %vecext769, 0x40797199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp60 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins771 = insertelement <4 x float> %tmp60, float %add770, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins771, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp61 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add776 = fadd float undef, 0xC055F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins777 = insertelement <4 x float> undef, float %add776, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp62 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp63 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add782 = fadd <4 x float> %tmp63, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add782, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp64 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext783 = extractelement <4 x float> %tmp64, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add784 = fadd float %vecext783, -3.455000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07A866660000000, float 0xC05CF999A0000000, float 0xC0757199A0000000, float -3.845000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add796 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add796, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp65 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add801 = fadd float undef, 3.045000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp66 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins802 = insertelement <4 x float> %tmp66, float %add801, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins802, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext803 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp67 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp68 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add810 = fadd <4 x float> undef, %tmp68 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add810, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp69 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext811 = extractelement <4 x float> %tmp69, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp70 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins813 = insertelement <4 x float> %tmp70, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext817 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add818 = fadd float %vecext817, -4.830000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins822 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins822, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 2.700000e+01, float 0xC05F666660000000, float 0xC07D0199A0000000, float 0x407A6CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp71 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp72 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add824 = fadd <4 x float> %tmp72, %tmp71 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add838 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add838, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp73 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext839 = extractelement <4 x float> %tmp73, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add849 = fadd float undef, 0xC07C266660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07D566660000000, float 0xC06D233340000000, float 0x4068B33340000000, float 0xC07ADCCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp74 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add852 = fadd <4 x float> %tmp74, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext856 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add857 = fadd float %vecext856, 0xC070666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp75 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp76 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext859 = extractelement <4 x float> %tmp76, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add860 = fadd float %vecext859, 4.705000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp77 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins861 = insertelement <4 x float> %tmp77, float %add860, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins889 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins889, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp78 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext890 = extractelement <4 x float> %tmp78, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add891 = fadd float %vecext890, 0xC070633340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp79 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins892 = insertelement <4 x float> %tmp79, float %add891, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins892, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4063D33340000000, float 0xC076433340000000, float 0x407C966660000000, float 0xC07B5199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp80 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp81 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add894 = fadd <4 x float> %tmp81, %tmp80 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add894, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext895 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add896 = fadd float %vecext895, 0xC070F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins897 = insertelement <4 x float> undef, float %add896, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp82 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext898 = extractelement <4 x float> %tmp82, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add899 = fadd float %vecext898, 0xC076F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins900 = insertelement <4 x float> undef, float %add899, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp83 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext901 = extractelement <4 x float> %tmp83, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add902 = fadd float %vecext901, 0xC054ECCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp84 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins903 = insertelement <4 x float> %tmp84, float %add902, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins903, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext904 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add905 = fadd float %vecext904, 0x4056A66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp85 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins906 = insertelement <4 x float> %tmp85, float %add905, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07EFCCCC0000000, float 1.795000e+02, float 0x407E3E6660000000, float 0x4070633340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp86 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp87 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add908 = fadd <4 x float> %tmp87, %tmp86 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add908, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp88 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp89 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp90 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext912 = extractelement <4 x float> %tmp90, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add913 = fadd float %vecext912, 2.575000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins914 = insertelement <4 x float> undef, float %add913, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp91 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext915 = extractelement <4 x float> %tmp91, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add916 = fadd float %vecext915, -3.115000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp92 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins917 = insertelement <4 x float> %tmp92, float %add916, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins917, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp93 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext918 = extractelement <4 x float> %tmp93, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add919 = fadd float %vecext918, 2.950000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp94 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins920 = insertelement <4 x float> %tmp94, float %add919, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins920, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp95 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins925 = insertelement <4 x float> %tmp95, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins925, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp96 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add927 = fadd float undef, 0xC0501999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp97 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins928 = insertelement <4 x float> %tmp97, float %add927, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext929 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add930 = fadd float %vecext929, 0xC07C8B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp98 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins931 = insertelement <4 x float> %tmp98, float %add930, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC047B33340000000, float 0x404ACCCCC0000000, float 0x40708E6660000000, float 0x4060F999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp99 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp100 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext937 = extractelement <4 x float> %tmp100, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add941 = fadd float undef, -4.665000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins942 = insertelement <4 x float> undef, float %add941, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins942, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp101 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext943 = extractelement <4 x float> %tmp101, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add944 = fadd float %vecext943, 4.580000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp102 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins945 = insertelement <4 x float> %tmp102, float %add944, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins945, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp103 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add947 = fadd float undef, 0xC051933340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp104 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins948 = insertelement <4 x float> %tmp104, float %add947, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins948, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4060CCCCC0000000, float 0xC07BAB3340000000, float 0xC061233340000000, float 0xC076C199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp105 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add955 = fadd float undef, 0x4077F4CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp106 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins956 = insertelement <4 x float> %tmp106, float %add955, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins956, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext971 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add972 = fadd float %vecext971, 0x4024333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp107 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins973 = insertelement <4 x float> %tmp107, float %add972, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins973, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp108 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext974 = extractelement <4 x float> %tmp108, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins976 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins976, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x407E266660000000, float -1.225000e+02, float 0x407EB199A0000000, float 0x407BA199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp109 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp110 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add978 = fadd <4 x float> %tmp110, %tmp109 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp111 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp112 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext982 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add983 = fadd float %vecext982, 0x407E1B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins984 = insertelement <4 x float> undef, float %add983, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins984, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp113 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext985 = extractelement <4 x float> %tmp113, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add986 = fadd float %vecext985, 0x406C8CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp114 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins987 = insertelement <4 x float> %tmp114, float %add986, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins987, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp115 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp116 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins995 = insertelement <4 x float> %tmp116, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins995, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp117 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add997 = fadd float undef, 0xC0798999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp118 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins998 = insertelement <4 x float> %tmp118, float %add997, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins998, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp119 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1013 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1014 = fadd float %vecext1013, 3.105000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp120 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp121 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1016 = extractelement <4 x float> %tmp121, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1017 = fadd float %vecext1016, 0x406A1999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp122 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1030 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1031 = fadd float %vecext1030, 2.010000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp123 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp124 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1085 = insertelement <4 x float> %tmp124, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp125 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1086 = extractelement <4 x float> %tmp125, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1087 = fadd float %vecext1086, -1.575000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp126 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1088 = insertelement <4 x float> %tmp126, float %add1087, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1088, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp127 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1090 = fadd <4 x float> undef, %tmp127 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp128 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1094 = extractelement <4 x float> %tmp128, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1095 = fadd float %vecext1094, 0x4072C999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp129 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1096 = insertelement <4 x float> %tmp129, float %add1095, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1096, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp130 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1097 = extractelement <4 x float> %tmp130, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1098 = fadd float %vecext1097, 0xC073E999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp131 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1099 = insertelement <4 x float> %tmp131, float %add1098, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1099, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp132 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1100 = extractelement <4 x float> %tmp132, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1101 = fadd float %vecext1100, 2.885000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp133 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1102 = insertelement <4 x float> %tmp133, float %add1101, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1102, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4059866660000000, float 0x4072466660000000, float 0xC078FE6660000000, float 0xC058ACCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp134 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1104 = fadd <4 x float> undef, %tmp134 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp135 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1105 = extractelement <4 x float> %tmp135, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1106 = fadd float %vecext1105, 0xC078A999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp136 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1107 = insertelement <4 x float> %tmp136, float %add1106, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1108 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp137 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1110 = insertelement <4 x float> %tmp137, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1110, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp138 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1111 = extractelement <4 x float> %tmp138, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1112 = fadd float %vecext1111, 0x407D566660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp139 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1113 = insertelement <4 x float> %tmp139, float %add1112, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1113, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1115 = fadd float undef, 0x4072B33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1116 = insertelement <4 x float> undef, float %add1115, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1116, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC0721999A0000000, float 0x4075633340000000, float 0x40794199A0000000, float 0x4061066660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp140 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1118 = fadd <4 x float> %tmp140, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1118, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp141 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1119 = extractelement <4 x float> %tmp141, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1120 = fadd float %vecext1119, 0xC065A66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1121 = insertelement <4 x float> undef, float %add1120, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1121, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp142 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1122 = extractelement <4 x float> %tmp142, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1123 = fadd float %vecext1122, 0x4072533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp143 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1124 = insertelement <4 x float> %tmp143, float %add1123, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1125 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1127 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1127, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp144 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1128 = extractelement <4 x float> %tmp144, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1129 = fadd float %vecext1128, 0x405C866660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp145 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1130 = insertelement <4 x float> %tmp145, float %add1129, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC06D6CCCC0000000, float 0xC032E66660000000, float -1.005000e+02, float 0x40765B3340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp146 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp147 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1132 = fadd <4 x float> %tmp147, %tmp146 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp148 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1133 = extractelement <4 x float> %tmp148, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1134 = fadd float %vecext1133, 0xC07EB999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp149 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1135 = insertelement <4 x float> %tmp149, float %add1134, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1135, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp150 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1136 = extractelement <4 x float> %tmp150, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp151 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1138 = insertelement <4 x float> %tmp151, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1138, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp152 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1140 = fadd float undef, 0x407AE999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp153 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1141 = insertelement <4 x float> %tmp153, float %add1140, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1142 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1143 = fadd float %vecext1142, 0x407A24CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp154 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1144 = insertelement <4 x float> %tmp154, float %add1143, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1144, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp155 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp156 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1146 = fadd <4 x float> %tmp156, %tmp155 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1146, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp157 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1148 = fadd float undef, 4.145000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp158 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1158 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1158, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40603999A0000000, float -9.150000e+01, float 0xC051E66660000000, float -4.825000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1218 = fadd float undef, 0xC078733340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1219 = insertelement <4 x float> undef, float %add1218, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC0655CCCC0000000, float -4.900000e+01, float -4.525000e+02, float 4.205000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp159 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1279 = extractelement <4 x float> %tmp159, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1280 = fadd float %vecext1279, 0xC062D999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp160 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1281 = insertelement <4 x float> %tmp160, float %add1280, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1281, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp161 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1282 = extractelement <4 x float> %tmp161, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1283 = fadd float %vecext1282, 4.365000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp162 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1284 = insertelement <4 x float> %tmp162, float %add1283, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1284, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp163 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp164 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1286 = fadd <4 x float> %tmp164, %tmp163 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1286, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp165 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1288 = fadd float undef, 0xC0731199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp166 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp167 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1444 = extractelement <4 x float> %tmp167, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1460 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1460, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp168 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1462 = fadd float undef, -1.670000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1463 = insertelement <4 x float> undef, float %add1462, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp169 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1464 = extractelement <4 x float> %tmp169, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1465 = fadd float %vecext1464, 0xC066333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp170 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1466 = insertelement <4 x float> %tmp170, float %add1465, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1466, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 3.885000e+02, float 0x4054266660000000, float -9.500000e+01, float 8.500000e+01>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp171 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp172 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1468 = fadd <4 x float> %tmp172, %tmp171 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1468, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp173 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1470 = fadd float undef, 0x4033B33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp174 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1471 = insertelement <4 x float> %tmp174, float %add1470, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1471, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp175 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1472 = extractelement <4 x float> %tmp175, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1473 = fadd float %vecext1472, 0xC05F666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp176 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1474 = insertelement <4 x float> %tmp176, float %add1473, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp177 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1475 = extractelement <4 x float> %tmp177, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp178 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1477 = insertelement <4 x float> %tmp178, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1477, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp179 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1478 = extractelement <4 x float> %tmp179, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1479 = fadd float %vecext1478, 0x407E2E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp180 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1480 = insertelement <4 x float> %tmp180, float %add1479, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1480, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC061B33340000000, float 3.290000e+02, float 0xC067766660000000, float 0x407DB33340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp181 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp182 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp183 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1483 = extractelement <4 x float> %tmp183, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1484 = fadd float %vecext1483, 0xC053D999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp184 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp185 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1486 = extractelement <4 x float> %tmp185, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1502 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1502, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1503 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1504 = fadd float %vecext1503, -2.475000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp186 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1505 = insertelement <4 x float> %tmp186, float %add1504, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1505, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp187 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1506 = extractelement <4 x float> %tmp187, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1507 = fadd float %vecext1506, 0x40715199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp188 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1508 = insertelement <4 x float> %tmp188, float %add1507, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1508, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40762B3340000000, float 0xC074566660000000, float 0xC07C74CCC0000000, float 0xC053F999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp189 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp190 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1510 = fadd <4 x float> %tmp190, %tmp189 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1510, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp191 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp192 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1654 = extractelement <4 x float> %tmp192, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1655 = fadd float %vecext1654, 0xC07D8CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp193 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1656 = insertelement <4 x float> %tmp193, float %add1655, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1656, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1658 = fadd float undef, 0x40709999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp194 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1660 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1661 = fadd float %vecext1660, 0xC06F166660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp195 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1662 = insertelement <4 x float> %tmp195, float %add1661, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1662, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC075266660000000, float 0xC072C4CCC0000000, float 0x407C4E6660000000, float -4.485000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1676 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp196 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1692 = fadd <4 x float> %tmp196, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1692, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp197 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1693 = extractelement <4 x float> %tmp197, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1694 = fadd float %vecext1693, 0x407A1999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp198 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1695 = insertelement <4 x float> %tmp198, float %add1694, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1695, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp199 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1696 = extractelement <4 x float> %tmp199, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1697 = fadd float %vecext1696, 2.850000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp200 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1698 = insertelement <4 x float> %tmp200, float %add1697, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1698, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp201 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1699 = extractelement <4 x float> %tmp201, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp202 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1701 = insertelement <4 x float> %tmp202, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1701, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp203 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1704 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC075933340000000, float 0xC0489999A0000000, float 0xC078AB3340000000, float 0x406DFCCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp204 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp205 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp206 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1709 = insertelement <4 x float> %tmp206, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1709, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp207 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1713 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1714 = fadd float %vecext1713, 0xC0703199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1723 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp208 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1730 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1731 = fadd float %vecext1730, 4.130000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp209 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1732 = insertelement <4 x float> %tmp209, float %add1731, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1732, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40551999A0000000, float 0xC0708999A0000000, float 0xC054F33340000000, float 0xC07C5999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp210 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1734 = fadd <4 x float> undef, %tmp210 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp211 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1736 = fadd float undef, 0x407C3999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp212 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1737 = insertelement <4 x float> %tmp212, float %add1736, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp213 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1738 = extractelement <4 x float> %tmp213, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1739 = fadd float %vecext1738, 0xC0711E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp214 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1740 = insertelement <4 x float> %tmp214, float %add1739, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1740, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp215 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1741 = extractelement <4 x float> %tmp215, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1742 = fadd float %vecext1741, -2.545000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp216 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1743 = insertelement <4 x float> %tmp216, float %add1742, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1743, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1744 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp217 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1746 = insertelement <4 x float> %tmp217, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC076466660000000, float 0x4060BCCCC0000000, float 0x405EF999A0000000, float 0x4074766660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp218 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1748 = fadd <4 x float> undef, %tmp218 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1748, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp219 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1750 = fadd float undef, 0x407C6B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1751 = insertelement <4 x float> undef, float %add1750, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp220 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1752 = extractelement <4 x float> %tmp220, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1753 = fadd float %vecext1752, 0x40730CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp221 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1754 = insertelement <4 x float> %tmp221, float %add1753, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp222 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1755 = extractelement <4 x float> %tmp222, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1756 = fadd float %vecext1755, 0xC059F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp223 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1759 = fadd float undef, 0x40678999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp224 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1760 = insertelement <4 x float> %tmp224, float %add1759, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1760, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x405E333340000000, float 0x40571999A0000000, float 0xC02E333340000000, float 0x4053A66660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp225 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1762 = fadd <4 x float> undef, %tmp225 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1762, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp226 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1763 = extractelement <4 x float> %tmp226, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1764 = fadd float %vecext1763, 0xC0299999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp227 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1765 = insertelement <4 x float> %tmp227, float %add1764, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1765, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp228 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1766 = extractelement <4 x float> %tmp228, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1767 = fadd float %vecext1766, 0x407DDE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp229 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1768 = insertelement <4 x float> %tmp229, float %add1767, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1768, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1769 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1770 = fadd float %vecext1769, 0x407A1B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp230 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1771 = insertelement <4 x float> %tmp230, float %add1770, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1771, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp231 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp232 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp233 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp234 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1779 = insertelement <4 x float> %tmp234, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1779, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp235 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp236 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1783 = extractelement <4 x float> %tmp236, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1784 = fadd float %vecext1783, 0x405E933340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1785 = insertelement <4 x float> undef, float %add1784, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1785, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07074CCC0000000, float 0xC04D666660000000, float 3.235000e+02, float 0xC0724199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp237 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1790 = fadd <4 x float> undef, %tmp237 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp238 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1791 = extractelement <4 x float> %tmp238, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1792 = fadd float %vecext1791, 0x4077DE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp239 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1793 = insertelement <4 x float> %tmp239, float %add1792, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1793, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp240 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1795 = fadd float undef, 0x4055266660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp241 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1796 = insertelement <4 x float> %tmp241, float %add1795, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1799 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1800 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp242 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -6.600000e+01, float 0xC07B2199A0000000, float 0x4011333340000000, float 0xC0635CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp243 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp244 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp245 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp246 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1865 = fadd float undef, -2.235000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp247 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1866 = insertelement <4 x float> %tmp247, float %add1865, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp248 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp249 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1872 = insertelement <4 x float> %tmp249, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x406B8999A0000000, float 0xC0696CCCC0000000, float 0xC07A34CCC0000000, float 0x407654CCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp250 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1874 = fadd <4 x float> %tmp250, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1874, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1875 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp251 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1894 = insertelement <4 x float> %tmp251, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp252 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1895 = extractelement <4 x float> %tmp252, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1900 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1900, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1905 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1905, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp253 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1906 = extractelement <4 x float> %tmp253, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1907 = fadd float %vecext1906, 0xC07E5E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1908 = insertelement <4 x float> undef, float %add1907, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1908, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1909 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp254 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1912 = extractelement <4 x float> %tmp254, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1913 = fadd float %vecext1912, 0xC063ECCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp255 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp256 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1916 = fadd <4 x float> %tmp256, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add1916, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1923 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp257 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1927 = fadd float undef, 0x40761999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp258 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1928 = insertelement <4 x float> %tmp258, float %add1927, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1928, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 7.100000e+01, float 0xC0634999A0000000, float 0x407B0B3340000000, float 0xC07DE999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp259 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp260 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1930 = fadd <4 x float> %tmp260, %tmp259 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp261 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp262 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1933 = insertelement <4 x float> %tmp262, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1933, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp263 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1934 = extractelement <4 x float> %tmp263, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1935 = fadd float %vecext1934, 0xC07D3199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp264 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1936 = insertelement <4 x float> %tmp264, float %add1935, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1940 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1942 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -8.200000e+01, float 0xC04C733340000000, float 0xC077ACCCC0000000, float 0x4074566660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp265 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp266 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp267 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1945 = extractelement <4 x float> %tmp267, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1946 = fadd float %vecext1945, 0xC074866660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1953 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1953, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp268 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp269 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp270 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1958 = fadd <4 x float> %tmp270, %tmp269 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp271 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1959 = extractelement <4 x float> %tmp271, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1960 = fadd float %vecext1959, 0x4065ACCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1962 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1963 = fadd float %vecext1962, 0xC07134CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp272 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1964 = insertelement <4 x float> %tmp272, float %add1963, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1964, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1965 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp273 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1967 = insertelement <4 x float> %tmp273, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1967, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp274 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1968 = extractelement <4 x float> %tmp274, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1969 = fadd float %vecext1968, 7.100000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp275 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1970 = insertelement <4 x float> %tmp275, float %add1969, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1970, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x402E9999A0000000, float 0x407344CCC0000000, float -4.165000e+02, float 0x4078FCCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp276 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp277 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp278 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1975 = insertelement <4 x float> %tmp278, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1975, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp279 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1976 = extractelement <4 x float> %tmp279, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1978 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1978, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1979 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1981 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1981, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1984 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1984, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC06A766660000000, float 0xC07CE4CCC0000000, float -1.055000e+02, float 0x40786E6660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1990 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext1996 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add1997 = fadd float %vecext1996, -1.400000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp280 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins1998 = insertelement <4 x float> %tmp280, float %add1997, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins1998, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC0794E6660000000, float 0xC073CCCCC0000000, float 0x407994CCC0000000, float 6.500000e+01>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2004 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2005 = fadd float %vecext2004, -1.970000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp281 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2006 = insertelement <4 x float> %tmp281, float %add2005, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2006, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp282 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2007 = extractelement <4 x float> %tmp282, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp283 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2009 = insertelement <4 x float> %tmp283, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp284 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2010 = extractelement <4 x float> %tmp284, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2011 = fadd float %vecext2010, 0xC074533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp285 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2012 = insertelement <4 x float> %tmp285, float %add2011, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2012, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC04E733340000000, float 0xC074566660000000, float 0x4079F66660000000, float 0xC0705B3340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp286 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp287 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp288 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2015 = extractelement <4 x float> %tmp288, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2016 = fadd float %vecext2015, 0xC060633340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp289 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2017 = insertelement <4 x float> %tmp289, float %add2016, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2022 = fadd float undef, 8.350000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp290 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2023 = insertelement <4 x float> %tmp290, float %add2022, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp291 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2024 = extractelement <4 x float> %tmp291, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp292 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2028 = fadd <4 x float> %tmp292, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add2028, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2029 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2030 = fadd float %vecext2029, -9.450000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp293 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp294 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2036 = fadd float undef, 0x407DE66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp295 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp296 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp297 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp298 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp299 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2045 = insertelement <4 x float> %tmp299, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2045, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp300 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2046 = extractelement <4 x float> %tmp300, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2047 = fadd float %vecext2046, 0xC065433340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2052 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp301 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2054 = insertelement <4 x float> %tmp301, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2054, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4024666660000000, float 0x4079366660000000, float 0x40721B3340000000, float 0x406E533340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp302 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2056 = fadd <4 x float> undef, %tmp302 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add2056, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp303 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp304 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2062 = insertelement <4 x float> %tmp304, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2062, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp305 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp306 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2066 = extractelement <4 x float> %tmp306, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2067 = fadd float %vecext2066, 0x40690999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2068 = insertelement <4 x float> undef, float %add2067, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2068, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07EFCCCC0000000, float -3.420000e+02, float 0xC07BC999A0000000, float 0x40751999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp307 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp308 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2070 = fadd <4 x float> %tmp308, %tmp307 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add2070, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp309 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2071 = extractelement <4 x float> %tmp309, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2072 = fadd float %vecext2071, 0x4057733340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp310 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2073 = insertelement <4 x float> %tmp310, float %add2072, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2073, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp311 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2074 = extractelement <4 x float> %tmp311, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp312 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2076 = insertelement <4 x float> %tmp312, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp313 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2077 = extractelement <4 x float> %tmp313, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2078 = fadd float %vecext2077, 0x4061F999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp314 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2079 = insertelement <4 x float> %tmp314, float %add2078, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2079, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp315 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2080 = extractelement <4 x float> %tmp315, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2081 = fadd float %vecext2080, 0x407A1B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp316 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2082 = insertelement <4 x float> %tmp316, float %add2081, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2082, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40764E6660000000, float 0x40501999A0000000, float 0xC079A4CCC0000000, float 0x4050533340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp317 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp318 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp319 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2085 = extractelement <4 x float> %tmp319, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2086 = fadd float %vecext2085, 0x406E666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2087 = insertelement <4 x float> undef, float %add2086, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2087, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2480 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2481 = fadd float %vecext2480, 0x4039666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2483 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2484 = fadd float %vecext2483, 0xC06A3999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp320 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2485 = insertelement <4 x float> %tmp320, float %add2484, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2485, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp321 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2487 = fadd float undef, 2.030000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp322 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4073DE6660000000, float 0x4067CCCCC0000000, float 0xC03F1999A0000000, float 4.350000e+01>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2491 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp323 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp324 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2494 = extractelement <4 x float> %tmp324, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2495 = fadd float %vecext2494, 0xC0743CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp325 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2499 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2499, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2500 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2501 = fadd float %vecext2500, 0x40796E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp326 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp327 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2508 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2518 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp328 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2519 = extractelement <4 x float> %tmp328, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2520 = fadd float %vecext2519, 0xC0399999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp329 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2534 = fadd float undef, 0x4072C66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2536 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2537 = fadd float %vecext2536, 0x407D066660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp330 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2538 = insertelement <4 x float> %tmp330, float %add2537, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2538, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2539 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2540 = fadd float %vecext2539, 0x406F9999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2580 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2580, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp331 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2581 = extractelement <4 x float> %tmp331, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2582 = fadd float %vecext2581, 0x406BE66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2583 = insertelement <4 x float> undef, float %add2582, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2583, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2584 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2585 = fadd float %vecext2584, 3.585000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp332 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40773199A0000000, float 0x407D7999A0000000, float 0xC0717199A0000000, float 0xC07E9CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2590 = fadd float undef, 0x407B1999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp333 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp334 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2672 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add2672, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp335 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2676 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2677 = fadd float %vecext2676, 0x406D6999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp336 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2678 = insertelement <4 x float> %tmp336, float %add2677, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2678, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp337 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2679 = extractelement <4 x float> %tmp337, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2681 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2681, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp338 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2682 = extractelement <4 x float> %tmp338, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2684 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp339 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp340 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp341 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2688 = fadd float undef, 0x4063266660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2692 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2692, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp342 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2696 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2697 = fadd float %vecext2696, 4.140000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp343 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins2698 = insertelement <4 x float> %tmp343, float %add2697, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins2698, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40547999A0000000, float 0xC060633340000000, float 0x4075766660000000, float 0x4072D33340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp344 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp345 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2700 = fadd <4 x float> %tmp345, %tmp344 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add2700, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp346 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp347 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp348 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext2704 = extractelement <4 x float> %tmp348, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add2705 = fadd float %vecext2704, 4.700000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp349 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3121 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3125 = fadd float undef, 0xC06F266660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3126 = insertelement <4 x float> undef, float %add3125, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3126, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp350 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3127 = extractelement <4 x float> %tmp350, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3128 = fadd float %vecext3127, 0x40638999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp351 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3129 = insertelement <4 x float> %tmp351, float %add3128, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3129, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp352 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3131 = fadd float undef, 3.215000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp353 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp354 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3134 = fadd <4 x float> %tmp354, %tmp353 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add3134, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp355 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3136 = fadd float undef, 0x4074333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3140 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3140, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp356 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3141 = extractelement <4 x float> %tmp356, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3142 = fadd float %vecext3141, 2.425000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp357 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3143 = insertelement <4 x float> %tmp357, float %add3142, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3143, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp358 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3144 = extractelement <4 x float> %tmp358, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3145 = fadd float %vecext3144, -3.760000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp359 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3146 = insertelement <4 x float> %tmp359, float %add3145, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3146, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp360 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3272 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3272, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x407B4999A0000000, float 0x40695CCCC0000000, float 0xC05C0CCCC0000000, float 0x407EB33340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp361 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp362 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3274 = fadd <4 x float> %tmp362, %tmp361 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add3274, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp363 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3275 = extractelement <4 x float> %tmp363, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3276 = fadd float %vecext3275, 0x4058066660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp364 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3277 = insertelement <4 x float> %tmp364, float %add3276, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3277, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp365 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3278 = extractelement <4 x float> %tmp365, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3279 = fadd float %vecext3278, 0xC053666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3280 = insertelement <4 x float> undef, float %add3279, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3280, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp366 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3281 = extractelement <4 x float> %tmp366, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3282 = fadd float %vecext3281, 0xC0650CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp367 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3283 = insertelement <4 x float> %tmp367, float %add3282, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3283, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp368 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3284 = extractelement <4 x float> %tmp368, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3285 = fadd float %vecext3284, 0x4062533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3286 = insertelement <4 x float> undef, float %add3285, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp369 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp370 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3289 = extractelement <4 x float> %tmp370, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3290 = fadd float %vecext3289, 0xC07E133340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp371 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3291 = insertelement <4 x float> %tmp371, float %add3290, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3291, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3292 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp372 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp373 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3328 = insertelement <4 x float> %tmp373, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3330 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add3330, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3331 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3332 = fadd float %vecext3331, 0x4061633340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp374 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3333 = insertelement <4 x float> %tmp374, float %add3332, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3333, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3334 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3335 = fadd float %vecext3334, 0x401B333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3336 = insertelement <4 x float> undef, float %add3335, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp375 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3337 = extractelement <4 x float> %tmp375, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3338 = fadd float %vecext3337, 0x403C4CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp376 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3339 = insertelement <4 x float> %tmp376, float %add3338, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3339, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp377 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3340 = extractelement <4 x float> %tmp377, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp378 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3342 = insertelement <4 x float> %tmp378, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp379 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3344 = fadd <4 x float> %tmp379, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add3344, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp380 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3345 = extractelement <4 x float> %tmp380, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3346 = fadd float %vecext3345, 0x407E7E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp381 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3347 = insertelement <4 x float> %tmp381, float %add3346, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3348 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3349 = fadd float %vecext3348, 0xC05F666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp382 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3350 = insertelement <4 x float> %tmp382, float %add3349, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3350, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3352 = fadd float undef, 0xC06ACCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp383 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3423 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3423, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3424 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3425 = fadd float %vecext3424, 0xC05DB33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp384 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3426 = insertelement <4 x float> %tmp384, float %add3425, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3426, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 2.795000e+02, float -4.065000e+02, float 0xC05CD999A0000000, float 1.825000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp385 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp386 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3428 = fadd <4 x float> %tmp386, %tmp385 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp387 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3429 = extractelement <4 x float> %tmp387, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3430 = fadd float %vecext3429, 0x40695CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp388 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3431 = insertelement <4 x float> %tmp388, float %add3430, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3431, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp389 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3432 = extractelement <4 x float> %tmp389, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3433 = fadd float %vecext3432, 0x4052A66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp390 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3434 = insertelement <4 x float> %tmp390, float %add3433, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3434, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3435 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp391 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3437 = insertelement <4 x float> %tmp391, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3437, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp392 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3438 = extractelement <4 x float> %tmp392, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3439 = fadd float %vecext3438, 0xC071D999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC0798199A0000000, float -3.385000e+02, float 0xC050066660000000, float 0xC075E999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp393 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp394 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3442 = fadd <4 x float> %tmp394, %tmp393 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add3442, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3443 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3444 = fadd float %vecext3443, 0xC07CF999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp395 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3446 = extractelement <4 x float> %tmp395, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3447 = fadd float %vecext3446, 0xC06E4999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp396 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3448 = insertelement <4 x float> %tmp396, float %add3447, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3448, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp397 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3449 = extractelement <4 x float> %tmp397, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3450 = fadd float %vecext3449, 0x40779B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp398 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3451 = insertelement <4 x float> %tmp398, float %add3450, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3451, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3453 = fadd float undef, 0xC07ADCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp399 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3454 = insertelement <4 x float> %tmp399, float %add3453, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3454, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp400 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3457 = extractelement <4 x float> %tmp400, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3458 = fadd float %vecext3457, -4.440000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3459 = insertelement <4 x float> undef, float %add3458, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3459, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp401 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3460 = extractelement <4 x float> %tmp401, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp402 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3462 = insertelement <4 x float> %tmp402, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3462, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp403 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3464 = fadd float undef, 0xC057B999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp404 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3465 = insertelement <4 x float> %tmp404, float %add3464, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3465, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp405 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3466 = extractelement <4 x float> %tmp405, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3467 = fadd float %vecext3466, 0xC07A9CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp406 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x405C3999A0000000, float 0xC07C6B3340000000, float 0x407ACB3340000000, float 0xC06E0999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp407 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp408 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3477 = extractelement <4 x float> %tmp408, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3479 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3479, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3480 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3481 = fadd float %vecext3480, 0xC053F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp409 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3482 = insertelement <4 x float> %tmp409, float %add3481, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3482, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 3.565000e+02, float 0xC0464CCCC0000000, float 0x4037666660000000, float 0xC0788CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp410 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3484 = fadd <4 x float> %tmp410, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add3484, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp411 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3486 = fadd float undef, -1.415000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3487 = insertelement <4 x float> undef, float %add3486, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3487, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp412 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3488 = extractelement <4 x float> %tmp412, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3489 = fadd float %vecext3488, 0x405A1999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp413 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3490 = insertelement <4 x float> %tmp413, float %add3489, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3490, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3492 = fadd float undef, 0x4078066660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp414 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3493 = insertelement <4 x float> %tmp414, float %add3492, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3493, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp415 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3495 = fadd float undef, 0xC0798999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp416 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3496 = insertelement <4 x float> %tmp416, float %add3495, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3496, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp417 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp418 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3498 = fadd <4 x float> %tmp418, %tmp417 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add3498, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3499 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3500 = fadd float %vecext3499, -1.605000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3501 = insertelement <4 x float> undef, float %add3500, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp419 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3502 = extractelement <4 x float> %tmp419, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3503 = fadd float %vecext3502, 0x4058C66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp420 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3506 = fadd float undef, 0xC074DB3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp421 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins3507 = insertelement <4 x float> %tmp421, float %add3506, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins3507, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3509 = fadd float undef, 0xC066033340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp422 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x404B333340000000, float 4.680000e+02, float 0x40577999A0000000, float 0xC07D9999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp423 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3513 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add3514 = fadd float %vecext3513, 2.300000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp424 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp425 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext3516 = extractelement <4 x float> %tmp425, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5414 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5414, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp426 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp427 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5416 = fadd <4 x float> %tmp427, %tmp426 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5416, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp428 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5418 = fadd float undef, 0xC07ED999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp429 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5419 = insertelement <4 x float> %tmp429, float %add5418, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5624 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5624, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07B4999A0000000, float 0x4078B33340000000, float 0xC07674CCC0000000, float 0xC07C533340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5626 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5626, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5627 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp430 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5629 = insertelement <4 x float> %tmp430, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5629, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp431 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5630 = extractelement <4 x float> %tmp431, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5631 = fadd float %vecext5630, 0x405EECCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5632 = insertelement <4 x float> undef, float %add5631, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5632, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp432 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5688 = insertelement <4 x float> %tmp432, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5688, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp433 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5689 = extractelement <4 x float> %tmp433, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp434 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5691 = insertelement <4 x float> %tmp434, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5691, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5692 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -4.350000e+02, float 0xC0775CCCC0000000, float 0xC0714999A0000000, float 0xC0661999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp435 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5696 = fadd <4 x float> undef, %tmp435 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5696, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5701 = fadd float undef, 0x4077D4CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp436 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5702 = insertelement <4 x float> %tmp436, float %add5701, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5702, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp437 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp438 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5705 = insertelement <4 x float> %tmp438, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5705, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp439 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5706 = extractelement <4 x float> %tmp439, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5707 = fadd float %vecext5706, 0xC0780B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp440 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5708 = insertelement <4 x float> %tmp440, float %add5707, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5708, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x405D666660000000, float 0xC069333340000000, float 0x407B6B3340000000, float 0xC06EB33340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp441 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp442 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5710 = fadd <4 x float> %tmp442, %tmp441 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5710, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp443 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5711 = extractelement <4 x float> %tmp443, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5712 = fadd float %vecext5711, 1.850000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp444 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5713 = insertelement <4 x float> %tmp444, float %add5712, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5713, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp445 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp446 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5716 = insertelement <4 x float> %tmp446, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp447 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5724 = fadd <4 x float> %tmp447, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5724, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp448 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5748 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp449 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5750 = insertelement <4 x float> %tmp449, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40692999A0000000, float 0xC07C4CCCC0000000, float 0x407D1E6660000000, float 0x407B4199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp450 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5752 = fadd <4 x float> undef, %tmp450 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5754 = fadd float undef, 0xC064033340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp451 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5755 = insertelement <4 x float> %tmp451, float %add5754, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5755, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp452 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5756 = extractelement <4 x float> %tmp452, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5757 = fadd float %vecext5756, 0x40787B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp453 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5758 = insertelement <4 x float> %tmp453, float %add5757, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5758, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp454 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5759 = extractelement <4 x float> %tmp454, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp455 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5761 = insertelement <4 x float> %tmp455, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5761, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp456 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5762 = extractelement <4 x float> %tmp456, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5763 = fadd float %vecext5762, 0x40703E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp457 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5764 = insertelement <4 x float> %tmp457, float %add5763, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5764, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x407A6B3340000000, float 0x40470CCCC0000000, float 0xC076F4CCC0000000, float 0x40791999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5766 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5766, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp458 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5767 = extractelement <4 x float> %tmp458, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5768 = fadd float %vecext5767, 0x4065533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp459 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5769 = insertelement <4 x float> %tmp459, float %add5768, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5769, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5771 = fadd float undef, 8.000000e+00 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp460 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5772 = insertelement <4 x float> %tmp460, float %add5771, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp461 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5796 = fadd float undef, 0x4058ECCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5797 = insertelement <4 x float> undef, float %add5796, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5797, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp462 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5798 = extractelement <4 x float> %tmp462, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp463 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5800 = insertelement <4 x float> %tmp463, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp464 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5801 = extractelement <4 x float> %tmp464, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5802 = fadd float %vecext5801, 0xC072A199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp465 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5803 = insertelement <4 x float> %tmp465, float %add5802, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5803, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp466 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5804 = extractelement <4 x float> %tmp466, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5805 = fadd float %vecext5804, 0x40785999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp467 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5806 = insertelement <4 x float> %tmp467, float %add5805, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5806, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp468 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp469 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5809 = extractelement <4 x float> %tmp469, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5810 = fadd float %vecext5809, 0x407B7B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp470 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp471 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5818 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5819 = fadd float %vecext5818, 0x4071733340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp472 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5820 = insertelement <4 x float> %tmp472, float %add5819, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5820, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40514CCCC0000000, float 0x406A7999A0000000, float 0xC078766660000000, float 0xC0522CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp473 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp474 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5822 = fadd <4 x float> %tmp474, %tmp473 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5822, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp475 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5823 = extractelement <4 x float> %tmp475, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp476 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5825 = insertelement <4 x float> %tmp476, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp477 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5826 = extractelement <4 x float> %tmp477, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5827 = fadd float %vecext5826, 0x407F14CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp478 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5828 = insertelement <4 x float> %tmp478, float %add5827, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5828, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp479 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5829 = extractelement <4 x float> %tmp479, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5830 = fadd float %vecext5829, 3.350000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp480 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5831 = insertelement <4 x float> %tmp480, float %add5830, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -3.370000e+02, float 0xC072DE6660000000, float -2.670000e+02, float 0x4062333340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp481 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5837 = extractelement <4 x float> %tmp481, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5839 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5839, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp482 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5840 = extractelement <4 x float> %tmp482, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp483 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5842 = insertelement <4 x float> %tmp483, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5842, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp484 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp485 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5845 = insertelement <4 x float> %tmp485, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5845, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC06EC999A0000000, float 0x406D5999A0000000, float 0x4056F33340000000, float 0xC07E14CCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5850 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5850, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp486 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5852 = fadd float undef, 2.985000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp487 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5853 = insertelement <4 x float> %tmp487, float %add5852, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5853, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp488 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5854 = extractelement <4 x float> %tmp488, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5855 = fadd float %vecext5854, 0xC053F999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp489 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5856 = insertelement <4 x float> %tmp489, float %add5855, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5856, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp490 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5858 = fadd float undef, 0x4071666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp491 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5859 = insertelement <4 x float> %tmp491, float %add5858, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5859, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp492 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5860 = extractelement <4 x float> %tmp492, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp493 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5899 = extractelement <4 x float> %tmp493, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5900 = fadd float %vecext5899, -2.700000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp494 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5901 = insertelement <4 x float> %tmp494, float %add5900, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5901, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5914 = fadd float undef, 0x40786E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5918 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5918, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x406F266660000000, float 7.900000e+01, float -4.695000e+02, float -4.880000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5920 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add5920, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5934 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5935 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5936 = fadd float %vecext5935, 0xC056B999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp495 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp496 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5994 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add5995 = fadd float %vecext5994, 0x4051666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins5996 = insertelement <4 x float> undef, float %add5995, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins5996, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp497 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext5997 = extractelement <4 x float> %tmp497, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp498 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6000 = extractelement <4 x float> %tmp498, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6001 = fadd float %vecext6000, -7.600000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp499 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6002 = insertelement <4 x float> %tmp499, float %add6001, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6002, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07EA199A0000000, float 0x407DC33340000000, float 0xC0753199A0000000, float -3.895000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp500 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6004 = fadd <4 x float> undef, %tmp500 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6004, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp501 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6005 = extractelement <4 x float> %tmp501, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp502 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6007 = insertelement <4 x float> %tmp502, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp503 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6008 = extractelement <4 x float> %tmp503, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp504 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6024 = insertelement <4 x float> %tmp504, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6024, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp505 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6025 = extractelement <4 x float> %tmp505, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6026 = fadd float %vecext6025, 3.700000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp506 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6027 = insertelement <4 x float> %tmp506, float %add6026, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6027, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6028 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6029 = fadd float %vecext6028, 0x4071666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp507 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6030 = insertelement <4 x float> %tmp507, float %add6029, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6030, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC0527999A0000000, float 0xC06AD999A0000000, float 0x3FF6666660000000, float 0xC03F666660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp508 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp509 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp510 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6033 = extractelement <4 x float> %tmp510, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp511 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6036 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6037 = fadd float %vecext6036, 0xC075CB3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6038 = insertelement <4 x float> undef, float %add6037, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6038, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp512 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6040 = fadd float undef, 0x4071ECCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp513 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6041 = insertelement <4 x float> %tmp513, float %add6040, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6041, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp514 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6042 = extractelement <4 x float> %tmp514, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6043 = fadd float %vecext6042, 0xC07DD33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp515 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6044 = insertelement <4 x float> %tmp515, float %add6043, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6044, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC065FCCCC0000000, float 0x40767CCCC0000000, float 0x4079D4CCC0000000, float 0xC07314CCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp516 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp517 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6046 = fadd <4 x float> %tmp517, %tmp516 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6046, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6047 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp518 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6049 = insertelement <4 x float> %tmp518, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6049, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp519 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6050 = extractelement <4 x float> %tmp519, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6051 = fadd float %vecext6050, 0x407E4E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6055 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6056 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp520 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6061 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp521 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp522 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6067 = extractelement <4 x float> %tmp522, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6068 = fadd float %vecext6067, 0x40768E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6070 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6071 = fadd float %vecext6070, 0xC07C6CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6072 = insertelement <4 x float> undef, float %add6071, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6072, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40546CCCC0000000, float 0x4067D66660000000, float 0xC060E33340000000, float 0x4061533340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp523 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp524 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6074 = fadd <4 x float> %tmp524, %tmp523 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6074, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp525 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6075 = extractelement <4 x float> %tmp525, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6076 = fadd float %vecext6075, 0x405D733340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp526 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6077 = insertelement <4 x float> %tmp526, float %add6076, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6077, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp527 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6079 = fadd float undef, 0xC07E9B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp528 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp529 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6082 = fadd float undef, 0x407DCE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6083 = insertelement <4 x float> undef, float %add6082, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6083, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp530 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6084 = extractelement <4 x float> %tmp530, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6085 = fadd float %vecext6084, 0xC061A33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6086 = insertelement <4 x float> undef, float %add6085, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6086, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4055C66660000000, float 0x40735199A0000000, float 0xC0713199A0000000, float 0x40729B3340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp531 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp532 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6088 = fadd <4 x float> %tmp532, %tmp531 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6088, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp533 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6089 = extractelement <4 x float> %tmp533, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6107 = fadd float undef, 0xC06A166660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp534 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6108 = insertelement <4 x float> %tmp534, float %add6107, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6108, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp535 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6109 = extractelement <4 x float> %tmp535, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6110 = fadd float %vecext6109, 0x4070FB3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp536 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp537 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6112 = extractelement <4 x float> %tmp537, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6113 = fadd float %vecext6112, 0xC04AF33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp538 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp539 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6117 = extractelement <4 x float> %tmp539, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6118 = fadd float %vecext6117, 0x407AB33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp540 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6119 = insertelement <4 x float> %tmp540, float %add6118, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6119, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp541 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6120 = extractelement <4 x float> %tmp541, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6121 = fadd float %vecext6120, 0x405AE66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp542 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6122 = insertelement <4 x float> %tmp542, float %add6121, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6122, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6123 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6124 = fadd float %vecext6123, -4.385000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp543 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6126 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp544 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6128 = insertelement <4 x float> %tmp544, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6128, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -2.980000e+02, float 0xC06F0CCCC0000000, float 0xC054A66660000000, float 0xC040CCCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp545 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp546 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6130 = fadd <4 x float> %tmp546, %tmp545 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp547 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6131 = extractelement <4 x float> %tmp547, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6132 = fadd float %vecext6131, 0x407BDE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6133 = insertelement <4 x float> undef, float %add6132, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6133, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6134 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6135 = fadd float %vecext6134, 0xC06B7999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp548 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6136 = insertelement <4 x float> %tmp548, float %add6135, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6137 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6138 = fadd float %vecext6137, 0x40752199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp549 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6172 = fadd <4 x float> undef, %tmp549 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp550 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp551 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6178 = insertelement <4 x float> %tmp551, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6178, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp552 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6179 = extractelement <4 x float> %tmp552, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6180 = fadd float %vecext6179, -3.905000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp553 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6181 = insertelement <4 x float> %tmp553, float %add6180, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp554 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6182 = extractelement <4 x float> %tmp554, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6183 = fadd float %vecext6182, 1.515000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp555 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6184 = insertelement <4 x float> %tmp555, float %add6183, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6184, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp556 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6189 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6189, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp557 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6190 = extractelement <4 x float> %tmp557, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6191 = fadd float %vecext6190, 0xC07BD33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp558 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6192 = insertelement <4 x float> %tmp558, float %add6191, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6192, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp559 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp560 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6196 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6197 = fadd float %vecext6196, -4.070000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp561 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6198 = insertelement <4 x float> %tmp561, float %add6197, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x407904CCC0000000, float 0x406A833340000000, float 4.895000e+02, float 0x40648999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp562 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp563 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6200 = fadd <4 x float> %tmp563, %tmp562 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6200, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp564 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6201 = extractelement <4 x float> %tmp564, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp565 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6203 = insertelement <4 x float> %tmp565, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp566 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6204 = extractelement <4 x float> %tmp566, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6205 = fadd float %vecext6204, 1.740000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp567 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6206 = insertelement <4 x float> %tmp567, float %add6205, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp568 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6209 = insertelement <4 x float> %tmp568, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6209, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp569 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6210 = extractelement <4 x float> %tmp569, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp570 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6219 = fadd float undef, 0xC0596CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp571 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6220 = insertelement <4 x float> %tmp571, float %add6219, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6224 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6225 = fadd float %vecext6224, 0xC074533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp572 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6228 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6228, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6229 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6230 = fadd float %vecext6229, 1.695000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp573 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6231 = insertelement <4 x float> %tmp573, float %add6230, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6231, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp574 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6232 = extractelement <4 x float> %tmp574, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6233 = fadd float %vecext6232, 0x4079C33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp575 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6234 = insertelement <4 x float> %tmp575, float %add6233, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6234, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6235 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6236 = fadd float %vecext6235, 0xC07D8199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6237 = insertelement <4 x float> undef, float %add6236, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6237, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp576 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6245 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6245, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp577 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6246 = extractelement <4 x float> %tmp577, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6247 = fadd float %vecext6246, 0x40631999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp578 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6251 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp579 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6253 = fadd float undef, 0xC0692999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6254 = insertelement <4 x float> undef, float %add6253, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6254, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 4.600000e+02, float 0xC0777B3340000000, float 0x40351999A0000000, float 0xC06E433340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp580 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp581 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6256 = fadd <4 x float> %tmp581, %tmp580 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6256, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp582 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6257 = extractelement <4 x float> %tmp582, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6258 = fadd float %vecext6257, 4.670000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp583 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6259 = insertelement <4 x float> %tmp583, float %add6258, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6259, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp584 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6260 = extractelement <4 x float> %tmp584, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6261 = fadd float %vecext6260, 0xC05F733340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp585 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6262 = insertelement <4 x float> %tmp585, float %add6261, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6262, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp586 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6263 = extractelement <4 x float> %tmp586, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp587 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6265 = insertelement <4 x float> %tmp587, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6265, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp588 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6266 = extractelement <4 x float> %tmp588, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6267 = fadd float %vecext6266, 0x407174CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp589 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6268 = insertelement <4 x float> %tmp589, float %add6267, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6268, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -3.130000e+02, float 0xC079733340000000, float -4.660000e+02, float 0xC064E66660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp590 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp591 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6270 = fadd <4 x float> %tmp591, %tmp590 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6270, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp592 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6271 = extractelement <4 x float> %tmp592, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6272 = fadd float %vecext6271, 1.765000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp593 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6273 = insertelement <4 x float> %tmp593, float %add6272, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6273, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp594 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6274 = extractelement <4 x float> %tmp594, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6275 = fadd float %vecext6274, 0x402C666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp595 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6276 = insertelement <4 x float> %tmp595, float %add6275, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6276, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp596 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6277 = extractelement <4 x float> %tmp596, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6278 = fadd float %vecext6277, -8.450000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp597 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6279 = insertelement <4 x float> %tmp597, float %add6278, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6279, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp598 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6280 = extractelement <4 x float> %tmp598, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6281 = fadd float %vecext6280, 0xC07A133340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6282 = insertelement <4 x float> undef, float %add6281, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6282, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4067ECCCC0000000, float 0xC040CCCCC0000000, float 0xC0762E6660000000, float -4.750000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6284 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6285 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6289 = fadd float undef, 0xC0738999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp599 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6293 = insertelement <4 x float> %tmp599, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6293, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp600 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6294 = extractelement <4 x float> %tmp600, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6295 = fadd float %vecext6294, 0xC01CCCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6296 = insertelement <4 x float> undef, float %add6295, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6296, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40704199A0000000, float 0x40753CCCC0000000, float 0xC07E2199A0000000, float 0xC068833340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp601 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6298 = fadd <4 x float> undef, %tmp601 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6298, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp602 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6299 = extractelement <4 x float> %tmp602, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6300 = fadd float %vecext6299, 0x4074B33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp603 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6301 = insertelement <4 x float> %tmp603, float %add6300, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6301, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp604 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6302 = extractelement <4 x float> %tmp604, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6303 = fadd float %vecext6302, 0xC05B333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp605 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6304 = insertelement <4 x float> %tmp605, float %add6303, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6304, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp606 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6305 = extractelement <4 x float> %tmp606, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6306 = fadd float %vecext6305, 0x4077E999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6307 = insertelement <4 x float> undef, float %add6306, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6307, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp607 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6308 = extractelement <4 x float> %tmp607, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6309 = fadd float %vecext6308, 0x40707E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp608 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6310 = insertelement <4 x float> %tmp608, float %add6309, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6310, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x407A233340000000, float 0x406DA33340000000, float 3.725000e+02, float 0x40761199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp609 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp610 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6312 = fadd <4 x float> %tmp610, %tmp609 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6312, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp611 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6313 = extractelement <4 x float> %tmp611, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6314 = fadd float %vecext6313, 0xC07CF33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp612 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6315 = insertelement <4 x float> %tmp612, float %add6314, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp613 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6655 = extractelement <4 x float> %tmp613, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6656 = fadd float %vecext6655, 2.185000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp614 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6657 = insertelement <4 x float> %tmp614, float %add6656, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6657, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6660 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6660, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC064E33340000000, float 0xC064833340000000, float 0xC0673CCCC0000000, float 0xC074266660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp615 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6663 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6664 = fadd float %vecext6663, 0xC05B7999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp616 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6665 = insertelement <4 x float> %tmp616, float %add6664, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp617 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6669 = extractelement <4 x float> %tmp617, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp618 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07CC4CCC0000000, float 0x404EE66660000000, float 0xC0754CCCC0000000, float 0xC0744B3340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp619 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6676 = fadd <4 x float> %tmp619, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6676, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp620 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6677 = extractelement <4 x float> %tmp620, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6678 = fadd float %vecext6677, 0x4077F4CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp621 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6679 = insertelement <4 x float> %tmp621, float %add6678, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6680 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6681 = fadd float %vecext6680, 0x4061766660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp622 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp623 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6683 = extractelement <4 x float> %tmp623, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6684 = fadd float %vecext6683, 0x40718999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp624 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6685 = insertelement <4 x float> %tmp624, float %add6684, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6685, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp625 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6686 = extractelement <4 x float> %tmp625, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6687 = fadd float %vecext6686, 0x4076D66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp626 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6688 = insertelement <4 x float> %tmp626, float %add6687, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6688, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 7.500000e+00, float 0x4077E33340000000, float 0xC0596CCCC0000000, float 0xC07D4E6660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp627 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6690 = fadd <4 x float> undef, %tmp627 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6690, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp628 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6691 = extractelement <4 x float> %tmp628, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6692 = fadd float %vecext6691, 3.250000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp629 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6693 = insertelement <4 x float> %tmp629, float %add6692, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6693, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp630 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6694 = extractelement <4 x float> %tmp630, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6695 = fadd float %vecext6694, 0x407DF999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp631 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6696 = insertelement <4 x float> %tmp631, float %add6695, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6696, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp632 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6697 = extractelement <4 x float> %tmp632, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6698 = fadd float %vecext6697, 0xC075FE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp633 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6699 = insertelement <4 x float> %tmp633, float %add6698, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6699, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp634 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6700 = extractelement <4 x float> %tmp634, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6701 = fadd float %vecext6700, 0xC07BCE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp635 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6702 = insertelement <4 x float> %tmp635, float %add6701, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6702, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40772CCCC0000000, float 0xC0625CCCC0000000, float 6.200000e+01, float 0xC06ADCCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp636 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp637 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6707 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6707, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp638 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6708 = extractelement <4 x float> %tmp638, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp639 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp640 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6714 = extractelement <4 x float> %tmp640, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6715 = fadd float %vecext6714, 0xC0537999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp641 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6716 = insertelement <4 x float> %tmp641, float %add6715, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6719 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6720 = fadd float %vecext6719, 2.870000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp642 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6721 = insertelement <4 x float> %tmp642, float %add6720, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp643 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6722 = extractelement <4 x float> %tmp643, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6723 = fadd float %vecext6722, 0xC07704CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp644 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6724 = insertelement <4 x float> %tmp644, float %add6723, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp645 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6726 = fadd float undef, 0x4059B999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp646 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6727 = insertelement <4 x float> %tmp646, float %add6726, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6727, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6728 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6729 = fadd float %vecext6728, 0xC073466660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC0309999A0000000, float -2.715000e+02, float 1.620000e+02, float 0x40674CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp647 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp648 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6732 = fadd <4 x float> %tmp648, %tmp647 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6732, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp649 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6733 = extractelement <4 x float> %tmp649, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6734 = fadd float %vecext6733, 0x4040733340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp650 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6735 = insertelement <4 x float> %tmp650, float %add6734, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6735, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp651 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6736 = extractelement <4 x float> %tmp651, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6737 = fadd float %vecext6736, 0xC07B74CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp652 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6738 = insertelement <4 x float> %tmp652, float %add6737, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6738, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp653 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6739 = extractelement <4 x float> %tmp653, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6740 = fadd float %vecext6739, 0x40699CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp654 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6741 = insertelement <4 x float> %tmp654, float %add6740, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6741, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp655 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6742 = extractelement <4 x float> %tmp655, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6743 = fadd float %vecext6742, 0x4078533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp656 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6744 = insertelement <4 x float> %tmp656, float %add6743, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6744, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp657 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp658 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6746 = fadd <4 x float> %tmp658, %tmp657 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6746, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp659 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6749 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6749, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp660 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6751 = fadd float undef, 0x4075DE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6752 = insertelement <4 x float> undef, float %add6751, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6752, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp661 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6753 = extractelement <4 x float> %tmp661, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6754 = fadd float %vecext6753, 0xC008CCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6755 = insertelement <4 x float> undef, float %add6754, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6755, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp662 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6756 = extractelement <4 x float> %tmp662, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6757 = fadd float %vecext6756, 0x406CA999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp663 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6758 = insertelement <4 x float> %tmp663, float %add6757, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6758, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x403D1999A0000000, float 0xC05F533340000000, float 3.945000e+02, float 3.950000e+01>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp664 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6760 = fadd <4 x float> undef, %tmp664 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6760, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp665 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6761 = extractelement <4 x float> %tmp665, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6762 = fadd float %vecext6761, 2.860000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6763 = insertelement <4 x float> undef, float %add6762, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp666 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC079BE6660000000, float 4.930000e+02, float 0x406CC33340000000, float 0xC062E999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp667 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6774 = fadd <4 x float> undef, %tmp667 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp668 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6775 = extractelement <4 x float> %tmp668, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6776 = fadd float %vecext6775, 0x407B8199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp669 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6777 = insertelement <4 x float> %tmp669, float %add6776, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6777, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp670 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6778 = extractelement <4 x float> %tmp670, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6779 = fadd float %vecext6778, 0x401C666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp671 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6784 = extractelement <4 x float> %tmp671, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6875 = insertelement <4 x float> undef, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6875, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp672 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6876 = extractelement <4 x float> %tmp672, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6877 = fadd float %vecext6876, 0x4073A66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6878 = insertelement <4 x float> undef, float %add6877, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6878, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6888 = fadd float undef, 0x4057CCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp673 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6889 = insertelement <4 x float> %tmp673, float %add6888, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6889, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp674 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6890 = extractelement <4 x float> %tmp674, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6891 = fadd float %vecext6890, -4.430000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp675 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6892 = insertelement <4 x float> %tmp675, float %add6891, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6892, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp676 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6893 = extractelement <4 x float> %tmp676, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6894 = fadd float %vecext6893, -3.280000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp677 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6895 = insertelement <4 x float> %tmp677, float %add6894, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6895, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp678 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp679 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp680 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6900 = fadd <4 x float> %tmp680, %tmp679 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6900, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp681 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6901 = extractelement <4 x float> %tmp681, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6902 = fadd float %vecext6901, 0x4079DCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp682 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6903 = insertelement <4 x float> %tmp682, float %add6902, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6903, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6905 = fadd float undef, 0x4031B33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp683 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6906 = insertelement <4 x float> %tmp683, float %add6905, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp684 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6912 = insertelement <4 x float> %tmp684, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 3.315000e+02, float 0xC066C999A0000000, float 0xC061F33340000000, float 0x4071166660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp685 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp686 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6914 = fadd <4 x float> %tmp686, %tmp685 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6914, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6915 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6920 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6920, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6921 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6922 = fadd float %vecext6921, 0xC064066660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp687 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6926 = insertelement <4 x float> %tmp687, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6926, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC03C4CCCC0000000, float 0xC07E5199A0000000, float -8.250000e+01, float 0xC043B33340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp688 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp689 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6928 = fadd <4 x float> %tmp689, %tmp688 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6928, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6930 = fadd float undef, -4.590000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6931 = insertelement <4 x float> undef, float %add6930, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6931, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp690 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6932 = extractelement <4 x float> %tmp690, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6933 = fadd float %vecext6932, 0xC063F999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp691 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp692 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6935 = extractelement <4 x float> %tmp692, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6936 = fadd float %vecext6935, -3.335000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp693 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6937 = insertelement <4 x float> %tmp693, float %add6936, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp694 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6938 = extractelement <4 x float> %tmp694, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6939 = fadd float %vecext6938, 0x405F3999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6942 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6943 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6944 = fadd float %vecext6943, 0x40530CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp695 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6950 = fadd float undef, 0xC078F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp696 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6951 = insertelement <4 x float> %tmp696, float %add6950, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6951, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp697 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6952 = extractelement <4 x float> %tmp697, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6953 = fadd float %vecext6952, 0xC06E5999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp698 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6954 = insertelement <4 x float> %tmp698, float %add6953, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6954, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp699 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp700 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6956 = fadd <4 x float> %tmp700, %tmp699 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6956, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp701 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6957 = extractelement <4 x float> %tmp701, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6958 = fadd float %vecext6957, 0xC077633340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp702 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6959 = insertelement <4 x float> %tmp702, float %add6958, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6959, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp703 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6963 = extractelement <4 x float> %tmp703, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6964 = fadd float %vecext6963, 0x4068666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp704 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6965 = insertelement <4 x float> %tmp704, float %add6964, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6965, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6975 = fadd float undef, 0x406AF33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp705 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6976 = insertelement <4 x float> %tmp705, float %add6975, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6976, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp706 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp707 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6984 = fadd <4 x float> %tmp707, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6984, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp708 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6985 = extractelement <4 x float> %tmp708, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6986 = fadd float %vecext6985, 0xC05E266660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp709 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6987 = insertelement <4 x float> %tmp709, float %add6986, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6987, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp710 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6988 = extractelement <4 x float> %tmp710, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6989 = fadd float %vecext6988, 0x40706E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp711 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins6996 = insertelement <4 x float> %tmp711, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins6996, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4077A4CCC0000000, float 0xC0757199A0000000, float 0xC072F4CCC0000000, float 0xC071DCCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp712 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp713 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add6998 = fadd <4 x float> %tmp713, %tmp712 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add6998, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp714 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext6999 = extractelement <4 x float> %tmp714, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7000 = fadd float %vecext6999, 0x4076233340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp715 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7001 = insertelement <4 x float> %tmp715, float %add7000, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7001, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp716 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7002 = extractelement <4 x float> %tmp716, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7003 = fadd float %vecext7002, 0x403BCCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp717 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7004 = insertelement <4 x float> %tmp717, float %add7003, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp718 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7140 = fadd float undef, 0x403D333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7141 = insertelement <4 x float> undef, float %add7140, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7142 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7143 = fadd float %vecext7142, 0xC058F999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7144 = insertelement <4 x float> undef, float %add7143, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp719 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7148 = extractelement <4 x float> %tmp719, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7149 = fadd float %vecext7148, 0x4075333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp720 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7150 = insertelement <4 x float> %tmp720, float %add7149, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7150, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 1.700000e+02, float 0xC077B4CCC0000000, float 0x40625999A0000000, float 0x406C166660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp721 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7152 = fadd <4 x float> %tmp721, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add7152, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7156 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7157 = fadd float %vecext7156, 0xC05F533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp722 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7158 = insertelement <4 x float> %tmp722, float %add7157, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7158, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp723 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7159 = extractelement <4 x float> %tmp723, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7160 = fadd float %vecext7159, 0x407A5999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp724 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7161 = insertelement <4 x float> %tmp724, float %add7160, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7161, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7168 = fadd float undef, 0xC072F199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp725 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7170 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7171 = fadd float %vecext7170, 0x406AACCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7172 = insertelement <4 x float> undef, float %add7171, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7172, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7173 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp726 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7419 = extractelement <4 x float> %tmp726, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7420 = fadd float %vecext7419, 0x404EA66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7421 = insertelement <4 x float> undef, float %add7420, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7421, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp727 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7422 = extractelement <4 x float> %tmp727, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7423 = fadd float %vecext7422, 4.800000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp728 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7424 = insertelement <4 x float> %tmp728, float %add7423, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7424, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp729 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7425 = extractelement <4 x float> %tmp729, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7426 = fadd float %vecext7425, 0xC072C999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp730 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7427 = insertelement <4 x float> %tmp730, float %add7426, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7427, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7428 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp731 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7568 = extractelement <4 x float> %tmp731, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7569 = fadd float %vecext7568, 1.090000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp732 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7570 = insertelement <4 x float> %tmp732, float %add7569, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7570, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40745199A0000000, float 0xC0411999A0000000, float -5.650000e+01, float -4.005000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp733 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp734 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7572 = fadd <4 x float> %tmp734, %tmp733 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add7572, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7573 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7574 = fadd float %vecext7573, -3.920000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp735 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7575 = insertelement <4 x float> %tmp735, float %add7574, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7575, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp736 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7577 = fadd float undef, 0xC051666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp737 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp738 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7579 = extractelement <4 x float> %tmp738, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7580 = fadd float %vecext7579, 0x407E9199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7581 = insertelement <4 x float> undef, float %add7580, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7581, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp739 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7582 = extractelement <4 x float> %tmp739, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7583 = fadd float %vecext7582, 2.760000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp740 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7584 = insertelement <4 x float> %tmp740, float %add7583, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC057533340000000, float 0x4060A33340000000, float 0x40791E6660000000, float 2.455000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp741 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp742 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7586 = fadd <4 x float> %tmp742, %tmp741 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add7586, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp743 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7587 = extractelement <4 x float> %tmp743, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7588 = fadd float %vecext7587, 6.100000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp744 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp745 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7590 = extractelement <4 x float> %tmp745, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7591 = fadd float %vecext7590, -3.935000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp746 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7592 = insertelement <4 x float> %tmp746, float %add7591, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7592, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp747 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7593 = extractelement <4 x float> %tmp747, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7595 = insertelement <4 x float> undef, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7595, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp748 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7596 = extractelement <4 x float> %tmp748, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7597 = fadd float %vecext7596, 0x407E666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x406A766660000000, float 0xBFC99999A0000000, float 0xC0751B3340000000, float -4.075000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp749 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7616 = fadd float undef, 0xC04DE66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp750 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7617 = insertelement <4 x float> %tmp750, float %add7616, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7617, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp751 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7618 = extractelement <4 x float> %tmp751, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7619 = fadd float %vecext7618, 6.050000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp752 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7620 = insertelement <4 x float> %tmp752, float %add7619, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7620, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp753 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7622 = fadd float undef, 0xC054B999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp754 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7626 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7626, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp755 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp756 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7628 = fadd <4 x float> %tmp756, %tmp755 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add7628, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp757 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7629 = extractelement <4 x float> %tmp757, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7630 = fadd float %vecext7629, 0xC05E2CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp758 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7631 = insertelement <4 x float> %tmp758, float %add7630, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7639 = fadd float undef, 0x407C5999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp759 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7640 = insertelement <4 x float> %tmp759, float %add7639, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x406AA66660000000, float 0x4067C66660000000, float 0xC054866660000000, float -2.400000e+01>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp760 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7642 = fadd <4 x float> %tmp760, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp761 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7644 = fadd float undef, 0xC0758999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp762 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7646 = extractelement <4 x float> %tmp762, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7647 = fadd float %vecext7646, 0xC07A3B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp763 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7648 = insertelement <4 x float> %tmp763, float %add7647, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7648, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp764 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7649 = extractelement <4 x float> %tmp764, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7650 = fadd float %vecext7649, 0x40760CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp765 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7651 = insertelement <4 x float> %tmp765, float %add7650, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7651, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp766 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7652 = extractelement <4 x float> %tmp766, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7653 = fadd float %vecext7652, 0x40620CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp767 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7654 = insertelement <4 x float> %tmp767, float %add7653, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7654, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp768 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp769 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7656 = fadd <4 x float> %tmp769, %tmp768 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add7656, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp770 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7657 = extractelement <4 x float> %tmp770, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7658 = fadd float %vecext7657, 0xC06EF999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp771 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7659 = insertelement <4 x float> %tmp771, float %add7658, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7659, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp772 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7660 = extractelement <4 x float> %tmp772, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7661 = fadd float %vecext7660, 0x404B9999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp773 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7662 = insertelement <4 x float> %tmp773, float %add7661, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7662, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp774 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7663 = extractelement <4 x float> %tmp774, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7664 = fadd float %vecext7663, 0x4074B66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp775 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7665 = insertelement <4 x float> %tmp775, float %add7664, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7665, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp776 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7666 = extractelement <4 x float> %tmp776, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7667 = fadd float %vecext7666, 0x4074166660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7668 = insertelement <4 x float> undef, float %add7667, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7668, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp777 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp778 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7670 = fadd <4 x float> %tmp778, %tmp777 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp779 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7671 = extractelement <4 x float> %tmp779, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7672 = fadd float %vecext7671, 0x406F166660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7726 = fadd <4 x float> undef, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp780 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7727 = extractelement <4 x float> %tmp780, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp781 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp782 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7731 = fadd float undef, 1.900000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp783 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7732 = insertelement <4 x float> %tmp783, float %add7731, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7732, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp784 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7735 = insertelement <4 x float> %tmp784, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7735, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp785 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext7736 = extractelement <4 x float> %tmp785, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7737 = fadd float %vecext7736, 0xC06AF66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins7850 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins7850, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4062A33340000000, float 2.290000e+02, float 0x40509999A0000000, float 0xC078BE6660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp786 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp787 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add7852 = fadd <4 x float> %tmp787, %tmp786 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add7852, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp788 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9396 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9397 = fadd float %vecext9396, 0xC074533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp789 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9398 = insertelement <4 x float> %tmp789, float %add9397, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9398, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9399 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp790 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9401 = insertelement <4 x float> %tmp790, float undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp791 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9402 = extractelement <4 x float> %tmp791, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9403 = fadd float %vecext9402, 0xC03E4CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp792 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9404 = insertelement <4 x float> %tmp792, float %add9403, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9404, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp793 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp794 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9407 = extractelement <4 x float> %tmp794, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9408 = fadd float %vecext9407, 0x407B2999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp795 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9410 = extractelement <4 x float> %tmp795, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9411 = fadd float %vecext9410, 0x40726E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp796 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp797 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9413 = extractelement <4 x float> %tmp797, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9414 = fadd float %vecext9413, 0xC057ECCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp798 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9415 = insertelement <4 x float> %tmp798, float %add9414, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9415, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp799 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9416 = extractelement <4 x float> %tmp799, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9417 = fadd float %vecext9416, 0x406B0CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp800 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9418 = insertelement <4 x float> %tmp800, float %add9417, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9418, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 3.555000e+02, float 0xC062E33340000000, float 0x4065C66660000000, float -3.645000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp801 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp802 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9420 = fadd <4 x float> %tmp802, %tmp801 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9420, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp803 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9421 = extractelement <4 x float> %tmp803, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp804 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9423 = insertelement <4 x float> %tmp804, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9423, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp805 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9424 = extractelement <4 x float> %tmp805, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9425 = fadd float %vecext9424, 0x4079C199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp806 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9426 = insertelement <4 x float> %tmp806, float %add9425, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9426, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp807 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9428 = fadd float undef, 0xC065466660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp808 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9429 = insertelement <4 x float> %tmp808, float %add9428, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9429, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp809 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9430 = extractelement <4 x float> %tmp809, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9431 = fadd float %vecext9430, 0xC0742CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp810 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9432 = insertelement <4 x float> %tmp810, float %add9431, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC07C7E6660000000, float 1.205000e+02, float 0x4050D999A0000000, float 0xC06B233340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp811 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp812 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9434 = fadd <4 x float> %tmp812, %tmp811 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9436 = fadd float undef, -3.185000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp813 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9437 = insertelement <4 x float> %tmp813, float %add9436, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp814 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp815 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9441 = extractelement <4 x float> %tmp815, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9442 = fadd float %vecext9441, 0xC079CE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp816 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9443 = insertelement <4 x float> %tmp816, float %add9442, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9443, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp817 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9444 = extractelement <4 x float> %tmp817, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9445 = fadd float %vecext9444, 0xC06F533340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp818 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9446 = insertelement <4 x float> %tmp818, float %add9445, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9446, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp819 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp820 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9448 = fadd <4 x float> %tmp820, %tmp819 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9448, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9450 = fadd float undef, 0xC0718199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp821 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9451 = insertelement <4 x float> %tmp821, float %add9450, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9451, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp822 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp823 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9454 = insertelement <4 x float> %tmp823, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9454, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp824 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9455 = extractelement <4 x float> %tmp824, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9456 = fadd float %vecext9455, -3.380000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp825 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9457 = insertelement <4 x float> %tmp825, float %add9456, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9457, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9458 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp826 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9460 = insertelement <4 x float> %tmp826, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9460, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x407B5E6660000000, float 0x40648999A0000000, float 0xC06B966660000000, float 0x40341999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp827 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9462 = fadd <4 x float> %tmp827, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9462, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp828 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9463 = extractelement <4 x float> %tmp828, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp829 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9465 = insertelement <4 x float> %tmp829, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9467 = fadd float undef, 0x405D666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp830 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9468 = insertelement <4 x float> %tmp830, float %add9467, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9468, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp831 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9470 = fadd float undef, 0x4077033340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp832 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9472 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9473 = fadd float %vecext9472, 0x402DCCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp833 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9474 = insertelement <4 x float> %tmp833, float %add9473, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9474, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x404F733340000000, float 0x407AB4CCC0000000, float 0x40605999A0000000, float 0xC03E4CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp834 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp835 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9476 = fadd <4 x float> %tmp835, %tmp834 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9476, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp836 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9477 = extractelement <4 x float> %tmp836, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9478 = fadd float %vecext9477, 0xC07F266660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp837 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9479 = insertelement <4 x float> %tmp837, float %add9478, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9479, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp838 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9481 = fadd float undef, 0x407BE33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp839 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9482 = insertelement <4 x float> %tmp839, float %add9481, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9482, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9483 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9484 = fadd float %vecext9483, 0xC073E999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp840 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9485 = insertelement <4 x float> %tmp840, float %add9484, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9485, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp841 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9486 = extractelement <4 x float> %tmp841, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9487 = fadd float %vecext9486, 0x4076E66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp842 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC076B999A0000000, float 0xC0706CCCC0000000, float 0x407904CCC0000000, float 0x407EE199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp843 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp844 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9491 = extractelement <4 x float> %tmp844, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9492 = fadd float %vecext9491, 0x407C166660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9495 = fadd float undef, 0x407DBB3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp845 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9496 = insertelement <4 x float> %tmp845, float %add9495, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9496, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp846 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9497 = extractelement <4 x float> %tmp846, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9498 = fadd float %vecext9497, 0x4042CCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp847 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9499 = insertelement <4 x float> %tmp847, float %add9498, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9499, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp848 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9501 = fadd float undef, 0x407D5CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp849 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9502 = insertelement <4 x float> %tmp849, float %add9501, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9502, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp850 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9504 = fadd <4 x float> %tmp850, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9504, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp851 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9506 = fadd float undef, 0x4076EE6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp852 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9507 = insertelement <4 x float> %tmp852, float %add9506, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9507, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp853 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9509 = fadd float undef, 0xC0535999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp854 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp855 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9511 = extractelement <4 x float> %tmp855, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9512 = fadd float %vecext9511, 0xC076766660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp856 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9513 = insertelement <4 x float> %tmp856, float %add9512, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9513, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp857 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9514 = extractelement <4 x float> %tmp857, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp858 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9516 = insertelement <4 x float> %tmp858, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9516, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x407254CCC0000000, float 0x407844CCC0000000, float 0xC04D9999A0000000, float 0xC0550CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp859 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp860 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9518 = fadd <4 x float> %tmp860, %tmp859 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp861 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp862 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9521 = insertelement <4 x float> %tmp862, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9521, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp863 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9522 = extractelement <4 x float> %tmp863, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9523 = fadd float %vecext9522, 0x4029333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp864 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9524 = insertelement <4 x float> %tmp864, float %add9523, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9524, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp865 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9526 = fadd float undef, 0x4072833340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp866 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9527 = insertelement <4 x float> %tmp866, float %add9526, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9527, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp867 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9530 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9530, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4072F4CCC0000000, float 0x4065CCCCC0000000, float 0x4051D33340000000, float 0x40680CCCC0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp868 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp869 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9532 = fadd <4 x float> %tmp869, %tmp868 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9533 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp870 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9535 = insertelement <4 x float> %tmp870, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9535, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp871 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9536 = extractelement <4 x float> %tmp871, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9537 = fadd float %vecext9536, 0xC079F199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp872 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9538 = insertelement <4 x float> %tmp872, float %add9537, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9538, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp873 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9542 = extractelement <4 x float> %tmp873, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9543 = fadd float %vecext9542, 0x4050D999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9576 = fadd float undef, 0x40219999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9577 = insertelement <4 x float> undef, float %add9576, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9577, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp874 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9580 = insertelement <4 x float> undef, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9580, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp875 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9581 = extractelement <4 x float> %tmp875, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9582 = fadd float %vecext9581, 0xC07EF33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp876 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9583 = insertelement <4 x float> %tmp876, float %add9582, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9583, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp877 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9673 = extractelement <4 x float> undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9674 = fadd float %vecext9673, 0xC04CF33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp878 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9675 = insertelement <4 x float> %tmp878, float %add9674, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9675, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9676 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9677 = fadd float %vecext9676, 1.455000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp879 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9678 = insertelement <4 x float> %tmp879, float %add9677, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp880 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9679 = extractelement <4 x float> %tmp880, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9680 = fadd float %vecext9679, 0x4073A33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp881 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9681 = insertelement <4 x float> %tmp881, float %add9680, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9681, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp882 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9682 = extractelement <4 x float> %tmp882, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp883 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9686 = fadd <4 x float> %tmp883, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9686, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp884 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9687 = extractelement <4 x float> %tmp884, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9688 = fadd float %vecext9687, 0xC046666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp885 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9689 = insertelement <4 x float> %tmp885, float %add9688, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9690 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9691 = fadd float %vecext9690, 0x4034CCCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp886 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9692 = insertelement <4 x float> %tmp886, float %add9691, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp887 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9693 = extractelement <4 x float> %tmp887, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9694 = fadd float %vecext9693, -3.710000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp888 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9695 = insertelement <4 x float> %tmp888, float %add9694, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9695, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp889 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9697 = fadd float undef, 0x4058D33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp890 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9698 = insertelement <4 x float> %tmp890, float %add9697, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9698, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4062CCCCC0000000, float 0x407AD999A0000000, float 0x40582CCCC0000000, float 0xC0712B3340000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp891 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9700 = fadd <4 x float> %tmp891, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp892 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9701 = extractelement <4 x float> %tmp892, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9702 = fadd float %vecext9701, 0x406DC33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp893 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9703 = insertelement <4 x float> %tmp893, float %add9702, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9703, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp894 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9704 = extractelement <4 x float> %tmp894, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9705 = fadd float %vecext9704, 0xC073B33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp895 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9706 = insertelement <4 x float> %tmp895, float %add9705, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9706, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9707 = extractelement <4 x float> undef, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9708 = fadd float %vecext9707, 0xC0729999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp896 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9709 = insertelement <4 x float> %tmp896, float %add9708, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9709, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp897 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9710 = extractelement <4 x float> %tmp897, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9712 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9712, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4069F33340000000, float 0xC048266660000000, float 0x40638CCCC0000000, float 0xC07EC199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp898 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9714 = fadd <4 x float> undef, %tmp898 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9714, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp899 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9715 = extractelement <4 x float> %tmp899, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp900 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9717 = insertelement <4 x float> %tmp900, float undef, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9717, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp901 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9718 = extractelement <4 x float> %tmp901, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9719 = fadd float %vecext9718, 0x406BC66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp902 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9720 = insertelement <4 x float> %tmp902, float %add9719, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9720, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp903 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9721 = extractelement <4 x float> %tmp903, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9722 = fadd float %vecext9721, -3.860000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp904 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9723 = insertelement <4 x float> %tmp904, float %add9722, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9723, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp905 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9724 = extractelement <4 x float> %tmp905, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9725 = fadd float %vecext9724, 0x407CF199A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp906 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9726 = insertelement <4 x float> %tmp906, float %add9725, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9726, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -4.575000e+02, float 0x40713E6660000000, float 0x407D133340000000, float -1.425000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp907 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9728 = fadd <4 x float> %tmp907, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9728, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp908 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9729 = extractelement <4 x float> %tmp908, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9730 = fadd float %vecext9729, 0x4079FB3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp909 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9731 = insertelement <4 x float> %tmp909, float %add9730, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9731, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp910 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9733 = fadd float undef, 0xC050F33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp911 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9734 = insertelement <4 x float> %tmp911, float %add9733, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9734, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp912 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9735 = extractelement <4 x float> %tmp912, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9736 = fadd float %vecext9735, 0x40582CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp913 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9737 = insertelement <4 x float> %tmp913, float %add9736, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9737, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp914 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9738 = extractelement <4 x float> %tmp914, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9740 = insertelement <4 x float> undef, float undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9740, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 2.150000e+02, float 0x405A2CCCC0000000, float 2.310000e+02, float 0x404E1999A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp915 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp916 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp917 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9743 = extractelement <4 x float> %tmp917, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9744 = fadd float %vecext9743, -2.510000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9745 = insertelement <4 x float> undef, float %add9744, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9745, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp918 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9746 = extractelement <4 x float> %tmp918, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9747 = fadd float %vecext9746, 4.685000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp919 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9748 = insertelement <4 x float> %tmp919, float %add9747, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9748, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp920 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9749 = extractelement <4 x float> %tmp920, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9750 = fadd float %vecext9749, 1.600000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp921 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9751 = insertelement <4 x float> %tmp921, float %add9750, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9751, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp922 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9752 = extractelement <4 x float> %tmp922, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9753 = fadd float %vecext9752, -2.600000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp923 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9754 = insertelement <4 x float> %tmp923, float %add9753, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9754, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 2.590000e+02, float 0x407B7199A0000000, float 0xC07ED199A0000000, float 0xC064FCCCC0000000>, <4 x float>* %.compoundliteral9755 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp924 = load <4 x float>, <4 x float>* %.compoundliteral9755 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp925 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9756 = fadd <4 x float> %tmp925, %tmp924 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp926 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9757 = extractelement <4 x float> %tmp926, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9758 = fadd float %vecext9757, -1.810000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp927 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9759 = insertelement <4 x float> %tmp927, float %add9758, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9759, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp928 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9760 = extractelement <4 x float> %tmp928, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9761 = fadd float %vecext9760, 0xC07C3E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp929 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9762 = insertelement <4 x float> %tmp929, float %add9761, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9762, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp930 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9764 = fadd float undef, 0xC060E66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp931 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9765 = insertelement <4 x float> %tmp931, float %add9764, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9765, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp932 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9766 = extractelement <4 x float> %tmp932, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9767 = fadd float %vecext9766, 0xC0753E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp933 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9768 = insertelement <4 x float> %tmp933, float %add9767, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9768, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4032CCCCC0000000, float -9.600000e+01, float -5.000000e+02, float 0x4078EE6660000000>, <4 x float>* %.compoundliteral9769 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp934 = load <4 x float>, <4 x float>* %.compoundliteral9769 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp935 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9770 = fadd <4 x float> %tmp935, %tmp934 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add9770, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp936 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9771 = extractelement <4 x float> %tmp936, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9772 = fadd float %vecext9771, 0xC0733E6660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp937 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9773 = insertelement <4 x float> %tmp937, float %add9772, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9773, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp938 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9774 = extractelement <4 x float> %tmp938, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add9775 = fadd float %vecext9774, 1.715000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp939 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9776 = insertelement <4 x float> %tmp939, float %add9775, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins9776, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext9816 = extractelement <4 x float> undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp940 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins9818 = insertelement <4 x float> %tmp940, float undef, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp941 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10388 = fadd float undef, 4.755000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp942 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10389 = insertelement <4 x float> %tmp942, float %add10388, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10389, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp943 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10390 = extractelement <4 x float> %tmp943, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10391 = fadd float %vecext10390, 0xC05AECCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp944 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10392 = insertelement <4 x float> %tmp944, float %add10391, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10392, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp945 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp946 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10405 = fadd float undef, -5.650000e+01 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp947 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10406 = insertelement <4 x float> %tmp947, float %add10405, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10406, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp948 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10407 = extractelement <4 x float> %tmp948, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10408 = fadd float %vecext10407, 0xC06A633340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp949 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10409 = insertelement <4 x float> %tmp949, float %add10408, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10409, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp950 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10410 = extractelement <4 x float> %tmp950, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10411 = fadd float %vecext10410, 0xC078D66660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp951 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float -2.340000e+02, float -4.720000e+02, float 4.350000e+02, float 0xC059A66660000000>, <4 x float>* %.compoundliteral10413 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp952 = load <4 x float>, <4 x float>* %.compoundliteral10413 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp953 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10414 = fadd <4 x float> %tmp953, %tmp952 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add10414, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp954 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10415 = extractelement <4 x float> %tmp954, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10416 = fadd float %vecext10415, 3.450000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp955 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10417 = insertelement <4 x float> %tmp955, float %add10416, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10417, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp956 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10418 = extractelement <4 x float> %tmp956, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10419 = fadd float %vecext10418, -6.000000e+00 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp957 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10420 = insertelement <4 x float> %tmp957, float %add10419, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10420, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10422 = fadd float undef, 0xC0662CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10424 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> undef, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x402B333340000000, float 0x40735E6660000000, float 0xC0567999A0000000, float 2.050000e+02>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp958 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp959 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10428 = fadd <4 x float> %tmp959, %tmp958 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add10428, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp960 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10429 = extractelement <4 x float> %tmp960, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10430 = fadd float %vecext10429, 0xC075166660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp961 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10436 = fadd float undef, 0xC06AF33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp962 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10437 = insertelement <4 x float> %tmp962, float %add10436, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10437, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10438 = extractelement <4 x float> undef, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10439 = fadd float %vecext10438, 0x405C7999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp963 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10440 = insertelement <4 x float> %tmp963, float %add10439, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10440, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC065E999A0000000, float 0x4067D33340000000, float 0xC070133340000000, float 0x406B666660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp964 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp965 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10443 = extractelement <4 x float> %tmp965, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10444 = fadd float %vecext10443, 0xC06CA999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp966 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10445 = insertelement <4 x float> %tmp966, float %add10444, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10445, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp967 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10446 = extractelement <4 x float> %tmp967, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10447 = fadd float %vecext10446, 0x4064B999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp968 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10448 = insertelement <4 x float> %tmp968, float %add10447, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10448, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp969 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10449 = extractelement <4 x float> %tmp969, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10450 = fadd float %vecext10449, 0x407B3CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp970 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10451 = insertelement <4 x float> %tmp970, float %add10450, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10451, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp971 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10452 = extractelement <4 x float> %tmp971, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10453 = fadd float %vecext10452, -2.225000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10454 = insertelement <4 x float> undef, float %add10453, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x406AFCCCC0000000, float 0xC07604CCC0000000, float 6.900000e+01, float 0xC060A66660000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp972 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp973 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10456 = fadd <4 x float> %tmp973, %tmp972 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %add10456, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp974 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10457 = extractelement <4 x float> %tmp974, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10458 = fadd float %vecext10457, 2.375000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10459 = insertelement <4 x float> undef, float %add10458, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10459, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp975 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10460 = extractelement <4 x float> %tmp975, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10461 = fadd float %vecext10460, 0xC06B3999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp976 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10462 = insertelement <4 x float> %tmp976, float %add10461, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp977 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10463 = extractelement <4 x float> %tmp977, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10464 = fadd float %vecext10463, 0x40655999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp978 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10465 = insertelement <4 x float> %tmp978, float %add10464, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10465, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp979 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10466 = extractelement <4 x float> %tmp979, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10467 = fadd float %vecext10466, 0xC07B6999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp980 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10468 = insertelement <4 x float> %tmp980, float %add10467, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10468, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x4078833340000000, float 0x40786CCCC0000000, float 0xC0468CCCC0000000, float 0xC0793199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp981 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10470 = fadd <4 x float> %tmp981, undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp982 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10471 = extractelement <4 x float> %tmp982, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10472 = fadd float %vecext10471, 0x40710CCCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp983 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10473 = insertelement <4 x float> %tmp983, float %add10472, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10473, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp984 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10474 = extractelement <4 x float> %tmp984, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10475 = fadd float %vecext10474, 0x40709B3340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp985 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10476 = insertelement <4 x float> %tmp985, float %add10475, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10476, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10489 = fadd float undef, 0x4074666660000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp986 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10490 = insertelement <4 x float> %tmp986, float %add10489, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10490, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp987 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp988 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10508 = extractelement <4 x float> %tmp988, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10509 = fadd float %vecext10508, 0xC027333340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp989 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10510 = insertelement <4 x float> %tmp989, float %add10509, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10510, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0x40656999A0000000, float 0xC073766660000000, float 1.685000e+02, float 0x40765199A0000000>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp990 = load <4 x float>, <4 x float>* undef + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10512 = fadd <4 x float> undef, %tmp990 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp991 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10513 = extractelement <4 x float> %tmp991, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10514 = fadd float %vecext10513, 0x405BB999A0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp992 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10515 = insertelement <4 x float> %tmp992, float %add10514, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10515, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp993 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10562 = fadd float undef, 2.035000e+02 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp994 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10563 = insertelement <4 x float> %tmp994, float %add10562, i32 2 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10563, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp995 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10564 = extractelement <4 x float> %tmp995, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10565 = fadd float %vecext10564, 0x407AE4CCC0000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp996 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10566 = insertelement <4 x float> %tmp996, float %add10565, i32 3 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10566, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> <float 0xC068B999A0000000, float 0xC050E66660000000, float 0xC0725999A0000000, float 0xC054D33340000000>, <4 x float>* %.compoundliteral10567 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp997 = load <4 x float>, <4 x float>* %.compoundliteral10567 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp998 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10568 = fadd <4 x float> %tmp998, %tmp997 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp999 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10569 = extractelement <4 x float> %tmp999, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10570 = fadd float %vecext10569, 0x4074C33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp1000 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10571 = insertelement <4 x float> %tmp1000, float %add10570, i32 0 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10571, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp1001 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecext10572 = extractelement <4 x float> %tmp1001, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %add10573 = fadd float %vecext10572, 0x407DF33340000000 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %tmp1002 = load <4 x float>, <4 x float>* undef, align 16 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + %vecins10574 = insertelement <4 x float> %tmp1002, float %add10573, i32 1 + tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q14}{q15}"() + store <4 x float> %vecins10574, <4 x float>* undef, align 16 + %tmp1003 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10575 = extractelement <4 x float> %tmp1003, i32 2 + %tmp1004 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10577 = insertelement <4 x float> %tmp1004, float undef, i32 2 + store <4 x float> %vecins10577, <4 x float>* undef, align 16 + %tmp1005 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10578 = extractelement <4 x float> %tmp1005, i32 3 + %add10579 = fadd float %vecext10578, 0x4076566660000000 + %tmp1006 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10580 = insertelement <4 x float> %tmp1006, float %add10579, i32 3 + store <4 x float> %vecins10580, <4 x float>* undef, align 16 + store <4 x float> <float 0x407CAB3340000000, float 1.685000e+02, float 0xC07B866660000000, float 0xC061ACCCC0000000>, <4 x float>* %.compoundliteral10581 + %tmp1007 = load <4 x float>, <4 x float>* %.compoundliteral10581 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1008 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10583 = extractelement <4 x float> %tmp1008, i32 0 + %add10584 = fadd float %vecext10583, 0xC060533340000000 + %tmp1009 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10585 = insertelement <4 x float> %tmp1009, float %add10584, i32 0 + store <4 x float> %vecins10585, <4 x float>* undef, align 16 + %tmp1010 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10586 = extractelement <4 x float> %tmp1010, i32 1 + %add10587 = fadd float %vecext10586, 0xC0694CCCC0000000 + %tmp1011 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10588 = insertelement <4 x float> %tmp1011, float %add10587, i32 1 + store <4 x float> %vecins10588, <4 x float>* undef, align 16 + %tmp1012 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10589 = extractelement <4 x float> %tmp1012, i32 2 + %add10590 = fadd float %vecext10589, 0xC0541999A0000000 + %tmp1013 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10591 = insertelement <4 x float> %tmp1013, float %add10590, i32 2 + store <4 x float> %vecins10591, <4 x float>* undef, align 16 + %tmp1014 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10592 = extractelement <4 x float> %tmp1014, i32 3 + %add10593 = fadd float %vecext10592, 0xC06C566660000000 + %tmp1015 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10594 = insertelement <4 x float> %tmp1015, float %add10593, i32 3 + store <4 x float> %vecins10594, <4 x float>* undef, align 16 + store <4 x float> <float 0x407A3199A0000000, float 0xC0659999A0000000, float 0x407E0999A0000000, float 0xC0334CCCC0000000>, <4 x float>* %.compoundliteral10595 + %tmp1016 = load <4 x float>, <4 x float>* %.compoundliteral10595 + %tmp1017 = load <4 x float>, <4 x float>* undef, align 16 + %add10596 = fadd <4 x float> %tmp1017, %tmp1016 + store <4 x float> %add10596, <4 x float>* undef, align 16 + %tmp1018 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10597 = extractelement <4 x float> %tmp1018, i32 0 + %add10598 = fadd float %vecext10597, 0x40640999A0000000 + %tmp1019 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10599 = insertelement <4 x float> %tmp1019, float %add10598, i32 0 + store <4 x float> %vecins10599, <4 x float>* undef, align 16 + %tmp1020 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10600 = extractelement <4 x float> %tmp1020, i32 1 + %add10601 = fadd float %vecext10600, 0xC073966660000000 + %tmp1021 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10602 = insertelement <4 x float> %tmp1021, float %add10601, i32 1 + %tmp1022 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10603 = extractelement <4 x float> %tmp1022, i32 2 + %add10604 = fadd float %vecext10603, 1.780000e+02 + %tmp1023 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10605 = insertelement <4 x float> %tmp1023, float %add10604, i32 2 + store <4 x float> %vecins10605, <4 x float>* undef, align 16 + %tmp1024 = load <4 x float>, <4 x float>* undef, align 16 + %add10607 = fadd float undef, 0x4070A33340000000 + %tmp1025 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> <float 0x407C5999A0000000, float 0x4046733340000000, float 0xC06E6CCCC0000000, float 0xC063C33340000000>, <4 x float>* %.compoundliteral10609 + %tmp1026 = load <4 x float>, <4 x float>* %.compoundliteral10609 + %tmp1027 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1028 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10611 = extractelement <4 x float> %tmp1028, i32 0 + %add10612 = fadd float %vecext10611, 0x40757199A0000000 + %vecins10613 = insertelement <4 x float> undef, float %add10612, i32 0 + store <4 x float> %vecins10613, <4 x float>* undef, align 16 + %tmp1029 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10614 = extractelement <4 x float> %tmp1029, i32 1 + %add10615 = fadd float %vecext10614, 0x40740CCCC0000000 + %tmp1030 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10616 = insertelement <4 x float> %tmp1030, float %add10615, i32 1 + store <4 x float> %vecins10616, <4 x float>* undef, align 16 + %tmp1031 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10617 = extractelement <4 x float> %tmp1031, i32 2 + %add10618 = fadd float %vecext10617, 0xC012CCCCC0000000 + %tmp1032 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10619 = insertelement <4 x float> %tmp1032, float %add10618, i32 2 + store <4 x float> %vecins10619, <4 x float>* undef, align 16 + %tmp1033 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10620 = extractelement <4 x float> %tmp1033, i32 3 + %add10621 = fadd float %vecext10620, 0x406E566660000000 + %tmp1034 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> <float 0x407B2199A0000000, float 0xC07D9CCCC0000000, float -4.350000e+01, float 0xC07D3B3340000000>, <4 x float>* %.compoundliteral10623 + %tmp1035 = load <4 x float>, <4 x float>* %.compoundliteral10623 + %add10624 = fadd <4 x float> undef, %tmp1035 + %tmp1036 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10625 = extractelement <4 x float> %tmp1036, i32 0 + %tmp1037 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10627 = insertelement <4 x float> %tmp1037, float undef, i32 0 + store <4 x float> %vecins10627, <4 x float>* undef, align 16 + %tmp1038 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10628 = extractelement <4 x float> %tmp1038, i32 1 + %add10629 = fadd float %vecext10628, 0x407E3CCCC0000000 + %tmp1039 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10630 = insertelement <4 x float> %tmp1039, float %add10629, i32 1 + store <4 x float> %vecins10630, <4 x float>* undef, align 16 + %tmp1040 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10631 = extractelement <4 x float> %tmp1040, i32 2 + %tmp1041 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1042 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10634 = extractelement <4 x float> %tmp1042, i32 3 + %add10635 = fadd float %vecext10634, 0xC067533340000000 + %tmp1043 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10636 = insertelement <4 x float> %tmp1043, float %add10635, i32 3 + store <4 x float> %vecins10636, <4 x float>* undef, align 16 + store <4 x float> <float 1.950000e+02, float 0x407E8E6660000000, float 0x407D7CCCC0000000, float 0x407E166660000000>, <4 x float>* %.compoundliteral10637 + %tmp1044 = load <4 x float>, <4 x float>* undef, align 16 + %add10638 = fadd <4 x float> %tmp1044, undef + %tmp1045 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10639 = extractelement <4 x float> %tmp1045, i32 0 + %add10640 = fadd float %vecext10639, 0x406CA33340000000 + %tmp1046 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10641 = insertelement <4 x float> %tmp1046, float %add10640, i32 0 + store <4 x float> %vecins10641, <4 x float>* undef, align 16 + %tmp1047 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10642 = extractelement <4 x float> %tmp1047, i32 1 + %add10643 = fadd float %vecext10642, 0xC07C8999A0000000 + %tmp1048 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10644 = insertelement <4 x float> %tmp1048, float %add10643, i32 1 + store <4 x float> %vecins10644, <4 x float>* undef, align 16 + %tmp1049 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10645 = extractelement <4 x float> %tmp1049, i32 2 + %tmp1050 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1051 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10748 = insertelement <4 x float> undef, float undef, i32 3 + %tmp1052 = load <4 x float>, <4 x float>* %.compoundliteral10749 + %add10750 = fadd <4 x float> undef, %tmp1052 + store <4 x float> %add10750, <4 x float>* undef, align 16 + %tmp1053 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10751 = extractelement <4 x float> %tmp1053, i32 0 + %add10752 = fadd float %vecext10751, 0x4071B33340000000 + %tmp1054 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10753 = insertelement <4 x float> %tmp1054, float %add10752, i32 0 + store <4 x float> %vecins10753, <4 x float>* undef, align 16 + %tmp1055 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10754 = extractelement <4 x float> %tmp1055, i32 1 + %add10755 = fadd float %vecext10754, 0xC076A66660000000 + %tmp1056 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10756 = insertelement <4 x float> %tmp1056, float %add10755, i32 1 + store <4 x float> %vecins10756, <4 x float>* undef, align 16 + %tmp1057 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10757 = extractelement <4 x float> %tmp1057, i32 2 + %add10758 = fadd float %vecext10757, 3.800000e+01 + %tmp1058 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10759 = insertelement <4 x float> %tmp1058, float %add10758, i32 2 + store <4 x float> %vecins10759, <4 x float>* undef, align 16 + %tmp1059 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10760 = extractelement <4 x float> %tmp1059, i32 3 + store <4 x float> undef, <4 x float>* undef, align 16 + store <4 x float> <float 0xC075BB3340000000, float 0x4074D4CCC0000000, float 0xC07A466660000000, float 0xC0691CCCC0000000>, <4 x float>* %.compoundliteral10763 + %tmp1060 = load <4 x float>, <4 x float>* %.compoundliteral10763 + %tmp1061 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1062 = load <4 x float>, <4 x float>* undef, align 16 + %add10985 = fadd float undef, 0x405E933340000000 + %tmp1063 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10986 = insertelement <4 x float> %tmp1063, float %add10985, i32 3 + store <4 x float> %vecins10986, <4 x float>* undef, align 16 + store <4 x float> <float 0xC0721E6660000000, float -4.180000e+02, float 0x406F366660000000, float 0xC055F999A0000000>, <4 x float>* %.compoundliteral10987 + %tmp1064 = load <4 x float>, <4 x float>* %.compoundliteral10987 + %tmp1065 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10994 = insertelement <4 x float> %tmp1065, float undef, i32 1 + %tmp1066 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10995 = extractelement <4 x float> %tmp1066, i32 2 + %add10996 = fadd float %vecext10995, 0x406F9999A0000000 + %tmp1067 = load <4 x float>, <4 x float>* undef, align 16 + %vecins10997 = insertelement <4 x float> %tmp1067, float %add10996, i32 2 + store <4 x float> %vecins10997, <4 x float>* undef, align 16 + %tmp1068 = load <4 x float>, <4 x float>* undef, align 16 + %vecext10998 = extractelement <4 x float> %tmp1068, i32 3 + %add10999 = fadd float %vecext10998, -2.765000e+02 + %tmp1069 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11000 = insertelement <4 x float> %tmp1069, float %add10999, i32 3 + store <4 x float> %vecins11000, <4 x float>* undef, align 16 + store <4 x float> <float 0x4078F999A0000000, float 0xC06D166660000000, float 0x40501999A0000000, float 0x406FC999A0000000>, <4 x float>* %.compoundliteral11001 + %tmp1070 = load <4 x float>, <4 x float>* undef, align 16 + %add11002 = fadd <4 x float> %tmp1070, undef + %vecext11003 = extractelement <4 x float> undef, i32 0 + %vecext11009 = extractelement <4 x float> undef, i32 2 + %tmp1071 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11033 = insertelement <4 x float> %tmp1071, float undef, i32 0 + store <4 x float> %vecins11033, <4 x float>* undef, align 16 + %tmp1072 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11034 = extractelement <4 x float> %tmp1072, i32 1 + %add11035 = fadd float %vecext11034, 0x4056D33340000000 + %tmp1073 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11036 = insertelement <4 x float> %tmp1073, float %add11035, i32 1 + store <4 x float> %vecins11036, <4 x float>* undef, align 16 + %tmp1074 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11037 = extractelement <4 x float> %tmp1074, i32 2 + %add11038 = fadd float %vecext11037, 0xC06EA33340000000 + %tmp1075 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1076 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11040 = extractelement <4 x float> %tmp1076, i32 3 + %add11041 = fadd float %vecext11040, 0x40746CCCC0000000 + %tmp1077 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11042 = insertelement <4 x float> %tmp1077, float %add11041, i32 3 + store <4 x float> <float 0x405DD999A0000000, float -3.775000e+02, float -1.265000e+02, float 0xC065C66660000000>, <4 x float>* undef + %tmp1078 = load <4 x float>, <4 x float>* undef, align 16 + %add11044 = fadd <4 x float> %tmp1078, undef + store <4 x float> %add11044, <4 x float>* undef, align 16 + %tmp1079 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11045 = extractelement <4 x float> %tmp1079, i32 0 + %add11046 = fadd float %vecext11045, 0xC076E66660000000 + %tmp1080 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11047 = insertelement <4 x float> %tmp1080, float %add11046, i32 0 + %tmp1081 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11048 = extractelement <4 x float> %tmp1081, i32 1 + %add11049 = fadd float %vecext11048, 4.100000e+02 + %vecins11064 = insertelement <4 x float> undef, float undef, i32 1 + %add11074 = fadd float undef, 0xC06FF999A0000000 + %tmp1082 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11075 = insertelement <4 x float> %tmp1082, float %add11074, i32 0 + store <4 x float> %vecins11075, <4 x float>* undef, align 16 + %add11077 = fadd float undef, 0xC075D33340000000 + %tmp1083 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1084 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1085 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11093 = extractelement <4 x float> %tmp1085, i32 2 + %add11094 = fadd float %vecext11093, 0xC07CD66660000000 + %tmp1086 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11095 = insertelement <4 x float> %tmp1086, float %add11094, i32 2 + store <4 x float> %vecins11095, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + store <4 x float> <float 0x4061F66660000000, float 0xC076DB3340000000, float 0xC055A66660000000, float 2.415000e+02>, <4 x float>* undef + %tmp1087 = load <4 x float>, <4 x float>* undef + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1088 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11513 = extractelement <4 x float> %tmp1088, i32 2 + %add11514 = fadd float %vecext11513, 0xC07C7199A0000000 + %vecins11515 = insertelement <4 x float> undef, float %add11514, i32 2 + store <4 x float> %vecins11515, <4 x float>* undef, align 16 + %add11520 = fadd <4 x float> undef, undef + store <4 x float> %add11520, <4 x float>* undef, align 16 + %vecext11521 = extractelement <4 x float> undef, i32 0 + %add11522 = fadd float %vecext11521, 0x4041733340000000 + %tmp1089 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1090 = load <4 x float>, <4 x float>* undef + %tmp1091 = load <4 x float>, <4 x float>* undef, align 16 + %add11562 = fadd <4 x float> %tmp1091, %tmp1090 + %tmp1092 = load <4 x float>, <4 x float>* undef, align 16 + %add11564 = fadd float undef, 0xC0411999A0000000 + %tmp1093 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11565 = insertelement <4 x float> %tmp1093, float %add11564, i32 0 + store <4 x float> undef, <4 x float>* undef, align 16 + %vecext11586 = extractelement <4 x float> undef, i32 3 + %add11587 = fadd float %vecext11586, 3.760000e+02 + %tmp1094 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + store <4 x float> <float 0xC06ED999A0000000, float 1.380000e+02, float 0xC073AB3340000000, float 0x4078A66660000000>, <4 x float>* undef + %tmp1095 = load <4 x float>, <4 x float>* undef + %tmp1096 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1097 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1098 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11593 = insertelement <4 x float> %tmp1098, float undef, i32 0 + %vecext11594 = extractelement <4 x float> undef, i32 1 + %tmp1099 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11596 = insertelement <4 x float> %tmp1099, float undef, i32 1 + store <4 x float> %vecins11596, <4 x float>* undef, align 16 + %tmp1100 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11597 = extractelement <4 x float> %tmp1100, i32 2 + %add11598 = fadd float %vecext11597, 0x40430CCCC0000000 + %tmp1101 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11599 = insertelement <4 x float> %tmp1101, float %add11598, i32 2 + %tmp1102 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11600 = extractelement <4 x float> %tmp1102, i32 3 + %tmp1103 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11602 = insertelement <4 x float> %tmp1103, float undef, i32 3 + store <4 x float> %vecins11602, <4 x float>* undef, align 16 + %tmp1104 = load <4 x float>, <4 x float>* undef + %tmp1105 = load <4 x float>, <4 x float>* undef, align 16 + %add11604 = fadd <4 x float> %tmp1105, %tmp1104 + %tmp1106 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11605 = extractelement <4 x float> %tmp1106, i32 0 + %tmp1107 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11607 = insertelement <4 x float> %tmp1107, float undef, i32 0 + %vecins11621 = insertelement <4 x float> undef, float undef, i32 0 + %vecins11630 = insertelement <4 x float> undef, float undef, i32 3 + store <4 x float> %vecins11630, <4 x float>* undef, align 16 + store <4 x float> <float -1.190000e+02, float 0x402F666660000000, float 0xC07BD33340000000, float -1.595000e+02>, <4 x float>* %.compoundliteral11631 + %tmp1108 = load <4 x float>, <4 x float>* %.compoundliteral11631 + %tmp1109 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %add11634 = fadd float undef, -1.075000e+02 + %vecext11647 = extractelement <4 x float> undef, i32 0 + %add11648 = fadd float %vecext11647, 0x40775999A0000000 + %tmp1110 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11650 = extractelement <4 x float> undef, i32 1 + %tmp1111 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11784 = insertelement <4 x float> %tmp1111, float undef, i32 3 + store <4 x float> %vecins11784, <4 x float>* undef, align 16 + store <4 x float> <float 1.605000e+02, float 0x4068366660000000, float 2.820000e+02, float 0x407CF66660000000>, <4 x float>* %.compoundliteral11785 + %tmp1112 = load <4 x float>, <4 x float>* %.compoundliteral11785 + %add11786 = fadd <4 x float> undef, %tmp1112 + store <4 x float> %add11786, <4 x float>* undef, align 16 + %tmp1113 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11787 = extractelement <4 x float> %tmp1113, i32 0 + %vecext11807 = extractelement <4 x float> undef, i32 2 + %add11808 = fadd float %vecext11807, 4.535000e+02 + %tmp1114 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11810 = extractelement <4 x float> undef, i32 3 + %add11811 = fadd float %vecext11810, 0x4068F66660000000 + %tmp1115 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11812 = insertelement <4 x float> %tmp1115, float %add11811, i32 3 + store <4 x float> %vecins11812, <4 x float>* undef, align 16 + %tmp1116 = load <4 x float>, <4 x float>* undef + %tmp1117 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11958 = extractelement <4 x float> undef, i32 1 + store <4 x float> undef, <4 x float>* undef, align 16 + %vecext11961 = extractelement <4 x float> undef, i32 2 + %add11962 = fadd float %vecext11961, -3.680000e+02 + %tmp1118 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %add11965 = fadd float undef, 0x4061133340000000 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1119 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11975 = extractelement <4 x float> %tmp1119, i32 2 + %tmp1120 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11977 = insertelement <4 x float> %tmp1120, float undef, i32 2 + store <4 x float> %vecins11977, <4 x float>* undef, align 16 + %vecext11978 = extractelement <4 x float> undef, i32 3 + %add11979 = fadd float %vecext11978, 0xC0688999A0000000 + %tmp1121 = load <4 x float>, <4 x float>* undef, align 16 + %vecins11980 = insertelement <4 x float> %tmp1121, float %add11979, i32 3 + store <4 x float> %vecins11980, <4 x float>* undef, align 16 + %add11982 = fadd <4 x float> undef, undef + store <4 x float> %add11982, <4 x float>* undef, align 16 + %tmp1122 = load <4 x float>, <4 x float>* undef, align 16 + %vecext11983 = extractelement <4 x float> %tmp1122, i32 0 + %add11984 = fadd float %vecext11983, 0xC075966660000000 + %tmp1123 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12005 = insertelement <4 x float> undef, float undef, i32 2 + store <4 x float> %vecins12005, <4 x float>* undef, align 16 + %tmp1124 = load <4 x float>, <4 x float>* undef, align 16 + %add12007 = fadd float undef, 0xC07124CCC0000000 + %vecins12008 = insertelement <4 x float> undef, float %add12007, i32 3 + store <4 x float> %vecins12008, <4 x float>* undef, align 16 + %tmp1125 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1126 = load <4 x float>, <4 x float>* undef, align 16 + %add12012 = fadd float undef, 0xC0750CCCC0000000 + %tmp1127 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12013 = insertelement <4 x float> %tmp1127, float %add12012, i32 0 + store <4 x float> %vecins12013, <4 x float>* undef, align 16 + %tmp1128 = load <4 x float>, <4 x float>* undef, align 16 + %add12015 = fadd float undef, 0x4079CE6660000000 + %tmp1129 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12016 = insertelement <4 x float> %tmp1129, float %add12015, i32 1 + store <4 x float> %vecins12016, <4 x float>* undef, align 16 + %add12018 = fadd float undef, 3.555000e+02 + %tmp1130 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12019 = insertelement <4 x float> %tmp1130, float %add12018, i32 2 + %tmp1131 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12020 = extractelement <4 x float> %tmp1131, i32 3 + store <4 x float> undef, <4 x float>* undef, align 16 + %vecext12028 = extractelement <4 x float> undef, i32 1 + store <4 x float> undef, <4 x float>* undef, align 16 + store <4 x float> <float 0x40791999A0000000, float 0x407C7CCCC0000000, float 0x4070F33340000000, float 0xC056ECCCC0000000>, <4 x float>* undef + %tmp1132 = load <4 x float>, <4 x float>* undef, align 16 + %add12038 = fadd <4 x float> %tmp1132, undef + %tmp1133 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12042 = extractelement <4 x float> %tmp1133, i32 1 + %add12043 = fadd float %vecext12042, 0x402F9999A0000000 + %tmp1134 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12044 = insertelement <4 x float> %tmp1134, float %add12043, i32 1 + store <4 x float> %vecins12044, <4 x float>* undef, align 16 + %vecext12045 = extractelement <4 x float> undef, i32 2 + %add12046 = fadd float %vecext12045, 0xC07EF33340000000 + %tmp1135 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12047 = insertelement <4 x float> %tmp1135, float %add12046, i32 2 + store <4 x float> %vecins12047, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1136 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12112 = extractelement <4 x float> %tmp1136, i32 1 + %tmp1137 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %add12116 = fadd float undef, 0xC074F4CCC0000000 + %tmp1138 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12117 = insertelement <4 x float> %tmp1138, float %add12116, i32 2 + store <4 x float> %vecins12117, <4 x float>* undef, align 16 + %tmp1139 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12118 = extractelement <4 x float> %tmp1139, i32 3 + %add12119 = fadd float %vecext12118, 0xC0638CCCC0000000 + %tmp1140 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12120 = insertelement <4 x float> %tmp1140, float %add12119, i32 3 + %add12152 = fadd float undef, 0x4039333340000000 + %tmp1141 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12153 = insertelement <4 x float> %tmp1141, float %add12152, i32 0 + %vecext12154 = extractelement <4 x float> undef, i32 1 + %add12155 = fadd float %vecext12154, 0xC07BBB3340000000 + %tmp1142 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12156 = insertelement <4 x float> %tmp1142, float %add12155, i32 1 + %tmp1143 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12157 = extractelement <4 x float> %tmp1143, i32 2 + %add12158 = fadd float %vecext12157, 0xC0428CCCC0000000 + %tmp1144 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12159 = insertelement <4 x float> %tmp1144, float %add12158, i32 2 + %tmp1145 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12160 = extractelement <4 x float> %tmp1145, i32 3 + %add12161 = fadd float %vecext12160, 0x407B1999A0000000 + %tmp1146 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12162 = insertelement <4 x float> %tmp1146, float %add12161, i32 3 + store <4 x float> %vecins12162, <4 x float>* undef, align 16 + %tmp1147 = load <4 x float>, <4 x float>* undef + %tmp1148 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1149 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12182 = extractelement <4 x float> %tmp1149, i32 1 + %tmp1150 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + store <4 x float> <float 0x4061833340000000, float 0x405CA66660000000, float -1.275000e+02, float 0x405BC66660000000>, <4 x float>* undef + %add12208 = fadd float undef, 0x407854CCC0000000 + %tmp1151 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1152 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1153 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12218 = insertelement <4 x float> undef, float undef, i32 3 + store <4 x float> %vecins12218, <4 x float>* undef, align 16 + store <4 x float> <float 0x407C3CCCC0000000, float 0xC057C66660000000, float 2.605000e+02, float 0xC07974CCC0000000>, <4 x float>* undef + %tmp1154 = load <4 x float>, <4 x float>* undef + %tmp1155 = load <4 x float>, <4 x float>* undef, align 16 + %add12220 = fadd <4 x float> %tmp1155, %tmp1154 + %tmp1156 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1157 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12223 = insertelement <4 x float> %tmp1157, float undef, i32 0 + store <4 x float> %vecins12223, <4 x float>* undef, align 16 + %tmp1158 = load <4 x float>, <4 x float>* undef, align 16 + %add12242 = fadd float undef, 0x4067E33340000000 + %tmp1159 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12243 = insertelement <4 x float> %tmp1159, float %add12242, i32 2 + store <4 x float> %vecins12243, <4 x float>* undef, align 16 + %tmp1160 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12244 = extractelement <4 x float> %tmp1160, i32 3 + %add12245 = fadd float %vecext12244, 0x4071AE6660000000 + %tmp1161 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12246 = insertelement <4 x float> %tmp1161, float %add12245, i32 3 + store <4 x float> %vecins12246, <4 x float>* undef, align 16 + store <4 x float> <float -4.880000e+02, float 0xC079966660000000, float -8.450000e+01, float 0xC0464CCCC0000000>, <4 x float>* %.compoundliteral12247 + %tmp1162 = load <4 x float>, <4 x float>* %.compoundliteral12247 + %tmp1163 = load <4 x float>, <4 x float>* undef, align 16 + %add12248 = fadd <4 x float> %tmp1163, %tmp1162 + store <4 x float> %add12248, <4 x float>* undef, align 16 + %tmp1164 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12249 = extractelement <4 x float> %tmp1164, i32 0 + %add12250 = fadd float %vecext12249, 1.075000e+02 + %tmp1165 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1166 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12252 = extractelement <4 x float> %tmp1166, i32 1 + %add12253 = fadd float %vecext12252, 0xC0662CCCC0000000 + %tmp1167 = load <4 x float>, <4 x float>* undef, align 16 + %vecins12254 = insertelement <4 x float> %tmp1167, float %add12253, i32 1 + store <4 x float> %vecins12254, <4 x float>* undef, align 16 + %tmp1168 = load <4 x float>, <4 x float>* undef, align 16 + %vecext12255 = extractelement <4 x float> %tmp1168, i32 2 + %add12256 = fadd float %vecext12255, 0x40554CCCC0000000 + store <4 x float> undef, <4 x float>* undef, align 16 + %add13141 = fadd float undef, 0x40768999A0000000 + %tmp1169 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13142 = insertelement <4 x float> %tmp1169, float %add13141, i32 3 + store <4 x float> %vecins13142, <4 x float>* undef, align 16 + %tmp1170 = load <4 x float>, <4 x float>* undef + %add13144 = fadd <4 x float> undef, %tmp1170 + store <4 x float> %add13144, <4 x float>* undef, align 16 + %tmp1171 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13145 = extractelement <4 x float> %tmp1171, i32 0 + %add13146 = fadd float %vecext13145, 3.975000e+02 + %tmp1172 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13378 = extractelement <4 x float> %tmp1172, i32 3 + %add13379 = fadd float %vecext13378, 0xC053B33340000000 + %tmp1173 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13380 = insertelement <4 x float> %tmp1173, float %add13379, i32 3 + store <4 x float> %vecins13380, <4 x float>* undef, align 16 + %tmp1174 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13408 = insertelement <4 x float> %tmp1174, float undef, i32 3 + store <4 x float> %vecins13408, <4 x float>* undef, align 16 + store <4 x float> <float 0xC0455999A0000000, float 0xC07D366660000000, float 4.240000e+02, float -1.670000e+02>, <4 x float>* undef + %tmp1175 = load <4 x float>, <4 x float>* undef + %tmp1176 = load <4 x float>, <4 x float>* undef, align 16 + %add13410 = fadd <4 x float> %tmp1176, %tmp1175 + store <4 x float> %add13410, <4 x float>* undef, align 16 + %tmp1177 = load <4 x float>, <4 x float>* undef, align 16 + %add13412 = fadd float undef, 0xC0708999A0000000 + %tmp1178 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13413 = insertelement <4 x float> %tmp1178, float %add13412, i32 0 + store <4 x float> undef, <4 x float>* undef, align 16 + %vecext13428 = extractelement <4 x float> undef, i32 1 + %add13429 = fadd float %vecext13428, 0xC063BCCCC0000000 + %tmp1179 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13430 = insertelement <4 x float> %tmp1179, float %add13429, i32 1 + store <4 x float> %vecins13430, <4 x float>* undef, align 16 + %tmp1180 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13431 = extractelement <4 x float> %tmp1180, i32 2 + %vecins13433 = insertelement <4 x float> undef, float undef, i32 2 + store <4 x float> undef, <4 x float>* undef, align 16 + %add13449 = fadd float undef, 4.590000e+02 + %tmp1181 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13450 = insertelement <4 x float> %tmp1181, float %add13449, i32 3 + store <4 x float> %vecins13450, <4 x float>* undef, align 16 + store <4 x float> <float 0xC073A66660000000, float 0xC041B33340000000, float 0x4066233340000000, float 0x4071C33340000000>, <4 x float>* undef + %tmp1182 = load <4 x float>, <4 x float>* undef + %tmp1183 = load <4 x float>, <4 x float>* undef, align 16 + %add13452 = fadd <4 x float> %tmp1183, %tmp1182 + store <4 x float> %add13452, <4 x float>* undef, align 16 + %tmp1184 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13453 = extractelement <4 x float> %tmp1184, i32 0 + %add13454 = fadd float %vecext13453, 0xC072866660000000 + %tmp1185 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13455 = insertelement <4 x float> %tmp1185, float %add13454, i32 0 + %add13471 = fadd float undef, 0xC0556CCCC0000000 + %tmp1186 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13472 = insertelement <4 x float> %tmp1186, float %add13471, i32 1 + store <4 x float> %vecins13472, <4 x float>* undef, align 16 + %tmp1187 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13473 = extractelement <4 x float> %tmp1187, i32 2 + %add13474 = fadd float %vecext13473, 0xC0786999A0000000 + %tmp1188 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13475 = insertelement <4 x float> %tmp1188, float %add13474, i32 2 + store <4 x float> %vecins13475, <4 x float>* undef, align 16 + %add13477 = fadd float undef, 0xC07C3E6660000000 + %tmp1189 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13478 = insertelement <4 x float> %tmp1189, float %add13477, i32 3 + store <4 x float> %vecins13478, <4 x float>* undef, align 16 + store <4 x float> <float -4.740000e+02, float 0x4023CCCCC0000000, float 0xC05C266660000000, float 0x407B7199A0000000>, <4 x float>* undef + %tmp1190 = load <4 x float>, <4 x float>* undef, align 16 + %add13480 = fadd <4 x float> %tmp1190, undef + store <4 x float> %add13480, <4 x float>* undef, align 16 + %tmp1191 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13481 = extractelement <4 x float> %tmp1191, i32 0 + %add13482 = fadd float %vecext13481, 0xC07BA4CCC0000000 + %tmp1192 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13483 = insertelement <4 x float> %tmp1192, float %add13482, i32 0 + store <4 x float> %vecins13483, <4 x float>* undef, align 16 + %tmp1193 = load <4 x float>, <4 x float>* undef, align 16 + %add13485 = fadd float undef, 0x406B1999A0000000 + %tmp1194 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13486 = insertelement <4 x float> %tmp1194, float %add13485, i32 1 + store <4 x float> %vecins13486, <4 x float>* undef, align 16 + %tmp1195 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13487 = extractelement <4 x float> %tmp1195, i32 2 + %add13488 = fadd float %vecext13487, 0x40647999A0000000 + %tmp1196 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13489 = insertelement <4 x float> %tmp1196, float %add13488, i32 2 + store <4 x float> %vecins13489, <4 x float>* undef, align 16 + %tmp1197 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13490 = extractelement <4 x float> %tmp1197, i32 3 + %tmp1198 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13492 = insertelement <4 x float> %tmp1198, float undef, i32 3 + store <4 x float> %vecins13492, <4 x float>* undef, align 16 + %tmp1199 = load <4 x float>, <4 x float>* %.compoundliteral13493 + %tmp1200 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %vecins13548 = insertelement <4 x float> undef, float undef, i32 3 + store <4 x float> <float 4.540000e+02, float 3.760000e+02, float 0x406EA33340000000, float 0x405AACCCC0000000>, <4 x float>* %.compoundliteral13549 + %tmp1201 = load <4 x float>, <4 x float>* undef, align 16 + %add13552 = fadd float undef, 3.230000e+02 + %tmp1202 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13553 = insertelement <4 x float> %tmp1202, float %add13552, i32 0 + %tmp1203 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13554 = extractelement <4 x float> %tmp1203, i32 1 + %tmp1204 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13556 = insertelement <4 x float> %tmp1204, float undef, i32 1 + store <4 x float> %vecins13556, <4 x float>* undef, align 16 + %tmp1205 = load <4 x float>, <4 x float>* undef, align 16 + %add13558 = fadd float undef, 2.625000e+02 + %tmp1206 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13559 = insertelement <4 x float> %tmp1206, float %add13558, i32 2 + store <4 x float> %vecins13559, <4 x float>* undef, align 16 + %add13575 = fadd float undef, -4.725000e+02 + %tmp1207 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13576 = insertelement <4 x float> %tmp1207, float %add13575, i32 3 + store <4 x float> %vecins13576, <4 x float>* undef, align 16 + store <4 x float> <float 0x40334CCCC0000000, float 0xC0785CCCC0000000, float 0xC078D66660000000, float 3.745000e+02>, <4 x float>* undef + %tmp1208 = load <4 x float>, <4 x float>* undef + %tmp1209 = load <4 x float>, <4 x float>* undef, align 16 + %add13578 = fadd <4 x float> %tmp1209, %tmp1208 + store <4 x float> %add13578, <4 x float>* undef, align 16 + %tmp1210 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1211 = load <4 x float>, <4 x float>* undef, align 16 + %add13592 = fadd <4 x float> %tmp1211, undef + store <4 x float> %add13592, <4 x float>* undef, align 16 + %tmp1212 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13593 = extractelement <4 x float> %tmp1212, i32 0 + %add13594 = fadd float %vecext13593, 0xC0708B3340000000 + %tmp1213 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1214 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13596 = extractelement <4 x float> %tmp1214, i32 1 + %add13597 = fadd float %vecext13596, 0x40660999A0000000 + %vecins13604 = insertelement <4 x float> undef, float undef, i32 3 + store <4 x float> %vecins13604, <4 x float>* undef, align 16 + store <4 x float> <float 0x407B4999A0000000, float 0xC067F66660000000, float 0xC068F999A0000000, float 0xC079233340000000>, <4 x float>* undef + %tmp1215 = load <4 x float>, <4 x float>* undef, align 16 + %add13606 = fadd <4 x float> %tmp1215, undef + %tmp1216 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13607 = extractelement <4 x float> %tmp1216, i32 0 + %vecins13609 = insertelement <4 x float> undef, float undef, i32 0 + %tmp1217 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1218 = load <4 x float>, <4 x float>* undef, align 16 + %add13622 = fadd float undef, -3.390000e+02 + %vecins13623 = insertelement <4 x float> undef, float %add13622, i32 0 + store <4 x float> %vecins13623, <4 x float>* undef, align 16 + %tmp1219 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13624 = extractelement <4 x float> %tmp1219, i32 1 + %add13625 = fadd float %vecext13624, 0x405C3999A0000000 + %vecext13627 = extractelement <4 x float> undef, i32 2 + %add13628 = fadd float %vecext13627, 0xC067033340000000 + %tmp1220 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1221 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13630 = extractelement <4 x float> %tmp1221, i32 3 + %add13631 = fadd float %vecext13630, 0xC060333340000000 + %tmp1222 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13632 = insertelement <4 x float> %tmp1222, float %add13631, i32 3 + store <4 x float> %vecins13632, <4 x float>* undef, align 16 + store <4 x float> <float 0x4078D66660000000, float 0x4048B33340000000, float 0x4051466660000000, float -2.965000e+02>, <4 x float>* undef + %tmp1223 = load <4 x float>, <4 x float>* undef + %tmp1224 = load <4 x float>, <4 x float>* undef, align 16 + %add13634 = fadd <4 x float> %tmp1224, %tmp1223 + store <4 x float> %add13634, <4 x float>* undef, align 16 + %vecext13635 = extractelement <4 x float> undef, i32 0 + %add13636 = fadd float %vecext13635, 0x406A5999A0000000 + %tmp1225 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13637 = insertelement <4 x float> %tmp1225, float %add13636, i32 0 + store <4 x float> %vecins13637, <4 x float>* undef, align 16 + %tmp1226 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1227 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13643 = insertelement <4 x float> %tmp1227, float undef, i32 2 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1228 = load <4 x float>, <4 x float>* undef, align 16 + %add13785 = fadd float undef, 0x4068866660000000 + %tmp1229 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13786 = insertelement <4 x float> %tmp1229, float %add13785, i32 3 + store <4 x float> %vecins13786, <4 x float>* undef, align 16 + store <4 x float> <float 0x407704CCC0000000, float 0x4047B33340000000, float 0x40797B3340000000, float 0xC0652CCCC0000000>, <4 x float>* %.compoundliteral13787 + %tmp1230 = load <4 x float>, <4 x float>* undef, align 16 + %add13788 = fadd <4 x float> %tmp1230, undef + %tmp1231 = load <4 x float>, <4 x float>* undef + %tmp1232 = load <4 x float>, <4 x float>* undef, align 16 + %add13802 = fadd <4 x float> %tmp1232, %tmp1231 + store <4 x float> %add13802, <4 x float>* undef, align 16 + %tmp1233 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13803 = extractelement <4 x float> %tmp1233, i32 0 + %add13804 = fadd float %vecext13803, -2.900000e+01 + %tmp1234 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13805 = insertelement <4 x float> %tmp1234, float %add13804, i32 0 + store <4 x float> %vecins13805, <4 x float>* undef, align 16 + %tmp1235 = load <4 x float>, <4 x float>* undef, align 16 + %add13807 = fadd float undef, 6.400000e+01 + %tmp1236 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1237 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13809 = extractelement <4 x float> %tmp1237, i32 2 + %tmp1238 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13812 = extractelement <4 x float> %tmp1238, i32 3 + %add13813 = fadd float %vecext13812, -3.615000e+02 + %vecins13814 = insertelement <4 x float> undef, float %add13813, i32 3 + store <4 x float> %vecins13814, <4 x float>* undef, align 16 + store <4 x float> <float -2.270000e+02, float -1.500000e+01, float 0x407084CCC0000000, float -1.425000e+02>, <4 x float>* undef + %tmp1239 = load <4 x float>, <4 x float>* undef + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1240 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13817 = extractelement <4 x float> %tmp1240, i32 0 + %vecins13856 = insertelement <4 x float> undef, float undef, i32 3 + store <4 x float> %vecins13856, <4 x float>* undef, align 16 + store <4 x float> <float 0x40656CCCC0000000, float 0xC0656999A0000000, float 0x40778E6660000000, float 0x407ECE6660000000>, <4 x float>* undef + %tmp1241 = load <4 x float>, <4 x float>* undef + %tmp1242 = load <4 x float>, <4 x float>* undef, align 16 + store <4 x float> undef, <4 x float>* undef, align 16 + %tmp1243 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13859 = extractelement <4 x float> %tmp1243, i32 0 + %tmp1244 = load <4 x float>, <4 x float>* undef, align 16 + %vecins13861 = insertelement <4 x float> %tmp1244, float undef, i32 0 + %tmp1245 = load <4 x float>, <4 x float>* undef, align 16 + %vecext13862 = extractelement <4 x float> %tmp1245, i32 1 + %add13863 = fadd float %vecext13862, -1.380000e+02 + %vecins13864 = insertelement <4 x float> undef, float %add13863, i32 1 + %vecins13867 = insertelement <4 x float> undef, float undef, i32 2 + store <4 x float> %vecins13867, <4 x float>* undef, align 16 + %tmp1246 = load <4 x float>, <4 x float>* undef, align 16 + %tmp1247 = load <4 x float>, <4 x float>* undef, align 16 + ret <4 x float> undef +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll index 8d5888d38f97..0637be03d565 100644 --- a/test/CodeGen/ARM/thumb1-varalloc.ll +++ b/test/CodeGen/ARM/thumb1-varalloc.ll @@ -12,7 +12,7 @@ entry: ; CHECK-LABEL: foo: %size = alloca i32, align 4 - %0 = load i8** @__bar, align 4 + %0 = load i8*, i8** @__bar, align 4 %1 = icmp eq i8* %0, null br i1 %1, label %bb1, label %bb3 ; CHECK: bne @@ -22,7 +22,7 @@ bb1: %2 = alloca [1026 x i8], align 1 ; CHECK: mov [[R0:r[0-9]+]], sp ; CHECK: adds {{r[0-9]+}}, [[R0]], {{r[0-9]+}} - %3 = getelementptr inbounds [1026 x i8]* %2, i32 0, i32 0 + %3 = getelementptr inbounds [1026 x i8], [1026 x i8]* %2, i32 0, i32 0 %4 = call i32 @_called_func(i8* %3, i32* %size) nounwind %5 = icmp eq i32 %4, 0 br i1 %5, label %bb2, label %bb3 @@ -43,26 +43,6 @@ bb3: declare noalias i8* @strdup(i8* nocapture) nounwind declare i32 @_called_func(i8*, i32*) nounwind -; Variable ending up at unaligned offset from sp (i.e. not a multiple of 4) -define void @test_local_var_addr() { -; CHECK-LABEL: test_local_var_addr: - - %addr1 = alloca i8 - %addr2 = alloca i8 - -; CHECK: mov r0, sp -; CHECK: adds r0, #{{[0-9]+}} -; CHECK: blx - call void @take_ptr(i8* %addr1) - -; CHECK: mov r0, sp -; CHECK: adds r0, #{{[0-9]+}} -; CHECK: blx - call void @take_ptr(i8* %addr2) - - ret void -} - ; Simple variable ending up *at* sp. define void @test_simple_var() { ; CHECK-LABEL: test_simple_var: @@ -126,14 +106,16 @@ define void @test_local_var_offset_1020() { ret void } -; Max range addressable with tADDrSPi + tADDi8 -define void @test_local_var_offset_1275() { -; CHECK-LABEL: test_local_var_offset_1275 +; Max range addressable with tADDrSPi + tADDi8 is 1275, however the automatic +; 4-byte aligning of objects on the stack combined with 8-byte stack alignment +; means that 1268 is the max offset we can use. +define void @test_local_var_offset_1268() { +; CHECK-LABEL: test_local_var_offset_1268 %addr1 = alloca i8, i32 1 - %addr2 = alloca i8, i32 1275 + %addr2 = alloca i8, i32 1268 ; CHECK: add r0, sp, #1020 -; CHECK: adds r0, #255 +; CHECK: adds r0, #248 ; CHECK-NEXT: blx call void @take_ptr(i8* %addr1) diff --git a/test/CodeGen/ARM/thumb1_return_sequence.ll b/test/CodeGen/ARM/thumb1_return_sequence.ll index 318e6e402370..9c62faeaa684 100644 --- a/test/CodeGen/ARM/thumb1_return_sequence.ll +++ b/test/CodeGen/ARM/thumb1_return_sequence.ll @@ -3,7 +3,7 @@ ; CHECK-V4T-LABEL: clobberframe ; CHECK-V5T-LABEL: clobberframe -define <4 x i32> @clobberframe() #0 { +define <4 x i32> @clobberframe(<6 x i32>* %p) #0 { entry: ; Prologue ; -------- @@ -11,11 +11,12 @@ entry: ; CHECK-V4T: sub sp, ; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr} - %b = alloca <4 x i32>, align 16 + %b = alloca <6 x i32>, align 16 %a = alloca <4 x i32>, align 16 - store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16 + %stuff = load <6 x i32>, <6 x i32>* %p, align 16 + store <6 x i32> %stuff, <6 x i32>* %b, align 16 store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16 - %0 = load <4 x i32>* %a, align 16 + %0 = load <4 x i32>, <4 x i32>* %a, align 16 ret <4 x i32> %0 ; Epilogue @@ -45,7 +46,7 @@ entry: %a = alloca <4 x i32>, align 16 store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16 store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16 - %0 = load <4 x i32>* %a, align 16 + %0 = load <4 x i32>, <4 x i32>* %a, align 16 call void @llvm.va_start(i8* null) ret <4 x i32> %0 @@ -70,40 +71,25 @@ entry: ; CHECK-V4T-LABEL: simpleframe ; CHECK-V5T-LABEL: simpleframe -define i32 @simpleframe() #0 { +define i32 @simpleframe(<6 x i32>* %p) #0 { entry: ; Prologue ; -------- ; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr} ; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr} - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - %d = alloca i32, align 4 - store i32 1, i32* %a, align 4 - store i32 2, i32* %b, align 4 - store i32 3, i32* %c, align 4 - store i32 4, i32* %d, align 4 - %0 = load i32* %a, align 4 - %inc = add nsw i32 %0, 1 - store i32 %inc, i32* %a, align 4 - %1 = load i32* %b, align 4 - %inc1 = add nsw i32 %1, 1 - store i32 %inc1, i32* %b, align 4 - %2 = load i32* %c, align 4 - %inc2 = add nsw i32 %2, 1 - store i32 %inc2, i32* %c, align 4 - %3 = load i32* %d, align 4 - %inc3 = add nsw i32 %3, 1 - store i32 %inc3, i32* %d, align 4 - %4 = load i32* %a, align 4 - %5 = load i32* %b, align 4 - %add = add nsw i32 %4, %5 - %6 = load i32* %c, align 4 - %add4 = add nsw i32 %add, %6 - %7 = load i32* %d, align 4 - %add5 = add nsw i32 %add4, %7 + %0 = load <6 x i32>, <6 x i32>* %p, align 16 + %1 = extractelement <6 x i32> %0, i32 0 + %2 = extractelement <6 x i32> %0, i32 1 + %3 = extractelement <6 x i32> %0, i32 2 + %4 = extractelement <6 x i32> %0, i32 3 + %5 = extractelement <6 x i32> %0, i32 4 + %6 = extractelement <6 x i32> %0, i32 5 + %add1 = add nsw i32 %1, %2 + %add2 = add nsw i32 %add1, %3 + %add3 = add nsw i32 %add2, %4 + %add4 = add nsw i32 %add3, %5 + %add5 = add nsw i32 %add4, %6 ret i32 %add5 ; Epilogue @@ -135,24 +121,24 @@ entry: store i32 2, i32* %b, align 4 store i32 3, i32* %c, align 4 store i32 4, i32* %d, align 4 - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %inc = add nsw i32 %0, 1 store i32 %inc, i32* %a, align 4 - %1 = load i32* %b, align 4 + %1 = load i32, i32* %b, align 4 %inc1 = add nsw i32 %1, 1 store i32 %inc1, i32* %b, align 4 - %2 = load i32* %c, align 4 + %2 = load i32, i32* %c, align 4 %inc2 = add nsw i32 %2, 1 store i32 %inc2, i32* %c, align 4 - %3 = load i32* %d, align 4 + %3 = load i32, i32* %d, align 4 %inc3 = add nsw i32 %3, 1 store i32 %inc3, i32* %d, align 4 - %4 = load i32* %a, align 4 - %5 = load i32* %b, align 4 + %4 = load i32, i32* %a, align 4 + %5 = load i32, i32* %b, align 4 %add = add nsw i32 %4, %5 - %6 = load i32* %c, align 4 + %6 = load i32, i32* %c, align 4 %add4 = add nsw i32 %add, %6 - %7 = load i32* %d, align 4 + %7 = load i32, i32* %d, align 4 %add5 = add nsw i32 %add4, %7 %add6 = add nsw i32 %add5, %i call void @llvm.va_start(i8* null) diff --git a/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll b/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll new file mode 100644 index 000000000000..578777f97c50 --- /dev/null +++ b/test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll @@ -0,0 +1,173 @@ +; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +%struct.cells = type { i32, i32, %struct.cells* } + +@reg_len = external global i32, align 4 + +; The thumb2 size reduction pass commutes arguments to make the first src of an add the same as the dest. +; It needs to also move the internal flag when commuting arguments. + +; CHECK-LABEL: @simulate + +; Function Attrs: nounwind optsize ssp +define i32 @simulate(i32 %iterations, %struct.cells* nocapture %present, double %prob, i8* nocapture readonly %structure) { +entry: + %0 = load i32, i32* @reg_len, align 4, !tbaa !3 + %sub = add nsw i32 %0, -1 + %div = sdiv i32 %sub, 31 + %rem2 = srem i32 %sub, 31 + %cmp35202 = icmp sgt i32 %rem2, 0 + br label %for.cond3.preheader + +for.cond3.preheader: ; preds = %if.end85, %entry + %call192 = tail call i32 @lrand48() #2 + br label %for.cond6.preheader + +for.cond34.preheader: ; preds = %for.inc30 + br i1 %cmp35202, label %for.body37, label %for.end73 + +for.cond6.preheader: ; preds = %for.inc30, %for.cond3.preheader + %call197 = phi i32 [ %call, %for.inc30 ], [ %call192, %for.cond3.preheader ] + %i.0196 = phi i32 [ %inc31, %for.inc30 ], [ 0, %for.cond3.preheader ] + %temp.1195 = phi %struct.cells* [ %5, %for.inc30 ], [ %present, %for.cond3.preheader ] + %savefaulty.0194 = phi i32 [ %add12, %for.inc30 ], [ 0, %for.cond3.preheader ] + %savef_free.0193 = phi i32 [ %add11, %for.inc30 ], [ 0, %for.cond3.preheader ] + br label %for.body8 + +for.body8: ; preds = %for.body8, %for.cond6.preheader + %randv.0190 = phi i32 [ %call197, %for.cond6.preheader ], [ %shr, %for.body8 ] + %j.0189 = phi i32 [ 0, %for.cond6.preheader ], [ %inc, %for.body8 ] + %temp.2188 = phi %struct.cells* [ %temp.1195, %for.cond6.preheader ], [ %5, %for.body8 ] + %savefaulty.1187 = phi i32 [ %savefaulty.0194, %for.cond6.preheader ], [ %add12, %for.body8 ] + %savef_free.1186 = phi i32 [ %savef_free.0193, %for.cond6.preheader ], [ %add11, %for.body8 ] + %f_free = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 0 + %1 = load i32, i32* %f_free, align 4, !tbaa !7 + %add11 = add nsw i32 %1, %savef_free.1186 + %faulty = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 1 + %2 = load i32, i32* %faulty, align 4, !tbaa !10 + %add12 = add nsw i32 %2, %savefaulty.1187 + %next = getelementptr inbounds %struct.cells, %struct.cells* %temp.2188, i32 0, i32 2 + %3 = load %struct.cells*, %struct.cells** %next, align 4, !tbaa !11 + %f_free13 = getelementptr inbounds %struct.cells, %struct.cells* %3, i32 0, i32 0 + %4 = load i32, i32* %f_free13, align 4, !tbaa !7 + %add14 = add nsw i32 %4, %randv.0190 + %and = and i32 %add14, 1 + store i32 %and, i32* %f_free, align 4, !tbaa !7 + %call16 = tail call i32 @lrand48() #2 + %rem17 = srem i32 %call16, 1000 + %conv18 = sitofp i32 %rem17 to double + %div19 = fdiv double %conv18, 1.000000e+03 + %cmp20 = fcmp olt double %div19, %prob + %xor = zext i1 %cmp20 to i32 + %randv.1 = xor i32 %xor, %randv.0190 + %5 = load %struct.cells*, %struct.cells** %next, align 4, !tbaa !11 + %faulty25 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1 + %6 = load i32, i32* %faulty25, align 4, !tbaa !10 + %add26 = add nsw i32 %randv.1, %6 + %and27 = and i32 %add26, 1 + store i32 %and27, i32* %faulty, align 4, !tbaa !10 + %shr = ashr i32 %randv.0190, 1 + %inc = add nuw nsw i32 %j.0189, 1 + %exitcond = icmp eq i32 %inc, 31 + br i1 %exitcond, label %for.inc30, label %for.body8 + +for.inc30: ; preds = %for.body8 + %inc31 = add nuw nsw i32 %i.0196, 1 + %cmp4 = icmp slt i32 %inc31, %div + %call = tail call i32 @lrand48() #2 + br i1 %cmp4, label %for.cond6.preheader, label %for.cond34.preheader + +for.body37: ; preds = %for.body37, %for.cond34.preheader + %randv.2207 = phi i32 [ %shr70, %for.body37 ], [ %call, %for.cond34.preheader ] + %temp.3205 = phi %struct.cells* [ %9, %for.body37 ], [ %5, %for.cond34.preheader ] + %f_free45 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 0 + %.pre220 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 1 + %next50 = getelementptr inbounds %struct.cells, %struct.cells* %temp.3205, i32 0, i32 2 + %7 = load %struct.cells*, %struct.cells** %next50, align 4, !tbaa !11 + %f_free51 = getelementptr inbounds %struct.cells, %struct.cells* %7, i32 0, i32 0 + %8 = load i32, i32* %f_free51, align 4, !tbaa !7 + %add52 = add nsw i32 %8, %randv.2207 + %and53 = and i32 %add52, 1 + store i32 %and53, i32* %f_free45, align 4, !tbaa !7 + %call55 = tail call i32 @lrand48() #2 + %rem56 = srem i32 %call55, 1000 + %conv57 = sitofp i32 %rem56 to double + %div58 = fdiv double %conv57, 1.000000e+03 + %cmp59 = fcmp olt double %div58, %prob + %xor62 = zext i1 %cmp59 to i32 + %randv.3 = xor i32 %xor62, %randv.2207 + %9 = load %struct.cells*, %struct.cells** %next50, align 4, !tbaa !11 + %faulty65 = getelementptr inbounds %struct.cells, %struct.cells* %9, i32 0, i32 1 + %10 = load i32, i32* %faulty65, align 4, !tbaa !10 + %add66 = add nsw i32 %randv.3, %10 + %and67 = and i32 %add66, 1 + store i32 %and67, i32* %.pre220, align 4, !tbaa !10 + %shr70 = ashr i32 %randv.2207, 1 + br label %for.body37 + +for.end73: ; preds = %for.cond34.preheader + %call74 = tail call i32 @lrand48() #2 + %11 = load i32, i32* @reg_len, align 4, !tbaa !3 + %sub75 = add nsw i32 %11, -1 + %arrayidx76 = getelementptr inbounds i8, i8* %structure, i32 %sub75 + %12 = load i8, i8* %arrayidx76, align 1, !tbaa !12 + %cmp78 = icmp eq i8 %12, 49 + %f_free81 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 0 + br i1 %cmp78, label %if.then80, label %for.end73.if.end85_crit_edge + +for.end73.if.end85_crit_edge: ; preds = %for.end73 + %.pre222 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1 + br label %if.end85 + +if.then80: ; preds = %for.end73 + %13 = load i32, i32* %f_free81, align 4, !tbaa !7 + %add82 = add nsw i32 %13, %add11 + %faulty83 = getelementptr inbounds %struct.cells, %struct.cells* %5, i32 0, i32 1 + %14 = load i32, i32* %faulty83, align 4, !tbaa !10 + %add84 = add nsw i32 %14, %add12 + br label %if.end85 + +if.end85: ; preds = %if.then80, %for.end73.if.end85_crit_edge + %faulty100.pre-phi = phi i32* [ %.pre222, %for.end73.if.end85_crit_edge ], [ %faulty83, %if.then80 ] + %savef_free.5 = phi i32 [ %add11, %for.end73.if.end85_crit_edge ], [ %add82, %if.then80 ] + %savefaulty.5 = phi i32 [ %add12, %for.end73.if.end85_crit_edge ], [ %add84, %if.then80 ] + %add86 = add nsw i32 %savef_free.5, %call74 + %and87 = and i32 %add86, 1 + store i32 %and87, i32* %f_free81, align 4, !tbaa !7 + %call89 = tail call i32 @lrand48() #2 + %rem90 = srem i32 %call89, 10000 + %conv91 = sitofp i32 %rem90 to double + %div92 = fdiv double %conv91, 1.000000e+04 + %cmp93 = fcmp olt double %div92, %prob + %xor96 = zext i1 %cmp93 to i32 + %randv.4 = xor i32 %xor96, %call74 + %add98 = add nsw i32 %randv.4, %savefaulty.5 + %and99 = and i32 %add98, 1 + store i32 %and99, i32* %faulty100.pre-phi, align 4, !tbaa !10 + br label %for.cond3.preheader +} + +; Function Attrs: optsize +declare i32 @lrand48() + +attributes #2 = { nounwind optsize } + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"min_enum_size", i32 4} +!2 = !{!"clang version 3.7.0 (trunk 236243)"} +!3 = !{!4, !4, i64 0} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!8, !4, i64 0} +!8 = !{!"cells", !4, i64 0, !4, i64 4, !9, i64 8} +!9 = !{!"any pointer", !5, i64 0} +!10 = !{!8, !4, i64 4} +!11 = !{!8, !9, i64 8} +!12 = !{!5, !5, i64 0} diff --git a/test/CodeGen/ARM/thumb_indirect_calls.ll b/test/CodeGen/ARM/thumb_indirect_calls.ll index 16a55a882d9a..9f1950c743c0 100644 --- a/test/CodeGen/ARM/thumb_indirect_calls.ll +++ b/test/CodeGen/ARM/thumb_indirect_calls.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL foo: define void @foo(i32 %x) { entry: - %0 = load void (i32)** @f, align 4 + %0 = load void (i32)*, void (i32)** @f, align 4 tail call void %0(i32 %x) ret void diff --git a/test/CodeGen/ARM/tls1.ll b/test/CodeGen/ARM/tls1.ll index b03f76b6ef08..d492522955ec 100644 --- a/test/CodeGen/ARM/tls1.ll +++ b/test/CodeGen/ARM/tls1.ll @@ -12,7 +12,7 @@ define i32 @f() { entry: - %tmp1 = load i32* @i ; <i32> [#uses=1] + %tmp1 = load i32, i32* @i ; <i32> [#uses=1] ret i32 %tmp1 } diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll index 24b4794b061a..d522da8f5714 100644 --- a/test/CodeGen/ARM/tls2.ll +++ b/test/CodeGen/ARM/tls2.ll @@ -12,7 +12,7 @@ define i32 @f() { ; CHECK-PIC-LABEL: f: ; CHECK-PIC: __tls_get_addr entry: - %tmp1 = load i32* @i ; <i32> [#uses=1] + %tmp1 = load i32, i32* @i ; <i32> [#uses=1] ret i32 %tmp1 } diff --git a/test/CodeGen/ARM/tls3.ll b/test/CodeGen/ARM/tls3.ll index e0e944f70c5d..7e17b13a3c99 100644 --- a/test/CodeGen/ARM/tls3.ll +++ b/test/CodeGen/ARM/tls3.ll @@ -6,6 +6,6 @@ define i32 @main() { entry: - %tmp2 = load i32* getelementptr (%struct.anon* @teste, i32 0, i32 0), align 8 ; <i32> [#uses=1] + %tmp2 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @teste, i32 0, i32 0), align 8 ; <i32> [#uses=1] ret i32 %tmp2 } diff --git a/test/CodeGen/ARM/trunc_ldr.ll b/test/CodeGen/ARM/trunc_ldr.ll index 2ce9b894d55a..ca7ad9a2fc62 100644 --- a/test/CodeGen/ARM/trunc_ldr.ll +++ b/test/CodeGen/ARM/trunc_ldr.ll @@ -4,18 +4,18 @@ %struct.B = type { float, float, i32, i32, i32, [0 x i8] } define i8 @f1(%struct.A* %d) { - %tmp2 = getelementptr %struct.A* %d, i32 0, i32 4 + %tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4 %tmp23 = bitcast i16* %tmp2 to i32* - %tmp4 = load i32* %tmp23 + %tmp4 = load i32, i32* %tmp23 %tmp512 = lshr i32 %tmp4, 24 %tmp56 = trunc i32 %tmp512 to i8 ret i8 %tmp56 } define i32 @f2(%struct.A* %d) { - %tmp2 = getelementptr %struct.A* %d, i32 0, i32 4 + %tmp2 = getelementptr %struct.A, %struct.A* %d, i32 0, i32 4 %tmp23 = bitcast i16* %tmp2 to i32* - %tmp4 = load i32* %tmp23 + %tmp4 = load i32, i32* %tmp23 %tmp512 = lshr i32 %tmp4, 24 %tmp56 = trunc i32 %tmp512 to i8 %tmp57 = sext i8 %tmp56 to i32 diff --git a/test/CodeGen/ARM/truncstore-dag-combine.ll b/test/CodeGen/ARM/truncstore-dag-combine.ll index 360e3e13f59e..11fa022451f6 100644 --- a/test/CodeGen/ARM/truncstore-dag-combine.ll +++ b/test/CodeGen/ARM/truncstore-dag-combine.ll @@ -3,7 +3,7 @@ define void @bar(i8* %P, i16* %Q) { entry: %P1 = bitcast i8* %P to i16* ; <i16*> [#uses=1] - %tmp = load i16* %Q, align 1 ; <i16> [#uses=1] + %tmp = load i16, i16* %Q, align 1 ; <i16> [#uses=1] store i16 %tmp, i16* %P1, align 1 ret void } @@ -11,7 +11,7 @@ entry: define void @foo(i8* %P, i32* %Q) { entry: %P1 = bitcast i8* %P to i32* ; <i32*> [#uses=1] - %tmp = load i32* %Q, align 1 ; <i32> [#uses=1] + %tmp = load i32, i32* %Q, align 1 ; <i32> [#uses=1] store i32 %tmp, i32* %P1, align 1 ret void } diff --git a/test/CodeGen/ARM/twoaddrinstr.ll b/test/CodeGen/ARM/twoaddrinstr.ll index 01df3b42d107..97a49334b742 100644 --- a/test/CodeGen/ARM/twoaddrinstr.ll +++ b/test/CodeGen/ARM/twoaddrinstr.ll @@ -12,7 +12,7 @@ define void @PR13378() nounwind { ; CHECK-NEXT: vst1.32 entry: - %0 = load <4 x float>* undef, align 4 + %0 = load <4 x float>, <4 x float>* undef, align 4 store <4 x float> zeroinitializer, <4 x float>* undef, align 4 store <4 x float> %0, <4 x float>* undef, align 4 %1 = insertelement <4 x float> %0, float 1.000000e+00, i32 3 diff --git a/test/CodeGen/ARM/uint64tof64.ll b/test/CodeGen/ARM/uint64tof64.ll index 32eb225a2ad6..cd35ce74d8ee 100644 --- a/test/CodeGen/ARM/uint64tof64.ll +++ b/test/CodeGen/ARM/uint64tof64.ll @@ -7,10 +7,10 @@ define fastcc void @t() { entry: - %0 = load i64* null, align 4 ; <i64> [#uses=1] + %0 = load i64, i64* null, align 4 ; <i64> [#uses=1] %1 = uitofp i64 %0 to double ; <double> [#uses=1] %2 = fdiv double 0.000000e+00, %1 ; <double> [#uses=1] - %3 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* null, i8* getelementptr ([54 x i8]* @"\01LC10", i32 0, i32 0), i64 0, double %2) ; <i32> [#uses=0] + %3 = call i32 (%struct.FILE*, i8*, ...) @fprintf(%struct.FILE* null, i8* getelementptr ([54 x i8], [54 x i8]* @"\01LC10", i32 0, i32 0), i64 0, double %2) ; <i32> [#uses=0] ret void } diff --git a/test/CodeGen/ARM/umulo-32.ll b/test/CodeGen/ARM/umulo-32.ll index 19875ce94071..1c8357314c28 100644 --- a/test/CodeGen/ARM/umulo-32.ll +++ b/test/CodeGen/ARM/umulo-32.ll @@ -28,7 +28,7 @@ store i32 0, i32* %1 store i32 %argc, i32* %2, align 4 store i8** %argv, i8*** %3, align 4 store i32 10, i32* %m_degree, align 4 -%4 = load i32* %m_degree, align 4 +%4 = load i32, i32* %m_degree, align 4 %5 = call %umul.ty @llvm.umul.with.overflow.i32(i32 %4, i32 8) %6 = extractvalue %umul.ty %5, 1 %7 = extractvalue %umul.ty %5, 0 diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index 72163ae30c38..0be3917ffa26 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -28,7 +28,7 @@ entry: %__src1.i = bitcast i8* %b to i32* ; <i32*> [#uses=1] %__dest2.i = bitcast i8* %a to i32* ; <i32*> [#uses=1] - %tmp.i = load i32* %__src1.i, align 1 ; <i32> [#uses=1] + %tmp.i = load i32, i32* %__src1.i, align 1 ; <i32> [#uses=1] store i32 %tmp.i, i32* %__dest2.i, align 1 ret void } @@ -44,7 +44,7 @@ entry: ; UNALIGNED-LABEL: hword: ; UNALIGNED: vld1.16 ; UNALIGNED: vst1.16 - %tmp = load double* %a, align 2 + %tmp = load double, double* %a, align 2 store double %tmp, double* %b, align 2 ret void } @@ -60,7 +60,7 @@ entry: ; UNALIGNED-LABEL: byte: ; UNALIGNED: vld1.8 ; UNALIGNED: vst1.8 - %tmp = load double* %a, align 1 + %tmp = load double, double* %a, align 1 store double %tmp, double* %b, align 1 ret void } @@ -76,7 +76,7 @@ entry: ; UNALIGNED: ldr ; UNALIGNED-NOT: strb ; UNALIGNED: str - %tmp = load i32* %a, align 1 + %tmp = load i32, i32* %a, align 1 store i32 %tmp, i32* %b, align 1 ret void } diff --git a/test/CodeGen/ARM/unaligned_load_store_vector.ll b/test/CodeGen/ARM/unaligned_load_store_vector.ll index 000ed489c4c0..abb523c22757 100644 --- a/test/CodeGen/ARM/unaligned_load_store_vector.ll +++ b/test/CodeGen/ARM/unaligned_load_store_vector.ll @@ -6,12 +6,12 @@ define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v8i8_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <8 x i8>* %vo = bitcast i8* %po to <8 x i8>* ;CHECK: vld1.8 - %v1 = load <8 x i8>* %vi, align 1 + %v1 = load <8 x i8>, <8 x i8>* %vi, align 1 ;CHECK: vst1.8 store <8 x i8> %v1, <8 x i8>* %vo, align 1 ret void @@ -24,12 +24,12 @@ entry: define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v4i16_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x i16>* %vo = bitcast i8* %po to <4 x i16>* ;CHECK: vld1.8 - %v1 = load <4 x i16>* %vi, align 1 + %v1 = load <4 x i16>, <4 x i16>* %vi, align 1 ;CHECK: vst1.8 store <4 x i16> %v1, <4 x i16>* %vo, align 1 ret void @@ -42,12 +42,12 @@ entry: define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v2i32_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x i32>* %vo = bitcast i8* %po to <2 x i32>* ;CHECK: vld1.8 - %v1 = load <2 x i32>* %vi, align 1 + %v1 = load <2 x i32>, <2 x i32>* %vi, align 1 ;CHECK: vst1.8 store <2 x i32> %v1, <2 x i32>* %vo, align 1 ret void @@ -60,12 +60,12 @@ entry: define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v2f32_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x float>* %vo = bitcast i8* %po to <2 x float>* ;CHECK: vld1.8 - %v1 = load <2 x float>* %vi, align 1 + %v1 = load <2 x float>, <2 x float>* %vi, align 1 ;CHECK: vst1.8 store <2 x float> %v1, <2 x float>* %vo, align 1 ret void @@ -78,12 +78,12 @@ entry: define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v16i8_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <16 x i8>* %vo = bitcast i8* %po to <16 x i8>* ;CHECK: vld1.8 - %v1 = load <16 x i8>* %vi, align 1 + %v1 = load <16 x i8>, <16 x i8>* %vi, align 1 ;CHECK: vst1.8 store <16 x i8> %v1, <16 x i8>* %vo, align 1 ret void @@ -96,12 +96,12 @@ entry: define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v8i16_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <8 x i16>* %vo = bitcast i8* %po to <8 x i16>* ;CHECK: vld1.8 - %v1 = load <8 x i16>* %vi, align 1 + %v1 = load <8 x i16>, <8 x i16>* %vi, align 1 ;CHECK: vst1.8 store <8 x i16> %v1, <8 x i16>* %vo, align 1 ret void @@ -114,12 +114,12 @@ entry: define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v4i32_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x i32>* %vo = bitcast i8* %po to <4 x i32>* ;CHECK: vld1.8 - %v1 = load <4 x i32>* %vi, align 1 + %v1 = load <4 x i32>, <4 x i32>* %vi, align 1 ;CHECK: vst1.8 store <4 x i32> %v1, <4 x i32>* %vo, align 1 ret void @@ -132,12 +132,12 @@ entry: define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v2i64_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x i64>* %vo = bitcast i8* %po to <2 x i64>* ;CHECK: vld1.8 - %v1 = load <2 x i64>* %vi, align 1 + %v1 = load <2 x i64>, <2 x i64>* %vi, align 1 ;CHECK: vst1.8 store <2 x i64> %v1, <2 x i64>* %vo, align 1 ret void @@ -150,12 +150,12 @@ entry: define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v4f32_1: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x float>* %vo = bitcast i8* %po to <4 x float>* ;CHECK: vld1.8 - %v1 = load <4 x float>* %vi, align 1 + %v1 = load <4 x float>, <4 x float>* %vi, align 1 ;CHECK: vst1.8 store <4 x float> %v1, <4 x float>* %vo, align 1 ret void @@ -168,12 +168,12 @@ entry: define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v8i8_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <8 x i8>* %vo = bitcast i8* %po to <8 x i8>* ;CHECK: vld1.16 - %v1 = load <8 x i8>* %vi, align 2 + %v1 = load <8 x i8>, <8 x i8>* %vi, align 2 ;CHECK: vst1.16 store <8 x i8> %v1, <8 x i8>* %vo, align 2 ret void @@ -186,12 +186,12 @@ entry: define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v4i16_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x i16>* %vo = bitcast i8* %po to <4 x i16>* ;CHECK: vld1.16 - %v1 = load <4 x i16>* %vi, align 2 + %v1 = load <4 x i16>, <4 x i16>* %vi, align 2 ;CHECK: vst1.16 store <4 x i16> %v1, <4 x i16>* %vo, align 2 ret void @@ -204,12 +204,12 @@ entry: define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v2i32_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x i32>* %vo = bitcast i8* %po to <2 x i32>* ;CHECK: vld1.16 - %v1 = load <2 x i32>* %vi, align 2 + %v1 = load <2 x i32>, <2 x i32>* %vi, align 2 ;CHECK: vst1.16 store <2 x i32> %v1, <2 x i32>* %vo, align 2 ret void @@ -222,12 +222,12 @@ entry: define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v2f32_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x float>* %vo = bitcast i8* %po to <2 x float>* ;CHECK: vld1.16 - %v1 = load <2 x float>* %vi, align 2 + %v1 = load <2 x float>, <2 x float>* %vi, align 2 ;CHECK: vst1.16 store <2 x float> %v1, <2 x float>* %vo, align 2 ret void @@ -240,12 +240,12 @@ entry: define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v16i8_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <16 x i8>* %vo = bitcast i8* %po to <16 x i8>* ;CHECK: vld1.16 - %v1 = load <16 x i8>* %vi, align 2 + %v1 = load <16 x i8>, <16 x i8>* %vi, align 2 ;CHECK: vst1.16 store <16 x i8> %v1, <16 x i8>* %vo, align 2 ret void @@ -258,12 +258,12 @@ entry: define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v8i16_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <8 x i16>* %vo = bitcast i8* %po to <8 x i16>* ;CHECK: vld1.16 - %v1 = load <8 x i16>* %vi, align 2 + %v1 = load <8 x i16>, <8 x i16>* %vi, align 2 ;CHECK: vst1.16 store <8 x i16> %v1, <8 x i16>* %vo, align 2 ret void @@ -276,12 +276,12 @@ entry: define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v4i32_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x i32>* %vo = bitcast i8* %po to <4 x i32>* ;CHECK: vld1.16 - %v1 = load <4 x i32>* %vi, align 2 + %v1 = load <4 x i32>, <4 x i32>* %vi, align 2 ;CHECK: vst1.16 store <4 x i32> %v1, <4 x i32>* %vo, align 2 ret void @@ -294,12 +294,12 @@ entry: define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v2i64_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x i64>* %vo = bitcast i8* %po to <2 x i64>* ;CHECK: vld1.16 - %v1 = load <2 x i64>* %vi, align 2 + %v1 = load <2 x i64>, <2 x i64>* %vi, align 2 ;CHECK: vst1.16 store <2 x i64> %v1, <2 x i64>* %vo, align 2 ret void @@ -312,12 +312,12 @@ entry: define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v4f32_2: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x float>* %vo = bitcast i8* %po to <4 x float>* ;CHECK: vld1.16 - %v1 = load <4 x float>* %vi, align 2 + %v1 = load <4 x float>, <4 x float>* %vi, align 2 ;CHECK: vst1.16 store <4 x float> %v1, <4 x float>* %vo, align 2 ret void @@ -330,12 +330,12 @@ entry: define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v8i8_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <8 x i8>* %vo = bitcast i8* %po to <8 x i8>* ;CHECK: vldr - %v1 = load <8 x i8>* %vi, align 4 + %v1 = load <8 x i8>, <8 x i8>* %vi, align 4 ;CHECK: vstr store <8 x i8> %v1, <8 x i8>* %vo, align 4 ret void @@ -348,12 +348,12 @@ entry: define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v4i16_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x i16>* %vo = bitcast i8* %po to <4 x i16>* ;CHECK: vldr - %v1 = load <4 x i16>* %vi, align 4 + %v1 = load <4 x i16>, <4 x i16>* %vi, align 4 ;CHECK: vstr store <4 x i16> %v1, <4 x i16>* %vo, align 4 ret void @@ -366,12 +366,12 @@ entry: define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v2i32_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x i32>* %vo = bitcast i8* %po to <2 x i32>* ;CHECK: vldr - %v1 = load <2 x i32>* %vi, align 4 + %v1 = load <2 x i32>, <2 x i32>* %vi, align 4 ;CHECK: vstr store <2 x i32> %v1, <2 x i32>* %vo, align 4 ret void @@ -384,12 +384,12 @@ entry: define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v64_v2f32_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x float>* %vo = bitcast i8* %po to <2 x float>* ;CHECK: vldr - %v1 = load <2 x float>* %vi, align 4 + %v1 = load <2 x float>, <2 x float>* %vi, align 4 ;CHECK: vstr store <2 x float> %v1, <2 x float>* %vo, align 4 ret void @@ -402,12 +402,12 @@ entry: define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v16i8_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <16 x i8>* %vo = bitcast i8* %po to <16 x i8>* ;CHECK: vld1.32 - %v1 = load <16 x i8>* %vi, align 4 + %v1 = load <16 x i8>, <16 x i8>* %vi, align 4 ;CHECK: vst1.32 store <16 x i8> %v1, <16 x i8>* %vo, align 4 ret void @@ -420,12 +420,12 @@ entry: define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v8i16_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <8 x i16>* %vo = bitcast i8* %po to <8 x i16>* ;CHECK: vld1.32 - %v1 = load <8 x i16>* %vi, align 4 + %v1 = load <8 x i16>, <8 x i16>* %vi, align 4 ;CHECK: vst1.32 store <8 x i16> %v1, <8 x i16>* %vo, align 4 ret void @@ -438,12 +438,12 @@ entry: define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v4i32_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x i32>* %vo = bitcast i8* %po to <4 x i32>* ;CHECK: vld1.32 - %v1 = load <4 x i32>* %vi, align 4 + %v1 = load <4 x i32>, <4 x i32>* %vi, align 4 ;CHECK: vst1.32 store <4 x i32> %v1, <4 x i32>* %vo, align 4 ret void @@ -456,12 +456,12 @@ entry: define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v2i64_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <2 x i64>* %vo = bitcast i8* %po to <2 x i64>* ;CHECK: vld1.32 - %v1 = load <2 x i64>* %vi, align 4 + %v1 = load <2 x i64>, <2 x i64>* %vi, align 4 ;CHECK: vst1.32 store <2 x i64> %v1, <2 x i64>* %vo, align 4 ret void @@ -474,12 +474,12 @@ entry: define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { ;CHECK-LABEL: v128_v4f32_4: entry: - %po = getelementptr i8* %out, i32 0 - %pi = getelementptr i8* %in, i32 0 + %po = getelementptr i8, i8* %out, i32 0 + %pi = getelementptr i8, i8* %in, i32 0 %vi = bitcast i8* %pi to <4 x float>* %vo = bitcast i8* %po to <4 x float>* ;CHECK: vld1.32 - %v1 = load <4 x float>* %vi, align 4 + %v1 = load <4 x float>, <4 x float>* %vi, align 4 ;CHECK: vst1.32 store <4 x float> %v1, <4 x float>* %vo, align 4 ret void diff --git a/test/CodeGen/ARM/undef-sext.ll b/test/CodeGen/ARM/undef-sext.ll index c6d76d0017df..bb06bcbaf44c 100644 --- a/test/CodeGen/ARM/undef-sext.ll +++ b/test/CodeGen/ARM/undef-sext.ll @@ -8,7 +8,7 @@ entry: ; CHECK: ldr r0, [r0] ; CHECK: bx lr %0 = sext i16 undef to i32 - %1 = getelementptr inbounds i32* %a, i32 %0 - %2 = load i32* %1, align 4 + %1 = getelementptr inbounds i32, i32* %a, i32 %0 + %2 = load i32, i32* %1, align 4 ret i32 %2 } diff --git a/test/CodeGen/ARM/vaba.ll b/test/CodeGen/ARM/vaba.ll index 6478b1843c69..4323f3184469 100644 --- a/test/CodeGen/ARM/vaba.ll +++ b/test/CodeGen/ARM/vaba.ll @@ -3,9 +3,9 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vabas8: ;CHECK: vaba.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) %tmp5 = add <8 x i8> %tmp1, %tmp4 ret <8 x i8> %tmp5 @@ -14,9 +14,9 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vabas16: ;CHECK: vaba.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) %tmp5 = add <4 x i16> %tmp1, %tmp4 ret <4 x i16> %tmp5 @@ -25,9 +25,9 @@ define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vabas32: ;CHECK: vaba.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) %tmp5 = add <2 x i32> %tmp1, %tmp4 ret <2 x i32> %tmp5 @@ -36,9 +36,9 @@ define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vabau8: ;CHECK: vaba.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) %tmp5 = add <8 x i8> %tmp1, %tmp4 ret <8 x i8> %tmp5 @@ -47,9 +47,9 @@ define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vabau16: ;CHECK: vaba.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) %tmp5 = add <4 x i16> %tmp1, %tmp4 ret <4 x i16> %tmp5 @@ -58,9 +58,9 @@ define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vabau32: ;CHECK: vaba.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) %tmp5 = add <2 x i32> %tmp1, %tmp4 ret <2 x i32> %tmp5 @@ -69,9 +69,9 @@ define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { ;CHECK-LABEL: vabaQs8: ;CHECK: vaba.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B - %tmp3 = load <16 x i8>* %C + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <16 x i8>, <16 x i8>* %C %tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3) %tmp5 = add <16 x i8> %tmp1, %tmp4 ret <16 x i8> %tmp5 @@ -80,9 +80,9 @@ define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: vabaQs16: ;CHECK: vaba.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3) %tmp5 = add <8 x i16> %tmp1, %tmp4 ret <8 x i16> %tmp5 @@ -91,9 +91,9 @@ define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: vabaQs32: ;CHECK: vaba.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3) %tmp5 = add <4 x i32> %tmp1, %tmp4 ret <4 x i32> %tmp5 @@ -102,9 +102,9 @@ define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { ;CHECK-LABEL: vabaQu8: ;CHECK: vaba.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B - %tmp3 = load <16 x i8>* %C + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <16 x i8>, <16 x i8>* %C %tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3) %tmp5 = add <16 x i8> %tmp1, %tmp4 ret <16 x i8> %tmp5 @@ -113,9 +113,9 @@ define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: vabaQu16: ;CHECK: vaba.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3) %tmp5 = add <8 x i16> %tmp1, %tmp4 ret <8 x i16> %tmp5 @@ -124,9 +124,9 @@ define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: vabaQu32: ;CHECK: vaba.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3) %tmp5 = add <4 x i32> %tmp1, %tmp4 ret <4 x i32> %tmp5 @@ -151,9 +151,9 @@ declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind read define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vabals8: ;CHECK: vabal.s8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) %tmp5 = zext <8 x i8> %tmp4 to <8 x i16> %tmp6 = add <8 x i16> %tmp1, %tmp5 @@ -163,9 +163,9 @@ define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vabals16: ;CHECK: vabal.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) %tmp5 = zext <4 x i16> %tmp4 to <4 x i32> %tmp6 = add <4 x i32> %tmp1, %tmp5 @@ -175,9 +175,9 @@ define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vabals32: ;CHECK: vabal.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) %tmp5 = zext <2 x i32> %tmp4 to <2 x i64> %tmp6 = add <2 x i64> %tmp1, %tmp5 @@ -187,9 +187,9 @@ define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vabalu8: ;CHECK: vabal.u8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) %tmp5 = zext <8 x i8> %tmp4 to <8 x i16> %tmp6 = add <8 x i16> %tmp1, %tmp5 @@ -199,9 +199,9 @@ define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vabalu16: ;CHECK: vabal.u16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) %tmp5 = zext <4 x i16> %tmp4 to <4 x i32> %tmp6 = add <4 x i32> %tmp1, %tmp5 @@ -211,9 +211,9 @@ define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vabalu32: ;CHECK: vabal.u32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) %tmp5 = zext <2 x i32> %tmp4 to <2 x i64> %tmp6 = add <2 x i64> %tmp1, %tmp5 diff --git a/test/CodeGen/ARM/vabd.ll b/test/CodeGen/ARM/vabd.ll index 9ba8be28c776..548b8a340461 100644 --- a/test/CodeGen/ARM/vabd.ll +++ b/test/CodeGen/ARM/vabd.ll @@ -3,8 +3,8 @@ define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vabds8: ;CHECK: vabd.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vabds16: ;CHECK: vabd.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vabds32: ;CHECK: vabd.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vabdu8: ;CHECK: vabd.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vabdu16: ;CHECK: vabd.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vabdu32: ;CHECK: vabd.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vabdf32: ;CHECK: vabd.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -66,8 +66,8 @@ define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vabdQs8: ;CHECK: vabd.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -75,8 +75,8 @@ define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vabdQs16: ;CHECK: vabd.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -84,8 +84,8 @@ define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vabdQs32: ;CHECK: vabd.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -93,8 +93,8 @@ define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vabdQu8: ;CHECK: vabd.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -102,8 +102,8 @@ define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vabdQu16: ;CHECK: vabd.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -111,8 +111,8 @@ define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vabdQu32: ;CHECK: vabd.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -120,8 +120,8 @@ define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vabdQf32: ;CHECK: vabd.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -149,8 +149,8 @@ declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwin define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vabdls8: ;CHECK: vabdl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp4 = zext <8 x i8> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -159,8 +159,8 @@ define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vabdls16: ;CHECK: vabdl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp4 = zext <4 x i16> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -169,8 +169,8 @@ define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vabdls32: ;CHECK: vabdl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp4 = zext <2 x i32> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -179,8 +179,8 @@ define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vabdlu8: ;CHECK: vabdl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp4 = zext <8 x i8> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -189,8 +189,8 @@ define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vabdlu16: ;CHECK: vabdl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp4 = zext <4 x i16> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -199,8 +199,8 @@ define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vabdlu32: ;CHECK: vabdl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp4 = zext <2 x i32> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll index 3a1aec86edfe..38c6d6c28aed 100644 --- a/test/CodeGen/ARM/vabs.ll +++ b/test/CodeGen/ARM/vabs.ll @@ -3,7 +3,7 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vabss8: ;CHECK: vabs.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -11,7 +11,7 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { define <4 x i16> @vabss16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vabss16: ;CHECK: vabs.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp2 } @@ -19,7 +19,7 @@ define <4 x i16> @vabss16(<4 x i16>* %A) nounwind { define <2 x i32> @vabss32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vabss32: ;CHECK: vabs.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -27,7 +27,7 @@ define <2 x i32> @vabss32(<2 x i32>* %A) nounwind { define <2 x float> @vabsf32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vabsf32: ;CHECK: vabs.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %tmp1) ret <2 x float> %tmp2 } @@ -35,7 +35,7 @@ define <2 x float> @vabsf32(<2 x float>* %A) nounwind { define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vabsQs8: ;CHECK: vabs.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -43,7 +43,7 @@ define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vabsQs16: ;CHECK: vabs.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp2 } @@ -51,7 +51,7 @@ define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vabsQs32: ;CHECK: vabs.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } @@ -59,7 +59,7 @@ define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind { define <4 x float> @vabsQf32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vabsQf32: ;CHECK: vabs.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %tmp1) ret <4 x float> %tmp2 } @@ -77,7 +77,7 @@ declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vqabss8: ;CHECK: vqabs.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -85,7 +85,7 @@ define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind { define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vqabss16: ;CHECK: vqabs.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp2 } @@ -93,7 +93,7 @@ define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind { define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vqabss32: ;CHECK: vqabs.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -101,7 +101,7 @@ define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind { define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vqabsQs8: ;CHECK: vqabs.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -109,7 +109,7 @@ define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqabsQs16: ;CHECK: vqabs.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp2 } @@ -117,7 +117,7 @@ define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqabsQs32: ;CHECK: vqabs.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll index 86b0d0297018..dd35dd1ccfb9 100644 --- a/test/CodeGen/ARM/vadd.ll +++ b/test/CodeGen/ARM/vadd.ll @@ -3,8 +3,8 @@ define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddi8: ;CHECK: vadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = add <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vaddi16: ;CHECK: vadd.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = add <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vaddi32: ;CHECK: vadd.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = add <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vaddi64: ;CHECK: vadd.i64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = add <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vaddf32: ;CHECK: vadd.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fadd <2 x float> %tmp1, %tmp2 ret <2 x float> %tmp3 } @@ -48,8 +48,8 @@ define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vaddQi8: ;CHECK: vadd.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = add <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -57,8 +57,8 @@ define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vaddQi16: ;CHECK: vadd.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = add <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -66,8 +66,8 @@ define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vaddQi32: ;CHECK: vadd.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = add <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -75,8 +75,8 @@ define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vaddQi64: ;CHECK: vadd.i64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = add <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -84,8 +84,8 @@ define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vaddQf32: ;CHECK: vadd.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = fadd <4 x float> %tmp1, %tmp2 ret <4 x float> %tmp3 } @@ -93,8 +93,8 @@ define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vraddhni16: ;CHECK: vraddhn.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i8> %tmp3 } @@ -102,8 +102,8 @@ define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vraddhni32: ;CHECK: vraddhn.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i16> %tmp3 } @@ -111,8 +111,8 @@ define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vraddhni64: ;CHECK: vraddhn.i64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i32> %tmp3 } @@ -151,8 +151,8 @@ define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind { define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddls8: ;CHECK: vaddl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -162,8 +162,8 @@ define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vaddls16: ;CHECK: vaddl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -173,8 +173,8 @@ define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vaddls32: ;CHECK: vaddl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = add <2 x i64> %tmp3, %tmp4 @@ -184,8 +184,8 @@ define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddlu8: ;CHECK: vaddl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -195,8 +195,8 @@ define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vaddlu16: ;CHECK: vaddl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -206,8 +206,8 @@ define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vaddlu32: ;CHECK: vaddl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = add <2 x i64> %tmp3, %tmp4 @@ -217,8 +217,8 @@ define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddws8: ;CHECK: vaddw.s8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp2 to <8 x i16> %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -227,8 +227,8 @@ define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vaddws16: ;CHECK: vaddw.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp2 to <4 x i32> %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -237,8 +237,8 @@ define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vaddws32: ;CHECK: vaddw.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp2 to <2 x i64> %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -247,8 +247,8 @@ define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddwu8: ;CHECK: vaddw.u8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp2 to <8 x i16> %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -257,8 +257,8 @@ define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vaddwu16: ;CHECK: vaddw.u16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -267,8 +267,8 @@ define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vaddwu32: ;CHECK: vaddw.u32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 diff --git a/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll b/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll index 148a79df0cb8..4879d73894d6 100644 --- a/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll +++ b/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll @@ -21,10 +21,10 @@ define void @varargs_func(i32 %arg1, ...) { ; CHECK-LABEL: varargs_func: ; Reserve space for the varargs save area. This currently reserves ; more than enough (16 bytes rather than the 12 bytes needed). -; CHECK: sub sp, sp, #16 +; CHECK: sub sp, sp, #12 ; CHECK: push {r11, lr} ; Align the stack pointer to a multiple of 16. -; CHECK: sub sp, sp, #8 +; CHECK: sub sp, sp, #12 ; Calculate the address of the varargs save area and save varargs ; arguments into it. ; CHECK-NEXT: add r0, sp, #20 diff --git a/test/CodeGen/ARM/vargs.ll b/test/CodeGen/ARM/vargs.ll index 3b810f36cc79..41ec03857f08 100644 --- a/test/CodeGen/ARM/vargs.ll +++ b/test/CodeGen/ARM/vargs.ll @@ -4,8 +4,8 @@ define i32 @main() { entry: - %tmp = call i32 (i8*, ...)* @printf( i8* getelementptr ([43 x i8]* @str, i32 0, i64 0), i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ) ; <i32> [#uses=0] - %tmp2 = call i32 (i8*, ...)* @printf( i8* getelementptr ([43 x i8]* @str, i32 0, i64 0), i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1 ) ; <i32> [#uses=0] + %tmp = call i32 (i8*, ...) @printf( i8* getelementptr ([43 x i8], [43 x i8]* @str, i32 0, i64 0), i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ) ; <i32> [#uses=0] + %tmp2 = call i32 (i8*, ...) @printf( i8* getelementptr ([43 x i8], [43 x i8]* @str, i32 0, i64 0), i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1 ) ; <i32> [#uses=0] ret i32 11 } diff --git a/test/CodeGen/ARM/vargs_align.ll b/test/CodeGen/ARM/vargs_align.ll index 3abb57ee51f8..6dc71352214b 100644 --- a/test/CodeGen/ARM/vargs_align.ll +++ b/test/CodeGen/ARM/vargs_align.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=EABI +; RUN: llc < %s -mtriple=armv7-linux-gnueabihf | FileCheck %s -check-prefix=EABI ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=OABI define i32 @f(i32 %a, ...) { @@ -8,16 +8,20 @@ entry: %tmp = alloca i32, align 4 ; <i32*> [#uses=2] store i32 %a, i32* %a_addr store i32 0, i32* %tmp - %tmp1 = load i32* %tmp ; <i32> [#uses=1] + %tmp1 = load i32, i32* %tmp ; <i32> [#uses=1] store i32 %tmp1, i32* %retval call void @llvm.va_start(i8* null) + call void asm sideeffect "", "~{d8}"() br label %return return: ; preds = %entry - %retval2 = load i32* %retval ; <i32> [#uses=1] + %retval2 = load i32, i32* %retval ; <i32> [#uses=1] ret i32 %retval2 -; EABI: add sp, sp, #12 ; EABI: add sp, sp, #16 +; EABI: vpop {d8} +; EABI: add sp, sp, #4 +; EABI: add sp, sp, #12 + ; OABI: add sp, sp, #12 ; OABI: add sp, sp, #12 } diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll index dfeaacf2085f..db9bc6ccdd0c 100644 --- a/test/CodeGen/ARM/vbits.ll +++ b/test/CodeGen/ARM/vbits.ll @@ -3,8 +3,8 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: v_andi8: ;CHECK: vand - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = and <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: v_andi16: ;CHECK: vand - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = and <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: v_andi32: ;CHECK: vand - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = and <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: v_andi64: ;CHECK: vand - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = and <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: v_andQi8: ;CHECK: vand - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = and <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -48,8 +48,8 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: v_andQi16: ;CHECK: vand - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = and <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -57,8 +57,8 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: v_andQi32: ;CHECK: vand - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = and <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -66,8 +66,8 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: v_andQi64: ;CHECK: vand - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = and <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -75,8 +75,8 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: v_bici8: ;CHECK: vbic - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp4 = and <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -85,8 +85,8 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: v_bici16: ;CHECK: vbic - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 > %tmp4 = and <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -95,8 +95,8 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: v_bici32: ;CHECK: vbic - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 > %tmp4 = and <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -105,8 +105,8 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: v_bici64: ;CHECK: vbic - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = xor <1 x i64> %tmp2, < i64 -1 > %tmp4 = and <1 x i64> %tmp1, %tmp3 ret <1 x i64> %tmp4 @@ -115,8 +115,8 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: v_bicQi8: ;CHECK: vbic - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp4 = and <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -125,8 +125,8 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: v_bicQi16: ;CHECK: vbic - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > %tmp4 = and <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -135,8 +135,8 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: v_bicQi32: ;CHECK: vbic - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 > %tmp4 = and <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -145,8 +145,8 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: v_bicQi64: ;CHECK: vbic - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 > %tmp4 = and <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -155,8 +155,8 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: v_eori8: ;CHECK: veor - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = xor <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -164,8 +164,8 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: v_eori16: ;CHECK: veor - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = xor <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -173,8 +173,8 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: v_eori32: ;CHECK: veor - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = xor <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -182,8 +182,8 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: v_eori64: ;CHECK: veor - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = xor <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -191,8 +191,8 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: v_eorQi8: ;CHECK: veor - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = xor <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -200,8 +200,8 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: v_eorQi16: ;CHECK: veor - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = xor <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -209,8 +209,8 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: v_eorQi32: ;CHECK: veor - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = xor <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -218,8 +218,8 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: v_eorQi64: ;CHECK: veor - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = xor <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -227,7 +227,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: v_mvni8: ;CHECK: vmvn - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > ret <8 x i8> %tmp2 } @@ -235,7 +235,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: v_mvni16: ;CHECK: vmvn - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 > ret <4 x i16> %tmp2 } @@ -243,7 +243,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: v_mvni32: ;CHECK: vmvn - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 > ret <2 x i32> %tmp2 } @@ -251,7 +251,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: v_mvni64: ;CHECK: vmvn - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = xor <1 x i64> %tmp1, < i64 -1 > ret <1 x i64> %tmp2 } @@ -259,7 +259,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: v_mvnQi8: ;CHECK: vmvn - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > ret <16 x i8> %tmp2 } @@ -267,7 +267,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: v_mvnQi16: ;CHECK: vmvn - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > ret <8 x i16> %tmp2 } @@ -275,7 +275,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: v_mvnQi32: ;CHECK: vmvn - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 > ret <4 x i32> %tmp2 } @@ -283,7 +283,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: v_mvnQi64: ;CHECK: vmvn - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 > ret <2 x i64> %tmp2 } @@ -291,8 +291,8 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: v_orri8: ;CHECK: vorr - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = or <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -300,8 +300,8 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: v_orri16: ;CHECK: vorr - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = or <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -309,8 +309,8 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: v_orri32: ;CHECK: vorr - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = or <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -318,8 +318,8 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: v_orri64: ;CHECK: vorr - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = or <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -327,8 +327,8 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: v_orrQi8: ;CHECK: vorr - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = or <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -336,8 +336,8 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: v_orrQi16: ;CHECK: vorr - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = or <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -345,8 +345,8 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: v_orrQi32: ;CHECK: vorr - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = or <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -354,8 +354,8 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: v_orrQi64: ;CHECK: vorr - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = or <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -363,8 +363,8 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: v_orni8: ;CHECK: vorn - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp4 = or <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -373,8 +373,8 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: v_orni16: ;CHECK: vorn - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 > %tmp4 = or <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -383,8 +383,8 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: v_orni32: ;CHECK: vorn - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 > %tmp4 = or <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -393,8 +393,8 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: v_orni64: ;CHECK: vorn - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = xor <1 x i64> %tmp2, < i64 -1 > %tmp4 = or <1 x i64> %tmp1, %tmp3 ret <1 x i64> %tmp4 @@ -403,8 +403,8 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: v_ornQi8: ;CHECK: vorn - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp4 = or <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -413,8 +413,8 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: v_ornQi16: ;CHECK: vorn - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > %tmp4 = or <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -423,8 +423,8 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: v_ornQi32: ;CHECK: vorn - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 > %tmp4 = or <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -433,8 +433,8 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: v_ornQi64: ;CHECK: vorn - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 > %tmp4 = or <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -443,8 +443,8 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vtsti8: ;CHECK: vtst.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = and <8 x i8> %tmp1, %tmp2 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer %tmp5 = sext <8 x i1> %tmp4 to <8 x i8> @@ -454,8 +454,8 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vtsti16: ;CHECK: vtst.16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = and <4 x i16> %tmp1, %tmp2 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer %tmp5 = sext <4 x i1> %tmp4 to <4 x i16> @@ -465,8 +465,8 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vtsti32: ;CHECK: vtst.32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = and <2 x i32> %tmp1, %tmp2 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer %tmp5 = sext <2 x i1> %tmp4 to <2 x i32> @@ -476,8 +476,8 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vtstQi8: ;CHECK: vtst.8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = and <16 x i8> %tmp1, %tmp2 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer %tmp5 = sext <16 x i1> %tmp4 to <16 x i8> @@ -487,8 +487,8 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vtstQi16: ;CHECK: vtst.16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = and <8 x i16> %tmp1, %tmp2 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer %tmp5 = sext <8 x i1> %tmp4 to <8 x i16> @@ -498,8 +498,8 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vtstQi32: ;CHECK: vtst.32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = and <4 x i32> %tmp1, %tmp2 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer %tmp5 = sext <4 x i1> %tmp4 to <4 x i32> @@ -511,7 +511,7 @@ define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { ; CHECK-NOT: vmov ; CHECK-NOT: vmvn ; CHECK: vorr - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> ret <8 x i8> %tmp3 } @@ -521,7 +521,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { ; CHECK-NOT: vmov ; CHECK-NOT: vmvn ; CHECK: vorr - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> ret <16 x i8> %tmp3 } @@ -531,7 +531,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { ; CHECK-NOT: vmov ; CHECK-NOT: vmvn ; CHECK: vbic - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > ret <8 x i8> %tmp3 } @@ -541,7 +541,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { ; CHECK-NOT: vmov ; CHECK-NOT: vmvn ; CHECK: vbic - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > ret <16 x i8> %tmp3 } diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll index 5e033fe2a647..6bcbbc8fa878 100644 --- a/test/CodeGen/ARM/vbsl-constant.ll +++ b/test/CodeGen/ARM/vbsl-constant.ll @@ -5,9 +5,9 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK: vldr ;CHECK: vldr ;CHECK: vbsl - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = and <8 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %tmp6 = and <8 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4> %tmp7 = or <8 x i8> %tmp4, %tmp6 @@ -19,9 +19,9 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind ;CHECK: vldr ;CHECK: vldr ;CHECK: vbsl - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = and <4 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3> %tmp6 = and <4 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4> %tmp7 = or <4 x i16> %tmp4, %tmp6 @@ -33,9 +33,9 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind ;CHECK: vldr ;CHECK: vldr ;CHECK: vbsl - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = and <2 x i32> %tmp1, <i32 3, i32 3> %tmp6 = and <2 x i32> %tmp3, <i32 -4, i32 -4> %tmp7 = or <2 x i32> %tmp4, %tmp6 @@ -48,9 +48,9 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind ;CHECK: vldr ;CHECK: vldr ;CHECK: vbsl - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B - %tmp3 = load <1 x i64>* %C + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B + %tmp3 = load <1 x i64>, <1 x i64>* %C %tmp4 = and <1 x i64> %tmp1, <i64 3> %tmp6 = and <1 x i64> %tmp3, <i64 -4> %tmp7 = or <1 x i64> %tmp4, %tmp6 @@ -62,9 +62,9 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind ;CHECK: vld1.32 ;CHECK: vld1.32 ;CHECK: vbsl - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B - %tmp3 = load <16 x i8>* %C + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <16 x i8>, <16 x i8>* %C %tmp4 = and <16 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4> %tmp7 = or <16 x i8> %tmp4, %tmp6 @@ -76,9 +76,9 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin ;CHECK: vld1.32 ;CHECK: vld1.32 ;CHECK: vbsl - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = and <8 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %tmp6 = and <8 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4> %tmp7 = or <8 x i16> %tmp4, %tmp6 @@ -90,9 +90,9 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin ;CHECK: vld1.32 ;CHECK: vld1.32 ;CHECK: vbsl - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = and <4 x i32> %tmp1, <i32 3, i32 3, i32 3, i32 3> %tmp6 = and <4 x i32> %tmp3, <i32 -4, i32 -4, i32 -4, i32 -4> %tmp7 = or <4 x i32> %tmp4, %tmp6 @@ -105,9 +105,9 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwin ;CHECK: vld1.32 ;CHECK: vld1.64 ;CHECK: vbsl - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = and <2 x i64> %tmp1, <i64 3, i64 3> %tmp6 = and <2 x i64> %tmp3, <i64 -4, i64 -4> %tmp7 = or <2 x i64> %tmp4, %tmp6 diff --git a/test/CodeGen/ARM/vbsl.ll b/test/CodeGen/ARM/vbsl.ll index ddc37cc82441..6812dd90a100 100644 --- a/test/CodeGen/ARM/vbsl.ll +++ b/test/CodeGen/ARM/vbsl.ll @@ -5,9 +5,9 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: v_bsli8: ;CHECK: vbsl - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = and <8 x i8> %tmp1, %tmp2 %tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp6 = and <8 x i8> %tmp5, %tmp3 @@ -18,9 +18,9 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: v_bsli16: ;CHECK: vbsl - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = and <4 x i16> %tmp1, %tmp2 %tmp5 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 > %tmp6 = and <4 x i16> %tmp5, %tmp3 @@ -31,9 +31,9 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: v_bsli32: ;CHECK: vbsl - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = and <2 x i32> %tmp1, %tmp2 %tmp5 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 > %tmp6 = and <2 x i32> %tmp5, %tmp3 @@ -44,9 +44,9 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind { ;CHECK-LABEL: v_bsli64: ;CHECK: vbsl - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B - %tmp3 = load <1 x i64>* %C + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B + %tmp3 = load <1 x i64>, <1 x i64>* %C %tmp4 = and <1 x i64> %tmp1, %tmp2 %tmp5 = xor <1 x i64> %tmp1, < i64 -1 > %tmp6 = and <1 x i64> %tmp5, %tmp3 @@ -57,9 +57,9 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { ;CHECK-LABEL: v_bslQi8: ;CHECK: vbsl - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B - %tmp3 = load <16 x i8>* %C + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <16 x i8>, <16 x i8>* %C %tmp4 = and <16 x i8> %tmp1, %tmp2 %tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp6 = and <16 x i8> %tmp5, %tmp3 @@ -70,9 +70,9 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: v_bslQi16: ;CHECK: vbsl - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = and <8 x i16> %tmp1, %tmp2 %tmp5 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > %tmp6 = and <8 x i16> %tmp5, %tmp3 @@ -83,9 +83,9 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: v_bslQi32: ;CHECK: vbsl - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = and <4 x i32> %tmp1, %tmp2 %tmp5 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 > %tmp6 = and <4 x i32> %tmp5, %tmp3 @@ -96,9 +96,9 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: v_bslQi64: ;CHECK: vbsl - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = and <2 x i64> %tmp1, %tmp2 %tmp5 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 > %tmp6 = and <2 x i64> %tmp5, %tmp3 diff --git a/test/CodeGen/ARM/vceq.ll b/test/CodeGen/ARM/vceq.ll index e3202e402cc7..3772401a2f95 100644 --- a/test/CodeGen/ARM/vceq.ll +++ b/test/CodeGen/ARM/vceq.ll @@ -3,8 +3,8 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vceqi8: ;CHECK: vceq.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = icmp eq <8 x i8> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -13,8 +13,8 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vceqi16: ;CHECK: vceq.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp eq <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -23,8 +23,8 @@ define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vceqi32: ;CHECK: vceq.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = icmp eq <2 x i32> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -33,8 +33,8 @@ define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vceqf32: ;CHECK: vceq.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -43,8 +43,8 @@ define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vceqQi8: ;CHECK: vceq.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = icmp eq <16 x i8> %tmp1, %tmp2 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -53,8 +53,8 @@ define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vceqQi16: ;CHECK: vceq.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = icmp eq <8 x i16> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -63,8 +63,8 @@ define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vceqQi32: ;CHECK: vceq.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = icmp eq <4 x i32> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -73,8 +73,8 @@ define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vceqQf32: ;CHECK: vceq.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -85,7 +85,7 @@ define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind { ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vceq.i8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll index 3739f5ee8c51..2cd33cf3a422 100644 --- a/test/CodeGen/ARM/vcge.ll +++ b/test/CodeGen/ARM/vcge.ll @@ -3,8 +3,8 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vcges8: ;CHECK: vcge.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = icmp sge <8 x i8> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -13,8 +13,8 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vcges16: ;CHECK: vcge.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp sge <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -23,8 +23,8 @@ define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vcges32: ;CHECK: vcge.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = icmp sge <2 x i32> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -33,8 +33,8 @@ define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vcgeu8: ;CHECK: vcge.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = icmp uge <8 x i8> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -43,8 +43,8 @@ define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vcgeu16: ;CHECK: vcge.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp uge <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -53,8 +53,8 @@ define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vcgeu32: ;CHECK: vcge.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = icmp uge <2 x i32> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -63,8 +63,8 @@ define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcgef32: ;CHECK: vcge.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp oge <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -73,8 +73,8 @@ define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vcgeQs8: ;CHECK: vcge.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = icmp sge <16 x i8> %tmp1, %tmp2 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -83,8 +83,8 @@ define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vcgeQs16: ;CHECK: vcge.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = icmp sge <8 x i16> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -93,8 +93,8 @@ define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vcgeQs32: ;CHECK: vcge.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = icmp sge <4 x i32> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -103,8 +103,8 @@ define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vcgeQu8: ;CHECK: vcge.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = icmp uge <16 x i8> %tmp1, %tmp2 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -113,8 +113,8 @@ define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vcgeQu16: ;CHECK: vcge.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = icmp uge <8 x i16> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -123,8 +123,8 @@ define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vcgeQu32: ;CHECK: vcge.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = icmp uge <4 x i32> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -133,8 +133,8 @@ define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vcgeQf32: ;CHECK: vcge.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = fcmp oge <4 x float> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -143,8 +143,8 @@ define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vacgef32: ;CHECK: vacge.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x i32> %tmp3 } @@ -152,8 +152,8 @@ define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vacgeQf32: ;CHECK: vacge.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x i32> %tmp3 } @@ -166,7 +166,7 @@ define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind { ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vcge.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = icmp sge <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -177,7 +177,7 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind { ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vcle.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll index 2f736f689ab1..c39c939d6c95 100644 --- a/test/CodeGen/ARM/vcgt.ll +++ b/test/CodeGen/ARM/vcgt.ll @@ -4,8 +4,8 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vcgts8: ;CHECK: vcgt.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -14,8 +14,8 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vcgts16: ;CHECK: vcgt.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -24,8 +24,8 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vcgts32: ;CHECK: vcgt.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -34,8 +34,8 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vcgtu8: ;CHECK: vcgt.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -44,8 +44,8 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vcgtu16: ;CHECK: vcgt.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -54,8 +54,8 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vcgtu32: ;CHECK: vcgt.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -64,8 +64,8 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcgtf32: ;CHECK: vcgt.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -74,8 +74,8 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vcgtQs8: ;CHECK: vcgt.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -84,8 +84,8 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vcgtQs16: ;CHECK: vcgt.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -94,8 +94,8 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vcgtQs32: ;CHECK: vcgt.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -104,8 +104,8 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vcgtQu8: ;CHECK: vcgt.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -114,8 +114,8 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vcgtQu16: ;CHECK: vcgt.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -124,8 +124,8 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vcgtQu32: ;CHECK: vcgt.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -134,8 +134,8 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vcgtQf32: ;CHECK: vcgt.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -144,8 +144,8 @@ define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vacgtf32: ;CHECK: vacgt.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x i32> %tmp3 } @@ -153,8 +153,8 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vacgtQf32: ;CHECK: vacgt.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x i32> %tmp3 } @@ -165,8 +165,8 @@ define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1 ;CHECK: vcgt.f32 [[Q1:q[0-9]+]] ;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]] - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2 %tmp4 = zext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -180,7 +180,7 @@ define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vcgt.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = icmp sgt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -191,7 +191,7 @@ define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind { ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vclt.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = icmp slt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll index 390559b82807..de251c58e6b9 100644 --- a/test/CodeGen/ARM/vcnt.ll +++ b/test/CodeGen/ARM/vcnt.ll @@ -4,7 +4,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vcnt8: ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -12,7 +12,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vcntQ8: ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -23,7 +23,7 @@ declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclz8: ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0) ret <8 x i8> %tmp2 } @@ -31,7 +31,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vclz16: ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0) ret <4 x i16> %tmp2 } @@ -39,7 +39,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vclz32: ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0) ret <2 x i32> %tmp2 } @@ -47,7 +47,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vclzQ8: ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0) ret <16 x i8> %tmp2 } @@ -55,7 +55,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vclzQ16: ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0) ret <8 x i16> %tmp2 } @@ -63,7 +63,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vclzQ32: ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0) ret <4 x i32> %tmp2 } @@ -79,7 +79,7 @@ declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclss8: ;CHECK: vcls.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -87,7 +87,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vclss16: ;CHECK: vcls.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp2 } @@ -95,7 +95,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vclss32: ;CHECK: vcls.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -103,7 +103,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vclsQs8: ;CHECK: vcls.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -111,7 +111,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vclsQs16: ;CHECK: vcls.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp2 } @@ -119,7 +119,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vclsQs32: ;CHECK: vcls.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } diff --git a/test/CodeGen/ARM/vcombine.ll b/test/CodeGen/ARM/vcombine.ll index 33aa71df0be3..9491c15aef58 100644 --- a/test/CodeGen/ARM/vcombine.ll +++ b/test/CodeGen/ARM/vcombine.ll @@ -7,8 +7,8 @@ define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LE: vmov r2, r3, d17 ; CHECK-BE: vmov r1, r0, d16 ; CHECK-BE: vmov r3, r2, d17 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp3 } @@ -19,8 +19,8 @@ define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LE: vmov r2, r3, d17 ; CHECK-BE: vmov r1, r0, d16 ; CHECK-BE: vmov r3, r2, d17 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp3 } @@ -31,8 +31,8 @@ define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LE: vmov r2, r3, d17 ; CHECK-BE: vmov r1, r0, d16 ; CHECK-BE: vmov r3, r2, d17 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp3 } @@ -43,8 +43,8 @@ define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind { ; CHECK-LE: vmov r2, r3, d17 ; CHECK-BE: vmov r1, r0, d16 ; CHECK-BE: vmov r3, r2, d17 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x float> %tmp3 } @@ -55,8 +55,8 @@ define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ; CHECK-LE: vmov r2, r3, d17 ; CHECK-BE: vmov r1, r0, d16 ; CHECK-BE: vmov r3, r2, d17 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> <i32 0, i32 1> ret <2 x i64> %tmp3 } @@ -69,7 +69,7 @@ define <4 x i16> @vget_low16(<8 x i16>* %A) nounwind { ; CHECK-NOT: vst ; CHECK-LE: vmov r0, r1, d16 ; CHECK-BE: vmov r1, r0, d16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i16> %tmp2 } @@ -79,7 +79,7 @@ define <8 x i8> @vget_high8(<16 x i8>* %A) nounwind { ; CHECK-NOT: vst ; CHECK-LE: vmov r0, r1, d17 ; CHECK-BE: vmov r1, r0, d16 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <8 x i8> %tmp2 } diff --git a/test/CodeGen/ARM/vcvt-cost.ll b/test/CodeGen/ARM/vcvt-cost.ll index 5e56a5b34cf0..c80450a28400 100644 --- a/test/CodeGen/ARM/vcvt-cost.ll +++ b/test/CodeGen/ARM/vcvt-cost.ll @@ -9,7 +9,7 @@ define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) { ; CHECK: vmovl.s8 ; CHECK: vmovl.s16 ; CHECK: vmovl.s16 - %v0 = load %T0_5* %loadaddr + %v0 = load %T0_5, %T0_5* %loadaddr ; COST: func_cvt5 ; COST: cost of 3 {{.*}} sext %r = sext %T0_5 %v0 to %T1_5 @@ -25,7 +25,7 @@ define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) { ; CHECK: vmovl.u8 ; CHECK: vmovl.u16 ; CHECK: vmovl.u16 - %v0 = load %TA0_5* %loadaddr + %v0 = load %TA0_5, %TA0_5* %loadaddr ; COST: func_cvt1 ; COST: cost of 3 {{.*}} zext %r = zext %TA0_5 %v0 to %TA1_5 @@ -40,7 +40,7 @@ define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) { ; CHECK: vmovn.i32 ; CHECK: vmovn.i32 ; CHECK: vmovn.i16 - %v0 = load %T0_51* %loadaddr + %v0 = load %T0_51, %T0_51* %loadaddr ; COST: func_cvt51 ; COST: cost of 3 {{.*}} trunc %r = trunc %T0_51 %v0 to %T1_51 @@ -56,7 +56,7 @@ define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) { ; CHECK: vmovl.s16 ; CHECK: vmovl.s16 ; CHECK: vmovl.s16 - %v0 = load %TT0_5* %loadaddr + %v0 = load %TT0_5, %TT0_5* %loadaddr ; COST: func_cvt52 ; COST: cost of 6 {{.*}} sext %r = sext %TT0_5 %v0 to %TT1_5 @@ -73,7 +73,7 @@ define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) { ; CHECK: vmovl.u16 ; CHECK: vmovl.u16 ; CHECK: vmovl.u16 - %v0 = load %TTA0_5* %loadaddr + %v0 = load %TTA0_5, %TTA0_5* %loadaddr ; COST: func_cvt12 ; COST: cost of 6 {{.*}} zext %r = zext %TTA0_5 %v0 to %TTA1_5 @@ -91,7 +91,7 @@ define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) { ; CHECK: vmovn.i32 ; CHECK: vmovn.i16 ; CHECK: vmovn.i16 - %v0 = load %TT0_51* %loadaddr + %v0 = load %TT0_51, %TT0_51* %loadaddr ; COST: func_cvt512 ; COST: cost of 6 {{.*}} trunc %r = trunc %TT0_51 %v0 to %TT1_51 @@ -103,7 +103,7 @@ define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) { define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { ; CHECK: vmovl.s32 ; CHECK: vmovl.s32 - %v0 = load <4 x i16>* %loadaddr + %v0 = load <4 x i16>, <4 x i16>* %loadaddr ; COST: sext_v4i16_v4i64 ; COST: cost of 3 {{.*}} sext %r = sext <4 x i16> %v0 to <4 x i64> @@ -115,7 +115,7 @@ define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { ; CHECK: vmovl.u32 ; CHECK: vmovl.u32 - %v0 = load <4 x i16>* %loadaddr + %v0 = load <4 x i16>, <4 x i16>* %loadaddr ; COST: zext_v4i16_v4i64 ; COST: cost of 3 {{.*}} zext %r = zext <4 x i16> %v0 to <4 x i64> @@ -129,7 +129,7 @@ define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { ; CHECK: vmovl.s32 ; CHECK: vmovl.s32 ; CHECK: vmovl.s32 - %v0 = load <8 x i16>* %loadaddr + %v0 = load <8 x i16>, <8 x i16>* %loadaddr ; COST: sext_v8i16_v8i64 ; COST: cost of 6 {{.*}} sext %r = sext <8 x i16> %v0 to <8 x i64> @@ -143,7 +143,7 @@ define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { ; CHECK: vmovl.u32 ; CHECK: vmovl.u32 ; CHECK: vmovl.u32 - %v0 = load <8 x i16>* %loadaddr + %v0 = load <8 x i16>, <8 x i16>* %loadaddr ; COST: zext_v8i16_v8i64 ; COST: cost of 6 {{.*}} zext %r = zext <8 x i16> %v0 to <8 x i64> diff --git a/test/CodeGen/ARM/vcvt-v8.ll b/test/CodeGen/ARM/vcvt-v8.ll index c449009e1e1f..9d5972fa4da5 100644 --- a/test/CodeGen/ARM/vcvt-v8.ll +++ b/test/CodeGen/ARM/vcvt-v8.ll @@ -2,7 +2,7 @@ define <4 x i32> @vcvtasq(<4 x float>* %A) { ; CHECK: vcvtasq ; CHECK: vcvta.s32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -10,7 +10,7 @@ define <4 x i32> @vcvtasq(<4 x float>* %A) { define <2 x i32> @vcvtasd(<2 x float>* %A) { ; CHECK: vcvtasd ; CHECK: vcvta.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } @@ -18,7 +18,7 @@ define <2 x i32> @vcvtasd(<2 x float>* %A) { define <4 x i32> @vcvtnsq(<4 x float>* %A) { ; CHECK: vcvtnsq ; CHECK: vcvtn.s32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -26,7 +26,7 @@ define <4 x i32> @vcvtnsq(<4 x float>* %A) { define <2 x i32> @vcvtnsd(<2 x float>* %A) { ; CHECK: vcvtnsd ; CHECK: vcvtn.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } @@ -34,7 +34,7 @@ define <2 x i32> @vcvtnsd(<2 x float>* %A) { define <4 x i32> @vcvtpsq(<4 x float>* %A) { ; CHECK: vcvtpsq ; CHECK: vcvtp.s32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -42,7 +42,7 @@ define <4 x i32> @vcvtpsq(<4 x float>* %A) { define <2 x i32> @vcvtpsd(<2 x float>* %A) { ; CHECK: vcvtpsd ; CHECK: vcvtp.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } @@ -50,7 +50,7 @@ define <2 x i32> @vcvtpsd(<2 x float>* %A) { define <4 x i32> @vcvtmsq(<4 x float>* %A) { ; CHECK: vcvtmsq ; CHECK: vcvtm.s32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -58,7 +58,7 @@ define <4 x i32> @vcvtmsq(<4 x float>* %A) { define <2 x i32> @vcvtmsd(<2 x float>* %A) { ; CHECK: vcvtmsd ; CHECK: vcvtm.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } @@ -66,7 +66,7 @@ define <2 x i32> @vcvtmsd(<2 x float>* %A) { define <4 x i32> @vcvtauq(<4 x float>* %A) { ; CHECK: vcvtauq ; CHECK: vcvta.u32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -74,7 +74,7 @@ define <4 x i32> @vcvtauq(<4 x float>* %A) { define <2 x i32> @vcvtaud(<2 x float>* %A) { ; CHECK: vcvtaud ; CHECK: vcvta.u32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } @@ -82,7 +82,7 @@ define <2 x i32> @vcvtaud(<2 x float>* %A) { define <4 x i32> @vcvtnuq(<4 x float>* %A) { ; CHECK: vcvtnuq ; CHECK: vcvtn.u32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -90,7 +90,7 @@ define <4 x i32> @vcvtnuq(<4 x float>* %A) { define <2 x i32> @vcvtnud(<2 x float>* %A) { ; CHECK: vcvtnud ; CHECK: vcvtn.u32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } @@ -98,7 +98,7 @@ define <2 x i32> @vcvtnud(<2 x float>* %A) { define <4 x i32> @vcvtpuq(<4 x float>* %A) { ; CHECK: vcvtpuq ; CHECK: vcvtp.u32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -106,7 +106,7 @@ define <4 x i32> @vcvtpuq(<4 x float>* %A) { define <2 x i32> @vcvtpud(<2 x float>* %A) { ; CHECK: vcvtpud ; CHECK: vcvtp.u32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } @@ -114,7 +114,7 @@ define <2 x i32> @vcvtpud(<2 x float>* %A) { define <4 x i32> @vcvtmuq(<4 x float>* %A) { ; CHECK: vcvtmuq ; CHECK: vcvtm.u32.f32 q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1) ret <4 x i32> %tmp2 } @@ -122,7 +122,7 @@ define <4 x i32> @vcvtmuq(<4 x float>* %A) { define <2 x i32> @vcvtmud(<2 x float>* %A) { ; CHECK: vcvtmud ; CHECK: vcvtm.u32.f32 d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %tmp1) ret <2 x i32> %tmp2 } diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll index af4e6a3b0465..78105f7e0ad1 100644 --- a/test/CodeGen/ARM/vcvt.ll +++ b/test/CodeGen/ARM/vcvt.ll @@ -3,7 +3,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vcvt_f32tos32: ;CHECK: vcvt.s32.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } @@ -11,7 +11,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vcvt_f32tou32: ;CHECK: vcvt.u32.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } @@ -19,7 +19,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vcvt_s32tof32: ;CHECK: vcvt.f32.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float> ret <2 x float> %tmp2 } @@ -27,7 +27,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vcvt_u32tof32: ;CHECK: vcvt.f32.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float> ret <2 x float> %tmp2 } @@ -35,7 +35,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vcvtQ_f32tos32: ;CHECK: vcvt.s32.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32> ret <4 x i32> %tmp2 } @@ -43,7 +43,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vcvtQ_f32tou32: ;CHECK: vcvt.u32.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32> ret <4 x i32> %tmp2 } @@ -51,7 +51,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vcvtQ_s32tof32: ;CHECK: vcvt.f32.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float> ret <4 x float> %tmp2 } @@ -59,7 +59,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vcvtQ_u32tof32: ;CHECK: vcvt.f32.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float> ret <4 x float> %tmp2 } @@ -67,7 +67,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vcvt_n_f32tos32: ;CHECK: vcvt.s32.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1) ret <2 x i32> %tmp2 } @@ -75,7 +75,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind { define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vcvt_n_f32tou32: ;CHECK: vcvt.u32.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1) ret <2 x i32> %tmp2 } @@ -83,7 +83,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind { define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vcvt_n_s32tof32: ;CHECK: vcvt.f32.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) ret <2 x float> %tmp2 } @@ -91,7 +91,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind { define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vcvt_n_u32tof32: ;CHECK: vcvt.f32.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) ret <2 x float> %tmp2 } @@ -104,7 +104,7 @@ declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwi define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vcvtQ_n_f32tos32: ;CHECK: vcvt.s32.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1) ret <4 x i32> %tmp2 } @@ -112,7 +112,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind { define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vcvtQ_n_f32tou32: ;CHECK: vcvt.u32.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1) ret <4 x i32> %tmp2 } @@ -120,7 +120,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind { define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vcvtQ_n_s32tof32: ;CHECK: vcvt.f32.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) ret <4 x float> %tmp2 } @@ -128,7 +128,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind { define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vcvtQ_n_u32tof32: ;CHECK: vcvt.f32.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) ret <4 x float> %tmp2 } @@ -141,7 +141,7 @@ declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwi define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vcvt_f16tof32: ;CHECK: vcvt.f32.f16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1) ret <4 x float> %tmp2 } @@ -149,7 +149,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind { ;CHECK-LABEL: vcvt_f32tof16: ;CHECK: vcvt.f16.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1) ret <4 x i16> %tmp2 } @@ -180,8 +180,8 @@ define <2 x i64> @fix_float_to_i64(<2 x float> %in) { define <4 x i16> @fix_double_to_i16(<4 x double> %in) { ; CHECK-LABEL: fix_double_to_i16: -; CHECK: vcvt.s32.f64 -; CHECK: vcvt.s32.f64 +; CHECK: vcvt.u32.f64 +; CHECK: vcvt.u32.f64 %scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0> %conv = fptoui <4 x double> %scale to <4 x i16> diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll index 07ba230757be..0c856e8d7617 100644 --- a/test/CodeGen/ARM/vcvt_combine.ll +++ b/test/CodeGen/ARM/vcvt_combine.ll @@ -7,7 +7,7 @@ ; CHECK-NOT: vmul define void @t0() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> @@ -23,7 +23,7 @@ declare void @foo_int32x2_t(<2 x i32>) ; CHECK-NOT: vmul define void @t1() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> @@ -39,7 +39,7 @@ declare void @foo_uint32x2_t(<2 x i32>) ; CHECK: vmul define void @t2() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000> @@ -53,7 +53,7 @@ entry: ; CHECK: vmul define void @t3() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000> @@ -67,7 +67,7 @@ entry: ; CHECK-NOT: vmul define void @t4() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000> @@ -81,7 +81,7 @@ entry: ; CHECK-NOT: vmul define void @t5() nounwind { entry: - %tmp = load float* @in, align 4 + %tmp = load float, float* @in, align 4 %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2 diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll index 96807f7280f8..8c6e4ba35054 100644 --- a/test/CodeGen/ARM/vdiv_combine.ll +++ b/test/CodeGen/ARM/vdiv_combine.ll @@ -11,7 +11,7 @@ declare void @foo_int32x4_t(<4 x i32>) ; CHECK-NOT: {{vdiv|vmul}} define void @t1() nounwind { entry: - %tmp = load i32* @iin, align 4 + %tmp = load i32, i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -27,7 +27,7 @@ declare void @foo_float32x2_t(<2 x float>) ; CHECK-NOT: {{vdiv|vmul}} define void @t2() nounwind { entry: - %tmp = load i32* @uin, align 4 + %tmp = load i32, i32* @uin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float> @@ -41,7 +41,7 @@ entry: ; CHECK: {{vdiv|vmul}} define void @t3() nounwind { entry: - %tmp = load i32* @iin, align 4 + %tmp = load i32, i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -55,7 +55,7 @@ entry: ; CHECK: {{vdiv|vmul}} define void @t4() nounwind { entry: - %tmp = load i32* @iin, align 4 + %tmp = load i32, i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -69,7 +69,7 @@ entry: ; CHECK-NOT: {{vdiv|vmul}} define void @t5() nounwind { entry: - %tmp = load i32* @iin, align 4 + %tmp = load i32, i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -83,7 +83,7 @@ entry: ; CHECK-NOT: {{vdiv|vmul}} define void @t6() nounwind { entry: - %tmp = load i32* @iin, align 4 + %tmp = load i32, i32* @iin, align 4 %vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1 %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2 diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index 89f355c68751..36eebbfc4650 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -166,7 +166,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind { define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vduplane8: ;CHECK: vdup.8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > ret <8 x i8> %tmp2 } @@ -174,7 +174,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vduplane16: ;CHECK: vdup.16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ret <4 x i16> %tmp2 } @@ -182,7 +182,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind { define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vduplane32: ;CHECK: vdup.32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 > ret <2 x i32> %tmp2 } @@ -190,7 +190,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind { define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind { ;CHECK-LABEL: vduplanefloat: ;CHECK: vdup.32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 > ret <2 x float> %tmp2 } @@ -198,7 +198,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind { define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vduplaneQ8: ;CHECK: vdup.8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > ret <16 x i8> %tmp2 } @@ -206,7 +206,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind { define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vduplaneQ16: ;CHECK: vdup.16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > ret <8 x i16> %tmp2 } @@ -214,7 +214,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind { define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vduplaneQ32: ;CHECK: vdup.32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ret <4 x i32> %tmp2 } @@ -222,7 +222,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind { define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { ;CHECK-LABEL: vduplaneQfloat: ;CHECK: vdup.32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ret <4 x float> %tmp2 } @@ -347,17 +347,17 @@ define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) { define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) { ;CHECK-LABEL: check_spr_splat4: -;CHECK: vdup.32 q +;CHECK: vld1.16 %conv = sitofp i16 %q to float %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer %sub = fsub <4 x float> %splat.splat, %p ret <4 x float> %sub } - +; Same codegen as above test; scalar is splatted using vld1, so shuffle index is irrelevant. define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) { ;CHECK-LABEL: check_spr_splat4_lane1: -;CHECK: vdup.32 q{{.*}}, d{{.*}}[1] +;CHECK: vld1.16 %conv = sitofp i16 %q to float %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index 759da2235e41..29f4bb972a24 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -21,12 +21,20 @@ bb.i19: ; preds = %bb.i19, %bb3 define void @test_illegal_build_vector() nounwind { entry: store <2 x i64> undef, <2 x i64>* undef, align 16 - %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] + %0 = load <16 x i8>, <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] store <16 x i8> %1, <16 x i8>* undef, align 16 ret void } +; PR22678 +; Check CONCAT_VECTORS DAG combiner pass doesn't introduce illegal types. +define void @test_pr22678() { + %1 = fptoui <16 x float> undef to <16 x i8> + store <16 x i8> %1, <16 x i8>* undef + ret void +} + ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is ; converted back to be used as a vector type. ; CHECK-LABEL: test_vmovrrd_combine: @@ -55,7 +63,7 @@ bb2: ; Test trying to do a ShiftCombine on illegal types. ; The vector should be split first. define void @lshrIllegalType(<8 x i32>* %A) nounwind { - %tmp1 = load <8 x i32>* %A + %tmp1 = load <8 x i32>, <8 x i32>* %A %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> store <8 x i32> %tmp2, <8 x i32>* %A ret void @@ -81,7 +89,7 @@ declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind { ; CHECK: i64_buildvector ; CHECK: vldr - %t0 = load i64* %ptr, align 4 + %t0 = load i64, i64* %ptr, align 4 %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0 store <2 x i64> %t1, <2 x i64>* %vp ret void @@ -90,8 +98,8 @@ define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind { define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind { ; CHECK: i64_insertelement ; CHECK: vldr - %t0 = load i64* %ptr, align 4 - %vec = load <2 x i64>* %vp + %t0 = load i64, i64* %ptr, align 4 + %vec = load <2 x i64>, <2 x i64>* %vp %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0 store <2 x i64> %t1, <2 x i64>* %vp ret void @@ -100,7 +108,7 @@ define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind { define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind { ; CHECK: i64_extractelement ; CHECK: vstr - %vec = load <2 x i64>* %vp + %vec = load <2 x i64>, <2 x i64>* %vp %t1 = extractelement <2 x i64> %vec, i32 0 store i64 %t1, i64* %ptr ret void @@ -108,7 +116,7 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind { ; Test trying to do a AND Combine on illegal types. define void @andVec(<3 x i8>* %A) nounwind { - %tmp = load <3 x i8>* %A, align 4 + %tmp = load <3 x i8>, <3 x i8>* %A, align 4 %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7> store <3 x i8> %and, <3 x i8>* %A ret void @@ -117,7 +125,7 @@ define void @andVec(<3 x i8>* %A) nounwind { ; Test trying to do an OR Combine on illegal types. define void @orVec(<3 x i8>* %A) nounwind { - %tmp = load <3 x i8>* %A, align 4 + %tmp = load <3 x i8>, <3 x i8>* %A, align 4 %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7> store <3 x i8> %or, <3 x i8>* %A ret void @@ -138,7 +146,7 @@ define i16 @foldBuildVectors() { ; shuffles. ; CHECK-LABEL: reverse_v8i16: define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) { - %v0 = load <8 x i16>* %loadaddr + %v0 = load <8 x i16>, <8 x i16>* %loadaddr ; CHECK: vrev64.16 ; CHECK: vext.16 %v1 = shufflevector <8 x i16> %v0, <8 x i16> undef, @@ -151,7 +159,7 @@ define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) { ; shuffles. ; CHECK-LABEL: reverse_v16i8: define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) { - %v0 = load <16 x i8>* %loadaddr + %v0 = load <16 x i8>, <16 x i8>* %loadaddr ; CHECK: vrev64.8 ; CHECK: vext.8 %v1 = shufflevector <16 x i8> %v0, <16 x i8> undef, @@ -172,9 +180,9 @@ define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) { define <8 x i16> @t3(i8 zeroext %xf, i8* nocapture %sp0, i8* nocapture %sp1, i32* nocapture %outp) { entry: %pix_sp0.0.cast = bitcast i8* %sp0 to i32* - %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1 + %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1 %pix_sp1.0.cast = bitcast i8* %sp1 to i32* - %pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1 + %pix_sp1.0.copyload = load i32, i32* %pix_sp1.0.cast, align 1 %vecinit = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 %vecinit1 = insertelement <2 x i32> %vecinit, i32 %pix_sp1.0.copyload, i32 1 %0 = bitcast <2 x i32> %vecinit1 to <8 x i8> @@ -192,7 +200,7 @@ define <8 x i16> @t4(i8* nocapture %sp0) { ; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0] entry: %pix_sp0.0.cast = bitcast i8* %sp0 to i32* - %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1 + %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1 %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 %0 = bitcast <2 x i32> %vec to <8 x i8> %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0) @@ -211,11 +219,11 @@ entry: define <8 x i16> @t5(i8* nocapture %sp0, i8* nocapture %sp1, i8* nocapture %sp2) { entry: %pix_sp0.0.cast = bitcast i8* %sp0 to i32* - %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1 + %pix_sp0.0.copyload = load i32, i32* %pix_sp0.0.cast, align 1 %pix_sp1.0.cast = bitcast i8* %sp1 to i32* - %pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1 + %pix_sp1.0.copyload = load i32, i32* %pix_sp1.0.cast, align 1 %pix_sp2.0.cast = bitcast i8* %sp2 to i32* - %pix_sp2.0.copyload = load i32* %pix_sp2.0.cast, align 1 + %pix_sp2.0.copyload = load i32, i32* %pix_sp2.0.cast, align 1 %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 1 %vecinit1 = insertelement <2 x i32> %vec, i32 %pix_sp1.0.copyload, i32 0 %vecinit2 = insertelement <2 x i32> %vec, i32 %pix_sp2.0.copyload, i32 0 diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll index f3218969c78e..d054bfda615e 100644 --- a/test/CodeGen/ARM/vector-extend-narrow.ll +++ b/test/CodeGen/ARM/vector-extend-narrow.ll @@ -2,9 +2,9 @@ ; CHECK-LABEL: f: define float @f(<4 x i16>* nocapture %in) { - ; CHECK: vldr + ; CHECK: vld1 ; CHECK: vmovl.u16 - %1 = load <4 x i16>* %in + %1 = load <4 x i16>, <4 x i16>* %in ; CHECK: vcvt.f32.u32 %2 = uitofp <4 x i16> %1 to <4 x float> %3 = extractelement <4 x float> %2, i32 0 @@ -25,7 +25,7 @@ define float @g(<4 x i8>* nocapture %in) { ; CHECK: vld1 ; CHECK: vmovl.u8 ; CHECK: vmovl.u16 - %1 = load <4 x i8>* %in + %1 = load <4 x i8>, <4 x i8>* %in ; CHECK: vcvt.f32.u32 %2 = uitofp <4 x i8> %1 to <4 x float> %3 = extractelement <4 x float> %2, i32 0 @@ -58,7 +58,7 @@ define <4 x i8> @i(<4 x i8>* %x) { ; CHECK: vrecps ; CHECK: vmul ; CHECK: vmovn - %1 = load <4 x i8>* %x, align 4 + %1 = load <4 x i8>, <4 x i8>* %x, align 4 %2 = sdiv <4 x i8> zeroinitializer, %1 ret <4 x i8> %2 } @@ -68,7 +68,7 @@ define <4 x i32> @j(<4 x i8>* %in) nounwind { ; CHECK: vmovl.u8 ; CHECK: vmovl.u16 ; CHECK-NOT: vand - %1 = load <4 x i8>* %in, align 4 + %1 = load <4 x i8>, <4 x i8>* %in, align 4 %2 = zext <4 x i8> %1 to <4 x i32> ret <4 x i32> %2 } diff --git a/test/CodeGen/ARM/vector-load.ll b/test/CodeGen/ARM/vector-load.ll new file mode 100644 index 000000000000..17f134f458a2 --- /dev/null +++ b/test/CodeGen/ARM/vector-load.ll @@ -0,0 +1,253 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +define <8 x i8> @load_v8i8(<8 x i8>** %ptr) { +;CHECK-LABEL: load_v8i8: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <8 x i8>*, <8 x i8>** %ptr + %lA = load <8 x i8>, <8 x i8>* %A, align 1 + ret <8 x i8> %lA +} + +define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) { +;CHECK-LABEL: load_v8i8_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i8>*, <8 x i8>** %ptr + %lA = load <8 x i8>, <8 x i8>* %A, align 1 + %inc = getelementptr <8 x i8>, <8 x i8>* %A, i38 1 + store <8 x i8>* %inc, <8 x i8>** %ptr + ret <8 x i8> %lA +} + +define <4 x i16> @load_v4i16(<4 x i16>** %ptr) { +;CHECK-LABEL: load_v4i16: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x i16>*, <4 x i16>** %ptr + %lA = load <4 x i16>, <4 x i16>* %A, align 1 + ret <4 x i16> %lA +} + +define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) { +;CHECK-LABEL: load_v4i16_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i16>*, <4 x i16>** %ptr + %lA = load <4 x i16>, <4 x i16>* %A, align 1 + %inc = getelementptr <4 x i16>, <4 x i16>* %A, i34 1 + store <4 x i16>* %inc, <4 x i16>** %ptr + ret <4 x i16> %lA +} + +define <2 x i32> @load_v2i32(<2 x i32>** %ptr) { +;CHECK-LABEL: load_v2i32: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x i32>*, <2 x i32>** %ptr + %lA = load <2 x i32>, <2 x i32>* %A, align 1 + ret <2 x i32> %lA +} + +define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) { +;CHECK-LABEL: load_v2i32_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i32>*, <2 x i32>** %ptr + %lA = load <2 x i32>, <2 x i32>* %A, align 1 + %inc = getelementptr <2 x i32>, <2 x i32>* %A, i32 1 + store <2 x i32>* %inc, <2 x i32>** %ptr + ret <2 x i32> %lA +} + +define <2 x float> @load_v2f32(<2 x float>** %ptr) { +;CHECK-LABEL: load_v2f32: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x float>*, <2 x float>** %ptr + %lA = load <2 x float>, <2 x float>* %A, align 1 + ret <2 x float> %lA +} + +define <2 x float> @load_v2f32_update(<2 x float>** %ptr) { +;CHECK-LABEL: load_v2f32_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x float>*, <2 x float>** %ptr + %lA = load <2 x float>, <2 x float>* %A, align 1 + %inc = getelementptr <2 x float>, <2 x float>* %A, i32 1 + store <2 x float>* %inc, <2 x float>** %ptr + ret <2 x float> %lA +} + +define <1 x i64> @load_v1i64(<1 x i64>** %ptr) { +;CHECK-LABEL: load_v1i64: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <1 x i64>*, <1 x i64>** %ptr + %lA = load <1 x i64>, <1 x i64>* %A, align 1 + ret <1 x i64> %lA +} + +define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) { +;CHECK-LABEL: load_v1i64_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <1 x i64>*, <1 x i64>** %ptr + %lA = load <1 x i64>, <1 x i64>* %A, align 1 + %inc = getelementptr <1 x i64>, <1 x i64>* %A, i31 1 + store <1 x i64>* %inc, <1 x i64>** %ptr + ret <1 x i64> %lA +} + +define <16 x i8> @load_v16i8(<16 x i8>** %ptr) { +;CHECK-LABEL: load_v16i8: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <16 x i8>*, <16 x i8>** %ptr + %lA = load <16 x i8>, <16 x i8>* %A, align 1 + ret <16 x i8> %lA +} + +define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) { +;CHECK-LABEL: load_v16i8_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <16 x i8>*, <16 x i8>** %ptr + %lA = load <16 x i8>, <16 x i8>* %A, align 1 + %inc = getelementptr <16 x i8>, <16 x i8>* %A, i316 1 + store <16 x i8>* %inc, <16 x i8>** %ptr + ret <16 x i8> %lA +} + +define <8 x i16> @load_v8i16(<8 x i16>** %ptr) { +;CHECK-LABEL: load_v8i16: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <8 x i16>*, <8 x i16>** %ptr + %lA = load <8 x i16>, <8 x i16>* %A, align 1 + ret <8 x i16> %lA +} + +define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) { +;CHECK-LABEL: load_v8i16_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i16>*, <8 x i16>** %ptr + %lA = load <8 x i16>, <8 x i16>* %A, align 1 + %inc = getelementptr <8 x i16>, <8 x i16>* %A, i38 1 + store <8 x i16>* %inc, <8 x i16>** %ptr + ret <8 x i16> %lA +} + +define <4 x i32> @load_v4i32(<4 x i32>** %ptr) { +;CHECK-LABEL: load_v4i32: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x i32>*, <4 x i32>** %ptr + %lA = load <4 x i32>, <4 x i32>* %A, align 1 + ret <4 x i32> %lA +} + +define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) { +;CHECK-LABEL: load_v4i32_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i32>*, <4 x i32>** %ptr + %lA = load <4 x i32>, <4 x i32>* %A, align 1 + %inc = getelementptr <4 x i32>, <4 x i32>* %A, i34 1 + store <4 x i32>* %inc, <4 x i32>** %ptr + ret <4 x i32> %lA +} + +define <4 x float> @load_v4f32(<4 x float>** %ptr) { +;CHECK-LABEL: load_v4f32: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x float>*, <4 x float>** %ptr + %lA = load <4 x float>, <4 x float>* %A, align 1 + ret <4 x float> %lA +} + +define <4 x float> @load_v4f32_update(<4 x float>** %ptr) { +;CHECK-LABEL: load_v4f32_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x float>*, <4 x float>** %ptr + %lA = load <4 x float>, <4 x float>* %A, align 1 + %inc = getelementptr <4 x float>, <4 x float>* %A, i34 1 + store <4 x float>* %inc, <4 x float>** %ptr + ret <4 x float> %lA +} + +define <2 x i64> @load_v2i64(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x i64>*, <2 x i64>** %ptr + %lA = load <2 x i64>, <2 x i64>* %A, align 1 + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + %lA = load <2 x i64>, <2 x i64>* %A, align 1 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +; Make sure we change the type to match alignment if necessary. +define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned2: +;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + %lA = load <2 x i64>, <2 x i64>* %A, align 2 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned4: +;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + %lA = load <2 x i64>, <2 x i64>* %A, align 4 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned8: +;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + %lA = load <2 x i64>, <2 x i64>* %A, align 8 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned16: +;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]! + %A = load <2 x i64>*, <2 x i64>** %ptr + %lA = load <2 x i64>, <2 x i64>* %A, align 16 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +; Make sure we don't break smaller-than-dreg extloads. +define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) { +;CHECK-LABEL: zextload_v8i8tov8i32: +;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32] +;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} +;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} + %A = load <4 x i8>*, <4 x i8>** %ptr + %lA = load <4 x i8>, <4 x i8>* %A, align 4 + %zlA = zext <4 x i8> %lA to <4 x i32> + ret <4 x i32> %zlA +} + +define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) { +;CHECK-LABEL: zextload_v8i8tov8i32_fake_update: +;CHECK: ldr.w r[[PTRREG:[0-9]+]], [r0] +;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32] +;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16 +;CHECK: str.w r[[INCREG]], [r0] +;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} +;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} + %A = load <4 x i8>*, <4 x i8>** %ptr + %lA = load <4 x i8>, <4 x i8>* %A, align 4 + %inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4 + store <4 x i8>* %inc, <4 x i8>** %ptr + %zlA = zext <4 x i8> %lA to <4 x i32> + ret <4 x i32> %zlA +} diff --git a/test/CodeGen/ARM/vector-promotion.ll b/test/CodeGen/ARM/vector-promotion.ll index 42ceb60c47f5..1dabee386089 100644 --- a/test/CodeGen/ARM/vector-promotion.ll +++ b/test/CodeGen/ARM/vector-promotion.ll @@ -3,7 +3,7 @@ ; RUN: llc -mtriple=thumbv7-apple-ios %s -o - -mattr=+neon | FileCheck --check-prefix=ASM %s ; IR-BOTH-LABEL: @simpleOneInstructionPromotion -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1> ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[VECTOR_OR]], i32 1 ; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest @@ -16,7 +16,7 @@ ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32] ; ASM-NEXT: bx define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = or i32 %extract, 1 store i32 %out, i32* %dest, align 4 @@ -24,7 +24,7 @@ define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) { } ; IR-BOTH-LABEL: @unsupportedInstructionForPromotion -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0 ; IR-BOTH-NEXT: [[CMP:%[a-zA-Z_0-9-]+]] = icmp eq i32 [[EXTRACT]], %in2 ; IR-BOTH-NEXT: store i1 [[CMP]], i1* %dest @@ -35,7 +35,7 @@ define void @simpleOneInstructionPromotion(<2 x i32>* %addr1, i32* %dest) { ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]] ; ASM: bx define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 0 %out = icmp eq i32 %extract, %in2 store i1 %out, i1* %dest, align 4 @@ -44,7 +44,7 @@ define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1* ; IR-BOTH-LABEL: @unsupportedChainInDifferentBBs -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0 ; IR-BOTH-NEXT: br i1 %bool, label %bb2, label %end ; BB2 @@ -58,7 +58,7 @@ define void @unsupportedInstructionForPromotion(<2 x i32>* %addr1, i32 %in2, i1* ; ASM: bx define void @unsupportedChainInDifferentBBs(<2 x i32>* %addr1, i32* %dest, i1 %bool) { bb1: - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 0 br i1 %bool, label %bb2, label %end bb2: @@ -70,7 +70,7 @@ end: } ; IR-LABEL: @chainOfInstructionsToPromote -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[VECTOR_OR1:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 1, i32 undef> ; IR-BOTH-NEXT: [[VECTOR_OR2:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR1]], <i32 1, i32 undef> ; IR-BOTH-NEXT: [[VECTOR_OR3:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[VECTOR_OR2]], <i32 1, i32 undef> @@ -87,7 +87,7 @@ end: ; ASM-NOT: vmov.32 {{r[0-9]+}}, [[LOAD]] ; ASM: bx define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 0 %out1 = or i32 %extract, 1 %out2 = or i32 %out1, 1 @@ -101,7 +101,7 @@ define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) { } ; IR-BOTH-LABEL: @unsupportedMultiUses -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 ; IR-BOTH-NEXT: [[OR:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1 ; IR-BOTH-NEXT: store i32 [[OR]], i32* %dest @@ -112,7 +112,7 @@ define void @chainOfInstructionsToPromote(<2 x i32>* %addr1, i32* %dest) { ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]] ; ASM: bx define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = or i32 %extract, 1 store i32 %out, i32* %dest, align 4 @@ -122,7 +122,7 @@ define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) { ; Check that we promote we a splat constant when this is a division. ; The NORMAL mode does not promote anything as divisions are not legal. ; IR-BOTH-LABEL: @udivCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7 @@ -133,7 +133,7 @@ define i32 @unsupportedMultiUses(<2 x i32>* %addr1, i32* %dest) { ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @udivCase(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = udiv i32 %extract, 7 store i32 %out, i32* %dest, align 4 @@ -141,7 +141,7 @@ define void @udivCase(<2 x i32>* %addr1, i32* %dest) { } ; IR-BOTH-LABEL: @uremCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7 @@ -152,7 +152,7 @@ define void @udivCase(<2 x i32>* %addr1, i32* %dest) { ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @uremCase(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = urem i32 %extract, 7 store i32 %out, i32* %dest, align 4 @@ -160,7 +160,7 @@ define void @uremCase(<2 x i32>* %addr1, i32* %dest) { } ; IR-BOTH-LABEL: @sdivCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7 @@ -171,7 +171,7 @@ define void @uremCase(<2 x i32>* %addr1, i32* %dest) { ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @sdivCase(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = sdiv i32 %extract, 7 store i32 %out, i32* %dest, align 4 @@ -179,7 +179,7 @@ define void @sdivCase(<2 x i32>* %addr1, i32* %dest) { } ; IR-BOTH-LABEL: @sremCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7 @@ -190,7 +190,7 @@ define void @sdivCase(<2 x i32>* %addr1, i32* %dest) { ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @sremCase(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = srem i32 %extract, 7 store i32 %out, i32* %dest, align 4 @@ -198,7 +198,7 @@ define void @sremCase(<2 x i32>* %addr1, i32* %dest) { } ; IR-BOTH-LABEL: @fdivCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fdiv float [[EXTRACT]], 7.0 @@ -209,7 +209,7 @@ define void @sremCase(<2 x i32>* %addr1, i32* %dest) { ; IR-BOTH-NEXT: store float [[RES]], float* %dest ; IR-BOTH-NEXT: ret define void @fdivCase(<2 x float>* %addr1, float* %dest) { - %in1 = load <2 x float>* %addr1, align 8 + %in1 = load <2 x float>, <2 x float>* %addr1, align 8 %extract = extractelement <2 x float> %in1, i32 1 %out = fdiv float %extract, 7.0 store float %out, float* %dest, align 4 @@ -217,7 +217,7 @@ define void @fdivCase(<2 x float>* %addr1, float* %dest) { } ; IR-BOTH-LABEL: @fremCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem float [[EXTRACT]], 7.0 @@ -228,7 +228,7 @@ define void @fdivCase(<2 x float>* %addr1, float* %dest) { ; IR-BOTH-NEXT: store float [[RES]], float* %dest ; IR-BOTH-NEXT: ret define void @fremCase(<2 x float>* %addr1, float* %dest) { - %in1 = load <2 x float>* %addr1, align 8 + %in1 = load <2 x float>, <2 x float>* %addr1, align 8 %extract = extractelement <2 x float> %in1, i32 1 %out = frem float %extract, 7.0 store float %out, float* %dest, align 4 @@ -238,13 +238,13 @@ define void @fremCase(<2 x float>* %addr1, float* %dest) { ; Check that we do not promote when we may introduce undefined behavior ; like division by zero. ; IR-BOTH-LABEL: @undefDivCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 ; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 7, [[EXTRACT]] ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = udiv i32 7, %extract store i32 %out, i32* %dest, align 4 @@ -255,13 +255,13 @@ define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) { ; Check that we do not promote when we may introduce undefined behavior ; like division by zero. ; IR-BOTH-LABEL: @undefRemCase -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 ; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 7, [[EXTRACT]] ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 %out = srem i32 7, %extract store i32 %out, i32* %dest, align 4 @@ -271,7 +271,7 @@ define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) { ; Check that we use an undef mask for undefined behavior if the fast-math ; flag is set. ; IR-BOTH-LABEL: @undefConstantFRemCaseWithFastMath -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float [[EXTRACT]], 7.0 @@ -282,7 +282,7 @@ define void @undefRemCase(<2 x i32>* %addr1, i32* %dest) { ; IR-BOTH-NEXT: store float [[RES]], float* %dest ; IR-BOTH-NEXT: ret define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) { - %in1 = load <2 x float>* %addr1, align 8 + %in1 = load <2 x float>, <2 x float>* %addr1, align 8 %extract = extractelement <2 x float> %in1, i32 1 %out = frem nnan float %extract, 7.0 store float %out, float* %dest, align 4 @@ -292,7 +292,7 @@ define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest ; Check that we use an undef mask for undefined behavior if the fast-math ; flag is set. ; IR-BOTH-LABEL: @undefVectorFRemCaseWithFastMath -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = frem nnan float 7.000000e+00, [[EXTRACT]] @@ -303,7 +303,7 @@ define void @undefConstantFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest ; IR-BOTH-NEXT: store float [[RES]], float* %dest ; IR-BOTH-NEXT: ret define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) { - %in1 = load <2 x float>* %addr1, align 8 + %in1 = load <2 x float>, <2 x float>* %addr1, align 8 %extract = extractelement <2 x float> %in1, i32 1 %out = frem nnan float 7.0, %extract store float %out, float* %dest, align 4 @@ -314,7 +314,7 @@ define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) ; This requires the STRESS mode, as floating point value are ; not promote on armv7. ; IR-BOTH-LABEL: @simpleOneInstructionPromotionFloat -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x float>, <2 x float>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x float> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = fadd float [[EXTRACT]], 1.0 @@ -325,7 +325,7 @@ define void @undefVectorFRemCaseWithFastMath(<2 x float>* %addr1, float* %dest) ; IR-BOTH-NEXT: store float [[RES]], float* %dest ; IR-BOTH-NEXT: ret define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %dest) { - %in1 = load <2 x float>* %addr1, align 8 + %in1 = load <2 x float>, <2 x float>* %addr1, align 8 %extract = extractelement <2 x float> %in1, i32 1 %out = fadd float %extract, 1.0 store float %out, float* %dest, align 4 @@ -337,7 +337,7 @@ define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %des ; This requires the STRESS modes, as variable index are expensive ; to lower. ; IR-BOTH-LABEL: @simpleOneInstructionPromotionVariableIdx -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 %idx ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1 @@ -348,7 +348,7 @@ define void @simpleOneInstructionPromotionFloat(<2 x float>* %addr1, float* %des ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %dest, i32 %idx) { - %in1 = load <2 x i32>* %addr1, align 8 + %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 %idx %out = or i32 %extract, 1 store i32 %out, i32* %dest, align 4 @@ -360,7 +360,7 @@ define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %d ; as legal or custom, althought the actual assembly is better if we were ; promoting it. ; IR-BOTH-LABEL: @simpleOneInstructionPromotion8x8 -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <8 x i8>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <8 x i8>, <8 x i8>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <8 x i8> [[LOAD]], i32 1 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = or i8 [[EXTRACT]], 1 @@ -371,7 +371,7 @@ define void @simpleOneInstructionPromotionVariableIdx(<2 x i32>* %addr1, i32* %d ; IR-BOTH-NEXT: store i8 [[RES]], i8* %dest ; IR-BOTH-NEXT: ret define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) { - %in1 = load <8 x i8>* %addr1, align 8 + %in1 = load <8 x i8>, <8 x i8>* %addr1, align 8 %extract = extractelement <8 x i8> %in1, i32 1 %out = or i8 %extract, 1 store i8 %out, i8* %dest, align 4 @@ -381,7 +381,7 @@ define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) { ; Check that we optimized the sequence correctly when it can be ; lowered on a Q register. ; IR-BOTH-LABEL: @simpleOneInstructionPromotion -; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <4 x i32>* %addr1 +; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <4 x i32>, <4 x i32>* %addr1 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <4 x i32> [[LOAD]], <i32 undef, i32 1, i32 undef, i32 undef> ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <4 x i32> [[VECTOR_OR]], i32 1 ; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest @@ -395,7 +395,7 @@ define void @simpleOneInstructionPromotion8x8(<8 x i8>* %addr1, i8* %dest) { ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1] ; ASM-NEXT: bx define void @simpleOneInstructionPromotion4x32(<4 x i32>* %addr1, i32* %dest) { - %in1 = load <4 x i32>* %addr1, align 8 + %in1 = load <4 x i32>, <4 x i32>* %addr1, align 8 %extract = extractelement <4 x i32> %in1, i32 1 %out = or i32 %extract, 1 store i32 %out, i32* %dest, align 1 diff --git a/test/CodeGen/ARM/vector-spilling.ll b/test/CodeGen/ARM/vector-spilling.ll index 746c6dfcd114..9e3225ebcda0 100644 --- a/test/CodeGen/ARM/vector-spilling.ll +++ b/test/CodeGen/ARM/vector-spilling.ll @@ -10,22 +10,22 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; CHECK: vldmia define void @test(<8 x i64>* %src) #0 { entry: - %0 = getelementptr inbounds <8 x i64>* %src, i32 0 - %1 = load <8 x i64>* %0, align 8 + %0 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 0 + %1 = load <8 x i64>, <8 x i64>* %0, align 8 - %2 = getelementptr inbounds <8 x i64>* %src, i32 1 - %3 = load <8 x i64>* %2, align 8 + %2 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 1 + %3 = load <8 x i64>, <8 x i64>* %2, align 8 - %4 = getelementptr inbounds <8 x i64>* %src, i32 2 - %5 = load <8 x i64>* %4, align 8 + %4 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 2 + %5 = load <8 x i64>, <8 x i64>* %4, align 8 - %6 = getelementptr inbounds <8 x i64>* %src, i32 3 - %7 = load <8 x i64>* %6, align 8 + %6 = getelementptr inbounds <8 x i64>, <8 x i64>* %src, i32 3 + %7 = load <8 x i64>, <8 x i64>* %6, align 8 %8 = shufflevector <8 x i64> %1, <8 x i64> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %9 = shufflevector <8 x i64> %1, <8 x i64> %3, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> - tail call void(<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>)* @foo(<8 x i64> %1, <8 x i64> %3, <8 x i64> %5, <8 x i64> %7, <8 x i64> %8, <8 x i64> %9) + tail call void(<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>) @foo(<8 x i64> %1, <8 x i64> %3, <8 x i64> %5, <8 x i64> %7, <8 x i64> %8, <8 x i64> %9) ret void } diff --git a/test/CodeGen/ARM/vector-store.ll b/test/CodeGen/ARM/vector-store.ll new file mode 100644 index 000000000000..30baa9a20ddc --- /dev/null +++ b/test/CodeGen/ARM/vector-store.ll @@ -0,0 +1,258 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) { +;CHECK-LABEL: store_v8i8: +;CHECK: str r1, [r0] + %A = load <8 x i8>*, <8 x i8>** %ptr + store <8 x i8> %val, <8 x i8>* %A, align 1 + ret void +} + +define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) { +;CHECK-LABEL: store_v8i8_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i8>*, <8 x i8>** %ptr + store <8 x i8> %val, <8 x i8>* %A, align 1 + %inc = getelementptr <8 x i8>, <8 x i8>* %A, i38 1 + store <8 x i8>* %inc, <8 x i8>** %ptr + ret void +} + +define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) { +;CHECK-LABEL: store_v4i16: +;CHECK: str r1, [r0] + %A = load <4 x i16>*, <4 x i16>** %ptr + store <4 x i16> %val, <4 x i16>* %A, align 1 + ret void +} + +define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) { +;CHECK-LABEL: store_v4i16_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i16>*, <4 x i16>** %ptr + store <4 x i16> %val, <4 x i16>* %A, align 1 + %inc = getelementptr <4 x i16>, <4 x i16>* %A, i34 1 + store <4 x i16>* %inc, <4 x i16>** %ptr + ret void +} + +define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) { +;CHECK-LABEL: store_v2i32: +;CHECK: str r1, [r0] + %A = load <2 x i32>*, <2 x i32>** %ptr + store <2 x i32> %val, <2 x i32>* %A, align 1 + ret void +} + +define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) { +;CHECK-LABEL: store_v2i32_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i32>*, <2 x i32>** %ptr + store <2 x i32> %val, <2 x i32>* %A, align 1 + %inc = getelementptr <2 x i32>, <2 x i32>* %A, i32 1 + store <2 x i32>* %inc, <2 x i32>** %ptr + ret void +} + +define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) { +;CHECK-LABEL: store_v2f32: +;CHECK: str r1, [r0] + %A = load <2 x float>*, <2 x float>** %ptr + store <2 x float> %val, <2 x float>* %A, align 1 + ret void +} + +define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) { +;CHECK-LABEL: store_v2f32_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x float>*, <2 x float>** %ptr + store <2 x float> %val, <2 x float>* %A, align 1 + %inc = getelementptr <2 x float>, <2 x float>* %A, i32 1 + store <2 x float>* %inc, <2 x float>** %ptr + ret void +} + +define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) { +;CHECK-LABEL: store_v1i64: +;CHECK: str r1, [r0] + %A = load <1 x i64>*, <1 x i64>** %ptr + store <1 x i64> %val, <1 x i64>* %A, align 1 + ret void +} + +define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) { +;CHECK-LABEL: store_v1i64_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <1 x i64>*, <1 x i64>** %ptr + store <1 x i64> %val, <1 x i64>* %A, align 1 + %inc = getelementptr <1 x i64>, <1 x i64>* %A, i31 1 + store <1 x i64>* %inc, <1 x i64>** %ptr + ret void +} + +define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) { +;CHECK-LABEL: store_v16i8: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <16 x i8>*, <16 x i8>** %ptr + store <16 x i8> %val, <16 x i8>* %A, align 1 + ret void +} + +define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) { +;CHECK-LABEL: store_v16i8_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <16 x i8>*, <16 x i8>** %ptr + store <16 x i8> %val, <16 x i8>* %A, align 1 + %inc = getelementptr <16 x i8>, <16 x i8>* %A, i316 1 + store <16 x i8>* %inc, <16 x i8>** %ptr + ret void +} + +define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) { +;CHECK-LABEL: store_v8i16: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <8 x i16>*, <8 x i16>** %ptr + store <8 x i16> %val, <8 x i16>* %A, align 1 + ret void +} + +define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) { +;CHECK-LABEL: store_v8i16_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i16>*, <8 x i16>** %ptr + store <8 x i16> %val, <8 x i16>* %A, align 1 + %inc = getelementptr <8 x i16>, <8 x i16>* %A, i38 1 + store <8 x i16>* %inc, <8 x i16>** %ptr + ret void +} + +define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: store_v4i32: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x i32>*, <4 x i32>** %ptr + store <4 x i32> %val, <4 x i32>* %A, align 1 + ret void +} + +define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: store_v4i32_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i32>*, <4 x i32>** %ptr + store <4 x i32> %val, <4 x i32>* %A, align 1 + %inc = getelementptr <4 x i32>, <4 x i32>* %A, i34 1 + store <4 x i32>* %inc, <4 x i32>** %ptr + ret void +} + +define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) { +;CHECK-LABEL: store_v4f32: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x float>*, <4 x float>** %ptr + store <4 x float> %val, <4 x float>* %A, align 1 + ret void +} + +define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) { +;CHECK-LABEL: store_v4f32_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x float>*, <4 x float>** %ptr + store <4 x float> %val, <4 x float>* %A, align 1 + %inc = getelementptr <4 x float>, <4 x float>* %A, i34 1 + store <4 x float>* %inc, <4 x float>** %ptr + ret void +} + +define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x i64>*, <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 1 + ret void +} + +define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 1 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned2: +;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 2 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned4: +;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 4 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned8: +;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>*, <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 8 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned16: +;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]! + %A = load <2 x i64>*, <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 16 + %inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: truncstore_v4i32tov4i8: +;CHECK: ldr.w r9, [sp] +;CHECK: vmov {{d[0-9]+}}, r3, r9 +;CHECK: vmov {{d[0-9]+}}, r1, r2 +;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} +;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} +;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] +;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32] + %A = load <4 x i8>*, <4 x i8>** %ptr + %trunc = trunc <4 x i32> %val to <4 x i8> + store <4 x i8> %trunc, <4 x i8>* %A, align 4 + ret void +} + +define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update: +;CHECK: ldr.w r9, [sp] +;CHECK: vmov {{d[0-9]+}}, r3, r9 +;CHECK: vmov {{d[0-9]+}}, r1, r2 +;CHECK: movs [[IMM16:r[0-9]+]], #16 +;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} +;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} +;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] +;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]] +;CHECK: str r[[PTRREG]], [r0] + %A = load <4 x i8>*, <4 x i8>** %ptr + %trunc = trunc <4 x i32> %val to <4 x i8> + store <4 x i8> %trunc, <4 x i8>* %A, align 4 + %inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4 + store <4 x i8>* %inc, <4 x i8>** %ptr + ret void +} diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 4407451244e9..72ecf0ef0626 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -3,8 +3,8 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextd: ;CHECK: vext - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextRd: ;CHECK: vext - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4> ret <8 x i8> %tmp3 } @@ -21,8 +21,8 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextq: ;CHECK: vext - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> ret <16 x i8> %tmp3 } @@ -30,8 +30,8 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextRq: ;CHECK: vext - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> ret <16 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: test_vextd16: ;CHECK: vext - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: test_vextq32: ;CHECK: vext - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> ret <4 x i32> %tmp3 } @@ -59,8 +59,8 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextd_undef: ;CHECK: vext - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10> ret <8 x i8> %tmp3 } @@ -68,8 +68,8 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextRq_undef: ;CHECK: vext - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6> ret <16 x i8> %tmp3 } @@ -118,8 +118,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: vext.16 ;CHECK-NOT: vext.16 ;CHECK: vzip.16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9> ret <4 x i16> %tmp3 } @@ -128,8 +128,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: test_undef: ;CHECK: vzip.16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9> ret <4 x i16> %tmp3 } @@ -143,7 +143,7 @@ define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind { ;CHECK: vmov.16 [[REG]][1] ;CHECK: vmov.16 [[REG]][2] ;CHECK: vmov.16 [[REG]][3] - %tmp1 = load <32 x i16>* %B + %tmp1 = load <32 x i16>, <32 x i16>* %B %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24> ret <4 x i16> %tmp2 } @@ -156,7 +156,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { ;CHECK: vmov.16 [[REG]][1] ;CHECK: vmov.16 [[REG]][2] ;CHECK: vmov.16 [[REG]][3] - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> ret <4 x i16> %tmp2 } @@ -174,8 +174,8 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: vmov.16 [[REG2]][1] ;CHECK: vmov.16 [[REG2]][2] ;CHECK: vmov.16 [[REG2]][3] - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9> ret <8 x i16> %tmp3 } @@ -185,7 +185,7 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind { ; CHECK-LABEL: test_elem_mismatch: ; CHECK: vstr - %tmp0 = load <2 x i64>* %src, align 16 + %tmp0 = load <2 x i64>, <2 x i64>* %src, align 16 %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32> %tmp2 = extractelement <4 x i32> %tmp1, i32 0 %tmp3 = extractelement <4 x i32> %tmp1, i32 2 diff --git a/test/CodeGen/ARM/vfcmp.ll b/test/CodeGen/ARM/vfcmp.ll index 4b2fea9baa09..8673b7d639d6 100644 --- a/test/CodeGen/ARM/vfcmp.ll +++ b/test/CodeGen/ARM/vfcmp.ll @@ -7,8 +7,8 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcunef32: ;CHECK: vceq.f32 ;CHECK-NEXT: vmvn - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp une <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -18,8 +18,8 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind { define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcoltf32: ;CHECK: vcgt.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp olt <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -29,8 +29,8 @@ define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcolef32: ;CHECK: vcge.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp ole <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -41,8 +41,8 @@ define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcugef32: ;CHECK: vcgt.f32 ;CHECK-NEXT: vmvn - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp uge <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -53,8 +53,8 @@ define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vculef32: ;CHECK: vcgt.f32 ;CHECK-NEXT: vmvn - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp ule <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -65,8 +65,8 @@ define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcugtf32: ;CHECK: vcge.f32 ;CHECK-NEXT: vmvn - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp ugt <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -77,8 +77,8 @@ define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vcultf32: ;CHECK: vcge.f32 ;CHECK-NEXT: vmvn - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp ult <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -91,8 +91,8 @@ define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr ;CHECK-NEXT: vmvn - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -104,8 +104,8 @@ define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK: vcgt.f32 ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp one <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -118,8 +118,8 @@ define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr ;CHECK-NEXT: vmvn - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp uno <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -131,8 +131,8 @@ define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK: vcge.f32 ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fcmp ord <2 x float> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 diff --git a/test/CodeGen/ARM/vfp-libcalls.ll b/test/CodeGen/ARM/vfp-libcalls.ll index 9d4e194e90ee..b08073ab62b3 100644 --- a/test/CodeGen/ARM/vfp-libcalls.ll +++ b/test/CodeGen/ARM/vfp-libcalls.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=armv6-apple-ios -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-HARD ; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFTISH -; RUN: llc -mtriple=armv7s-apple-ios -soft-float -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFT +; RUN: llc -mtriple=armv7s-apple-ios -mattr=+soft-float -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFT define float @test_call(float %a, float %b) { ; CHECK-HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} @@ -8,4 +8,4 @@ define float @test_call(float %a, float %b) { ; CHECK-SOFT: bl ___addsf3{{$}} %sum = fadd float %a, %b ret float %sum -}
\ No newline at end of file +} diff --git a/test/CodeGen/ARM/vfp-regs-dwarf.ll b/test/CodeGen/ARM/vfp-regs-dwarf.ll index b67f770bfd13..eca0c26e5562 100644 --- a/test/CodeGen/ARM/vfp-regs-dwarf.ll +++ b/test/CodeGen/ARM/vfp-regs-dwarf.ll @@ -31,14 +31,14 @@ define void @stack_offsets() { !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!8, !9} -!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/tim/llvm/build/tmp.c] [DW_LANG_C99] -!1 = !{!"tmp.c", !"/Users/tim/llvm/build"} +!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!1 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build") !2 = !{} !3 = !{!4} -!4 = !{!"0x2e\00bar\00bar\00\001\000\001\000\006\000\000\001", !1, !5, !6, null, void ()* @stack_offsets, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [bar] -!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/Users/tim/llvm/build/tmp.c] -!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @stack_offsets, variables: !2) +!5 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build") +!6 = !DISubroutineType(types: !7) !7 = !{null} !8 = !{i32 2, !"Dwarf Version", i32 4} -!9 = !{i32 1, !"Debug Info Version", i32 2} +!9 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll index 5d2943cbfd2f..03c0354aa1df 100644 --- a/test/CodeGen/ARM/vfp.ll +++ b/test/CodeGen/ARM/vfp.ll @@ -2,8 +2,8 @@ ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s define void @test(float* %P, double* %D) { - %A = load float* %P ; <float> [#uses=1] - %B = load double* %D ; <double> [#uses=1] + %A = load float, float* %P ; <float> [#uses=1] + %B = load double, double* %D ; <double> [#uses=1] store float %A, float* %P store double %B, double* %D ret void @@ -15,11 +15,11 @@ declare double @fabs(double) define void @test_abs(float* %P, double* %D) { ;CHECK-LABEL: test_abs: - %a = load float* %P ; <float> [#uses=1] + %a = load float, float* %P ; <float> [#uses=1] ;CHECK: vabs.f32 %b = call float @fabsf( float %a ) readnone ; <float> [#uses=1] store float %b, float* %P - %A = load double* %D ; <double> [#uses=1] + %A = load double, double* %D ; <double> [#uses=1] ;CHECK: vabs.f64 %B = call double @fabs( double %A ) readnone ; <double> [#uses=1] store double %B, double* %D @@ -28,10 +28,10 @@ define void @test_abs(float* %P, double* %D) { define void @test_add(float* %P, double* %D) { ;CHECK-LABEL: test_add: - %a = load float* %P ; <float> [#uses=2] + %a = load float, float* %P ; <float> [#uses=2] %b = fadd float %a, %a ; <float> [#uses=1] store float %b, float* %P - %A = load double* %D ; <double> [#uses=2] + %A = load double, double* %D ; <double> [#uses=2] %B = fadd double %A, %A ; <double> [#uses=1] store double %B, double* %D ret void @@ -39,11 +39,11 @@ define void @test_add(float* %P, double* %D) { define void @test_ext_round(float* %P, double* %D) { ;CHECK-LABEL: test_ext_round: - %a = load float* %P ; <float> [#uses=1] + %a = load float, float* %P ; <float> [#uses=1] ;CHECK: vcvt.f64.f32 ;CHECK: vcvt.f32.f64 %b = fpext float %a to double ; <double> [#uses=1] - %A = load double* %D ; <double> [#uses=1] + %A = load double, double* %D ; <double> [#uses=1] %B = fptrunc double %A to float ; <float> [#uses=1] store double %b, double* %D store float %B, float* %P @@ -52,9 +52,9 @@ define void @test_ext_round(float* %P, double* %D) { define void @test_fma(float* %P1, float* %P2, float* %P3) { ;CHECK-LABEL: test_fma: - %a1 = load float* %P1 ; <float> [#uses=1] - %a2 = load float* %P2 ; <float> [#uses=1] - %a3 = load float* %P3 ; <float> [#uses=1] + %a1 = load float, float* %P1 ; <float> [#uses=1] + %a2 = load float, float* %P2 ; <float> [#uses=1] + %a3 = load float, float* %P3 ; <float> [#uses=1] ;CHECK: vnmls.f32 %X = fmul float %a1, %a2 ; <float> [#uses=1] %Y = fsub float %X, %a3 ; <float> [#uses=1] @@ -64,7 +64,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) { define i32 @test_ftoi(float* %P1) { ;CHECK-LABEL: test_ftoi: - %a1 = load float* %P1 ; <float> [#uses=1] + %a1 = load float, float* %P1 ; <float> [#uses=1] ;CHECK: vcvt.s32.f32 %b1 = fptosi float %a1 to i32 ; <i32> [#uses=1] ret i32 %b1 @@ -72,7 +72,7 @@ define i32 @test_ftoi(float* %P1) { define i32 @test_ftou(float* %P1) { ;CHECK-LABEL: test_ftou: - %a1 = load float* %P1 ; <float> [#uses=1] + %a1 = load float, float* %P1 ; <float> [#uses=1] ;CHECK: vcvt.u32.f32 %b1 = fptoui float %a1 to i32 ; <i32> [#uses=1] ret i32 %b1 @@ -80,7 +80,7 @@ define i32 @test_ftou(float* %P1) { define i32 @test_dtoi(double* %P1) { ;CHECK-LABEL: test_dtoi: - %a1 = load double* %P1 ; <double> [#uses=1] + %a1 = load double, double* %P1 ; <double> [#uses=1] ;CHECK: vcvt.s32.f64 %b1 = fptosi double %a1 to i32 ; <i32> [#uses=1] ret i32 %b1 @@ -88,7 +88,7 @@ define i32 @test_dtoi(double* %P1) { define i32 @test_dtou(double* %P1) { ;CHECK-LABEL: test_dtou: - %a1 = load double* %P1 ; <double> [#uses=1] + %a1 = load double, double* %P1 ; <double> [#uses=1] ;CHECK: vcvt.u32.f64 %b1 = fptoui double %a1 to i32 ; <i32> [#uses=1] ret i32 %b1 @@ -113,9 +113,9 @@ define void @test_utod2(double* %P1, i8 %X) { define void @test_cmp(float* %glob, i32 %X) { ;CHECK-LABEL: test_cmp: entry: - %tmp = load float* %glob ; <float> [#uses=2] - %tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1] - %tmp4 = load float* %tmp3 ; <float> [#uses=2] + %tmp = load float, float* %glob ; <float> [#uses=2] + %tmp3 = getelementptr float, float* %glob, i32 2 ; <float*> [#uses=1] + %tmp4 = load float, float* %tmp3 ; <float> [#uses=2] %tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4 ; <i1> [#uses=1] %tmp5 = fcmp uno float %tmp, %tmp4 ; <i1> [#uses=1] %tmp6 = or i1 %tmp.upgrd.1, %tmp5 ; <i1> [#uses=1] @@ -124,11 +124,11 @@ entry: br i1 %tmp6, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp.upgrd.2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp.upgrd.2 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] ret void cond_false: ; preds = %entry - %tmp7 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0] + %tmp7 = tail call i32 (...) @baz( ) ; <i32> [#uses=0] ret void } @@ -141,16 +141,16 @@ declare i32 @baz(...) define void @test_cmpfp0(float* %glob, i32 %X) { ;CHECK-LABEL: test_cmpfp0: entry: - %tmp = load float* %glob ; <float> [#uses=1] + %tmp = load float, float* %glob ; <float> [#uses=1] ;CHECK: vcmpe.f32 %tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00 ; <i1> [#uses=1] br i1 %tmp.upgrd.3, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp.upgrd.4 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp.upgrd.4 = tail call i32 (...) @bar( ) ; <i32> [#uses=0] ret void cond_false: ; preds = %entry - %tmp1 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0] + %tmp1 = tail call i32 (...) @baz( ) ; <i32> [#uses=0] ret void } diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll index 2518ee2278cc..d4cbfad5be6f 100644 --- a/test/CodeGen/ARM/vget_lane.ll +++ b/test/CodeGen/ARM/vget_lane.ll @@ -5,7 +5,7 @@ target triple = "thumbv7-elf" define i32 @vget_lanes8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vget_lanes8: ;CHECK: vmov.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = extractelement <8 x i8> %tmp1, i32 1 %tmp3 = sext i8 %tmp2 to i32 ret i32 %tmp3 @@ -14,7 +14,7 @@ define i32 @vget_lanes8(<8 x i8>* %A) nounwind { define i32 @vget_lanes16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vget_lanes16: ;CHECK: vmov.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = extractelement <4 x i16> %tmp1, i32 1 %tmp3 = sext i16 %tmp2 to i32 ret i32 %tmp3 @@ -23,7 +23,7 @@ define i32 @vget_lanes16(<4 x i16>* %A) nounwind { define i32 @vget_laneu8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vget_laneu8: ;CHECK: vmov.u8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = extractelement <8 x i8> %tmp1, i32 1 %tmp3 = zext i8 %tmp2 to i32 ret i32 %tmp3 @@ -32,7 +32,7 @@ define i32 @vget_laneu8(<8 x i8>* %A) nounwind { define i32 @vget_laneu16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vget_laneu16: ;CHECK: vmov.u16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = extractelement <4 x i16> %tmp1, i32 1 %tmp3 = zext i16 %tmp2 to i32 ret i32 %tmp3 @@ -42,7 +42,7 @@ define i32 @vget_laneu16(<4 x i16>* %A) nounwind { define i32 @vget_lanei32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vget_lanei32: ;CHECK: vmov.32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = add <2 x i32> %tmp1, %tmp1 %tmp3 = extractelement <2 x i32> %tmp2, i32 1 ret i32 %tmp3 @@ -51,7 +51,7 @@ define i32 @vget_lanei32(<2 x i32>* %A) nounwind { define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vgetQ_lanes8: ;CHECK: vmov.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = extractelement <16 x i8> %tmp1, i32 1 %tmp3 = sext i8 %tmp2 to i32 ret i32 %tmp3 @@ -60,7 +60,7 @@ define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind { define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vgetQ_lanes16: ;CHECK: vmov.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = extractelement <8 x i16> %tmp1, i32 1 %tmp3 = sext i16 %tmp2 to i32 ret i32 %tmp3 @@ -69,7 +69,7 @@ define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind { define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vgetQ_laneu8: ;CHECK: vmov.u8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = extractelement <16 x i8> %tmp1, i32 1 %tmp3 = zext i8 %tmp2 to i32 ret i32 %tmp3 @@ -78,7 +78,7 @@ define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind { define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vgetQ_laneu16: ;CHECK: vmov.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = extractelement <8 x i16> %tmp1, i32 1 %tmp3 = zext i16 %tmp2 to i32 ret i32 %tmp3 @@ -88,7 +88,7 @@ define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind { define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vgetQ_lanei32: ;CHECK: vmov.32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = add <4 x i32> %tmp1, %tmp1 %tmp3 = extractelement <4 x i32> %tmp2, i32 1 ret i32 %tmp3 @@ -100,7 +100,7 @@ entry: %arg0_uint16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] %out_uint16_t = alloca i16 ; <i16*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - %0 = load <4 x i16>* %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1] + %0 = load <4 x i16>, <4 x i16>* %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1] %1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1] %2 = add i16 %1, %1 store i16 %2, i16* %out_uint16_t, align 2 @@ -116,7 +116,7 @@ entry: %arg0_uint8x8_t = alloca <8 x i8> ; <<8 x i8>*> [#uses=1] %out_uint8_t = alloca i8 ; <i8*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - %0 = load <8 x i8>* %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1] + %0 = load <8 x i8>, <8 x i8>* %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1] %1 = extractelement <8 x i8> %0, i32 1 ; <i8> [#uses=1] %2 = add i8 %1, %1 store i8 %2, i8* %out_uint8_t, align 1 @@ -132,7 +132,7 @@ entry: %arg0_uint16x8_t = alloca <8 x i16> ; <<8 x i16>*> [#uses=1] %out_uint16_t = alloca i16 ; <i16*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - %0 = load <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1] + %0 = load <8 x i16>, <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1] %1 = extractelement <8 x i16> %0, i32 1 ; <i16> [#uses=1] %2 = add i16 %1, %1 store i16 %2, i16* %out_uint16_t, align 2 @@ -148,7 +148,7 @@ entry: %arg0_uint8x16_t = alloca <16 x i8> ; <<16 x i8>*> [#uses=1] %out_uint8_t = alloca i8 ; <i8*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - %0 = load <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1] + %0 = load <16 x i8>, <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1] %1 = extractelement <16 x i8> %0, i32 1 ; <i8> [#uses=1] %2 = add i8 %1, %1 store i8 %2, i8* %out_uint8_t, align 1 @@ -161,7 +161,7 @@ return: ; preds = %entry define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind { ;CHECK-LABEL: vset_lane8: ;CHECK: vmov.8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1 ret <8 x i8> %tmp2 } @@ -169,7 +169,7 @@ define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind { define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind { ;CHECK-LABEL: vset_lane16: ;CHECK: vmov.16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1 ret <4 x i16> %tmp2 } @@ -177,7 +177,7 @@ define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind { define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind { ;CHECK-LABEL: vset_lane32: ;CHECK: vmov.32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1 ret <2 x i32> %tmp2 } @@ -185,7 +185,7 @@ define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind { define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind { ;CHECK-LABEL: vsetQ_lane8: ;CHECK: vmov.8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1 ret <16 x i8> %tmp2 } @@ -193,7 +193,7 @@ define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind { define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind { ;CHECK-LABEL: vsetQ_lane16: ;CHECK: vmov.16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1 ret <8 x i16> %tmp2 } @@ -201,7 +201,7 @@ define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind { define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind { ;CHECK-LABEL: vsetQ_lane32: ;CHECK: vmov.32 d{{.*}}[1], r1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1 ret <4 x i32> %tmp2 } @@ -219,14 +219,14 @@ entry: ; be an immediate constant. Make sure a variable lane number is handled. define i32 @vget_variable_lanes8(<8 x i8>* %A, i32 %B) nounwind { - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = extractelement <8 x i8> %tmp1, i32 %B %tmp3 = sext i8 %tmp2 to i32 ret i32 %tmp3 } define i32 @vgetQ_variable_lanei32(<4 x i32>* %A, i32 %B) nounwind { - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = add <4 x i32> %tmp1, %tmp1 %tmp3 = extractelement <4 x i32> %tmp2, i32 %B ret i32 %tmp3 diff --git a/test/CodeGen/ARM/vhadd.ll b/test/CodeGen/ARM/vhadd.ll index 6183db3702b3..01e239d5c73a 100644 --- a/test/CodeGen/ARM/vhadd.ll +++ b/test/CodeGen/ARM/vhadd.ll @@ -3,8 +3,8 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vhadds8: ;CHECK: vhadd.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vhadds16: ;CHECK: vhadd.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vhadds32: ;CHECK: vhadd.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vhaddu8: ;CHECK: vhadd.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vhaddu16: ;CHECK: vhadd.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vhaddu32: ;CHECK: vhadd.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vhaddQs8: ;CHECK: vhadd.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -66,8 +66,8 @@ define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vhaddQs16: ;CHECK: vhadd.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -75,8 +75,8 @@ define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vhaddQs32: ;CHECK: vhadd.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -84,8 +84,8 @@ define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vhaddQu8: ;CHECK: vhadd.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -93,8 +93,8 @@ define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vhaddQu16: ;CHECK: vhadd.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -102,8 +102,8 @@ define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vhaddQu32: ;CHECK: vhadd.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -127,8 +127,8 @@ declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind rea define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vrhadds8: ;CHECK: vrhadd.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -136,8 +136,8 @@ define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vrhadds16: ;CHECK: vrhadd.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -145,8 +145,8 @@ define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vrhadds32: ;CHECK: vrhadd.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -154,8 +154,8 @@ define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vrhaddu8: ;CHECK: vrhadd.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -163,8 +163,8 @@ define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vrhaddu16: ;CHECK: vrhadd.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -172,8 +172,8 @@ define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vrhaddu32: ;CHECK: vrhadd.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -181,8 +181,8 @@ define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vrhaddQs8: ;CHECK: vrhadd.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -190,8 +190,8 @@ define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrhaddQs16: ;CHECK: vrhadd.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -199,8 +199,8 @@ define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vrhaddQs32: ;CHECK: vrhadd.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -208,8 +208,8 @@ define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vrhaddQu8: ;CHECK: vrhadd.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -217,8 +217,8 @@ define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrhaddQu16: ;CHECK: vrhadd.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -226,8 +226,8 @@ define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vrhaddQu32: ;CHECK: vrhadd.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } diff --git a/test/CodeGen/ARM/vhsub.ll b/test/CodeGen/ARM/vhsub.ll index f1a0cb27f576..7b3b29ac6e1a 100644 --- a/test/CodeGen/ARM/vhsub.ll +++ b/test/CodeGen/ARM/vhsub.ll @@ -3,8 +3,8 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vhsubs8: ;CHECK: vhsub.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vhsubs16: ;CHECK: vhsub.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vhsubs32: ;CHECK: vhsub.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vhsubu8: ;CHECK: vhsub.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vhsubu16: ;CHECK: vhsub.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vhsubu32: ;CHECK: vhsub.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vhsubQs8: ;CHECK: vhsub.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -66,8 +66,8 @@ define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vhsubQs16: ;CHECK: vhsub.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -75,8 +75,8 @@ define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vhsubQs32: ;CHECK: vhsub.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -84,8 +84,8 @@ define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vhsubQu8: ;CHECK: vhsub.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -93,8 +93,8 @@ define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vhsubQu16: ;CHECK: vhsub.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -102,8 +102,8 @@ define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vhsubQu32: ;CHECK: vhsub.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } diff --git a/test/CodeGen/ARM/vicmp.ll b/test/CodeGen/ARM/vicmp.ll index bebb32062f71..21b104a0d045 100644 --- a/test/CodeGen/ARM/vicmp.ll +++ b/test/CodeGen/ARM/vicmp.ll @@ -10,8 +10,8 @@ define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vcnei8: ;CHECK: vceq.i8 ;CHECK-NEXT: vmvn - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = icmp ne <8 x i8> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -21,8 +21,8 @@ define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vcnei16: ;CHECK: vceq.i16 ;CHECK-NEXT: vmvn - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp ne <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -32,8 +32,8 @@ define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vcnei32: ;CHECK: vceq.i32 ;CHECK-NEXT: vmvn - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = icmp ne <2 x i32> %tmp1, %tmp2 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -43,8 +43,8 @@ define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vcneQi8: ;CHECK: vceq.i8 ;CHECK-NEXT: vmvn - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = icmp ne <16 x i8> %tmp1, %tmp2 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -54,8 +54,8 @@ define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vcneQi16: ;CHECK: vceq.i16 ;CHECK-NEXT: vmvn - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = icmp ne <8 x i16> %tmp1, %tmp2 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -65,8 +65,8 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vcneQi32: ;CHECK: vceq.i32 ;CHECK-NEXT: vmvn - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = icmp ne <4 x i32> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -75,8 +75,8 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vcltQs8: ;CHECK: vcgt.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = icmp slt <16 x i8> %tmp1, %tmp2 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -85,8 +85,8 @@ define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vcles16: ;CHECK: vcge.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp sle <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -95,8 +95,8 @@ define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vcltu16: ;CHECK: vcgt.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = icmp ult <4 x i16> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -105,8 +105,8 @@ define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vcleQu32: ;CHECK: vcge.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = icmp ule <4 x i32> %tmp1, %tmp2 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index db640f54b0e6..8064ea4a320a 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -23,10 +23,10 @@ define <4 x i16> @vld1i16(i16* %A) nounwind { define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { ;CHECK-LABEL: vld1i16_update: ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]! - %A = load i16** %ptr + %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) - %tmp2 = getelementptr i16* %A, i32 4 + %tmp2 = getelementptr i16, i16* %A, i32 4 store i16* %tmp2, i16** %ptr ret <4 x i16> %tmp1 } @@ -43,10 +43,10 @@ define <2 x i32> @vld1i32(i32* %A) nounwind { define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld1i32_update: ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}} - %A = load i32** %ptr + %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) - %tmp2 = getelementptr i32* %A, i32 %inc + %tmp2 = getelementptr i32, i32* %A, i32 %inc store i32* %tmp2, i32** %ptr ret <2 x i32> %tmp1 } @@ -79,9 +79,9 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { ;CHECK-LABEL: vld1Qi8_update: ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]! - %A = load i8** %ptr + %A = load i8*, i8** %ptr %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) - %tmp2 = getelementptr i8* %A, i32 16 + %tmp2 = getelementptr i8, i8* %A, i32 16 store i8* %tmp2, i8** %ptr ret <16 x i8> %tmp1 } diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index 7ac5cc709b33..391b49152cd9 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -60,13 +60,13 @@ define <2 x float> @vld2f(float* %A) nounwind { define <2 x float> @vld2f_update(float** %ptr) nounwind { ;CHECK-LABEL: vld2f_update: ;CHECK: vld2.32 {d16, d17}, [r1]! - %A = load float** %ptr + %A = load float*, float** %ptr %tmp0 = bitcast float* %A to i8* %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1 %tmp4 = fadd <2 x float> %tmp2, %tmp3 - %tmp5 = getelementptr float* %A, i32 4 + %tmp5 = getelementptr float, float* %A, i32 4 store float* %tmp5, float** %ptr ret <2 x float> %tmp4 } @@ -98,12 +98,12 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind { define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld2Qi8_update: ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1 - %A = load i8** %ptr + %A = load i8*, i8** %ptr %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16) %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1 %tmp4 = add <16 x i8> %tmp2, %tmp3 - %tmp5 = getelementptr i8* %A, i32 %inc + %tmp5 = getelementptr i8, i8* %A, i32 %inc store i8* %tmp5, i8** %ptr ret <16 x i8> %tmp4 } diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index 171a03c24da1..0d14179ba73a 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -38,13 +38,13 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld3i16_update: ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}} - %A = load i16** %ptr + %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 - %tmp5 = getelementptr i16* %A, i32 %inc + %tmp5 = getelementptr i16, i16* %A, i32 %inc store i16* %tmp5, i16** %ptr ret <4 x i16> %tmp4 } @@ -88,7 +88,7 @@ define <1 x i64> @vld3i64_update(i64** %ptr, i64* %A) nounwind { ;CHECK: vld1.64 {d16, d17, d18}, [r1:64]! %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16) - %tmp5 = getelementptr i64* %A, i32 3 + %tmp5 = getelementptr i64, i64* %A, i32 3 store i64* %tmp5, i64** %ptr %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2 @@ -137,13 +137,13 @@ define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { ;CHECK-LABEL: vld3Qi32_update: ;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]! ;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]! - %A = load i32** %ptr + %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 - %tmp5 = getelementptr i32* %A, i32 12 + %tmp5 = getelementptr i32, i32* %A, i32 12 store i32* %tmp5, i32** %ptr ret <4 x i32> %tmp4 } diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index 94ad143ae0fd..575e0fa717fb 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -26,12 +26,12 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld4i8_update: ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1 - %A = load i8** %ptr + %A = load i8*, i8** %ptr %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16) %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 %tmp4 = add <8 x i8> %tmp2, %tmp3 - %tmp5 = getelementptr i8* %A, i32 %inc + %tmp5 = getelementptr i8, i8* %A, i32 %inc store i8* %tmp5, i8** %ptr ret <8 x i8> %tmp4 } @@ -88,7 +88,7 @@ define <1 x i64> @vld4i64_update(i64** %ptr, i64* %A) nounwind { ;CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]! %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64) - %tmp5 = getelementptr i64* %A, i32 4 + %tmp5 = getelementptr i64, i64* %A, i32 4 store i64* %tmp5, i64** %ptr %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 @@ -126,13 +126,13 @@ define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { ;CHECK-LABEL: vld4Qi16_update: ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]! ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]! - %A = load i16** %ptr + %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8) %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 - %tmp5 = getelementptr i16* %A, i32 32 + %tmp5 = getelementptr i16, i16* %A, i32 32 store i16* %tmp5, i16** %ptr ret <8 x i16> %tmp4 } diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll index 64aac562c1eb..09304d87d53b 100644 --- a/test/CodeGen/ARM/vlddup.ll +++ b/test/CodeGen/ARM/vlddup.ll @@ -4,7 +4,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounwind { ;CHECK-LABEL: vld1dupi8: ;Check the (default) alignment value. ;CHECK: vld1.8 {d16[]}, [r0] - %tmp1 = load i8* %A, align 8 + %tmp1 = load i8, i8* %A, align 8 %tmp2 = insertelement <8 x i8> undef, i8 %tmp1, i32 0 %tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <8 x i32> zeroinitializer ret <8 x i8> %tmp3 @@ -14,7 +14,7 @@ define <4 x i16> @vld1dupi16(i16* %A) nounwind { ;CHECK-LABEL: vld1dupi16: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vld1.16 {d16[]}, [r0:16] - %tmp1 = load i16* %A, align 8 + %tmp1 = load i16, i16* %A, align 8 %tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0 %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer ret <4 x i16> %tmp3 @@ -24,7 +24,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind { ;CHECK-LABEL: vld1dupi32: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld1.32 {d16[]}, [r0:32] - %tmp1 = load i32* %A, align 8 + %tmp1 = load i32, i32* %A, align 8 %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0 %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer ret <2 x i32> %tmp3 @@ -33,7 +33,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind { define <2 x float> @vld1dupf(float* %A) nounwind { ;CHECK-LABEL: vld1dupf: ;CHECK: vld1.32 {d16[]}, [r0:32] - %tmp0 = load float* %A + %tmp0 = load float, float* %A %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer ret <2 x float> %tmp2 @@ -43,7 +43,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind { ;CHECK-LABEL: vld1dupQi8: ;Check the (default) alignment value. ;CHECK: vld1.8 {d16[], d17[]}, [r0] - %tmp1 = load i8* %A, align 8 + %tmp1 = load i8, i8* %A, align 8 %tmp2 = insertelement <16 x i8> undef, i8 %tmp1, i32 0 %tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <16 x i32> zeroinitializer ret <16 x i8> %tmp3 @@ -52,7 +52,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind { define <4 x float> @vld1dupQf(float* %A) nounwind { ;CHECK-LABEL: vld1dupQf: ;CHECK: vld1.32 {d16[], d17[]}, [r0:32] - %tmp0 = load float* %A + %tmp0 = load float, float* %A %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer ret <4 x float> %tmp2 @@ -93,7 +93,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind { define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { ;CHECK-LABEL: vld2dupi16_update: ;CHECK: vld2.16 {d16[], d17[]}, [r1]! - %A = load i16** %ptr + %A = load i16*, i16** %ptr %A2 = bitcast i16* %A to i8* %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0 @@ -101,7 +101,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer %tmp5 = add <4 x i16> %tmp2, %tmp4 - %tmp6 = getelementptr i16* %A, i32 2 + %tmp6 = getelementptr i16, i16* %A, i32 2 store i16* %tmp6, i16** %ptr ret <4 x i16> %tmp5 } @@ -130,7 +130,7 @@ declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld3dupi8_update: ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1 - %A = load i8** %ptr + %A = load i8*, i8** %ptr %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 0 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer @@ -140,7 +140,7 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { %tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <8 x i32> zeroinitializer %tmp7 = add <8 x i8> %tmp2, %tmp4 %tmp8 = add <8 x i8> %tmp7, %tmp6 - %tmp9 = getelementptr i8* %A, i32 %inc + %tmp9 = getelementptr i8, i8* %A, i32 %inc store i8* %tmp9, i8** %ptr ret <8 x i8> %tmp8 } @@ -171,7 +171,7 @@ declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind { ;CHECK-LABEL: vld4dupi16_update: ;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]! - %A = load i16** %ptr + %A = load i16*, i16** %ptr %A2 = bitcast i16* %A to i8* %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %A2, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1) %tmp1 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 0 @@ -185,7 +185,7 @@ define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind { %tmp9 = add <4 x i16> %tmp2, %tmp4 %tmp10 = add <4 x i16> %tmp6, %tmp8 %tmp11 = add <4 x i16> %tmp9, %tmp10 - %tmp12 = getelementptr i16* %A, i32 4 + %tmp12 = getelementptr i16, i16* %A, i32 4 store i16* %tmp12, i16** %ptr ret <4 x i16> %tmp11 } diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index c7d69ff9780a..ac2be7f87f53 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -7,8 +7,8 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vld1lanei8: ;Check the (default) alignment value. ;CHECK: vld1.8 {d16[3]}, [r0] - %tmp1 = load <8 x i8>* %B - %tmp2 = load i8* %A, align 8 + %tmp1 = load <8 x i8>, <8 x i8>* %B + %tmp2 = load i8, i8* %A, align 8 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3 ret <8 x i8> %tmp3 } @@ -17,8 +17,8 @@ define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vld1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vld1.16 {d16[2]}, [r0:16] - %tmp1 = load <4 x i16>* %B - %tmp2 = load i16* %A, align 8 + %tmp1 = load <4 x i16>, <4 x i16>* %B + %tmp2 = load i16, i16* %A, align 8 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2 ret <4 x i16> %tmp3 } @@ -27,8 +27,8 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vld1lanei32: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld1.32 {d16[1]}, [r0:32] - %tmp1 = load <2 x i32>* %B - %tmp2 = load i32* %A, align 8 + %tmp1 = load <2 x i32>, <2 x i32>* %B + %tmp2 = load i32, i32* %A, align 8 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 ret <2 x i32> %tmp3 } @@ -37,8 +37,8 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vld1lanei32a32: ;Check the alignment value. Legal values are none or :32. ;CHECK: vld1.32 {d16[1]}, [r0:32] - %tmp1 = load <2 x i32>* %B - %tmp2 = load i32* %A, align 4 + %tmp1 = load <2 x i32>, <2 x i32>* %B + %tmp2 = load i32, i32* %A, align 4 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 ret <2 x i32> %tmp3 } @@ -46,8 +46,8 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vld1lanef: ;CHECK: vld1.32 {d16[1]}, [r0:32] - %tmp1 = load <2 x float>* %B - %tmp2 = load float* %A, align 4 + %tmp1 = load <2 x float>, <2 x float>* %B + %tmp2 = load float, float* %A, align 4 %tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1 ret <2 x float> %tmp3 } @@ -55,8 +55,8 @@ define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind { define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vld1laneQi8: ;CHECK: vld1.8 {d17[1]}, [r0] - %tmp1 = load <16 x i8>* %B - %tmp2 = load i8* %A, align 8 + %tmp1 = load <16 x i8>, <16 x i8>* %B + %tmp2 = load i8, i8* %A, align 8 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9 ret <16 x i8> %tmp3 } @@ -64,8 +64,8 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vld1laneQi16: ;CHECK: vld1.16 {d17[1]}, [r0:16] - %tmp1 = load <8 x i16>* %B - %tmp2 = load i16* %A, align 8 + %tmp1 = load <8 x i16>, <8 x i16>* %B + %tmp2 = load i16, i16* %A, align 8 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5 ret <8 x i16> %tmp3 } @@ -73,8 +73,8 @@ define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vld1laneQi32: ;CHECK: vld1.32 {d17[1]}, [r0:32] - %tmp1 = load <4 x i32>* %B - %tmp2 = load i32* %A, align 8 + %tmp1 = load <4 x i32>, <4 x i32>* %B + %tmp2 = load i32, i32* %A, align 8 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3 ret <4 x i32> %tmp3 } @@ -82,8 +82,8 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vld1laneQf: ;CHECK: vld1.32 {d16[0]}, [r0:32] - %tmp1 = load <4 x float>* %B - %tmp2 = load float* %A + %tmp1 = load <4 x float>, <4 x float>* %B + %tmp2 = load float, float* %A %tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0 ret <4 x float> %tmp3 } @@ -101,7 +101,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vld2lanei8: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 @@ -114,7 +114,7 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1 @@ -126,7 +126,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vld2lanei32: ;CHECK: vld2.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1 @@ -138,14 +138,14 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vld2lanei32_update: ;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]! - %A = load i32** %ptr + %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1 %tmp5 = add <2 x i32> %tmp3, %tmp4 - %tmp6 = getelementptr i32* %A, i32 2 + %tmp6 = getelementptr i32, i32* %A, i32 2 store i32* %tmp6, i32** %ptr ret <2 x i32> %tmp5 } @@ -154,7 +154,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vld2lanef: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1 @@ -167,7 +167,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the (default) alignment. ;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 @@ -180,7 +180,7 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 @@ -192,7 +192,7 @@ define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vld2laneQf: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1 @@ -221,7 +221,7 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x flo define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vld3lanei8: ;CHECK: vld3.8 - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1 @@ -236,7 +236,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;Check the (default) alignment value. VLD3 does not support alignment. ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1 @@ -250,7 +250,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vld3lanei32: ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1 @@ -264,7 +264,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vld3lanef: ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1 @@ -279,7 +279,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the (default) alignment value. VLD3 does not support alignment. ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 @@ -293,16 +293,16 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { ;CHECK-LABEL: vld3laneQi16_update: ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}} - %A = load i16** %ptr + %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2 %tmp6 = add <8 x i16> %tmp3, %tmp4 %tmp7 = add <8 x i16> %tmp5, %tmp6 - %tmp8 = getelementptr i16* %A, i32 %inc + %tmp8 = getelementptr i16, i16* %A, i32 %inc store i16* %tmp8, i16** %ptr ret <8 x i16> %tmp7 } @@ -311,7 +311,7 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vld3laneQi32: ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1) %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1 @@ -325,7 +325,7 @@ define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vld3laneQf: ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1 @@ -357,7 +357,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vld4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 @@ -373,8 +373,8 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vld4lanei8_update: ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]! - %A = load i8** %ptr - %tmp1 = load <8 x i8>* %B + %A = load i8*, i8** %ptr + %tmp1 = load <8 x i8>, <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 @@ -383,7 +383,7 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { %tmp7 = add <8 x i8> %tmp3, %tmp4 %tmp8 = add <8 x i8> %tmp5, %tmp6 %tmp9 = add <8 x i8> %tmp7, %tmp8 - %tmp10 = getelementptr i8* %A, i32 4 + %tmp10 = getelementptr i8, i8* %A, i32 4 store i8* %tmp10, i8** %ptr ret <8 x i8> %tmp9 } @@ -394,7 +394,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;being loaded is ignored. ;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4) %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1 @@ -412,7 +412,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;it is smaller than the total size of the memory being loaded. ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1 @@ -428,7 +428,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vld4lanef: ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1 @@ -445,7 +445,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16) %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1 @@ -462,7 +462,7 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check the (default) alignment. ;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1 @@ -478,7 +478,7 @@ define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vld4laneQf: ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1 diff --git a/test/CodeGen/ARM/vldm-liveness.ll b/test/CodeGen/ARM/vldm-liveness.ll index 751f447077be..e114e6970a32 100644 --- a/test/CodeGen/ARM/vldm-liveness.ll +++ b/test/CodeGen/ARM/vldm-liveness.ll @@ -22,14 +22,14 @@ define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) { ; CHECK: vldr s3, [r0, #8] ; CHECK: vldmia r0, {s0, s1} ; CHECK: vldr s2, [r0, #16] - %off0 = getelementptr float* %ptr, i32 0 - %val0 = load float* %off0 - %off1 = getelementptr float* %ptr, i32 1 - %val1 = load float* %off1 - %off4 = getelementptr float* %ptr, i32 4 - %val4 = load float* %off4 - %off2 = getelementptr float* %ptr, i32 2 - %val2 = load float* %off2 + %off0 = getelementptr float, float* %ptr, i32 0 + %val0 = load float, float* %off0 + %off1 = getelementptr float, float* %ptr, i32 1 + %val1 = load float, float* %off1 + %off4 = getelementptr float, float* %ptr, i32 4 + %val4 = load float, float* %off4 + %off2 = getelementptr float, float* %ptr, i32 2 + %val2 = load float, float* %off2 %vec1 = insertelement <4 x float> undef, float %val0, i32 0 %vec2 = insertelement <4 x float> %vec1, float %val1, i32 1 diff --git a/test/CodeGen/ARM/vldm-sched-a9.ll b/test/CodeGen/ARM/vldm-sched-a9.ll index e5e7bc08fa4a..0e0cf97d4365 100644 --- a/test/CodeGen/ARM/vldm-sched-a9.ll +++ b/test/CodeGen/ARM/vldm-sched-a9.ll @@ -10,12 +10,12 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; CHECK: vldmia define void @test(i64* %src) #0 { entry: - %arrayidx39 = getelementptr inbounds i64* %src, i32 13 + %arrayidx39 = getelementptr inbounds i64, i64* %src, i32 13 %vecinit285 = shufflevector <16 x i64> undef, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> store <16 x i64> %vecinit285, <16 x i64>* undef, align 128 - %0 = load i64* undef, align 8 + %0 = load i64, i64* undef, align 8 %vecinit379 = insertelement <16 x i64> undef, i64 %0, i32 9 - %1 = load i64* undef, align 8 + %1 = load i64, i64* undef, align 8 %vecinit419 = insertelement <16 x i64> undef, i64 %1, i32 15 store <16 x i64> %vecinit419, <16 x i64>* undef, align 128 %vecinit579 = insertelement <16 x i64> undef, i64 0, i32 4 @@ -23,14 +23,14 @@ entry: %vecinit584 = insertelement <16 x i64> %vecinit582, i64 undef, i32 9 %vecinit586 = insertelement <16 x i64> %vecinit584, i64 0, i32 10 %vecinit589 = shufflevector <16 x i64> %vecinit586, <16 x i64> <i64 12, i64 13, i64 14, i64 15, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 16, i32 17, i32 18, i32 19, i32 undef> - %2 = load i64* undef, align 8 + %2 = load i64, i64* undef, align 8 %vecinit591 = insertelement <16 x i64> %vecinit589, i64 %2, i32 15 store <16 x i64> %vecinit591, <16 x i64>* undef, align 128 %vecinit694 = shufflevector <16 x i64> undef, <16 x i64> <i64 13, i64 14, i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19> store <16 x i64> %vecinit694, <16 x i64>* undef, align 128 - %3 = load i64* undef, align 8 + %3 = load i64, i64* undef, align 8 %vecinit1331 = insertelement <16 x i64> undef, i64 %3, i32 14 - %4 = load i64* undef, align 8 + %4 = load i64, i64* undef, align 8 %vecinit1468 = insertelement <16 x i64> undef, i64 %4, i32 11 %vecinit1471 = shufflevector <16 x i64> %vecinit1468, <16 x i64> <i64 13, i64 14, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 undef, i32 undef> %vecinit1474 = shufflevector <16 x i64> %vecinit1471, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> @@ -45,14 +45,14 @@ entry: %vecinit1599 = insertelement <16 x i64> %vecinit1597, i64 undef, i32 8 %vecinit1601 = insertelement <16 x i64> %vecinit1599, i64 undef, i32 9 %vecinit1603 = insertelement <16 x i64> %vecinit1601, i64 undef, i32 10 - %5 = load i64* undef, align 8 + %5 = load i64, i64* undef, align 8 %vecinit1605 = insertelement <16 x i64> %vecinit1603, i64 %5, i32 11 %vecinit1608 = shufflevector <16 x i64> %vecinit1605, <16 x i64> <i64 13, i64 14, i64 15, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 undef> - %6 = load i64* undef, align 8 + %6 = load i64, i64* undef, align 8 %vecinit1610 = insertelement <16 x i64> %vecinit1608, i64 %6, i32 15 store <16 x i64> %vecinit1610, <16 x i64>* undef, align 128 %vecinit2226 = shufflevector <16 x i64> undef, <16 x i64> <i64 6, i64 7, i64 8, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> - %7 = load i64* undef, align 8 + %7 = load i64, i64* undef, align 8 %vecinit2228 = insertelement <16 x i64> %vecinit2226, i64 %7, i32 8 %vecinit2230 = insertelement <16 x i64> %vecinit2228, i64 undef, i32 9 %vecinit2233 = shufflevector <16 x i64> %vecinit2230, <16 x i64> <i64 11, i64 12, i64 13, i64 14, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef> @@ -62,7 +62,7 @@ entry: %vecinit2249 = shufflevector <16 x i64> %vecinit2246, <16 x i64> <i64 7, i64 8, i64 9, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %vecinit2252 = shufflevector <16 x i64> %vecinit2249, <16 x i64> <i64 10, i64 11, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 16, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %vecinit2255 = shufflevector <16 x i64> %vecinit2252, <16 x i64> <i64 12, i64 13, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 16, i32 17, i32 undef, i32 undef, i32 undef> - %8 = load i64* %arrayidx39, align 8 + %8 = load i64, i64* %arrayidx39, align 8 %vecinit2257 = insertelement <16 x i64> %vecinit2255, i64 %8, i32 13 %vecinit2260 = shufflevector <16 x i64> %vecinit2257, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> store <16 x i64> %vecinit2260, <16 x i64>* null, align 128 diff --git a/test/CodeGen/ARM/vminmax.ll b/test/CodeGen/ARM/vminmax.ll index 1167ebe06717..011bfd7ff88e 100644 --- a/test/CodeGen/ARM/vminmax.ll +++ b/test/CodeGen/ARM/vminmax.ll @@ -3,8 +3,8 @@ define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmins8: ;CHECK: vmin.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmins16: ;CHECK: vmin.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmins32: ;CHECK: vmin.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vminu8: ;CHECK: vmin.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vminu16: ;CHECK: vmin.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vminu32: ;CHECK: vmin.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vminf32: ;CHECK: vmin.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -66,8 +66,8 @@ define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vminQs8: ;CHECK: vmin.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -75,8 +75,8 @@ define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vminQs16: ;CHECK: vmin.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -84,8 +84,8 @@ define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vminQs32: ;CHECK: vmin.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -93,8 +93,8 @@ define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vminQu8: ;CHECK: vmin.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -102,8 +102,8 @@ define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vminQu16: ;CHECK: vmin.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -111,8 +111,8 @@ define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vminQu32: ;CHECK: vmin.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -120,8 +120,8 @@ define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vminQf32: ;CHECK: vmin.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -149,8 +149,8 @@ declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwin define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmaxs8: ;CHECK: vmax.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -158,8 +158,8 @@ define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmaxs16: ;CHECK: vmax.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -167,8 +167,8 @@ define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmaxs32: ;CHECK: vmax.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -176,8 +176,8 @@ define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmaxu8: ;CHECK: vmax.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -185,8 +185,8 @@ define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmaxu16: ;CHECK: vmax.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -194,8 +194,8 @@ define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmaxu32: ;CHECK: vmax.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -203,8 +203,8 @@ define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vmaxf32: ;CHECK: vmax.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -212,8 +212,8 @@ define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vmaxQs8: ;CHECK: vmax.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -221,8 +221,8 @@ define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vmaxQs16: ;CHECK: vmax.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -230,8 +230,8 @@ define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vmaxQs32: ;CHECK: vmax.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -239,8 +239,8 @@ define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vmaxQu8: ;CHECK: vmax.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -248,8 +248,8 @@ define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vmaxQu16: ;CHECK: vmax.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -257,8 +257,8 @@ define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vmaxQu32: ;CHECK: vmax.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -266,8 +266,8 @@ define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vmaxQf32: ;CHECK: vmax.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } diff --git a/test/CodeGen/ARM/vminmaxnm.ll b/test/CodeGen/ARM/vminmaxnm.ll index 39289a0bafb3..3632ffd00213 100644 --- a/test/CodeGen/ARM/vminmaxnm.ll +++ b/test/CodeGen/ARM/vminmaxnm.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s -; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST +; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 | FileCheck %s +; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 \ +; RUN: -enable-no-nans-fp-math -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST + +; vectors define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vmaxnmq: ; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -13,8 +16,8 @@ define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind { ; CHECK-LABEL: vmaxnmd: ; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -22,8 +25,8 @@ define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vminnmq: ; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -31,12 +34,14 @@ define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind { ; CHECK-LABEL: vminnmd: ; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } +; scalars + define float @fp-armv8_vminnm_o(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vminnm_o": ; CHECK-FAST-NOT: vcmp @@ -48,6 +53,17 @@ define float @fp-armv8_vminnm_o(float %a, float %b) { ret float %cond } +define double @fp-armv8_vminnm_ole(double %a, double %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_ole": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f64 +; CHECK-LABEL: "fp-armv8_vminnm_ole": +; CHECK-NOT: vminnm.f64 + %cmp = fcmp ole double %a, %b + %cond = select i1 %cmp, double %a, double %b + ret double %cond +} + define float @fp-armv8_vminnm_o_rev(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vminnm_o_rev": ; CHECK-FAST-NOT: vcmp @@ -59,6 +75,17 @@ define float @fp-armv8_vminnm_o_rev(float %a, float %b) { ret float %cond } +define double @fp-armv8_vminnm_oge_rev(double %a, double %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_oge_rev": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f64 +; CHECK-LABEL: "fp-armv8_vminnm_oge_rev": +; CHECK-NOT: vminnm.f64 + %cmp = fcmp oge double %a, %b + %cond = select i1 %cmp, double %b, double %a + ret double %cond +} + define float @fp-armv8_vminnm_u(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vminnm_u": ; CHECK-FAST-NOT: vcmp @@ -70,6 +97,17 @@ define float @fp-armv8_vminnm_u(float %a, float %b) { ret float %cond } +define float @fp-armv8_vminnm_ule(float %a, float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_ule": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f32 +; CHECK-LABEL: "fp-armv8_vminnm_ule": +; CHECK-NOT: vminnm.f32 + %cmp = fcmp ule float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + define float @fp-armv8_vminnm_u_rev(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vminnm_u_rev": ; CHECK-FAST-NOT: vcmp @@ -81,6 +119,17 @@ define float @fp-armv8_vminnm_u_rev(float %a, float %b) { ret float %cond } +define double @fp-armv8_vminnm_uge_rev(double %a, double %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_uge_rev": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f64 +; CHECK-LABEL: "fp-armv8_vminnm_uge_rev": +; CHECK-NOT: vminnm.f64 + %cmp = fcmp uge double %a, %b + %cond = select i1 %cmp, double %b, double %a + ret double %cond +} + define float @fp-armv8_vmaxnm_o(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o": ; CHECK-FAST-NOT: vcmp @@ -92,6 +141,17 @@ define float @fp-armv8_vmaxnm_o(float %a, float %b) { ret float %cond } +define float @fp-armv8_vmaxnm_oge(float %a, float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_oge": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_oge": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp oge float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o_rev": ; CHECK-FAST-NOT: vcmp @@ -103,6 +163,17 @@ define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) { ret float %cond } +define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ole_rev": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp ole float %a, %b + %cond = select i1 %cmp, float %b, float %a + ret float %cond +} + define float @fp-armv8_vmaxnm_u(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u": ; CHECK-FAST-NOT: vcmp @@ -114,6 +185,17 @@ define float @fp-armv8_vmaxnm_u(float %a, float %b) { ret float %cond } +define float @fp-armv8_vmaxnm_uge(float %a, float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_uge": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_uge": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp uge float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) { ; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u_rev": ; CHECK-FAST-NOT: vcmp @@ -125,6 +207,302 @@ define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) { ret float %cond } +define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ule_rev": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vmaxnm.f64 +; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev": +; CHECK-NOT: vmaxnm.f64 + %cmp = fcmp ule double %a, %b + %cond = select i1 %cmp, double %b, double %a + ret double %cond +} + +; known non-NaNs + +define float @fp-armv8_vminnm_NNNo(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo": +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vminnm.f32 +; CHECK-LABEL: "fp-armv8_vminnm_NNNo": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp olt float %a, 12. + %cond1 = select i1 %cmp1, float %a, float 12. + %cmp2 = fcmp olt float 34., %cond1 + %cond2 = select i1 %cmp2, float 34., float %cond1 + ret float %cond2 +} + +define double @fp-armv8_vminnm_NNNole(double %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNole": +; CHECK-FAST: vminnm.f64 +; CHECK-FAST: vminnm.f64 +; CHECK-LABEL: "fp-armv8_vminnm_NNNole": +; CHECK: vminnm.f64 +; CHECK-NOT: vminnm.f64 + %cmp1 = fcmp ole double %a, 34. + %cond1 = select i1 %cmp1, double %a, double 34. + %cmp2 = fcmp ole double 56., %cond1 + %cond2 = select i1 %cmp2, double 56., double %cond1 + ret double %cond2 +} + +define float @fp-armv8_vminnm_NNNo_rev(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo_rev": +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vminnm.f32 +; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ogt float %a, 56. + %cond1 = select i1 %cmp1, float 56., float %a + %cmp2 = fcmp ogt float 78., %cond1 + %cond2 = select i1 %cmp2, float %cond1, float 78. + ret float %cond2 +} + +define double @fp-armv8_vminnm_NNNoge_rev(double %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNoge_rev": +; CHECK-FAST: vminnm.f64 +; CHECK-FAST: vminnm.f64 +; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev": +; CHECK: vminnm.f64 +; CHECK-NOT: vminnm.f64 + %cmp1 = fcmp oge double %a, 78. + %cond1 = select i1 %cmp1, double 78., double %a + %cmp2 = fcmp oge double 90., %cond1 + %cond2 = select i1 %cmp2, double %cond1, double 90. + ret double %cond2 +} + +define float @fp-armv8_vminnm_NNNu(float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu": +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vminnm.f32 +; CHECK-LABEL: "fp-armv8_vminnm_NNNu": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ult float 12., %b + %cond1 = select i1 %cmp1, float 12., float %b + %cmp2 = fcmp ult float %cond1, 34. + %cond2 = select i1 %cmp2, float %cond1, float 34. + ret float %cond2 +} + +define float @fp-armv8_vminnm_NNNule(float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNule": +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vminnm.f32 +; CHECK-LABEL: "fp-armv8_vminnm_NNNule": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ule float 34., %b + %cond1 = select i1 %cmp1, float 34., float %b + %cmp2 = fcmp ule float %cond1, 56. + %cond2 = select i1 %cmp2, float %cond1, float 56. + ret float %cond2 +} + +define float @fp-armv8_vminnm_NNNu_rev(float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu_rev": +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vminnm.f32 +; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ugt float 56., %b + %cond1 = select i1 %cmp1, float %b, float 56. + %cmp2 = fcmp ugt float %cond1, 78. + %cond2 = select i1 %cmp2, float 78., float %cond1 + ret float %cond2 +} + +define double @fp-armv8_vminnm_NNNuge_rev(double %b) { +; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNuge_rev": +; CHECK-FAST: vminnm.f64 +; CHECK-FAST: vminnm.f64 +; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev": +; CHECK: vminnm.f64 +; CHECK-NOT: vminnm.f64 + %cmp1 = fcmp uge double 78., %b + %cond1 = select i1 %cmp1, double %b, double 78. + %cmp2 = fcmp uge double %cond1, 90. + %cond2 = select i1 %cmp2, double 90., double %cond1 + ret double %cond2 +} + +define float @fp-armv8_vmaxnm_NNNo(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo": +; CHECK-FAST: vmaxnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp ogt float %a, 12. + %cond1 = select i1 %cmp1, float %a, float 12. + %cmp2 = fcmp ogt float 34., %cond1 + %cond2 = select i1 %cmp2, float 34., float %cond1 + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNoge(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNoge": +; CHECK-FAST: vmaxnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNoge": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp oge float %a, 34. + %cond1 = select i1 %cmp1, float %a, float 34. + %cmp2 = fcmp oge float 56., %cond1 + %cond2 = select i1 %cmp2, float 56., float %cond1 + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNo_rev(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo_rev": +; CHECK-FAST: vmaxnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo_rev": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp olt float %a, 56. + %cond1 = select i1 %cmp1, float 56., float %a + %cmp2 = fcmp olt float 78., %cond1 + %cond2 = select i1 %cmp2, float %cond1, float 78. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNole_rev(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNole_rev": +; CHECK-FAST: vmaxnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNole_rev": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp ole float %a, 78. + %cond1 = select i1 %cmp1, float 78., float %a + %cmp2 = fcmp ole float 90., %cond1 + %cond2 = select i1 %cmp2, float %cond1, float 90. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNu(float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu": +; CHECK-FAST: vmaxnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu": +; CHECK: vmaxnm.f32 +; CHEC-NOT: vmaxnm.f32 + %cmp1 = fcmp ugt float 12., %b + %cond1 = select i1 %cmp1, float 12., float %b + %cmp2 = fcmp ugt float %cond1, 34. + %cond2 = select i1 %cmp2, float %cond1, float 34. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNuge(float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNuge": +; CHECK-FAST: vmaxnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNuge": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp uge float 34., %b + %cond1 = select i1 %cmp1, float 34., float %b + %cmp2 = fcmp uge float %cond1, 56. + %cond2 = select i1 %cmp2, float %cond1, float 56. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNu_rev(float %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu_rev": +; CHECK-FAST: vmaxnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu_rev": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp ult float 56., %b + %cond1 = select i1 %cmp1, float %b, float 56. + %cmp2 = fcmp ult float %cond1, 78. + %cond2 = select i1 %cmp2, float 78., float %cond1 + ret float %cond2 +} + +define double @fp-armv8_vmaxnm_NNNule_rev( double %b) { +; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNule_rev": +; CHECK-FAST: vmaxnm.f64 +; CHECK-FAST: vmaxnm.f64 +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNule_rev": +; CHECK: vmaxnm.f64 +; CHECK-NOT: vmaxnm.f64 + %cmp1 = fcmp ule double 78., %b + %cond1 = select i1 %cmp1, double %b, double 78. + %cmp2 = fcmp ule double %cond1, 90. + %cond2 = select i1 %cmp2, double 90., double %cond1 + ret double %cond2 +} + +define float @fp-armv8_vminmaxnm_0(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_0": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vminmaxnm_0": +; CHECK-NOT: vminnm.f32 +; CHECK: vmaxnm.f32 + %cmp1 = fcmp olt float %a, 0. + %cond1 = select i1 %cmp1, float %a, float 0. + %cmp2 = fcmp ogt float %cond1, 0. + %cond2 = select i1 %cmp2, float %cond1, float 0. + ret float %cond2 +} + +define float @fp-armv8_vminmaxnm_neg0(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_neg0": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vminmaxnm_neg0": +; CHECK: vminnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp olt float %a, -0. + %cond1 = select i1 %cmp1, float %a, float -0. + %cmp2 = fcmp ogt float %cond1, -0. + %cond2 = select i1 %cmp2, float %cond1, float -0. + ret float %cond2 +} + +define float @fp-armv8_vminmaxnm_e_0(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_0": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vminmaxnm_e_0": +; CHECK-NOT: vminnm.f32 +; CHECK: vmaxnm.f32 + %cmp1 = fcmp ule float 0., %a + %cond1 = select i1 %cmp1, float 0., float %a + %cmp2 = fcmp uge float 0., %cond1 + %cond2 = select i1 %cmp2, float 0., float %cond1 + ret float %cond2 +} + +define float @fp-armv8_vminmaxnm_e_neg0(float %a) { +; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_neg0": +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f32 +; CHECK-FAST: vmaxnm.f32 +; CHECK-LABEL: "fp-armv8_vminmaxnm_e_neg0": +; CHECK: vminnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp ule float -0., %a + %cond1 = select i1 %cmp1, float -0., float %a + %cmp2 = fcmp uge float -0., %cond1 + %cond2 = select i1 %cmp2, float -0., float %cond1 + ret float %cond2 +} declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/vmla.ll b/test/CodeGen/ARM/vmla.ll index 6073fc5566fd..8ca33a9eecac 100644 --- a/test/CodeGen/ARM/vmla.ll +++ b/test/CodeGen/ARM/vmla.ll @@ -3,9 +3,9 @@ define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { ;CHECK-LABEL: vmlai8: ;CHECK: vmla.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = mul <8 x i8> %tmp2, %tmp3 %tmp5 = add <8 x i8> %tmp1, %tmp4 ret <8 x i8> %tmp5 @@ -14,9 +14,9 @@ define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vmlai16: ;CHECK: vmla.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = mul <4 x i16> %tmp2, %tmp3 %tmp5 = add <4 x i16> %tmp1, %tmp4 ret <4 x i16> %tmp5 @@ -25,9 +25,9 @@ define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vmlai32: ;CHECK: vmla.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = mul <2 x i32> %tmp2, %tmp3 %tmp5 = add <2 x i32> %tmp1, %tmp4 ret <2 x i32> %tmp5 @@ -36,9 +36,9 @@ define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { ;CHECK-LABEL: vmlaf32: ;CHECK: vmla.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B - %tmp3 = load <2 x float>* %C + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = load <2 x float>, <2 x float>* %C %tmp4 = fmul <2 x float> %tmp2, %tmp3 %tmp5 = fadd <2 x float> %tmp1, %tmp4 ret <2 x float> %tmp5 @@ -47,9 +47,9 @@ define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind { ;CHECK-LABEL: vmlaQi8: ;CHECK: vmla.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B - %tmp3 = load <16 x i8>* %C + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <16 x i8>, <16 x i8>* %C %tmp4 = mul <16 x i8> %tmp2, %tmp3 %tmp5 = add <16 x i8> %tmp1, %tmp4 ret <16 x i8> %tmp5 @@ -58,9 +58,9 @@ define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: vmlaQi16: ;CHECK: vmla.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = mul <8 x i16> %tmp2, %tmp3 %tmp5 = add <8 x i16> %tmp1, %tmp4 ret <8 x i16> %tmp5 @@ -69,9 +69,9 @@ define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: vmlaQi32: ;CHECK: vmla.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = mul <4 x i32> %tmp2, %tmp3 %tmp5 = add <4 x i32> %tmp1, %tmp4 ret <4 x i32> %tmp5 @@ -80,9 +80,9 @@ define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { ;CHECK-LABEL: vmlaQf32: ;CHECK: vmla.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B - %tmp3 = load <4 x float>* %C + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = load <4 x float>, <4 x float>* %C %tmp4 = fmul <4 x float> %tmp2, %tmp3 %tmp5 = fadd <4 x float> %tmp1, %tmp4 ret <4 x float> %tmp5 @@ -91,9 +91,9 @@ define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vmlals8: ;CHECK: vmlal.s8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -104,9 +104,9 @@ define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vmlals16: ;CHECK: vmlal.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -117,9 +117,9 @@ define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vmlals32: ;CHECK: vmlal.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 @@ -130,9 +130,9 @@ define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vmlalu8: ;CHECK: vmlal.u8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -143,9 +143,9 @@ define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vmlalu16: ;CHECK: vmlal.u16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -156,9 +156,9 @@ define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vmlalu32: ;CHECK: vmlal.u32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 diff --git a/test/CodeGen/ARM/vmls.ll b/test/CodeGen/ARM/vmls.ll index f86739cea3f1..d14928147a36 100644 --- a/test/CodeGen/ARM/vmls.ll +++ b/test/CodeGen/ARM/vmls.ll @@ -3,9 +3,9 @@ define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { ;CHECK-LABEL: vmlsi8: ;CHECK: vmls.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = mul <8 x i8> %tmp2, %tmp3 %tmp5 = sub <8 x i8> %tmp1, %tmp4 ret <8 x i8> %tmp5 @@ -14,9 +14,9 @@ define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vmlsi16: ;CHECK: vmls.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = mul <4 x i16> %tmp2, %tmp3 %tmp5 = sub <4 x i16> %tmp1, %tmp4 ret <4 x i16> %tmp5 @@ -25,9 +25,9 @@ define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vmlsi32: ;CHECK: vmls.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = mul <2 x i32> %tmp2, %tmp3 %tmp5 = sub <2 x i32> %tmp1, %tmp4 ret <2 x i32> %tmp5 @@ -36,9 +36,9 @@ define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { ;CHECK-LABEL: vmlsf32: ;CHECK: vmls.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B - %tmp3 = load <2 x float>* %C + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = load <2 x float>, <2 x float>* %C %tmp4 = fmul <2 x float> %tmp2, %tmp3 %tmp5 = fsub <2 x float> %tmp1, %tmp4 ret <2 x float> %tmp5 @@ -47,9 +47,9 @@ define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind { ;CHECK-LABEL: vmlsQi8: ;CHECK: vmls.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B - %tmp3 = load <16 x i8>* %C + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <16 x i8>, <16 x i8>* %C %tmp4 = mul <16 x i8> %tmp2, %tmp3 %tmp5 = sub <16 x i8> %tmp1, %tmp4 ret <16 x i8> %tmp5 @@ -58,9 +58,9 @@ define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: vmlsQi16: ;CHECK: vmls.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = mul <8 x i16> %tmp2, %tmp3 %tmp5 = sub <8 x i16> %tmp1, %tmp4 ret <8 x i16> %tmp5 @@ -69,9 +69,9 @@ define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: vmlsQi32: ;CHECK: vmls.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = mul <4 x i32> %tmp2, %tmp3 %tmp5 = sub <4 x i32> %tmp1, %tmp4 ret <4 x i32> %tmp5 @@ -80,9 +80,9 @@ define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { ;CHECK-LABEL: vmlsQf32: ;CHECK: vmls.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B - %tmp3 = load <4 x float>* %C + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = load <4 x float>, <4 x float>* %C %tmp4 = fmul <4 x float> %tmp2, %tmp3 %tmp5 = fsub <4 x float> %tmp1, %tmp4 ret <4 x float> %tmp5 @@ -91,9 +91,9 @@ define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vmlsls8: ;CHECK: vmlsl.s8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -104,9 +104,9 @@ define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vmlsls16: ;CHECK: vmlsl.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -117,9 +117,9 @@ define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vmlsls32: ;CHECK: vmlsl.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 @@ -130,9 +130,9 @@ define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vmlslu8: ;CHECK: vmlsl.u8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -143,9 +143,9 @@ define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vmlslu16: ;CHECK: vmlsl.u16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -156,9 +156,9 @@ define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vmlslu32: ;CHECK: vmlsl.u32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index 7900af44ef08..b7a23b7bb59c 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -174,7 +174,7 @@ define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) noun entry: ;CHECK-LABEL: vdupn128: ;CHECK: vmov.i8 d{{.*}}, #0x80 - %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] + %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8 ret void } @@ -183,7 +183,7 @@ define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) no entry: ;CHECK-LABEL: vdupnneg75: ;CHECK: vmov.i8 d{{.*}}, #0xb5 - %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] + %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8 ret void } @@ -191,7 +191,7 @@ entry: define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vmovls8: ;CHECK: vmovl.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> ret <8 x i16> %tmp2 } @@ -199,7 +199,7 @@ define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vmovls16: ;CHECK: vmovl.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> ret <4 x i32> %tmp2 } @@ -207,7 +207,7 @@ define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vmovls32: ;CHECK: vmovl.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> ret <2 x i64> %tmp2 } @@ -215,7 +215,7 @@ define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vmovlu8: ;CHECK: vmovl.u8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> ret <8 x i16> %tmp2 } @@ -223,7 +223,7 @@ define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vmovlu16: ;CHECK: vmovl.u16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> ret <4 x i32> %tmp2 } @@ -231,7 +231,7 @@ define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vmovlu32: ;CHECK: vmovl.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> ret <2 x i64> %tmp2 } @@ -239,7 +239,7 @@ define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vmovni16: ;CHECK: vmovn.i16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8> ret <8 x i8> %tmp2 } @@ -247,7 +247,7 @@ define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vmovni32: ;CHECK: vmovn.i32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> ret <4 x i16> %tmp2 } @@ -255,7 +255,7 @@ define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vmovni64: ;CHECK: vmovn.i64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } @@ -263,7 +263,7 @@ define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqmovns16: ;CHECK: vqmovn.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1) ret <8 x i8> %tmp2 } @@ -271,7 +271,7 @@ define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqmovns32: ;CHECK: vqmovn.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1) ret <4 x i16> %tmp2 } @@ -279,7 +279,7 @@ define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqmovns64: ;CHECK: vqmovn.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1) ret <2 x i32> %tmp2 } @@ -287,7 +287,7 @@ define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqmovnu16: ;CHECK: vqmovn.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1) ret <8 x i8> %tmp2 } @@ -295,7 +295,7 @@ define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqmovnu32: ;CHECK: vqmovn.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1) ret <4 x i16> %tmp2 } @@ -303,7 +303,7 @@ define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqmovnu64: ;CHECK: vqmovn.u64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1) ret <2 x i32> %tmp2 } @@ -311,7 +311,7 @@ define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqmovuns16: ;CHECK: vqmovun.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1) ret <8 x i8> %tmp2 } @@ -319,7 +319,7 @@ define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqmovuns32: ;CHECK: vqmovun.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1) ret <4 x i16> %tmp2 } @@ -327,7 +327,7 @@ define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqmovuns64: ;CHECK: vqmovun.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1) ret <2 x i32> %tmp2 } @@ -348,7 +348,7 @@ declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone ; Radar 8598391. define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind { ;CHECK: vmovn - %tmp1 = load <4 x i32>* %a, align 16 + %tmp1 = load <4 x i32>, <4 x i32>* %a, align 16 %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> store <4 x i16> %tmp2, <4 x i16>* %b, align 8 ret void @@ -376,7 +376,7 @@ define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind { entry: ;CHECK-LABEL: v_mov_v4f32_undef: ;CHECK: vmov.f32 q{{.*}}, #1.000000e+00 - %a = load <4 x float> *%p + %a = load <4 x float> , <4 x float> *%p %b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0> store <4 x float> %b, <4 x float> *%p ret void diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 0fa43d801bbe..c3e41cacde4c 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -3,8 +3,8 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmuli8: ;CHECK: vmul.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = mul <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmuli16: ;CHECK: vmul.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = mul <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmuli32: ;CHECK: vmul.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = mul <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vmulf32: ;CHECK: vmul.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fmul <2 x float> %tmp1, %tmp2 ret <2 x float> %tmp3 } @@ -39,8 +39,8 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmulp8: ;CHECK: vmul.p8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -48,8 +48,8 @@ define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vmulQi8: ;CHECK: vmul.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = mul <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -57,8 +57,8 @@ define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vmulQi16: ;CHECK: vmul.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = mul <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -66,8 +66,8 @@ define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vmulQi32: ;CHECK: vmul.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = mul <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -75,8 +75,8 @@ define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vmulQf32: ;CHECK: vmul.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = fmul <4 x float> %tmp1, %tmp2 ret <4 x float> %tmp3 } @@ -84,8 +84,8 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vmulQp8: ;CHECK: vmul.p8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -150,8 +150,8 @@ entry: define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmulls8: ;CHECK: vmull.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = mul <8 x i16> %tmp3, %tmp4 @@ -161,8 +161,8 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmulls8_int: ;CHECK: vmull.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -170,8 +170,8 @@ define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmulls16: ;CHECK: vmull.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = mul <4 x i32> %tmp3, %tmp4 @@ -181,8 +181,8 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmulls16_int: ;CHECK: vmull.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -190,8 +190,8 @@ define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmulls32: ;CHECK: vmull.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = mul <2 x i64> %tmp3, %tmp4 @@ -201,8 +201,8 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmulls32_int: ;CHECK: vmull.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i64> %tmp3 } @@ -210,8 +210,8 @@ define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmullu8: ;CHECK: vmull.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = mul <8 x i16> %tmp3, %tmp4 @@ -221,8 +221,8 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmullu8_int: ;CHECK: vmull.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -230,8 +230,8 @@ define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmullu16: ;CHECK: vmull.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = mul <4 x i32> %tmp3, %tmp4 @@ -241,8 +241,8 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vmullu16_int: ;CHECK: vmull.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -250,8 +250,8 @@ define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmullu32: ;CHECK: vmull.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = mul <2 x i64> %tmp3, %tmp4 @@ -261,8 +261,8 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vmullu32_int: ;CHECK: vmull.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i64> %tmp3 } @@ -270,8 +270,8 @@ define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmullp8: ;CHECK: vmull.p8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -488,7 +488,7 @@ entry: %8 = bitcast double %7 to <8 x i8> %9 = add <8 x i8> %6, %8 %10 = mul <8 x i8> %9, %2 - %11 = getelementptr inbounds %struct.uint8x8_t* %dst, i32 0, i32 0 + %11 = getelementptr inbounds %struct.uint8x8_t, %struct.uint8x8_t* %dst, i32 0, i32 0 store <8 x i8> %10, <8 x i8>* %11, align 8 ret void } @@ -510,7 +510,7 @@ entry: %8 = bitcast double %7 to <8 x i8> %9 = add <8 x i8> %6, %8 %10 = mul <8 x i8> %2, %9 - %11 = getelementptr inbounds %struct.uint8x8_t* %dst, i32 0, i32 0 + %11 = getelementptr inbounds %struct.uint8x8_t, %struct.uint8x8_t* %dst, i32 0, i32 0 store <8 x i8> %10, <8 x i8>* %11, align 8 ret void } @@ -560,7 +560,7 @@ for.body33.lr.ph: ; preds = %for.body for.body33: ; preds = %for.body33, %for.body33.lr.ph %add45 = add i32 undef, undef %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* undef, i32 1) - %0 = load i32** undef, align 4 + %0 = load i32*, i32** undef, align 4 %shuffle.i250 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer %1 = bitcast <1 x i64> %shuffle.i250 to <8 x i8> %vmovl.i249 = zext <8 x i8> %1 to <8 x i16> @@ -616,7 +616,7 @@ declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone ; PR15970 define void @no_illegal_types_vmull_sext(<4 x i32> %a) { entry: - %wide.load283.i = load <4 x i8>* undef, align 1 + %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1 %0 = sext <4 x i8> %wide.load283.i to <4 x i32> %1 = sub nsw <4 x i32> %0, %a %2 = mul nsw <4 x i32> %1, %1 @@ -626,7 +626,7 @@ entry: } define void @no_illegal_types_vmull_zext(<4 x i32> %a) { entry: - %wide.load283.i = load <4 x i8>* undef, align 1 + %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1 %0 = zext <4 x i8> %wide.load283.i to <4 x i32> %1 = sub nsw <4 x i32> %0, %a %2 = mul nsw <4 x i32> %1, %1 @@ -642,8 +642,8 @@ define void @foo(<4 x float> * %a, <4 x float>* nocapture %dst, float* nocapture ; and used a vector * scalar instruction. ; CHECK: vldr {{s[0-9]+}}, [r2] ; CHECK: vmul.f32 q8, q8, d0[0] - %tmp = load float* %src, align 4 - %tmp5 = load <4 x float>* %a, align 4 + %tmp = load float, float* %src, align 4 + %tmp5 = load <4 x float>, <4 x float>* %a, align 4 %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0 %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1 %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2 diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll index 4d548ddf8141..24a585f65a4b 100644 --- a/test/CodeGen/ARM/vneg.ll +++ b/test/CodeGen/ARM/vneg.ll @@ -3,7 +3,7 @@ define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vnegs8: ;CHECK: vneg.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = sub <8 x i8> zeroinitializer, %tmp1 ret <8 x i8> %tmp2 } @@ -11,7 +11,7 @@ define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vnegs16: ;CHECK: vneg.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = sub <4 x i16> zeroinitializer, %tmp1 ret <4 x i16> %tmp2 } @@ -19,7 +19,7 @@ define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind { define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vnegs32: ;CHECK: vneg.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = sub <2 x i32> zeroinitializer, %tmp1 ret <2 x i32> %tmp2 } @@ -27,7 +27,7 @@ define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind { define <2 x float> @vnegf32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vnegf32: ;CHECK: vneg.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1 ret <2 x float> %tmp2 } @@ -35,7 +35,7 @@ define <2 x float> @vnegf32(<2 x float>* %A) nounwind { define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vnegQs8: ;CHECK: vneg.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = sub <16 x i8> zeroinitializer, %tmp1 ret <16 x i8> %tmp2 } @@ -43,7 +43,7 @@ define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vnegQs16: ;CHECK: vneg.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = sub <8 x i16> zeroinitializer, %tmp1 ret <8 x i16> %tmp2 } @@ -51,7 +51,7 @@ define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vnegQs32: ;CHECK: vneg.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = sub <4 x i32> zeroinitializer, %tmp1 ret <4 x i32> %tmp2 } @@ -59,7 +59,7 @@ define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind { define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vnegQf32: ;CHECK: vneg.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1 ret <4 x float> %tmp2 } @@ -67,7 +67,7 @@ define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vqnegs8: ;CHECK: vqneg.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -75,7 +75,7 @@ define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind { define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vqnegs16: ;CHECK: vqneg.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp2 } @@ -83,7 +83,7 @@ define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind { define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vqnegs32: ;CHECK: vqneg.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -91,7 +91,7 @@ define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind { define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vqnegQs8: ;CHECK: vqneg.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -99,7 +99,7 @@ define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqnegQs16: ;CHECK: vqneg.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp2 } @@ -107,7 +107,7 @@ define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqnegQs32: ;CHECK: vqneg.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } diff --git a/test/CodeGen/ARM/vpadal.ll b/test/CodeGen/ARM/vpadal.ll index ffeac737fa36..ffb69243b884 100644 --- a/test/CodeGen/ARM/vpadal.ll +++ b/test/CodeGen/ARM/vpadal.ll @@ -3,8 +3,8 @@ define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpadals8: ;CHECK: vpadal.s8 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) ret <4 x i16> %tmp3 } @@ -12,8 +12,8 @@ define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vpadals16: ;CHECK: vpadal.s16 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) ret <2 x i32> %tmp3 } @@ -21,8 +21,8 @@ define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vpadals32: ;CHECK: vpadal.s32 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) ret <1 x i64> %tmp3 } @@ -30,8 +30,8 @@ define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpadalu8: ;CHECK: vpadal.u8 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) ret <4 x i16> %tmp3 } @@ -39,8 +39,8 @@ define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vpadalu16: ;CHECK: vpadal.u16 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) ret <2 x i32> %tmp3 } @@ -48,8 +48,8 @@ define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vpadalu32: ;CHECK: vpadal.u32 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) ret <1 x i64> %tmp3 } @@ -57,8 +57,8 @@ define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vpadalQs8: ;CHECK: vpadal.s8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -66,8 +66,8 @@ define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vpadalQs16: ;CHECK: vpadal.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -75,8 +75,8 @@ define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vpadalQs32: ;CHECK: vpadal.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) ret <2 x i64> %tmp3 } @@ -84,8 +84,8 @@ define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vpadalQu8: ;CHECK: vpadal.u8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vpadalQu16: ;CHECK: vpadal.u16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vpadalQu32: ;CHECK: vpadal.u32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll index 01cb1c74e38e..e362ce36f8ba 100644 --- a/test/CodeGen/ARM/vpadd.ll +++ b/test/CodeGen/ARM/vpadd.ll @@ -3,8 +3,8 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpaddi8: ;CHECK: vpadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vpaddi16: ;CHECK: vpadd.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vpaddi32: ;CHECK: vpadd.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vpaddf32: ;CHECK: vpadd.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -45,7 +45,7 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwin define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vpaddls8: ;CHECK: vpaddl.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1) ret <4 x i16> %tmp2 } @@ -53,7 +53,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vpaddls16: ;CHECK: vpaddl.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1) ret <2 x i32> %tmp2 } @@ -61,7 +61,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vpaddls32: ;CHECK: vpaddl.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1) ret <1 x i64> %tmp2 } @@ -69,7 +69,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vpaddlu8: ;CHECK: vpaddl.u8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1) ret <4 x i16> %tmp2 } @@ -77,7 +77,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vpaddlu16: ;CHECK: vpaddl.u16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1) ret <2 x i32> %tmp2 } @@ -85,7 +85,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vpaddlu32: ;CHECK: vpaddl.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1) ret <1 x i64> %tmp2 } @@ -93,7 +93,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vpaddlQs8: ;CHECK: vpaddl.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1) ret <8 x i16> %tmp2 } @@ -101,7 +101,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vpaddlQs16: ;CHECK: vpaddl.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1) ret <4 x i32> %tmp2 } @@ -109,7 +109,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vpaddlQs32: ;CHECK: vpaddl.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1) ret <2 x i64> %tmp2 } @@ -117,7 +117,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vpaddlQu8: ;CHECK: vpaddl.u8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1) ret <8 x i16> %tmp2 } @@ -125,7 +125,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vpaddlQu16: ;CHECK: vpaddl.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1) ret <4 x i32> %tmp2 } @@ -133,7 +133,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vpaddlQu32: ;CHECK: vpaddl.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1) ret <2 x i64> %tmp2 } @@ -143,9 +143,9 @@ define void @addCombineToVPADDL() nounwind ssp { ; CHECK: vpaddl.s8 %cbcr = alloca <16 x i8>, align 16 %X = alloca <8 x i8>, align 8 - %tmp = load <16 x i8>* %cbcr + %tmp = load <16 x i8>, <16 x i8>* %cbcr %tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> - %tmp2 = load <16 x i8>* %cbcr + %tmp2 = load <16 x i8>, <16 x i8>* %cbcr %tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %add = add <8 x i8> %tmp3, %tmp1 store <8 x i8> %add, <8 x i8>* %X, align 8 diff --git a/test/CodeGen/ARM/vpminmax.ll b/test/CodeGen/ARM/vpminmax.ll index 0b893e5bc892..9ea8c69612c5 100644 --- a/test/CodeGen/ARM/vpminmax.ll +++ b/test/CodeGen/ARM/vpminmax.ll @@ -3,8 +3,8 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpmins8: ;CHECK: vpmin.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vpmins16: ;CHECK: vpmin.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vpmins32: ;CHECK: vpmin.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpminu8: ;CHECK: vpmin.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vpminu16: ;CHECK: vpmin.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vpminu32: ;CHECK: vpmin.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vpminf32: ;CHECK: vpmin.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -76,8 +76,8 @@ declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwi define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpmaxs8: ;CHECK: vpmax.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -85,8 +85,8 @@ define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vpmaxs16: ;CHECK: vpmax.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -94,8 +94,8 @@ define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vpmaxs32: ;CHECK: vpmax.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -103,8 +103,8 @@ define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpmaxu8: ;CHECK: vpmax.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -112,8 +112,8 @@ define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vpmaxu16: ;CHECK: vpmax.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -121,8 +121,8 @@ define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vpmaxu32: ;CHECK: vpmax.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -130,8 +130,8 @@ define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vpmaxf32: ;CHECK: vpmax.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } diff --git a/test/CodeGen/ARM/vqadd.ll b/test/CodeGen/ARM/vqadd.ll index 81acc8bc5abb..d1e90cb20944 100644 --- a/test/CodeGen/ARM/vqadd.ll +++ b/test/CodeGen/ARM/vqadd.ll @@ -3,8 +3,8 @@ define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqadds8: ;CHECK: vqadd.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqadds16: ;CHECK: vqadd.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqadds32: ;CHECK: vqadd.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqadds64: ;CHECK: vqadd.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqaddu8: ;CHECK: vqadd.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -48,8 +48,8 @@ define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqaddu16: ;CHECK: vqadd.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -57,8 +57,8 @@ define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqaddu32: ;CHECK: vqadd.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -66,8 +66,8 @@ define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqaddu64: ;CHECK: vqadd.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -75,8 +75,8 @@ define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqaddQs8: ;CHECK: vqadd.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -84,8 +84,8 @@ define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqaddQs16: ;CHECK: vqadd.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqaddQs32: ;CHECK: vqadd.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqaddQs64: ;CHECK: vqadd.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -111,8 +111,8 @@ define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqaddQu8: ;CHECK: vqadd.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -120,8 +120,8 @@ define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqaddQu16: ;CHECK: vqadd.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -129,8 +129,8 @@ define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqaddQu32: ;CHECK: vqadd.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -138,8 +138,8 @@ define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqaddQu64: ;CHECK: vqadd.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/ARM/vqdmul.ll b/test/CodeGen/ARM/vqdmul.ll index d298167d3a91..6da080012a1e 100644 --- a/test/CodeGen/ARM/vqdmul.ll +++ b/test/CodeGen/ARM/vqdmul.ll @@ -5,8 +5,8 @@ target triple = "thumbv7-elf" define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqdmulhs16: ;CHECK: vqdmulh.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -14,8 +14,8 @@ define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqdmulhs32: ;CHECK: vqdmulh.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -23,8 +23,8 @@ define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqdmulhQs16: ;CHECK: vqdmulh.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -32,8 +32,8 @@ define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqdmulhQs32: ;CHECK: vqdmulh.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -83,8 +83,8 @@ declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind re define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqrdmulhs16: ;CHECK: vqrdmulh.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -92,8 +92,8 @@ define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqrdmulhs32: ;CHECK: vqrdmulh.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -101,8 +101,8 @@ define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqrdmulhQs16: ;CHECK: vqrdmulh.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -110,8 +110,8 @@ define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqrdmulhQs32: ;CHECK: vqrdmulh.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -161,8 +161,8 @@ declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind r define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqdmulls16: ;CHECK: vqdmull.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -170,8 +170,8 @@ define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqdmulls32: ;CHECK: vqdmull.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i64> %tmp3 } @@ -200,9 +200,9 @@ declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind r define <4 x i32> @vqdmlals16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vqdmlals16_natural: ;CHECK: vqdmlal.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3) %tmp5 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4) ret <4 x i32> %tmp5 @@ -211,9 +211,9 @@ define <4 x i32> @vqdmlals16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C define <2 x i64> @vqdmlals32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vqdmlals32_natural: ;CHECK: vqdmlal.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3) %tmp5 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4) ret <2 x i64> %tmp5 @@ -245,9 +245,9 @@ declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) nounwind re define <4 x i32> @vqdmlsls16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: vqdmlsls16_natural: ;CHECK: vqdmlsl.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3) %tmp5 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4) ret <4 x i32> %tmp5 @@ -256,9 +256,9 @@ define <4 x i32> @vqdmlsls16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C define <2 x i64> @vqdmlsls32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: vqdmlsls32_natural: ;CHECK: vqdmlsl.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3) %tmp5 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4) ret <2 x i64> %tmp5 diff --git a/test/CodeGen/ARM/vqshl.ll b/test/CodeGen/ARM/vqshl.ll index 4afef6dbd658..6a6d9af7a2b3 100644 --- a/test/CodeGen/ARM/vqshl.ll +++ b/test/CodeGen/ARM/vqshl.ll @@ -3,8 +3,8 @@ define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqshls8: ;CHECK: vqshl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqshls16: ;CHECK: vqshl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqshls32: ;CHECK: vqshl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqshls64: ;CHECK: vqshl.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqshlu8: ;CHECK: vqshl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -48,8 +48,8 @@ define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqshlu16: ;CHECK: vqshl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -57,8 +57,8 @@ define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqshlu32: ;CHECK: vqshl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -66,8 +66,8 @@ define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqshlu64: ;CHECK: vqshl.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -75,8 +75,8 @@ define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqshlQs8: ;CHECK: vqshl.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -84,8 +84,8 @@ define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqshlQs16: ;CHECK: vqshl.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqshlQs32: ;CHECK: vqshl.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqshlQs64: ;CHECK: vqshl.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -111,8 +111,8 @@ define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqshlQu8: ;CHECK: vqshl.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -120,8 +120,8 @@ define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqshlQu16: ;CHECK: vqshl.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -129,8 +129,8 @@ define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqshlQu32: ;CHECK: vqshl.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -138,8 +138,8 @@ define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqshlQu64: ;CHECK: vqshl.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -147,7 +147,7 @@ define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vqshls_n8: ;CHECK: vqshl.s8{{.*#7}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <8 x i8> %tmp2 } @@ -155,7 +155,7 @@ define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind { define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vqshls_n16: ;CHECK: vqshl.s16{{.*#15}} - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) ret <4 x i16> %tmp2 } @@ -163,7 +163,7 @@ define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind { define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vqshls_n32: ;CHECK: vqshl.s32{{.*#31}} - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) ret <2 x i32> %tmp2 } @@ -171,7 +171,7 @@ define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind { define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vqshls_n64: ;CHECK: vqshl.s64{{.*#63}} - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) ret <1 x i64> %tmp2 } @@ -179,7 +179,7 @@ define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind { define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vqshlu_n8: ;CHECK: vqshl.u8{{.*#7}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <8 x i8> %tmp2 } @@ -187,7 +187,7 @@ define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind { define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vqshlu_n16: ;CHECK: vqshl.u16{{.*#15}} - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) ret <4 x i16> %tmp2 } @@ -195,7 +195,7 @@ define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind { define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vqshlu_n32: ;CHECK: vqshl.u32{{.*#31}} - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) ret <2 x i32> %tmp2 } @@ -203,7 +203,7 @@ define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind { define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vqshlu_n64: ;CHECK: vqshl.u64{{.*#63}} - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) ret <1 x i64> %tmp2 } @@ -211,7 +211,7 @@ define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind { define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vqshlsu_n8: ;CHECK: vqshlu.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <8 x i8> %tmp2 } @@ -219,7 +219,7 @@ define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind { define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vqshlsu_n16: ;CHECK: vqshlu.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) ret <4 x i16> %tmp2 } @@ -227,7 +227,7 @@ define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind { define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vqshlsu_n32: ;CHECK: vqshlu.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) ret <2 x i32> %tmp2 } @@ -235,7 +235,7 @@ define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind { define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vqshlsu_n64: ;CHECK: vqshlu.s64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) ret <1 x i64> %tmp2 } @@ -243,7 +243,7 @@ define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind { define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vqshlQs_n8: ;CHECK: vqshl.s8{{.*#7}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <16 x i8> %tmp2 } @@ -251,7 +251,7 @@ define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind { define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqshlQs_n16: ;CHECK: vqshl.s16{{.*#15}} - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) ret <8 x i16> %tmp2 } @@ -259,7 +259,7 @@ define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind { define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqshlQs_n32: ;CHECK: vqshl.s32{{.*#31}} - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) ret <4 x i32> %tmp2 } @@ -267,7 +267,7 @@ define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind { define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqshlQs_n64: ;CHECK: vqshl.s64{{.*#63}} - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) ret <2 x i64> %tmp2 } @@ -275,7 +275,7 @@ define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind { define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vqshlQu_n8: ;CHECK: vqshl.u8{{.*#7}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <16 x i8> %tmp2 } @@ -283,7 +283,7 @@ define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind { define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqshlQu_n16: ;CHECK: vqshl.u16{{.*#15}} - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) ret <8 x i16> %tmp2 } @@ -291,7 +291,7 @@ define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind { define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqshlQu_n32: ;CHECK: vqshl.u32{{.*#31}} - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) ret <4 x i32> %tmp2 } @@ -299,7 +299,7 @@ define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind { define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqshlQu_n64: ;CHECK: vqshl.u64{{.*#63}} - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) ret <2 x i64> %tmp2 } @@ -307,7 +307,7 @@ define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind { define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vqshlQsu_n8: ;CHECK: vqshlu.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <16 x i8> %tmp2 } @@ -315,7 +315,7 @@ define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind { define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqshlQsu_n16: ;CHECK: vqshlu.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) ret <8 x i16> %tmp2 } @@ -323,7 +323,7 @@ define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind { define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqshlQsu_n32: ;CHECK: vqshlu.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) ret <4 x i32> %tmp2 } @@ -331,7 +331,7 @@ define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind { define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqshlQsu_n64: ;CHECK: vqshlu.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) ret <2 x i64> %tmp2 } @@ -369,8 +369,8 @@ declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqrshls8: ;CHECK: vqrshl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -378,8 +378,8 @@ define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqrshls16: ;CHECK: vqrshl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -387,8 +387,8 @@ define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqrshls32: ;CHECK: vqrshl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -396,8 +396,8 @@ define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqrshls64: ;CHECK: vqrshl.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -405,8 +405,8 @@ define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqrshlu8: ;CHECK: vqrshl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -414,8 +414,8 @@ define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqrshlu16: ;CHECK: vqrshl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -423,8 +423,8 @@ define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqrshlu32: ;CHECK: vqrshl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -432,8 +432,8 @@ define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqrshlu64: ;CHECK: vqrshl.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -441,8 +441,8 @@ define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqrshlQs8: ;CHECK: vqrshl.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -450,8 +450,8 @@ define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqrshlQs16: ;CHECK: vqrshl.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -459,8 +459,8 @@ define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqrshlQs32: ;CHECK: vqrshl.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -468,8 +468,8 @@ define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqrshlQs64: ;CHECK: vqrshl.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -477,8 +477,8 @@ define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqrshlQu8: ;CHECK: vqrshl.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -486,8 +486,8 @@ define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqrshlQu16: ;CHECK: vqrshl.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -495,8 +495,8 @@ define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqrshlQu32: ;CHECK: vqrshl.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -504,8 +504,8 @@ define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqrshlQu64: ;CHECK: vqrshl.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll index f02482c0f77c..b4b5e96d4579 100644 --- a/test/CodeGen/ARM/vqshrn.ll +++ b/test/CodeGen/ARM/vqshrn.ll @@ -3,7 +3,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqshrns8: ;CHECK: vqshrn.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) ret <8 x i8> %tmp2 } @@ -11,7 +11,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind { define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqshrns16: ;CHECK: vqshrn.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) ret <4 x i16> %tmp2 } @@ -19,7 +19,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind { define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqshrns32: ;CHECK: vqshrn.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) ret <2 x i32> %tmp2 } @@ -27,7 +27,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind { define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqshrnu8: ;CHECK: vqshrn.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) ret <8 x i8> %tmp2 } @@ -35,7 +35,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind { define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqshrnu16: ;CHECK: vqshrn.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) ret <4 x i16> %tmp2 } @@ -43,7 +43,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind { define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqshrnu32: ;CHECK: vqshrn.u64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) ret <2 x i32> %tmp2 } @@ -51,7 +51,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind { define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqshruns8: ;CHECK: vqshrun.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) ret <8 x i8> %tmp2 } @@ -59,7 +59,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind { define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqshruns16: ;CHECK: vqshrun.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) ret <4 x i16> %tmp2 } @@ -67,7 +67,7 @@ define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind { define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqshruns32: ;CHECK: vqshrun.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) ret <2 x i32> %tmp2 } @@ -87,7 +87,7 @@ declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqrshrns8: ;CHECK: vqrshrn.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) ret <8 x i8> %tmp2 } @@ -95,7 +95,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind { define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqrshrns16: ;CHECK: vqrshrn.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) ret <4 x i16> %tmp2 } @@ -103,7 +103,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind { define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqrshrns32: ;CHECK: vqrshrn.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) ret <2 x i32> %tmp2 } @@ -111,7 +111,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind { define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqrshrnu8: ;CHECK: vqrshrn.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) ret <8 x i8> %tmp2 } @@ -119,7 +119,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind { define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqrshrnu16: ;CHECK: vqrshrn.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) ret <4 x i16> %tmp2 } @@ -127,7 +127,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind { define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqrshrnu32: ;CHECK: vqrshrn.u64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) ret <2 x i32> %tmp2 } @@ -135,7 +135,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind { define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqrshruns8: ;CHECK: vqrshrun.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) ret <8 x i8> %tmp2 } @@ -143,7 +143,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind { define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vqrshruns16: ;CHECK: vqrshrun.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) ret <4 x i16> %tmp2 } @@ -151,7 +151,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind { define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vqrshruns32: ;CHECK: vqrshrun.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) ret <2 x i32> %tmp2 } diff --git a/test/CodeGen/ARM/vqsub.ll b/test/CodeGen/ARM/vqsub.ll index 4af438019208..40963ce82486 100644 --- a/test/CodeGen/ARM/vqsub.ll +++ b/test/CodeGen/ARM/vqsub.ll @@ -3,8 +3,8 @@ define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqsubs8: ;CHECK: vqsub.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqsubs16: ;CHECK: vqsub.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqsubs32: ;CHECK: vqsub.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqsubs64: ;CHECK: vqsub.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqsubu8: ;CHECK: vqsub.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -48,8 +48,8 @@ define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vqsubu16: ;CHECK: vqsub.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -57,8 +57,8 @@ define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vqsubu32: ;CHECK: vqsub.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -66,8 +66,8 @@ define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vqsubu64: ;CHECK: vqsub.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -75,8 +75,8 @@ define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqsubQs8: ;CHECK: vqsub.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -84,8 +84,8 @@ define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqsubQs16: ;CHECK: vqsub.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqsubQs32: ;CHECK: vqsub.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqsubQs64: ;CHECK: vqsub.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -111,8 +111,8 @@ define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vqsubQu8: ;CHECK: vqsub.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -120,8 +120,8 @@ define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vqsubQu16: ;CHECK: vqsub.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -129,8 +129,8 @@ define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vqsubQu32: ;CHECK: vqsub.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -138,8 +138,8 @@ define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vqsubQu64: ;CHECK: vqsub.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/ARM/vrec.ll b/test/CodeGen/ARM/vrec.ll index 91979e5a3343..a7ebd79289d8 100644 --- a/test/CodeGen/ARM/vrec.ll +++ b/test/CodeGen/ARM/vrec.ll @@ -3,7 +3,7 @@ define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vrecpei32: ;CHECK: vrecpe.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -11,7 +11,7 @@ define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind { define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vrecpeQi32: ;CHECK: vrecpe.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } @@ -19,7 +19,7 @@ define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind { define <2 x float> @vrecpef32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vrecpef32: ;CHECK: vrecpe.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1) ret <2 x float> %tmp2 } @@ -27,7 +27,7 @@ define <2 x float> @vrecpef32(<2 x float>* %A) nounwind { define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vrecpeQf32: ;CHECK: vrecpe.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1) ret <4 x float> %tmp2 } @@ -41,8 +41,8 @@ declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vrecpsf32: ;CHECK: vrecps.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -50,8 +50,8 @@ define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vrecpsQf32: ;CHECK: vrecps.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -62,7 +62,7 @@ declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwi define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vrsqrtei32: ;CHECK: vrsqrte.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -70,7 +70,7 @@ define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind { define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vrsqrteQi32: ;CHECK: vrsqrte.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } @@ -78,7 +78,7 @@ define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind { define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vrsqrtef32: ;CHECK: vrsqrte.f32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1) ret <2 x float> %tmp2 } @@ -86,7 +86,7 @@ define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind { define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind { ;CHECK-LABEL: vrsqrteQf32: ;CHECK: vrsqrte.f32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1) ret <4 x float> %tmp2 } @@ -100,8 +100,8 @@ declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vrsqrtsf32: ;CHECK: vrsqrts.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -109,8 +109,8 @@ define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vrsqrtsQf32: ;CHECK: vrsqrts.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index 7215ad615e81..a20d4b6baf29 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -3,7 +3,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev64D8: ;CHECK: vrev64.8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ret <8 x i8> %tmp2 } @@ -11,7 +11,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev64D16: ;CHECK: vrev64.16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ret <4 x i16> %tmp2 } @@ -19,7 +19,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: test_vrev64D32: ;CHECK: vrev64.32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0> ret <2 x i32> %tmp2 } @@ -27,7 +27,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ;CHECK-LABEL: test_vrev64Df: ;CHECK: vrev64.32 - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0> ret <2 x float> %tmp2 } @@ -35,7 +35,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev64Q8: ;CHECK: vrev64.8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> ret <16 x i8> %tmp2 } @@ -43,7 +43,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev64Q16: ;CHECK: vrev64.16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> ret <8 x i16> %tmp2 } @@ -51,7 +51,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: test_vrev64Q32: ;CHECK: vrev64.32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> ret <4 x i32> %tmp2 } @@ -59,7 +59,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ;CHECK-LABEL: test_vrev64Qf: ;CHECK: vrev64.32 - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> ret <4 x float> %tmp2 } @@ -67,7 +67,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev32D8: ;CHECK: vrev32.8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> ret <8 x i8> %tmp2 } @@ -75,7 +75,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev32D16: ;CHECK: vrev32.16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> ret <4 x i16> %tmp2 } @@ -83,7 +83,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev32Q8: ;CHECK: vrev32.8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> ret <16 x i8> %tmp2 } @@ -91,7 +91,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev32Q16: ;CHECK: vrev32.16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ret <8 x i16> %tmp2 } @@ -99,7 +99,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev16D8: ;CHECK: vrev16.8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ret <8 x i8> %tmp2 } @@ -107,7 +107,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev16Q8: ;CHECK: vrev16.8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> ret <16 x i8> %tmp2 } @@ -117,7 +117,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev64D8_undef: ;CHECK: vrev64.8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0> ret <8 x i8> %tmp2 } @@ -125,7 +125,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind { define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev32Q16_undef: ;CHECK: vrev32.16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef> ret <8 x i16> %tmp2 } @@ -136,7 +136,7 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind { ;CHECK-LABEL: test_with_vcombine: ;CHECK-NOT: vext ;CHECK: vrev64.32 - %tmp1 = load <4 x float>* %v, align 16 + %tmp1 = load <4 x float>, <4 x float>* %v, align 16 %tmp2 = bitcast <4 x float> %tmp1 to <2 x double> %tmp3 = extractelement <2 x double> %tmp2, i32 0 %tmp4 = bitcast double %tmp3 to <2 x float> @@ -155,7 +155,7 @@ define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst ; CHECK: vst1.32 entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* - %tmp2 = load <8 x i16>* %0, align 4 + %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4 %tmp3 = extractelement <8 x i16> %tmp2, i32 6 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 %tmp9 = extractelement <8 x i16> %tmp2, i32 5 @@ -171,9 +171,9 @@ define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest ; CHECK: vrev64.32 entry: %0 = bitcast float* %source to <4 x float>* - %tmp2 = load <4 x float>* %0, align 4 + %tmp2 = load <4 x float>, <4 x float>* %0, align 4 %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0> - %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11 + %arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11 store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4 ret void } diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll index e999034fa47e..0eb051036d99 100644 --- a/test/CodeGen/ARM/vselect_imax.ll +++ b/test/CodeGen/ARM/vselect_imax.ll @@ -18,8 +18,8 @@ define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: func_blend10: define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2, %T1_10* %blend, %T0_10* %storeaddr) { - %v0 = load %T0_10* %loadaddr - %v1 = load %T0_10* %loadaddr2 + %v0 = load %T0_10, %T0_10* %loadaddr + %v1 = load %T0_10, %T0_10* %loadaddr2 %c = icmp slt %T0_10 %v0, %v1 ; CHECK: vbsl ; CHECK: vbsl @@ -34,8 +34,8 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2, ; CHECK-LABEL: func_blend14: define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, %T1_14* %blend, %T0_14* %storeaddr) { - %v0 = load %T0_14* %loadaddr - %v1 = load %T0_14* %loadaddr2 + %v0 = load %T0_14, %T0_14* %loadaddr + %v1 = load %T0_14, %T0_14* %loadaddr2 %c = icmp slt %T0_14 %v0, %v1 ; CHECK: vbsl ; CHECK: vbsl @@ -52,8 +52,8 @@ define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2, %T1_15* %blend, %T0_15* %storeaddr) { ; CHECK: vbsl ; CHECK: vbsl - %v0 = load %T0_15* %loadaddr - %v1 = load %T0_15* %loadaddr2 + %v0 = load %T0_15, %T0_15* %loadaddr + %v1 = load %T0_15, %T0_15* %loadaddr2 %c = icmp slt %T0_15 %v0, %v1 ; COST: func_blend15 ; COST: cost of 82 {{.*}} select @@ -68,8 +68,8 @@ define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2, %T1_18* %blend, %T0_18* %storeaddr) { ; CHECK: vbsl ; CHECK: vbsl - %v0 = load %T0_18* %loadaddr - %v1 = load %T0_18* %loadaddr2 + %v0 = load %T0_18, %T0_18* %loadaddr + %v1 = load %T0_18, %T0_18* %loadaddr2 %c = icmp slt %T0_18 %v0, %v1 ; COST: func_blend18 ; COST: cost of 19 {{.*}} select @@ -86,8 +86,8 @@ define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2, ; CHECK: vbsl ; CHECK: vbsl ; CHECK: vbsl - %v0 = load %T0_19* %loadaddr - %v1 = load %T0_19* %loadaddr2 + %v0 = load %T0_19, %T0_19* %loadaddr + %v1 = load %T0_19, %T0_19* %loadaddr2 %c = icmp slt %T0_19 %v0, %v1 ; COST: func_blend19 ; COST: cost of 50 {{.*}} select @@ -108,8 +108,8 @@ define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2, ; CHECK: vbsl ; CHECK: vbsl ; CHECK: vbsl - %v0 = load %T0_20* %loadaddr - %v1 = load %T0_20* %loadaddr2 + %v0 = load %T0_20, %T0_20* %loadaddr + %v1 = load %T0_20, %T0_20* %loadaddr2 %c = icmp slt %T0_20 %v0, %v1 ; COST: func_blend20 ; COST: cost of 100 {{.*}} select diff --git a/test/CodeGen/ARM/vshift.ll b/test/CodeGen/ARM/vshift.ll index 618a137b5b05..31e4cb05dd20 100644 --- a/test/CodeGen/ARM/vshift.ll +++ b/test/CodeGen/ARM/vshift.ll @@ -3,8 +3,8 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vshls8: ;CHECK: vshl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shl <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vshls16: ;CHECK: vshl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shl <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vshls32: ;CHECK: vshl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shl <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vshls64: ;CHECK: vshl.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = shl <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -39,7 +39,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshli8: ;CHECK: vshl.i8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > ret <8 x i8> %tmp2 } @@ -47,7 +47,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vshli16: ;CHECK: vshl.i16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 > ret <4 x i16> %tmp2 } @@ -55,7 +55,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vshli32: ;CHECK: vshl.i32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 > ret <2 x i32> %tmp2 } @@ -63,7 +63,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vshli64: ;CHECK: vshl.i64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = shl <1 x i64> %tmp1, < i64 63 > ret <1 x i64> %tmp2 } @@ -71,8 +71,8 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vshlQs8: ;CHECK: vshl.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shl <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -80,8 +80,8 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vshlQs16: ;CHECK: vshl.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shl <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -89,8 +89,8 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vshlQs32: ;CHECK: vshl.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shl <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -98,8 +98,8 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vshlQs64: ;CHECK: vshl.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = shl <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -107,7 +107,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vshlQi8: ;CHECK: vshl.i8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > ret <16 x i8> %tmp2 } @@ -115,7 +115,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vshlQi16: ;CHECK: vshl.i16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > ret <8 x i16> %tmp2 } @@ -123,7 +123,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vshlQi32: ;CHECK: vshl.i32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 > ret <4 x i32> %tmp2 } @@ -131,7 +131,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vshlQi64: ;CHECK: vshl.i64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 > ret <2 x i64> %tmp2 } @@ -140,8 +140,8 @@ define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vlshru8: ;CHECK: vneg.s8 ;CHECK: vshl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = lshr <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -150,8 +150,8 @@ define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vlshru16: ;CHECK: vneg.s16 ;CHECK: vshl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = lshr <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -160,8 +160,8 @@ define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vlshru32: ;CHECK: vneg.s32 ;CHECK: vshl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = lshr <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -170,8 +170,8 @@ define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vlshru64: ;CHECK: vsub.i64 ;CHECK: vshl.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = lshr <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -179,7 +179,7 @@ define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vlshri8: ;CHECK: vshr.u8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = lshr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > ret <8 x i8> %tmp2 } @@ -187,7 +187,7 @@ define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind { define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vlshri16: ;CHECK: vshr.u16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = lshr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 > ret <4 x i16> %tmp2 } @@ -195,7 +195,7 @@ define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind { define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vlshri32: ;CHECK: vshr.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = lshr <2 x i32> %tmp1, < i32 31, i32 31 > ret <2 x i32> %tmp2 } @@ -203,7 +203,7 @@ define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind { define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vlshri64: ;CHECK: vshr.u64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = lshr <1 x i64> %tmp1, < i64 63 > ret <1 x i64> %tmp2 } @@ -212,8 +212,8 @@ define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vlshrQu8: ;CHECK: vneg.s8 ;CHECK: vshl.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = lshr <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -222,8 +222,8 @@ define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vlshrQu16: ;CHECK: vneg.s16 ;CHECK: vshl.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = lshr <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -232,8 +232,8 @@ define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vlshrQu32: ;CHECK: vneg.s32 ;CHECK: vshl.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = lshr <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -242,8 +242,8 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vlshrQu64: ;CHECK: vsub.i64 ;CHECK: vshl.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = lshr <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -251,7 +251,7 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vlshrQi8: ;CHECK: vshr.u8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = lshr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > ret <16 x i8> %tmp2 } @@ -259,7 +259,7 @@ define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind { define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vlshrQi16: ;CHECK: vshr.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = lshr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > ret <8 x i16> %tmp2 } @@ -267,7 +267,7 @@ define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind { define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vlshrQi32: ;CHECK: vshr.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = lshr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 > ret <4 x i32> %tmp2 } @@ -275,7 +275,7 @@ define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind { define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vlshrQi64: ;CHECK: vshr.u64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = lshr <2 x i64> %tmp1, < i64 63, i64 63 > ret <2 x i64> %tmp2 } @@ -291,8 +291,8 @@ define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vashrs8: ;CHECK: vneg.s8 ;CHECK: vshl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = ashr <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -301,8 +301,8 @@ define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vashrs16: ;CHECK: vneg.s16 ;CHECK: vshl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = ashr <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -311,8 +311,8 @@ define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vashrs32: ;CHECK: vneg.s32 ;CHECK: vshl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = ashr <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -321,8 +321,8 @@ define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vashrs64: ;CHECK: vsub.i64 ;CHECK: vshl.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = ashr <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -330,7 +330,7 @@ define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vashri8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vashri8: ;CHECK: vshr.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = ashr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > ret <8 x i8> %tmp2 } @@ -338,7 +338,7 @@ define <8 x i8> @vashri8(<8 x i8>* %A) nounwind { define <4 x i16> @vashri16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vashri16: ;CHECK: vshr.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = ashr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 > ret <4 x i16> %tmp2 } @@ -346,7 +346,7 @@ define <4 x i16> @vashri16(<4 x i16>* %A) nounwind { define <2 x i32> @vashri32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vashri32: ;CHECK: vshr.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = ashr <2 x i32> %tmp1, < i32 31, i32 31 > ret <2 x i32> %tmp2 } @@ -354,7 +354,7 @@ define <2 x i32> @vashri32(<2 x i32>* %A) nounwind { define <1 x i64> @vashri64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vashri64: ;CHECK: vshr.s64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = ashr <1 x i64> %tmp1, < i64 63 > ret <1 x i64> %tmp2 } @@ -363,8 +363,8 @@ define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vashrQs8: ;CHECK: vneg.s8 ;CHECK: vshl.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = ashr <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -373,8 +373,8 @@ define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vashrQs16: ;CHECK: vneg.s16 ;CHECK: vshl.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = ashr <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -383,8 +383,8 @@ define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vashrQs32: ;CHECK: vneg.s32 ;CHECK: vshl.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = ashr <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -393,8 +393,8 @@ define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vashrQs64: ;CHECK: vsub.i64 ;CHECK: vshl.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = ashr <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -402,7 +402,7 @@ define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vashrQi8: ;CHECK: vshr.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = ashr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > ret <16 x i8> %tmp2 } @@ -410,7 +410,7 @@ define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind { define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vashrQi16: ;CHECK: vshr.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = ashr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > ret <8 x i16> %tmp2 } @@ -418,7 +418,7 @@ define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind { define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vashrQi32: ;CHECK: vshr.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = ashr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 > ret <4 x i32> %tmp2 } @@ -426,7 +426,7 @@ define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind { define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vashrQi64: ;CHECK: vshr.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = ashr <2 x i64> %tmp1, < i64 63, i64 63 > ret <2 x i64> %tmp2 } diff --git a/test/CodeGen/ARM/vshiftins.ll b/test/CodeGen/ARM/vshiftins.ll index 9526c3222017..29487378317d 100644 --- a/test/CodeGen/ARM/vshiftins.ll +++ b/test/CodeGen/ARM/vshiftins.ll @@ -3,8 +3,8 @@ define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsli8: ;CHECK: vsli.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsli16: ;CHECK: vsli.16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsli32: ;CHECK: vsli.32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vsli64: ;CHECK: vsli.64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >) ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vsliQ8: ;CHECK: vsli.8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <16 x i8> %tmp3 } @@ -48,8 +48,8 @@ define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vsliQ16: ;CHECK: vsli.16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) ret <8 x i16> %tmp3 } @@ -57,8 +57,8 @@ define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vsliQ32: ;CHECK: vsli.32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) ret <4 x i32> %tmp3 } @@ -66,8 +66,8 @@ define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vsliQ64: ;CHECK: vsli.64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >) ret <2 x i64> %tmp3 } @@ -75,8 +75,8 @@ define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsri8: ;CHECK: vsri.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <8 x i8> %tmp3 } @@ -84,8 +84,8 @@ define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsri16: ;CHECK: vsri.16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) ret <4 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsri32: ;CHECK: vsri.32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) ret <2 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vsri64: ;CHECK: vsri.64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >) ret <1 x i64> %tmp3 } @@ -111,8 +111,8 @@ define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vsriQ8: ;CHECK: vsri.8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <16 x i8> %tmp3 } @@ -120,8 +120,8 @@ define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vsriQ16: ;CHECK: vsri.16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) ret <8 x i16> %tmp3 } @@ -129,8 +129,8 @@ define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vsriQ32: ;CHECK: vsri.32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) ret <4 x i32> %tmp3 } @@ -138,8 +138,8 @@ define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vsriQ64: ;CHECK: vsri.64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/ARM/vshl.ll b/test/CodeGen/ARM/vshl.ll index 6228652fc715..ef76e3d9a36c 100644 --- a/test/CodeGen/ARM/vshl.ll +++ b/test/CodeGen/ARM/vshl.ll @@ -3,8 +3,8 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vshls8: ;CHECK: vshl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vshls16: ;CHECK: vshl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vshls32: ;CHECK: vshl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vshls64: ;CHECK: vshl.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vshlu8: ;CHECK: vshl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -48,8 +48,8 @@ define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vshlu16: ;CHECK: vshl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -57,8 +57,8 @@ define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vshlu32: ;CHECK: vshl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -66,8 +66,8 @@ define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vshlu64: ;CHECK: vshl.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -75,8 +75,8 @@ define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vshlQs8: ;CHECK: vshl.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -84,8 +84,8 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vshlQs16: ;CHECK: vshl.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vshlQs32: ;CHECK: vshl.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vshlQs64: ;CHECK: vshl.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -111,8 +111,8 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vshlQu8: ;CHECK: vshl.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -120,8 +120,8 @@ define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vshlQu16: ;CHECK: vshl.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -129,8 +129,8 @@ define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vshlQu32: ;CHECK: vshl.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -138,8 +138,8 @@ define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vshlQu64: ;CHECK: vshl.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -150,7 +150,7 @@ define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshli8: ;CHECK: vshl.i8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <8 x i8> %tmp2 } @@ -158,7 +158,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vshli16: ;CHECK: vshl.i16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) ret <4 x i16> %tmp2 } @@ -166,7 +166,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vshli32: ;CHECK: vshl.i32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) ret <2 x i32> %tmp2 } @@ -174,7 +174,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vshli64: ;CHECK: vshl.i64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) ret <1 x i64> %tmp2 } @@ -182,7 +182,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vshlQi8: ;CHECK: vshl.i8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) ret <16 x i8> %tmp2 } @@ -190,7 +190,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vshlQi16: ;CHECK: vshl.i16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) ret <8 x i16> %tmp2 } @@ -198,7 +198,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vshlQi32: ;CHECK: vshl.i32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) ret <4 x i32> %tmp2 } @@ -206,7 +206,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vshlQi64: ;CHECK: vshl.i64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) ret <2 x i64> %tmp2 } @@ -216,7 +216,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshrs8: ;CHECK: vshr.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <8 x i8> %tmp2 } @@ -224,7 +224,7 @@ define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind { define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vshrs16: ;CHECK: vshr.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) ret <4 x i16> %tmp2 } @@ -232,7 +232,7 @@ define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind { define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vshrs32: ;CHECK: vshr.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) ret <2 x i32> %tmp2 } @@ -240,7 +240,7 @@ define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind { define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vshrs64: ;CHECK: vshr.s64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) ret <1 x i64> %tmp2 } @@ -248,7 +248,7 @@ define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind { define <8 x i8> @vshru8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshru8: ;CHECK: vshr.u8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <8 x i8> %tmp2 } @@ -256,7 +256,7 @@ define <8 x i8> @vshru8(<8 x i8>* %A) nounwind { define <4 x i16> @vshru16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vshru16: ;CHECK: vshr.u16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) ret <4 x i16> %tmp2 } @@ -264,7 +264,7 @@ define <4 x i16> @vshru16(<4 x i16>* %A) nounwind { define <2 x i32> @vshru32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vshru32: ;CHECK: vshr.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) ret <2 x i32> %tmp2 } @@ -272,7 +272,7 @@ define <2 x i32> @vshru32(<2 x i32>* %A) nounwind { define <1 x i64> @vshru64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vshru64: ;CHECK: vshr.u64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) ret <1 x i64> %tmp2 } @@ -280,7 +280,7 @@ define <1 x i64> @vshru64(<1 x i64>* %A) nounwind { define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vshrQs8: ;CHECK: vshr.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <16 x i8> %tmp2 } @@ -288,7 +288,7 @@ define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vshrQs16: ;CHECK: vshr.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) ret <8 x i16> %tmp2 } @@ -296,7 +296,7 @@ define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vshrQs32: ;CHECK: vshr.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) ret <4 x i32> %tmp2 } @@ -304,7 +304,7 @@ define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind { define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vshrQs64: ;CHECK: vshr.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) ret <2 x i64> %tmp2 } @@ -312,7 +312,7 @@ define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind { define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vshrQu8: ;CHECK: vshr.u8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <16 x i8> %tmp2 } @@ -320,7 +320,7 @@ define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind { define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vshrQu16: ;CHECK: vshr.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) ret <8 x i16> %tmp2 } @@ -328,7 +328,7 @@ define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind { define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vshrQu32: ;CHECK: vshr.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) ret <4 x i32> %tmp2 } @@ -336,7 +336,7 @@ define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind { define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vshrQu64: ;CHECK: vshr.u64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) ret <2 x i64> %tmp2 } @@ -364,8 +364,8 @@ declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind re define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vrshls8: ;CHECK: vrshl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -373,8 +373,8 @@ define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vrshls16: ;CHECK: vrshl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -382,8 +382,8 @@ define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vrshls32: ;CHECK: vrshl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -391,8 +391,8 @@ define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vrshls64: ;CHECK: vrshl.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -400,8 +400,8 @@ define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vrshlu8: ;CHECK: vrshl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -409,8 +409,8 @@ define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vrshlu16: ;CHECK: vrshl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -418,8 +418,8 @@ define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vrshlu32: ;CHECK: vrshl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -427,8 +427,8 @@ define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vrshlu64: ;CHECK: vrshl.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) ret <1 x i64> %tmp3 } @@ -436,8 +436,8 @@ define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vrshlQs8: ;CHECK: vrshl.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -445,8 +445,8 @@ define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrshlQs16: ;CHECK: vrshl.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -454,8 +454,8 @@ define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vrshlQs32: ;CHECK: vrshl.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -463,8 +463,8 @@ define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vrshlQs64: ;CHECK: vrshl.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -472,8 +472,8 @@ define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vrshlQu8: ;CHECK: vrshl.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -481,8 +481,8 @@ define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrshlQu16: ;CHECK: vrshl.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -490,8 +490,8 @@ define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vrshlQu32: ;CHECK: vrshl.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -499,8 +499,8 @@ define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vrshlQu64: ;CHECK: vrshl.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -508,7 +508,7 @@ define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vrshrs8: ;CHECK: vrshr.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <8 x i8> %tmp2 } @@ -516,7 +516,7 @@ define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind { define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vrshrs16: ;CHECK: vrshr.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) ret <4 x i16> %tmp2 } @@ -524,7 +524,7 @@ define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind { define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vrshrs32: ;CHECK: vrshr.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) ret <2 x i32> %tmp2 } @@ -532,7 +532,7 @@ define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind { define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vrshrs64: ;CHECK: vrshr.s64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) ret <1 x i64> %tmp2 } @@ -540,7 +540,7 @@ define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind { define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vrshru8: ;CHECK: vrshr.u8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <8 x i8> %tmp2 } @@ -548,7 +548,7 @@ define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind { define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vrshru16: ;CHECK: vrshr.u16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) ret <4 x i16> %tmp2 } @@ -556,7 +556,7 @@ define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind { define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vrshru32: ;CHECK: vrshr.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) ret <2 x i32> %tmp2 } @@ -564,7 +564,7 @@ define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind { define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind { ;CHECK-LABEL: vrshru64: ;CHECK: vrshr.u64 - %tmp1 = load <1 x i64>* %A + %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) ret <1 x i64> %tmp2 } @@ -572,7 +572,7 @@ define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind { define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vrshrQs8: ;CHECK: vrshr.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <16 x i8> %tmp2 } @@ -580,7 +580,7 @@ define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vrshrQs16: ;CHECK: vrshr.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) ret <8 x i16> %tmp2 } @@ -588,7 +588,7 @@ define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vrshrQs32: ;CHECK: vrshr.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) ret <4 x i32> %tmp2 } @@ -596,7 +596,7 @@ define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind { define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vrshrQs64: ;CHECK: vrshr.s64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) ret <2 x i64> %tmp2 } @@ -604,7 +604,7 @@ define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind { define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vrshrQu8: ;CHECK: vrshr.u8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) ret <16 x i8> %tmp2 } @@ -612,7 +612,7 @@ define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind { define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vrshrQu16: ;CHECK: vrshr.u16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) ret <8 x i16> %tmp2 } @@ -620,7 +620,7 @@ define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind { define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vrshrQu32: ;CHECK: vrshr.u32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) ret <4 x i32> %tmp2 } @@ -628,7 +628,7 @@ define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind { define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vrshrQu64: ;CHECK: vrshr.u64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) ret <2 x i64> %tmp2 } diff --git a/test/CodeGen/ARM/vshll.ll b/test/CodeGen/ARM/vshll.ll index 27873eb72753..a8230134d91f 100644 --- a/test/CodeGen/ARM/vshll.ll +++ b/test/CodeGen/ARM/vshll.ll @@ -3,7 +3,7 @@ define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshlls8: ;CHECK: vshll.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %sext = sext <8 x i8> %tmp1 to <8 x i16> %shift = shl <8 x i16> %sext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> ret <8 x i16> %shift @@ -12,7 +12,7 @@ define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind { define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vshlls16: ;CHECK: vshll.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %sext = sext <4 x i16> %tmp1 to <4 x i32> %shift = shl <4 x i32> %sext, <i32 15, i32 15, i32 15, i32 15> ret <4 x i32> %shift @@ -21,7 +21,7 @@ define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind { define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vshlls32: ;CHECK: vshll.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %sext = sext <2 x i32> %tmp1 to <2 x i64> %shift = shl <2 x i64> %sext, <i64 31, i64 31> ret <2 x i64> %shift @@ -30,7 +30,7 @@ define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind { define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshllu8: ;CHECK: vshll.u8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %zext = zext <8 x i8> %tmp1 to <8 x i16> %shift = shl <8 x i16> %zext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> ret <8 x i16> %shift @@ -39,7 +39,7 @@ define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind { define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vshllu16: ;CHECK: vshll.u16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %zext = zext <4 x i16> %tmp1 to <4 x i32> %shift = shl <4 x i32> %zext, <i32 15, i32 15, i32 15, i32 15> ret <4 x i32> %shift @@ -48,7 +48,7 @@ define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind { define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vshllu32: ;CHECK: vshll.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %zext = zext <2 x i32> %tmp1 to <2 x i64> %shift = shl <2 x i64> %zext, <i64 31, i64 31> ret <2 x i64> %shift @@ -59,7 +59,7 @@ define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind { define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshlli8: ;CHECK: vshll.i8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %sext = sext <8 x i8> %tmp1 to <8 x i16> %shift = shl <8 x i16> %sext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> ret <8 x i16> %shift @@ -68,7 +68,7 @@ define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind { define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vshlli16: ;CHECK: vshll.i16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %zext = zext <4 x i16> %tmp1 to <4 x i32> %shift = shl <4 x i32> %zext, <i32 16, i32 16, i32 16, i32 16> ret <4 x i32> %shift @@ -77,7 +77,7 @@ define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind { define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vshlli32: ;CHECK: vshll.i32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %zext = zext <2 x i32> %tmp1 to <2 x i64> %shift = shl <2 x i64> %zext, <i64 32, i64 32> ret <2 x i64> %shift @@ -89,7 +89,7 @@ define <8 x i16> @vshllu8_bad(<8 x i8>* %A) nounwind { ; CHECK-LABEL: vshllu8_bad: ; CHECK: vmovl.u8 ; CHECK: vshl.i16 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %zext = zext <8 x i8> %tmp1 to <8 x i16> %shift = shl <8 x i16> %zext, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9> ret <8 x i16> %shift @@ -99,7 +99,7 @@ define <4 x i32> @vshlls16_bad(<4 x i16>* %A) nounwind { ; CHECK-LABEL: vshlls16_bad: ; CHECK: vmovl.s16 ; CHECK: vshl.i32 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %sext = sext <4 x i16> %tmp1 to <4 x i32> %shift = shl <4 x i32> %sext, <i32 17, i32 17, i32 17, i32 17> ret <4 x i32> %shift @@ -109,7 +109,7 @@ define <2 x i64> @vshllu32_bad(<2 x i32>* %A) nounwind { ; CHECK-LABEL: vshllu32_bad: ; CHECK: vmovl.u32 ; CHECK: vshl.i64 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %zext = zext <2 x i32> %tmp1 to <2 x i64> %shift = shl <2 x i64> %zext, <i64 33, i64 33> ret <2 x i64> %shift diff --git a/test/CodeGen/ARM/vshrn.ll b/test/CodeGen/ARM/vshrn.ll index 8aa009ab823e..e033486562c6 100644 --- a/test/CodeGen/ARM/vshrn.ll +++ b/test/CodeGen/ARM/vshrn.ll @@ -3,7 +3,7 @@ define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vshrns8: ;CHECK: vshrn.i16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = lshr <8 x i16> %tmp1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8> ret <8 x i8> %tmp3 @@ -12,7 +12,7 @@ define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vshrns16: ;CHECK: vshrn.i32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = ashr <4 x i32> %tmp1, <i32 16, i32 16, i32 16, i32 16> %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16> ret <4 x i16> %tmp3 @@ -21,7 +21,7 @@ define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind { define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vshrns32: ;CHECK: vshrn.i64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = ashr <2 x i64> %tmp1, <i64 32, i64 32> %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32> ret <2 x i32> %tmp3 @@ -31,7 +31,7 @@ define <8 x i8> @vshrns8_bad(<8 x i16>* %A) nounwind { ; CHECK-LABEL: vshrns8_bad: ; CHECK: vshr.s16 ; CHECK: vmovn.i16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = ashr <8 x i16> %tmp1, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9> %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8> ret <8 x i8> %tmp3 @@ -41,7 +41,7 @@ define <4 x i16> @vshrns16_bad(<4 x i32>* %A) nounwind { ; CHECK-LABEL: vshrns16_bad: ; CHECK: vshr.u32 ; CHECK: vmovn.i32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = lshr <4 x i32> %tmp1, <i32 17, i32 17, i32 17, i32 17> %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16> ret <4 x i16> %tmp3 @@ -51,7 +51,7 @@ define <2 x i32> @vshrns32_bad(<2 x i64>* %A) nounwind { ; CHECK-LABEL: vshrns32_bad: ; CHECK: vshr.u64 ; CHECK: vmovn.i64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = lshr <2 x i64> %tmp1, <i64 33, i64 33> %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32> ret <2 x i32> %tmp3 @@ -60,7 +60,7 @@ define <2 x i32> @vshrns32_bad(<2 x i64>* %A) nounwind { define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vrshrns8: ;CHECK: vrshrn.i16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) ret <8 x i8> %tmp2 } @@ -68,7 +68,7 @@ define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind { define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vrshrns16: ;CHECK: vrshrn.i32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) ret <4 x i16> %tmp2 } @@ -76,7 +76,7 @@ define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind { define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind { ;CHECK-LABEL: vrshrns32: ;CHECK: vrshrn.i64 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) ret <2 x i32> %tmp2 } diff --git a/test/CodeGen/ARM/vsra.ll b/test/CodeGen/ARM/vsra.ll index fa5985a330c4..cb758fa2f386 100644 --- a/test/CodeGen/ARM/vsra.ll +++ b/test/CodeGen/ARM/vsra.ll @@ -3,8 +3,8 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsras8: ;CHECK: vsra.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -13,8 +13,8 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsras16: ;CHECK: vsra.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -23,8 +23,8 @@ define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsras32: ;CHECK: vsra.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 > %tmp4 = add <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -33,8 +33,8 @@ define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vsras64: ;CHECK: vsra.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = ashr <1 x i64> %tmp2, < i64 63 > %tmp4 = add <1 x i64> %tmp1, %tmp3 ret <1 x i64> %tmp4 @@ -43,8 +43,8 @@ define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vsraQs8: ;CHECK: vsra.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -53,8 +53,8 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vsraQs16: ;CHECK: vsra.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -63,8 +63,8 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vsraQs32: ;CHECK: vsra.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 > %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -73,8 +73,8 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vsraQs64: ;CHECK: vsra.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 > %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -83,8 +83,8 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsrau8: ;CHECK: vsra.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -93,8 +93,8 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsrau16: ;CHECK: vsra.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -103,8 +103,8 @@ define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsrau32: ;CHECK: vsra.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 > %tmp4 = add <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -113,8 +113,8 @@ define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vsrau64: ;CHECK: vsra.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = lshr <1 x i64> %tmp2, < i64 63 > %tmp4 = add <1 x i64> %tmp1, %tmp3 ret <1 x i64> %tmp4 @@ -123,8 +123,8 @@ define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vsraQu8: ;CHECK: vsra.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -133,8 +133,8 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vsraQu16: ;CHECK: vsra.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -143,8 +143,8 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vsraQu32: ;CHECK: vsra.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 > %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -153,8 +153,8 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vsraQu64: ;CHECK: vsra.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 > %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -163,8 +163,8 @@ define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vrsras8: ;CHECK: vrsra.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) %tmp4 = add <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -173,8 +173,8 @@ define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vrsras16: ;CHECK: vrsra.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) %tmp4 = add <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -183,8 +183,8 @@ define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vrsras32: ;CHECK: vrsra.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) %tmp4 = add <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -193,8 +193,8 @@ define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vrsras64: ;CHECK: vrsra.s64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >) %tmp4 = add <1 x i64> %tmp1, %tmp3 ret <1 x i64> %tmp4 @@ -203,8 +203,8 @@ define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vrsrau8: ;CHECK: vrsra.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) %tmp4 = add <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -213,8 +213,8 @@ define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vrsrau16: ;CHECK: vrsra.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) %tmp4 = add <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -223,8 +223,8 @@ define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vrsrau32: ;CHECK: vrsra.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) %tmp4 = add <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -233,8 +233,8 @@ define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vrsrau64: ;CHECK: vrsra.u64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >) %tmp4 = add <1 x i64> %tmp1, %tmp3 ret <1 x i64> %tmp4 @@ -243,8 +243,8 @@ define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vrsraQs8: ;CHECK: vrsra.s8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) %tmp4 = add <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -253,8 +253,8 @@ define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrsraQs16: ;CHECK: vrsra.s16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -263,8 +263,8 @@ define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vrsraQs32: ;CHECK: vrsra.s32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -273,8 +273,8 @@ define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vrsraQs64: ;CHECK: vrsra.s64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -283,8 +283,8 @@ define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vrsraQu8: ;CHECK: vrsra.u8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) %tmp4 = add <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -293,8 +293,8 @@ define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrsraQu16: ;CHECK: vrsra.u16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -303,8 +303,8 @@ define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vrsraQu32: ;CHECK: vrsra.u32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -313,8 +313,8 @@ define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vrsraQu64: ;CHECK: vrsra.u64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index a6bcf7d8ead3..f605fa4d6003 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -4,7 +4,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1i8: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vst1.8 {d16}, [r0:64] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16) ret void } @@ -13,7 +13,7 @@ define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vst1i16: ;CHECK: vst1.16 %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1) ret void } @@ -22,7 +22,7 @@ define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst1i32: ;CHECK: vst1.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1) ret void } @@ -31,7 +31,7 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst1f: ;CHECK: vst1.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1) ret void } @@ -40,11 +40,11 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind { define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst1f_update: ;CHECK: vst1.32 {d16}, [r1]! - %A = load float** %ptr + %A = load float*, float** %ptr %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1) - %tmp2 = getelementptr float* %A, i32 2 + %tmp2 = getelementptr float, float* %A, i32 2 store float* %tmp2, float** %ptr ret void } @@ -53,7 +53,7 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vst1i64: ;CHECK: vst1.64 %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %B call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1) ret void } @@ -62,7 +62,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vst1Qi8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst1.8 {d16, d17}, [r0:64] - %tmp1 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %B call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8) ret void } @@ -72,7 +72,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst1.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32) ret void } @@ -81,11 +81,11 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { ;CHECK-LABEL: vst1Qi16_update: ;CHECK: vst1.16 {d16, d17}, [r1:64], r2 - %A = load i16** %ptr + %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8) - %tmp2 = getelementptr i16* %A, i32 %inc + %tmp2 = getelementptr i16, i16* %A, i32 %inc store i16* %tmp2, i16** %ptr ret void } @@ -94,7 +94,7 @@ define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst1Qi32: ;CHECK: vst1.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst1.v4i32(i8* %tmp0, <4 x i32> %tmp1, i32 1) ret void } @@ -103,7 +103,7 @@ define void @vst1Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst1Qf: ;CHECK: vst1.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1) ret void } @@ -112,7 +112,7 @@ define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vst1Qi64: ;CHECK: vst1.64 %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %B call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1) ret void } @@ -121,7 +121,7 @@ define void @vst1Qf64(double* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: vst1Qf64: ;CHECK: vst1.64 %tmp0 = bitcast double* %A to i8* - %tmp1 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %B call void @llvm.arm.neon.vst1.v2f64(i8* %tmp0, <2 x double> %tmp1, i32 1) ret void } diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll index 2180259d57f7..17c8a4bdad9b 100644 --- a/test/CodeGen/ARM/vst2.ll +++ b/test/CodeGen/ARM/vst2.ll @@ -4,7 +4,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst2i8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst2.8 {d16, d17}, [r0:64] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) ret void } @@ -13,10 +13,10 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { ;CHECK-LABEL: vst2i8_update: ;CHECK: vst2.8 {d16, d17}, [r1], r2 - %A = load i8** %ptr - %tmp1 = load <8 x i8>* %B + %A = load i8*, i8** %ptr + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4) - %tmp2 = getelementptr i8* %A, i32 %inc + %tmp2 = getelementptr i8, i8* %A, i32 %inc store i8* %tmp2, i8** %ptr ret void } @@ -26,7 +26,7 @@ define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst2.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32) ret void } @@ -35,7 +35,7 @@ define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst2i32: ;CHECK: vst2.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst2.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } @@ -44,7 +44,7 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst2f: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst2.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } @@ -54,7 +54,7 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst1.64 {d16, d17}, [r0:128] %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %B call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32) ret void } @@ -63,11 +63,11 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vst2i64_update: ;CHECK: vst1.64 {d16, d17}, [r1:64]! - %A = load i64** %ptr + %A = load i64*, i64** %ptr %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %B call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8) - %tmp2 = getelementptr i64* %A, i32 2 + %tmp2 = getelementptr i64, i64* %A, i32 2 store i64* %tmp2, i64** %ptr ret void } @@ -76,7 +76,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vst2Qi8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] - %tmp1 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %B call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8) ret void } @@ -86,7 +86,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16) ret void } @@ -96,7 +96,7 @@ define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64) ret void } @@ -105,7 +105,7 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst2Qf: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst2.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } @@ -113,18 +113,18 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind { define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vst2update: ;CHECK: vst2.16 {d16, d17}, [r0]! - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2) - %t5 = getelementptr inbounds i8* %out, i32 16 + %t5 = getelementptr inbounds i8, i8* %out, i32 16 ret i8* %t5 } define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 { ;CHECK-LABEL: vst2update2: ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]! - %tmp1 = load <4 x float>* %this + %tmp1 = load <4 x float>, <4 x float>* %this call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind - %tmp2 = getelementptr inbounds i8* %out, i32 32 + %tmp2 = getelementptr inbounds i8, i8* %out, i32 32 ret i8* %tmp2 } diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index 5f150edf31da..691ee3bd28f3 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -5,7 +5,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;This test runs at -O0 so do not check for specific register numbers. ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32) ret void } @@ -14,7 +14,7 @@ define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vst3i16: ;CHECK: vst3.16 %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } @@ -23,7 +23,7 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst3i32: ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } @@ -32,11 +32,11 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst3i32_update: ;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! - %A = load i32** %ptr + %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) - %tmp2 = getelementptr i32* %A, i32 6 + %tmp2 = getelementptr i32, i32* %A, i32 6 store i32* %tmp2, i32** %ptr ret void } @@ -45,7 +45,7 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst3f: ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } @@ -56,7 +56,7 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { ;This test runs at -O0 so do not check for specific register numbers. ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %B call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16) ret void } @@ -64,11 +64,11 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { define void @vst3i64_update(i64** %ptr, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vst3i64_update ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! - %A = load i64** %ptr + %A = load i64*, i64** %ptr %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %B call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) - %tmp2 = getelementptr i64* %A, i32 3 + %tmp2 = getelementptr i64, i64* %A, i32 3 store i64* %tmp2, i64** %ptr ret void } @@ -79,7 +79,7 @@ define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind { ;This test runs at -O0 so do not check for specific register numbers. ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]! ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] - %tmp1 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %B call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32) ret void } @@ -89,7 +89,7 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3.16 ;CHECK: vst3.16 %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ret void } @@ -99,11 +99,11 @@ define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vst3Qi16_update: ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! - %A = load i16** %ptr + %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) - %tmp2 = getelementptr i16* %A, i32 24 + %tmp2 = getelementptr i16, i16* %A, i32 24 store i16* %tmp2, i16** %ptr ret void } @@ -113,7 +113,7 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3.32 ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst3.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) ret void } @@ -123,7 +123,7 @@ define void @vst3Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3.32 ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst3.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll index 44c76b5ed189..c343c6c86959 100644 --- a/test/CodeGen/ARM/vst4.ll +++ b/test/CodeGen/ARM/vst4.ll @@ -4,7 +4,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst4i8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) ret void } @@ -13,10 +13,10 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { ;CHECK-LABEL: vst4i8_update: ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2 - %A = load i8** %ptr - %tmp1 = load <8 x i8>* %B + %A = load i8*, i8** %ptr + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16) - %tmp2 = getelementptr i8* %A, i32 %inc + %tmp2 = getelementptr i8, i8* %A, i32 %inc store i8* %tmp2, i8** %ptr ret void } @@ -26,7 +26,7 @@ define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16) ret void } @@ -36,7 +36,7 @@ define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32) ret void } @@ -45,7 +45,7 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst4f: ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst4.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } @@ -55,7 +55,7 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %B call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64) ret void } @@ -63,11 +63,11 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { define void @vst4i64_update(i64** %ptr, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vst4i64_update: ;CHECK: vst1.64 {d16, d17, d18, d19}, [r1]! - %A = load i64** %ptr + %A = load i64*, i64** %ptr %tmp0 = bitcast i64* %A to i8* - %tmp1 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %B call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) - %tmp2 = getelementptr i64* %A, i32 4 + %tmp2 = getelementptr i64, i64* %A, i32 4 store i64* %tmp2, i64** %ptr ret void } @@ -77,7 +77,7 @@ define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256] - %tmp1 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %B call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64) ret void } @@ -88,7 +88,7 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! ;CHECK: vst4.16 {d17, d19, d21, d23}, [r0] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst4.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ret void } @@ -98,7 +98,7 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4.32 ;CHECK: vst4.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst4.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) ret void } @@ -108,7 +108,7 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst4.32 ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } @@ -118,11 +118,11 @@ define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst4Qf_update: ;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]! ;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]! - %A = load float** %ptr + %A = load float*, float** %ptr %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) - %tmp2 = getelementptr float* %A, i32 16 + %tmp2 = getelementptr float, float* %A, i32 16 store float* %tmp2, float** %ptr ret void } diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 7dd6e7b439ea..a4575417bce5 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -4,7 +4,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1lanei8: ;Check the (default) alignment. ;CHECK: vst1.8 {d16[3]}, [r0] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B %tmp2 = extractelement <8 x i8> %tmp1, i32 3 store i8 %tmp2, i8* %A, align 8 ret void @@ -14,11 +14,11 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1lanei8_update: ;CHECK: vst1.8 {d16[3]}, [{{r[0-9]}}]! - %A = load i8** %ptr - %tmp1 = load <8 x i8>* %B + %A = load i8*, i8** %ptr + %tmp1 = load <8 x i8>, <8 x i8>* %B %tmp2 = extractelement <8 x i8> %tmp1, i32 3 store i8 %tmp2, i8* %A, align 8 - %tmp3 = getelementptr i8* %A, i32 1 + %tmp3 = getelementptr i8, i8* %A, i32 1 store i8* %tmp3, i8** %ptr ret void } @@ -27,7 +27,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vst1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vst1.16 {d16[2]}, [r0:16] - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B %tmp2 = extractelement <4 x i16> %tmp1, i32 2 store i16 %tmp2, i16* %A, align 8 ret void @@ -37,7 +37,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst1lanei32: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vst1.32 {d16[1]}, [r0:32] - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B %tmp2 = extractelement <2 x i32> %tmp1, i32 1 store i32 %tmp2, i32* %A, align 8 ret void @@ -46,7 +46,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst1lanef: ;CHECK: vst1.32 {d16[1]}, [r0:32] - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B %tmp2 = extractelement <2 x float> %tmp1, i32 1 store float %tmp2, float* %A ret void @@ -56,7 +56,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vst1laneQi8: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.8 {d17[1]}, [r0] - %tmp1 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %B %tmp2 = extractelement <16 x i8> %tmp1, i32 9 store i8 %tmp2, i8* %A, align 8 ret void @@ -65,7 +65,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vst1laneQi16: ;CHECK: vst1.16 {d17[1]}, [r0:16] - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B %tmp2 = extractelement <8 x i16> %tmp1, i32 5 store i16 %tmp2, i16* %A, align 8 ret void @@ -75,7 +75,7 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst1laneQi32: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.32 {d17[1]}, [r0:32] - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 store i32 %tmp2, i32* %A, align 8 ret void @@ -86,11 +86,11 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst1laneQi32_update: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.32 {d17[1]}, [r1:32]! - %A = load i32** %ptr - %tmp1 = load <4 x i32>* %B + %A = load i32*, i32** %ptr + %tmp1 = load <4 x i32>, <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 store i32 %tmp2, i32* %A, align 8 - %tmp3 = getelementptr i32* %A, i32 1 + %tmp3 = getelementptr i32, i32* %A, i32 1 store i32* %tmp3, i32** %ptr ret void } @@ -99,7 +99,7 @@ define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst1laneQf: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.32 {d17[1]}, [r0] - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B %tmp2 = extractelement <4 x float> %tmp1, i32 3 store float %tmp2, float* %A ret void @@ -109,7 +109,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst2lanei8: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) ret void } @@ -119,7 +119,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) ret void } @@ -128,11 +128,11 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind { ;CHECK-LABEL: vst2lanei16_update: ;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2 - %A = load i16** %ptr + %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2) - %tmp2 = getelementptr i16* %A, i32 %inc + %tmp2 = getelementptr i16, i16* %A, i32 %inc store i16* %tmp2, i16** %ptr ret void } @@ -141,7 +141,7 @@ define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst2lanei32: ;CHECK: vst2.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) ret void } @@ -150,7 +150,7 @@ define void @vst2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst2lanef: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) ret void } @@ -160,7 +160,7 @@ define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the (default) alignment. ;CHECK: vst2.16 {d17[1], d19[1]}, [r0] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) ret void } @@ -170,7 +170,7 @@ define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) ret void } @@ -179,7 +179,7 @@ define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst2laneQf: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1) ret void } @@ -196,7 +196,7 @@ declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst3lanei8: ;CHECK: vst3.8 - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ret void } @@ -206,7 +206,7 @@ define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;Check the (default) alignment value. VST3 does not support alignment. ;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) ret void } @@ -215,7 +215,7 @@ define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst3lanei32: ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) ret void } @@ -224,7 +224,7 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst3lanef: ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) ret void } @@ -234,7 +234,7 @@ define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the (default) alignment value. VST3 does not support alignment. ;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8) ret void } @@ -243,7 +243,7 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst3laneQi32: ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) ret void } @@ -252,11 +252,11 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst3laneQi32_update: ;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]! - %A = load i32** %ptr + %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) - %tmp2 = getelementptr i32* %A, i32 3 + %tmp2 = getelementptr i32, i32* %A, i32 3 store i32* %tmp2, i32** %ptr ret void } @@ -265,7 +265,7 @@ define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst3laneQf: ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) ret void } @@ -284,7 +284,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] - %tmp1 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) ret void } @@ -293,10 +293,10 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst4lanei8_update: ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! - %A = load i8** %ptr - %tmp1 = load <8 x i8>* %B + %A = load i8*, i8** %ptr + %tmp1 = load <8 x i8>, <8 x i8>* %B call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) - %tmp2 = getelementptr i8* %A, i32 4 + %tmp2 = getelementptr i8, i8* %A, i32 4 store i8* %tmp2, i8** %ptr ret void } @@ -305,7 +305,7 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vst4lanei16: ;CHECK: vst4.16 %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B call void @llvm.arm.neon.vst4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) ret void } @@ -315,7 +315,7 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %B call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16) ret void } @@ -324,7 +324,7 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst4lanef: ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %B call void @llvm.arm.neon.vst4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) ret void } @@ -334,7 +334,7 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] %tmp0 = bitcast i16* %A to i8* - %tmp1 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %B call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16) ret void } @@ -344,7 +344,7 @@ define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check the (default) alignment. ;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] %tmp0 = bitcast i32* %A to i8* - %tmp1 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %B call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) ret void } @@ -353,7 +353,7 @@ define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst4laneQf: ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %B call void @llvm.arm.neon.vst4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) ret void } diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll index d1a094b92755..75fb7d493a59 100644 --- a/test/CodeGen/ARM/vsub.ll +++ b/test/CodeGen/ARM/vsub.ll @@ -3,8 +3,8 @@ define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsubi8: ;CHECK: vsub.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sub <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsubi16: ;CHECK: vsub.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sub <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsubi32: ;CHECK: vsub.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sub <2 x i32> %tmp1, %tmp2 ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: vsubi64: ;CHECK: vsub.i64 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = sub <1 x i64> %tmp1, %tmp2 ret <1 x i64> %tmp3 } @@ -39,8 +39,8 @@ define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vsubf32: ;CHECK: vsub.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = fsub <2 x float> %tmp1, %tmp2 ret <2 x float> %tmp3 } @@ -48,8 +48,8 @@ define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vsubQi8: ;CHECK: vsub.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = sub <16 x i8> %tmp1, %tmp2 ret <16 x i8> %tmp3 } @@ -57,8 +57,8 @@ define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vsubQi16: ;CHECK: vsub.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = sub <8 x i16> %tmp1, %tmp2 ret <8 x i16> %tmp3 } @@ -66,8 +66,8 @@ define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vsubQi32: ;CHECK: vsub.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = sub <4 x i32> %tmp1, %tmp2 ret <4 x i32> %tmp3 } @@ -75,8 +75,8 @@ define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vsubQi64: ;CHECK: vsub.i64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = sub <2 x i64> %tmp1, %tmp2 ret <2 x i64> %tmp3 } @@ -84,8 +84,8 @@ define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vsubQf32: ;CHECK: vsub.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = fsub <4 x float> %tmp1, %tmp2 ret <4 x float> %tmp3 } @@ -120,8 +120,8 @@ define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind { define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrsubhni16: ;CHECK: vrsubhn.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i8> %tmp3 } @@ -129,8 +129,8 @@ define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vrsubhni32: ;CHECK: vrsubhn.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i16> %tmp3 } @@ -138,8 +138,8 @@ define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vrsubhni64: ;CHECK: vrsubhn.i64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i32> %tmp3 } @@ -151,8 +151,8 @@ declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind re define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsubls8: ;CHECK: vsubl.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sub <8 x i16> %tmp3, %tmp4 @@ -162,8 +162,8 @@ define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsubls16: ;CHECK: vsubl.s16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sub <4 x i32> %tmp3, %tmp4 @@ -173,8 +173,8 @@ define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsubls32: ;CHECK: vsubl.s32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sub <2 x i64> %tmp3, %tmp4 @@ -184,8 +184,8 @@ define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsublu8: ;CHECK: vsubl.u8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sub <8 x i16> %tmp3, %tmp4 @@ -195,8 +195,8 @@ define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsublu16: ;CHECK: vsubl.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sub <4 x i32> %tmp3, %tmp4 @@ -206,8 +206,8 @@ define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsublu32: ;CHECK: vsubl.u32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sub <2 x i64> %tmp3, %tmp4 @@ -217,8 +217,8 @@ define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsubws8: ;CHECK: vsubw.s8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp2 to <8 x i16> %tmp4 = sub <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -227,8 +227,8 @@ define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsubws16: ;CHECK: vsubw.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp2 to <4 x i32> %tmp4 = sub <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -237,8 +237,8 @@ define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsubws32: ;CHECK: vsubw.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp2 to <2 x i64> %tmp4 = sub <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -247,8 +247,8 @@ define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsubwu8: ;CHECK: vsubw.u8 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp2 to <8 x i16> %tmp4 = sub <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -257,8 +257,8 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsubwu16: ;CHECK: vsubw.u16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = sub <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -267,8 +267,8 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsubwu32: ;CHECK: vsubw.u32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = sub <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 diff --git a/test/CodeGen/ARM/vtbl.ll b/test/CodeGen/ARM/vtbl.ll index 32258a30da96..e4dd572a41b4 100644 --- a/test/CodeGen/ARM/vtbl.ll +++ b/test/CodeGen/ARM/vtbl.ll @@ -7,8 +7,8 @@ define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vtbl1: ;CHECK: vtbl.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -16,8 +16,8 @@ define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind { ;CHECK-LABEL: vtbl2: ;CHECK: vtbl.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x2_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 %tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4) @@ -27,8 +27,8 @@ define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind { define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind { ;CHECK-LABEL: vtbl3: ;CHECK: vtbl.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x3_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x3_t, %struct.__neon_int8x8x3_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2 @@ -39,8 +39,8 @@ define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind { define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind { ;CHECK-LABEL: vtbl4: ;CHECK: vtbl.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x4_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 @@ -52,9 +52,9 @@ define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind { define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vtbx1: ;CHECK: vtbx.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) ret <8 x i8> %tmp4 } @@ -62,11 +62,11 @@ define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vtbx2: ;CHECK: vtbx.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x2_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x2_t, %struct.__neon_int8x8x2_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 - %tmp5 = load <8 x i8>* %C + %tmp5 = load <8 x i8>, <8 x i8>* %C %tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5) ret <8 x i8> %tmp6 } @@ -74,12 +74,12 @@ define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vtbx3: ;CHECK: vtbx.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x3_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x3_t, %struct.__neon_int8x8x3_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2 - %tmp6 = load <8 x i8>* %C + %tmp6 = load <8 x i8>, <8 x i8>* %C %tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6) ret <8 x i8> %tmp7 } @@ -87,13 +87,13 @@ define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vtbx4: ;CHECK: vtbx.8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x4_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3 - %tmp7 = load <8 x i8>* %C + %tmp7 = load <8 x i8>, <8 x i8>* %C %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7) ret <8 x i8> %tmp8 } diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll index cdae7f8ec370..caa5becac1d9 100644 --- a/test/CodeGen/ARM/vtrn.ll +++ b/test/CodeGen/ARM/vtrn.ll @@ -4,8 +4,8 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vtrni8: ;CHECK: vtrn.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -16,8 +16,8 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vtrni16: ;CHECK: vtrn.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -28,8 +28,8 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vtrni32: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.i32 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2> %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3> %tmp5 = add <2 x i32> %tmp3, %tmp4 @@ -40,8 +40,8 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vtrnf: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.f32 - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2> %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3> %tmp5 = fadd <2 x float> %tmp3, %tmp4 @@ -52,8 +52,8 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vtrnQi8: ;CHECK: vtrn.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 @@ -64,8 +64,8 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vtrnQi16: ;CHECK: vtrn.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -76,8 +76,8 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vtrnQi32: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -88,8 +88,8 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vtrnQf: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp5 = fadd <4 x float> %tmp3, %tmp4 @@ -102,8 +102,8 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vtrni8_undef: ;CHECK: vtrn.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -114,8 +114,8 @@ define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vtrnQi16_undef: ;CHECK: vtrn.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef> %tmp5 = add <8 x i16> %tmp3, %tmp4 diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll index 832be6c3daf1..7a7306a26593 100644 --- a/test/CodeGen/ARM/vuzp.ll +++ b/test/CodeGen/ARM/vuzp.ll @@ -4,8 +4,8 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vuzpi8: ;CHECK: vuzp.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -16,8 +16,8 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vuzpi16: ;CHECK: vuzp.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -30,8 +30,8 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vuzpQi8: ;CHECK: vuzp.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 @@ -42,8 +42,8 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vuzpQi16: ;CHECK: vuzp.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -54,8 +54,8 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vuzpQi32: ;CHECK: vuzp.32 ;CHECK-NEXT: vadd.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -66,8 +66,8 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vuzpQf: ;CHECK: vuzp.32 ;CHECK-NEXT: vadd.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp5 = fadd <4 x float> %tmp3, %tmp4 @@ -80,8 +80,8 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vuzpi8_undef: ;CHECK: vuzp.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -92,8 +92,8 @@ define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vuzpQi16_undef: ;CHECK: vuzp.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll index f74dc62599cf..a1b5b4549ac2 100644 --- a/test/CodeGen/ARM/vzip.ll +++ b/test/CodeGen/ARM/vzip.ll @@ -4,8 +4,8 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vzipi8: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -16,8 +16,8 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vzipi16: ;CHECK: vzip.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -30,8 +30,8 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vzipQi8: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 @@ -42,8 +42,8 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vzipQi16: ;CHECK: vzip.16 ;CHECK-NEXT: vadd.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -54,8 +54,8 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vzipQi32: ;CHECK: vzip.32 ;CHECK-NEXT: vadd.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -66,8 +66,8 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vzipQf: ;CHECK: vzip.32 ;CHECK-NEXT: vadd.f32 - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp5 = fadd <4 x float> %tmp3, %tmp4 @@ -80,8 +80,8 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vzipi8_undef: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -92,8 +92,8 @@ define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vzipQi8_undef: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 diff --git a/test/CodeGen/ARM/warn-stack.ll b/test/CodeGen/ARM/warn-stack.ll index 90a3e1f798ed..474dc1dfb447 100644 --- a/test/CodeGen/ARM/warn-stack.ll +++ b/test/CodeGen/ARM/warn-stack.ll @@ -7,7 +7,7 @@ define void @nowarn() nounwind ssp { entry: %buffer = alloca [12 x i8], align 1 - %arraydecay = getelementptr inbounds [12 x i8]* %buffer, i64 0, i64 0 + %arraydecay = getelementptr inbounds [12 x i8], [12 x i8]* %buffer, i64 0, i64 0 call void @doit(i8* %arraydecay) nounwind ret void } @@ -16,7 +16,7 @@ entry: define void @warn() nounwind ssp { entry: %buffer = alloca [80 x i8], align 1 - %arraydecay = getelementptr inbounds [80 x i8]* %buffer, i64 0, i64 0 + %arraydecay = getelementptr inbounds [80 x i8], [80 x i8]* %buffer, i64 0, i64 0 call void @doit(i8* %arraydecay) nounwind ret void } diff --git a/test/CodeGen/ARM/weak2.ll b/test/CodeGen/ARM/weak2.ll index 82ab90efb118..a2911d780fef 100644 --- a/test/CodeGen/ARM/weak2.ll +++ b/test/CodeGen/ARM/weak2.ll @@ -8,7 +8,7 @@ entry: br i1 %tmp5, label %UnifiedReturnBlock, label %cond_true8 cond_true8: ; preds = %entry - %tmp10 = tail call i32 (...)* %t.0( ) ; <i32> [#uses=1] + %tmp10 = tail call i32 (...) %t.0( ) ; <i32> [#uses=1] ret i32 %tmp10 UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll b/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll index 7ecd25283108..4b274d2aedc2 100644 --- a/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll +++ b/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll @@ -7,11 +7,11 @@ declare i8* @llvm.returnaddress(i32) define i32* @wrong-t2stmia-size-reduction(i32* %addr, i32 %val0) minsize { store i32 %val0, i32* %addr - %addr1 = getelementptr i32* %addr, i32 1 + %addr1 = getelementptr i32, i32* %addr, i32 1 %lr = call i8* @llvm.returnaddress(i32 0) %lr32 = ptrtoint i8* %lr to i32 store i32 %lr32, i32* %addr1 - %addr2 = getelementptr i32* %addr1, i32 1 + %addr2 = getelementptr i32, i32* %addr1, i32 1 ret i32* %addr2 } diff --git a/test/CodeGen/ARM/zextload_demandedbits.ll b/test/CodeGen/ARM/zextload_demandedbits.ll index 6b6ce97ed9e2..ba7393c2dc20 100644 --- a/test/CodeGen/ARM/zextload_demandedbits.ll +++ b/test/CodeGen/ARM/zextload_demandedbits.ll @@ -14,8 +14,8 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; CHECK: pop define void @quux(%struct.eggs* %arg) { bb: - %tmp1 = getelementptr inbounds %struct.eggs* %arg, i32 0, i32 1 - %0 = load i16* %tmp1, align 2 + %tmp1 = getelementptr inbounds %struct.eggs, %struct.eggs* %arg, i32 0, i32 1 + %0 = load i16, i16* %tmp1, align 2 %tobool = icmp eq i16 %0, 0 br i1 %tobool, label %bb16, label %bb3 @@ -24,7 +24,7 @@ bb3: ; preds = %bb %tmp5 = ptrtoint i16* %tmp1 to i32 %tmp6 = shl i32 %tmp5, 20 %tmp7 = ashr exact i32 %tmp6, 20 - %tmp14 = getelementptr inbounds %struct.barney* undef, i32 %tmp7 + %tmp14 = getelementptr inbounds %struct.barney, %struct.barney* undef, i32 %tmp7 %tmp15 = tail call i32 @widget(%struct.barney* %tmp14, i8* %tmp4, i32 %tmp7) br label %bb16 |