diff options
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir | 39 | ||||
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll | 52 | ||||
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-isel.ll | 39 | ||||
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir | 174 | ||||
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 36 | ||||
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 30 | ||||
-rw-r--r-- | test/CodeGen/ARM/atomic-op.ll | 15 |
7 files changed, 385 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 6a1da0dfe85f..0e3ef479bc3c 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -45,6 +45,8 @@ define void @test_select_s32() { ret void } define void @test_select_ptr() { ret void } + define void @test_br() { ret void } + define void @test_soft_fp_double() #0 { ret void } attributes #0 = { "target-features"="+vfp2,-neonfp" } @@ -1173,6 +1175,43 @@ body: | ; CHECK: BX_RET 14, _, implicit %r0 ... --- +name: test_br +# CHECK-LABEL: name: test_br +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } +body: | + bb.0: + ; CHECK: bb.0 + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: %r0 + + %0(s1) = COPY %r0 + ; CHECK: [[COND:%[0-9]+]] = COPY %r0 + + G_BRCOND %0(s1), %bb.1 + ; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr + ; CHECK: Bcc %bb.1, 0, %cpsr + G_BR %bb.2 + ; CHECK: B %bb.2 + + bb.1: + ; CHECK: bb.1 + successors: %bb.2(0x80000000) + + G_BR %bb.2 + ; CHECK: B %bb.2 + + bb.2: + ; CHECK: bb.2 + + BX_RET 14, _ + ; CHECK: BX_RET 14, _ +... +--- name: test_soft_fp_double # CHECK-LABEL: name: test_soft_fp_double legalized: true diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll b/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll index c778caacd0f4..c2e8c5abca4e 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll @@ -87,3 +87,55 @@ define arm_aapcscc i32 @test_urem_i32(i32 %x, i32 %y) { %r = urem i32 %x, %y ret i32 %r } + +define arm_aapcscc i16 @test_srem_i16(i16 %x, i16 %y) { +; CHECK-LABEL: test_srem_i16: +; CHECK-DAG: sxth r0, r0 +; CHECK-DAG: sxth r1, r1 +; HWDIV: sdiv [[Q:r[0-9]+]], r0, r1 +; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1 +; HWDIV: sub r0, r0, [[P]] +; SOFT-AEABI: blx __aeabi_idivmod +; SOFT-DEFAULT: blx __modsi3 + %r = srem i16 %x, %y + ret i16 %r +} + +define arm_aapcscc i16 @test_urem_i16(i16 %x, i16 %y) { +; CHECK-LABEL: test_urem_i16: +; CHECK-DAG: uxth r0, r0 +; CHECK-DAG: uxth r1, r1 +; HWDIV: udiv [[Q:r[0-9]+]], r0, r1 +; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1 +; HWDIV: sub r0, r0, [[P]] +; SOFT-AEABI: blx __aeabi_uidivmod +; SOFT-DEFAULT: blx __umodsi3 + %r = urem i16 %x, %y + ret i16 %r +} + +define arm_aapcscc i8 @test_srem_i8(i8 %x, i8 %y) { +; CHECK-LABEL: test_srem_i8: +; CHECK-DAG: sxtb r0, r0 +; CHECK-DAG: sxtb r1, r1 +; HWDIV: sdiv [[Q:r[0-9]+]], r0, r1 +; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1 +; HWDIV: sub r0, r0, [[P]] +; SOFT-AEABI: blx __aeabi_idivmod +; SOFT-DEFAULT: blx __modsi3 + %r = srem i8 %x, %y + ret i8 %r +} + +define arm_aapcscc i8 @test_urem_i8(i8 %x, i8 %y) { +; CHECK-LABEL: test_urem_i8: +; CHECK-DAG: uxtb r0, r0 +; CHECK-DAG: uxtb r1, r1 +; HWDIV: udiv [[Q:r[0-9]+]], r0, r1 +; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1 +; HWDIV: sub r0, r0, [[P]] +; SOFT-AEABI: blx __aeabi_uidivmod +; SOFT-DEFAULT: blx __umodsi3 + %r = urem i8 %x, %y + ret i8 %r +} diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/test/CodeGen/ARM/GlobalISel/arm-isel.ll index 4c498ff6ca9b..419bcf71c106 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-isel.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-isel.ll @@ -420,3 +420,42 @@ entry: %r = select i1 %cond, i32* %a, i32* %b ret i32* %r } + +define arm_aapcscc void @test_br() { +; CHECK-LABEL: test_br +; CHECK: [[LABEL:.L[[:alnum:]_]+]]: +; CHECK: b [[LABEL]] +entry: + br label %infinite + +infinite: + br label %infinite +} + +declare arm_aapcscc void @brcond1() +declare arm_aapcscc void @brcond2() + +define arm_aapcscc void @test_brcond(i32 %n) { +; CHECK-LABEL: test_brcond +; CHECK: cmp r0 +; CHECK-NEXT: movgt [[RCMP:r[0-9]+]], #1 +; CHECK: tst [[RCMP]], #1 +; CHECK-NEXT: bne [[FALSE:.L[[:alnum:]_]+]] +; CHECK: blx brcond1 +; CHECK: [[FALSE]]: +; CHECK: blx brcond2 +entry: + %cmp = icmp sgt i32 %n, 0 + br i1 %cmp, label %if.true, label %if.false + +if.true: + call arm_aapcscc void @brcond1() + br label %if.end + +if.false: + call arm_aapcscc void @brcond2() + br label %if.end + +if.end: + ret void +} diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir index 9a0877846fc3..f436c3774c86 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir @@ -14,6 +14,12 @@ define void @test_srem_i32() { ret void } define void @test_urem_i32() { ret void } + + define void @test_srem_i16() { ret void } + define void @test_urem_i16() { ret void } + + define void @test_srem_i8() { ret void } + define void @test_urem_i8() { ret void } ... --- name: test_sdiv_i32 @@ -323,3 +329,171 @@ body: | %r0 = COPY %2(s32) BX_RET 14, _, implicit %r0 ... +--- +name: test_srem_i16 +# CHECK-LABEL: name: test_srem_i16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1 + ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s16) + ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s16) + %0(s16) = COPY %r0 + %1(s16) = COPY %r1 + ; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_SREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1 + ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SREM + ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]] + ; SOFT-NOT: G_SREM + %2(s16) = G_SREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s16) + BX_RET 14, _, implicit %r0 +... +--- +name: test_urem_i16 +# CHECK-LABEL: name: test_urem_i16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1 + ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s16) + ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s16) + %0(s16) = COPY %r0 + %1(s16) = COPY %r1 + ; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_UREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1 + ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UREM + ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]] + ; SOFT-NOT: G_UREM + %2(s16) = G_UREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s16) + BX_RET 14, _, implicit %r0 +... +--- +name: test_srem_i8 +# CHECK-LABEL: name: test_srem_i8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1 + ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s8) + ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s8) + %0(s8) = COPY %r0 + %1(s8) = COPY %r1 + ; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_SREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1 + ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SREM + ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]] + ; SOFT-NOT: G_SREM + %2(s8) = G_SREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s8) + BX_RET 14, _, implicit %r0 +... +--- +name: test_urem_i8 +# CHECK-LABEL: name: test_urem_i8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1 + ; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s8) + ; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s8) + %0(s8) = COPY %r0 + %1(s8) = COPY %r1 + ; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_UREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1 + ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UREM + ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]] + ; SOFT-NOT: G_UREM + %2(s8) = G_UREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s8) + BX_RET 14, _, implicit %r0 +... diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir index 4575341dfc29..616f29d3b068 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -42,6 +42,8 @@ define void @test_select_s32() { ret void } define void @test_select_ptr() { ret void } + define void @test_brcond() { ret void } + define void @test_fadd_s32() #0 { ret void } define void @test_fadd_s64() #0 { ret void } @@ -863,6 +865,40 @@ body: | BX_RET 14, _, implicit %r0 ... --- +name: test_brcond +# CHECK-LABEL: name: test_brcond +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 + G_BRCOND %2(s1), %bb.1 + ; G_BRCOND with s1 is legal, so we should find it unchanged in the output + ; CHECK: G_BRCOND {{%[0-9]+}}(s1), %bb.1 + G_BR %bb.2 + + bb.1: + %r0 = COPY %1(s32) + BX_RET 14, _, implicit %r0 + + bb.2: + %r0 = COPY %0(s32) + BX_RET 14, _, implicit %r0 + +... +--- name: test_fadd_s32 # CHECK-LABEL: name: test_fadd_s32 legalized: false diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index ffca431d96ea..638c6e620926 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -40,6 +40,8 @@ define void @test_select_s32() { ret void } + define void @test_br() { ret void } + define void @test_fadd_s32() #0 { ret void } define void @test_fadd_s64() #0 { ret void } @@ -830,6 +832,34 @@ body: | ... --- +name: test_br +# CHECK-LABEL: name: test_br +legalized: true +regBankSelected: false +# CHECK: regBankSelected: true +selected: false +registers: + - { id: 0, class: _ } +# CHECK: { id: 0, class: gprb, preferred-register: '' } +# Check that we map the condition of the G_BRCOND into the GPR. +# For the G_BR, there are no registers to map, but make sure we don't crash. +body: | + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: %r0 + + %0(s1) = COPY %r0 + G_BRCOND %0(s1), %bb.1 + G_BR %bb.2 + + bb.1: + BX_RET 14, _ + + bb.2: + BX_RET 14, _ + +... +--- name: test_fadd_s32 # CHECK-LABEL: name: test_fadd_s32 legalized: true diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll index 23c4ccea4604..644a7fbf8d9a 100644 --- a/test/CodeGen/ARM/atomic-op.ll +++ b/test/CodeGen/ARM/atomic-op.ll @@ -26,6 +26,7 @@ entry: store i32 3855, i32* %xort store i32 4, i32* %temp %tmp = load i32, i32* %temp + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: add ; CHECK: strex @@ -35,6 +36,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %0 = atomicrmw add i32* %val1, i32 %tmp monotonic store i32 %0, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: sub ; CHECK: strex @@ -44,6 +46,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %1 = atomicrmw sub i32* %val2, i32 30 monotonic store i32 %1, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: add ; CHECK: strex @@ -53,6 +56,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %2 = atomicrmw add i32* %val2, i32 1 monotonic store i32 %2, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: sub ; CHECK: strex @@ -62,6 +66,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %3 = atomicrmw sub i32* %val2, i32 1 monotonic store i32 %3, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: and ; CHECK: strex @@ -71,6 +76,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %4 = atomicrmw and i32* %andt, i32 4080 monotonic store i32 %4, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: or ; CHECK: strex @@ -80,6 +86,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %5 = atomicrmw or i32* %ort, i32 4080 monotonic store i32 %5, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: eor ; CHECK: strex @@ -89,6 +96,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %6 = atomicrmw xor i32* %xort, i32 4080 monotonic store i32 %6, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex @@ -98,6 +106,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %7 = atomicrmw min i32* %val2, i32 16 monotonic store i32 %7, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() %neg = sub i32 0, 1 ; CHECK: ldrex ; CHECK: cmp @@ -108,6 +117,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %8 = atomicrmw min i32* %val2, i32 %neg monotonic store i32 %8, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex @@ -117,6 +127,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %9 = atomicrmw max i32* %val2, i32 1 monotonic store i32 %9, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex @@ -126,6 +137,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %10 = atomicrmw max i32* %val2, i32 0 monotonic store i32 %10, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex @@ -135,6 +147,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %11 = atomicrmw umin i32* %val2, i32 16 monotonic store i32 %11, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() %uneg = sub i32 0, 1 ; CHECK: ldrex ; CHECK: cmp @@ -145,6 +158,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic store i32 %12, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex @@ -154,6 +168,7 @@ entry: ; CHECK-BAREMETAL-NOT: __sync %13 = atomicrmw umax i32* %val2, i32 1 monotonic store i32 %13, i32* %old + call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"() ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex |