diff options
Diffstat (limited to 'test/CodeGen/ARM')
19 files changed, 3129 insertions, 63 deletions
diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index 9dcfe5007c00..ed5255bfbebd 100644 --- a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -6,23 +6,23 @@ ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}}Volatile -; CHECK-NOT: ord SU -; CHECK: ord SU(3): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(3): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile -; CHECK-NOT: ord SU -; CHECK: ord SU(2): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(2): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: Successors: ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}} -; CHECK-NOT: ord SU -; CHECK: ord SU(3): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(3): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3){{.*}}LDR{{.*}} -; CHECK-NOT: ord SU -; CHECK: ord SU(2): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(2): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir index 111375ece51b..6c8bc7123a1a 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir @@ -10,6 +10,46 @@ define void @test_icmp_sge_s32() { ret void } define void @test_icmp_slt_s32() { ret void } define void @test_icmp_sle_s32() { ret void } + + define void @test_fcmp_true_s32() #0 { ret void } + define void @test_fcmp_false_s32() #0 { ret void } + + define void @test_fcmp_oeq_s32() #0 { ret void } + define void @test_fcmp_ogt_s32() #0 { ret void } + define void @test_fcmp_oge_s32() #0 { ret void } + define void @test_fcmp_olt_s32() #0 { ret void } + define void @test_fcmp_ole_s32() #0 { ret void } + define void @test_fcmp_ord_s32() #0 { ret void } + define void @test_fcmp_ugt_s32() #0 { ret void } + define void @test_fcmp_uge_s32() #0 { ret void } + define void @test_fcmp_ult_s32() #0 { ret void } + define void @test_fcmp_ule_s32() #0 { ret void } + define void @test_fcmp_une_s32() #0 { ret void } + define void @test_fcmp_uno_s32() #0 { ret void } + + define void @test_fcmp_one_s32() #0 { ret void } + define void @test_fcmp_ueq_s32() #0 { ret void } + + define void @test_fcmp_true_s64() #0 { ret void } + define void @test_fcmp_false_s64() #0 { ret void } + + define void @test_fcmp_oeq_s64() #0 { ret void } + define void @test_fcmp_ogt_s64() #0 { ret void } + define void @test_fcmp_oge_s64() #0 { ret void } + define void @test_fcmp_olt_s64() #0 { ret void } + define void @test_fcmp_ole_s64() #0 { ret void } + define void @test_fcmp_ord_s64() #0 { ret void } + define void @test_fcmp_ugt_s64() #0 { ret void } + define void @test_fcmp_uge_s64() #0 { ret void } + define void @test_fcmp_ult_s64() #0 { ret void } + define void @test_fcmp_ule_s64() #0 { ret void } + define void @test_fcmp_une_s64() #0 { ret void } + define void @test_fcmp_uno_s64() #0 { ret void } + + define void @test_fcmp_one_s64() #0 { ret void } + define void @test_fcmp_ueq_s64() #0 { ret void } + + attributes #0 = { "target-features"="+vfp2" } ... --- name: test_icmp_eq_s32 @@ -35,8 +75,8 @@ body: | %2(s1) = G_ICMP intpred(eq), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -71,8 +111,8 @@ body: | %2(s1) = G_ICMP intpred(ne), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -107,8 +147,8 @@ body: | %2(s1) = G_ICMP intpred(ugt), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -143,8 +183,8 @@ body: | %2(s1) = G_ICMP intpred(uge), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 2, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 2, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -179,8 +219,8 @@ body: | %2(s1) = G_ICMP intpred(ult), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 3, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 3, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -215,8 +255,8 @@ body: | %2(s1) = G_ICMP intpred(ule), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -251,8 +291,8 @@ body: | %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -287,8 +327,8 @@ body: | %2(s1) = G_ICMP intpred(sge), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -323,8 +363,8 @@ body: | %2(s1) = G_ICMP intpred(slt), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ @@ -359,8 +399,1180 @@ body: | %2(s1) = G_ICMP intpred(sle), %0(s32), %1 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr - ; CHECK: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr + ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_true_s32 +# CHECK-LABEL: name: test_fcmp_true_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + %1(s32) = COPY %s1 + + %2(s1) = G_FCMP floatpred(true), %0(s32), %1 + ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _ + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_false_s32 +# CHECK-LABEL: name: test_fcmp_false_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + %1(s32) = COPY %s1 + + %2(s1) = G_FCMP floatpred(false), %0(s32), %1 + ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _ + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oeq_s32 +# CHECK-LABEL: name: test_fcmp_oeq_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ogt_s32 +# CHECK-LABEL: name: test_fcmp_ogt_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oge_s32 +# CHECK-LABEL: name: test_fcmp_oge_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(oge), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_olt_s32 +# CHECK-LABEL: name: test_fcmp_olt_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(olt), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ole_s32 +# CHECK-LABEL: name: test_fcmp_ole_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(ole), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ord_s32 +# CHECK-LABEL: name: test_fcmp_ord_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(ord), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ugt_s32 +# CHECK-LABEL: name: test_fcmp_ugt_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uge_s32 +# CHECK-LABEL: name: test_fcmp_uge_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(uge), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ult_s32 +# CHECK-LABEL: name: test_fcmp_ult_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(ult), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ule_s32 +# CHECK-LABEL: name: test_fcmp_ule_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(ule), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_une_s32 +# CHECK-LABEL: name: test_fcmp_une_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(une), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uno_s32 +# CHECK-LABEL: name: test_fcmp_uno_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(uno), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_one_s32 +# CHECK-LABEL: name: test_fcmp_one_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(one), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ueq_s32 +# CHECK-LABEL: name: test_fcmp_ueq_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0 + + %1(s32) = COPY %s1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1 + + %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr + ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_true_s64 +# CHECK-LABEL: name: test_fcmp_true_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + %1(s64) = COPY %d1 + + %2(s1) = G_FCMP floatpred(true), %0(s64), %1 + ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _ + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_false_s64 +# CHECK-LABEL: name: test_fcmp_false_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + %1(s64) = COPY %d1 + + %2(s1) = G_FCMP floatpred(false), %0(s64), %1 + ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _ + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oeq_s64 +# CHECK-LABEL: name: test_fcmp_oeq_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ogt_s64 +# CHECK-LABEL: name: test_fcmp_ogt_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oge_s64 +# CHECK-LABEL: name: test_fcmp_oge_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(oge), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_olt_s64 +# CHECK-LABEL: name: test_fcmp_olt_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(olt), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ole_s64 +# CHECK-LABEL: name: test_fcmp_ole_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(ole), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ord_s64 +# CHECK-LABEL: name: test_fcmp_ord_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(ord), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ugt_s64 +# CHECK-LABEL: name: test_fcmp_ugt_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uge_s64 +# CHECK-LABEL: name: test_fcmp_uge_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(uge), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ult_s64 +# CHECK-LABEL: name: test_fcmp_ult_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(ult), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ule_s64 +# CHECK-LABEL: name: test_fcmp_ule_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(ule), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_une_s64 +# CHECK-LABEL: name: test_fcmp_une_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(une), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uno_s64 +# CHECK-LABEL: name: test_fcmp_uno_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(uno), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_one_s64 +# CHECK-LABEL: name: test_fcmp_one_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(one), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr + + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ + + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[RET]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ueq_s64 +# CHECK-LABEL: name: test_fcmp_ueq_s64 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: fprb } + - { id: 1, class: fprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0 + + %1(s64) = COPY %d1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1 + + %2(s1) = G_FCMP floatpred(ueq), %0(s64), %1 + ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _ + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr + ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv + ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr %3(s32) = G_ZEXT %2(s1) ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _ diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll b/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll index 7d021fdb43dd..98b39e444ac7 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll @@ -49,3 +49,33 @@ define arm_aapcscc double @test_add_double(double %x, double %y) { %r = fadd double %x, %y ret double %r } + +define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) { +; CHECK-LABEL: test_cmp_float_ogt +; HARD: vcmp.f32 +; HARD: vmrs APSR_nzcv, fpscr +; HARD-NEXT: movgt +; SOFT-AEABI: blx __aeabi_fcmpgt +; SOFT-DEFAULT: blx __gtsf2 +entry: + %v = fcmp ogt float %x, %y + %r = zext i1 %v to i32 + ret i32 %r +} + +define arm_aapcs_vfpcc i32 @test_cmp_float_one(float %x, float %y) { +; CHECK-LABEL: test_cmp_float_one +; HARD: vcmp.f32 +; HARD: vmrs APSR_nzcv, fpscr +; HARD: movgt +; HARD-NOT: vcmp +; HARD: movmi +; SOFT-AEABI-DAG: blx __aeabi_fcmpgt +; SOFT-AEABI-DAG: blx __aeabi_fcmplt +; SOFT-DEFAULT-DAG: blx __gtsf2 +; SOFT-DEFAULT-DAG: blx __ltsf2 +entry: + %v = fcmp one float %x, %y + %r = zext i1 %v to i32 + ret i32 %r +} diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir index c93e7fa0ec56..9a0877846fc3 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir @@ -36,6 +36,7 @@ body: | %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; HWDIV: [[R:%[0-9]+]](s32) = G_SDIV [[X]], [[Y]] + ; SOFT-NOT: G_SDIV ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] @@ -44,6 +45,7 @@ body: | ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SDIV %2(s32) = G_SDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) @@ -70,6 +72,7 @@ body: | %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; HWDIV: [[R:%[0-9]+]](s32) = G_UDIV [[X]], [[Y]] + ; SOFT-NOT: G_UDIV ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] @@ -78,6 +81,7 @@ body: | ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UDIV %2(s32) = G_UDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) @@ -106,6 +110,7 @@ body: | %0(s16) = COPY %r0 %1(s16) = COPY %r1 ; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_SDIV ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] @@ -114,7 +119,9 @@ body: | ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SDIV ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]] + ; SOFT-NOT: G_SDIV %2(s16) = G_SDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s16) @@ -143,6 +150,7 @@ body: | %0(s16) = COPY %r0 %1(s16) = COPY %r1 ; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_UDIV ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] @@ -151,7 +159,9 @@ body: | ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UDIV ; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]] + ; SOFT-NOT: G_UDIV %2(s16) = G_UDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s16) @@ -180,6 +190,7 @@ body: | %0(s8) = COPY %r0 %1(s8) = COPY %r1 ; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_SDIV ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] @@ -188,7 +199,9 @@ body: | ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SDIV ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]] + ; SOFT-NOT: G_SDIV %2(s8) = G_SDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s8) @@ -217,6 +230,7 @@ body: | %0(s8) = COPY %r0 %1(s8) = COPY %r1 ; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_UDIV ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] @@ -225,7 +239,9 @@ body: | ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UDIV ; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]] + ; SOFT-NOT: G_UDIV %2(s8) = G_UDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s8) @@ -254,6 +270,7 @@ body: | ; HWDIV: [[Q:%[0-9]+]](s32) = G_SDIV [[X]], [[Y]] ; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]] ; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]] + ; SOFT-NOT: G_SREM ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] @@ -262,6 +279,7 @@ body: | ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SREM %2(s32) = G_SREM %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) @@ -290,6 +308,7 @@ body: | ; HWDIV: [[Q:%[0-9]+]](s32) = G_UDIV [[X]], [[Y]] ; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]] ; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]] + ; SOFT-NOT: G_UREM ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] @@ -298,6 +317,7 @@ body: | ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UREM %2(s32) = G_UREM %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir index 803135ba595e..cb61f95b10ce 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir @@ -10,6 +10,44 @@ define void @test_fadd_float() { ret void } define void @test_fadd_double() { ret void } + + define void @test_fcmp_true_s32() { ret void } + define void @test_fcmp_false_s32() { ret void } + + define void @test_fcmp_oeq_s32() { ret void } + define void @test_fcmp_ogt_s32() { ret void } + define void @test_fcmp_oge_s32() { ret void } + define void @test_fcmp_olt_s32() { ret void } + define void @test_fcmp_ole_s32() { ret void } + define void @test_fcmp_ord_s32() { ret void } + define void @test_fcmp_ugt_s32() { ret void } + define void @test_fcmp_uge_s32() { ret void } + define void @test_fcmp_ult_s32() { ret void } + define void @test_fcmp_ule_s32() { ret void } + define void @test_fcmp_une_s32() { ret void } + define void @test_fcmp_uno_s32() { ret void } + + define void @test_fcmp_one_s32() { ret void } + define void @test_fcmp_ueq_s32() { ret void } + + define void @test_fcmp_true_s64() { ret void } + define void @test_fcmp_false_s64() { ret void } + + define void @test_fcmp_oeq_s64() { ret void } + define void @test_fcmp_ogt_s64() { ret void } + define void @test_fcmp_oge_s64() { ret void } + define void @test_fcmp_olt_s64() { ret void } + define void @test_fcmp_ole_s64() { ret void } + define void @test_fcmp_ord_s64() { ret void } + define void @test_fcmp_ugt_s64() { ret void } + define void @test_fcmp_uge_s64() { ret void } + define void @test_fcmp_ult_s64() { ret void } + define void @test_fcmp_ule_s64() { ret void } + define void @test_fcmp_une_s64() { ret void } + define void @test_fcmp_uno_s64() { ret void } + + define void @test_fcmp_one_s64() { ret void } + define void @test_fcmp_ueq_s64() { ret void } ... --- name: test_frem_float @@ -31,6 +69,7 @@ body: | ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 + ; CHECK-NOT: G_FREM ; CHECK: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] @@ -41,6 +80,7 @@ body: | ; SOFT: [[R:%[0-9]+]](s32) = COPY %r0 ; HARD: [[R:%[0-9]+]](s32) = COPY %s0 ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FREM %2(s32) = G_FREM %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) @@ -86,6 +126,7 @@ body: | ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]] %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) + ; CHECK-NOT: G_FREM ; CHECK: ADJCALLSTACKDOWN ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] @@ -96,6 +137,7 @@ body: | ; SOFT: BLX $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; HARD: BLX $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FREM %6(s64) = G_FREM %4, %5 %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) @@ -122,6 +164,7 @@ body: | ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 + ; CHECK-NOT: G_FPOW ; CHECK: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] @@ -132,6 +175,7 @@ body: | ; SOFT: [[R:%[0-9]+]](s32) = COPY %r0 ; HARD: [[R:%[0-9]+]](s32) = COPY %s0 ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FPOW %2(s32) = G_FPOW %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) @@ -177,6 +221,7 @@ body: | ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]] %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) + ; CHECK-NOT: G_FPOW ; CHECK: ADJCALLSTACKDOWN ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] @@ -187,6 +232,7 @@ body: | ; SOFT: BLX $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; HARD: BLX $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FPOW %6(s64) = G_FPOW %4, %5 %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) @@ -214,6 +260,7 @@ body: | %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; HARD: [[R:%[0-9]+]](s32) = G_FADD [[X]], [[Y]] + ; SOFT-NOT: G_FADD ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] @@ -221,6 +268,7 @@ body: | ; SOFT-DEFAULT: BLX $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[R:%[0-9]+]](s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FADD %2(s32) = G_FADD %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) @@ -261,6 +309,7 @@ body: | %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) ; HARD: [[R:%[0-9]+]](s64) = G_FADD [[X]], [[Y]] + ; SOFT-NOT: G_FADD ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] @@ -269,6 +318,7 @@ body: | ; SOFT-AEABI: BLX $__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT-DEFAULT: BLX $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FADD %6(s64) = G_FADD %4, %5 ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) @@ -276,3 +326,1565 @@ body: | %r1 = COPY %8(s32) BX_RET 14, _, implicit %r0, implicit %r1 ... +--- +name: test_fcmp_true_s32 +# CHECK-LABEL: name: test_fcmp_true_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(true), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 -1 + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_false_s32 +# CHECK-LABEL: name: test_fcmp_false_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(false), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oeq_s32 +# CHECK-LABEL: name: test_fcmp_oeq_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ogt_s32 +# CHECK-LABEL: name: test_fcmp_ogt_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oge_s32 +# CHECK-LABEL: name: test_fcmp_oge_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(oge), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_olt_s32 +# CHECK-LABEL: name: test_fcmp_olt_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(olt), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ole_s32 +# CHECK-LABEL: name: test_fcmp_ole_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ole), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ord_s32 +# CHECK-LABEL: name: test_fcmp_ord_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ord), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ugt_s32 +# CHECK-LABEL: name: test_fcmp_ugt_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uge_s32 +# CHECK-LABEL: name: test_fcmp_uge_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(uge), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ult_s32 +# CHECK-LABEL: name: test_fcmp_ult_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ult), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ule_s32 +# CHECK-LABEL: name: test_fcmp_ule_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ule), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_une_s32 +# CHECK-LABEL: name: test_fcmp_une_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(une), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uno_s32 +# CHECK-LABEL: name: test_fcmp_uno_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(uno), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_one_s32 +# CHECK-LABEL: name: test_fcmp_one_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(one), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R1:%[0-9]+]](s1) = G_TRUNC [[RET1]] + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R2:%[0-9]+]](s1) = G_TRUNC [[RET2]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] + ; SOFT-DAG: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]] + ; SOFT-DAG: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ueq_s32 +# CHECK-LABEL: name: test_fcmp_ueq_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R1:%[0-9]+]](s1) = G_TRUNC [[RET1]] + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R2:%[0-9]+]](s1) = G_TRUNC [[RET2]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] + ; SOFT-DAG: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]] + ; SOFT-DAG: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_true_s64 +# CHECK-LABEL: name: test_fcmp_true_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(true), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 -1 + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_false_s64 +# CHECK-LABEL: name: test_fcmp_false_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(false), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oeq_s64 +# CHECK-LABEL: name: test_fcmp_oeq_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(oeq), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ogt_s64 +# CHECK-LABEL: name: test_fcmp_ogt_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ogt), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oge_s64 +# CHECK-LABEL: name: test_fcmp_oge_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(oge), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_olt_s64 +# CHECK-LABEL: name: test_fcmp_olt_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(olt), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ole_s64 +# CHECK-LABEL: name: test_fcmp_ole_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ole), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ord_s64 +# CHECK-LABEL: name: test_fcmp_ord_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ord), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ugt_s64 +# CHECK-LABEL: name: test_fcmp_ugt_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ugt), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uge_s64 +# CHECK-LABEL: name: test_fcmp_uge_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(uge), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ult_s64 +# CHECK-LABEL: name: test_fcmp_ult_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ult), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ule_s64 +# CHECK-LABEL: name: test_fcmp_ule_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ule), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_une_s64 +# CHECK-LABEL: name: test_fcmp_une_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(une), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uno_s64 +# CHECK-LABEL: name: test_fcmp_uno_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(uno), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_one_s64 +# CHECK-LABEL: name: test_fcmp_one_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(one), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R1:%[0-9]+]](s1) = G_TRUNC [[RET1]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R2:%[0-9]+]](s1) = G_TRUNC [[RET2]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] + ; SOFT-DAG: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]] + ; SOFT-DAG: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ueq_s64 +# CHECK-LABEL: name: test_fcmp_ueq_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ueq), %4(s64), %5 + ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R1:%[0-9]+]](s1) = G_TRUNC [[RET1]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R2:%[0-9]+]](s1) = G_TRUNC [[RET2]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] + ; SOFT-DAG: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]] + ; SOFT-DAG: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir index bf759728c365..4575341dfc29 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -111,6 +111,7 @@ body: | %1(s8) = COPY %r1 %2(s8) = G_ADD %0, %1 ; G_ADD with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s8) @@ -136,6 +137,7 @@ body: | %1(s16) = COPY %r1 %2(s16) = G_ADD %0, %1 ; G_ADD with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s16) @@ -187,6 +189,7 @@ body: | %1(s8) = COPY %r1 %2(s8) = G_SUB %0, %1 ; G_SUB with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s8) @@ -212,6 +215,7 @@ body: | %1(s16) = COPY %r1 %2(s16) = G_SUB %0, %1 ; G_SUB with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s16) @@ -263,6 +267,7 @@ body: | %1(s8) = COPY %r1 %2(s8) = G_MUL %0, %1 ; G_MUL with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s8) @@ -288,6 +293,7 @@ body: | %1(s16) = COPY %r1 %2(s16) = G_MUL %0, %1 ; G_MUL with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s16) @@ -339,6 +345,7 @@ body: | %1(s8) = COPY %r1 %2(s8) = G_AND %0, %1 ; G_AND with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}(s8) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s8) = G_AND {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s8) @@ -364,6 +371,7 @@ body: | %1(s16) = COPY %r1 %2(s16) = G_AND %0, %1 ; G_AND with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}(s16) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s16) = G_AND {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s16) @@ -415,6 +423,7 @@ body: | %1(s8) = COPY %r1 %2(s8) = G_OR %0, %1 ; G_OR with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}(s8) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s8) = G_OR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s8) @@ -440,6 +449,7 @@ body: | %1(s16) = COPY %r1 %2(s16) = G_OR %0, %1 ; G_OR with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}(s16) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s16) = G_OR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s16) @@ -491,6 +501,7 @@ body: | %1(s8) = COPY %r1 %2(s8) = G_XOR %0, %1 ; G_XOR with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}(s8) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s8) = G_XOR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s8) @@ -516,6 +527,7 @@ body: | %1(s16) = COPY %r1 %2(s16) = G_XOR %0, %1 ; G_XOR with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}(s16) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}(s16) = G_XOR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s16) @@ -689,11 +701,32 @@ selected: false tracksRegLiveness: true registers: - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } body: | bb.0: %0(s32) = G_CONSTANT 42 ; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT 42 + %1(s16) = G_CONSTANT i16 21 + ; CHECK-NOT: G_CONSTANT i16 + ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 21 + ; CHECK: {{%[0-9]+}}(s16) = G_TRUNC [[EXT]](s32) + ; CHECK-NOT: G_CONSTANT i16 + + %2(s8) = G_CONSTANT i8 10 + ; CHECK-NOT: G_CONSTANT i8 + ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 10 + ; CHECK: {{%[0-9]+}}(s8) = G_TRUNC [[EXT]](s32) + ; CHECK-NOT: G_CONSTANT i8 + + %3(s1) = G_CONSTANT i1 1 + ; CHECK-NOT: G_CONSTANT i1 + ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 -1 + ; CHECK: {{%[0-9]+}}(s1) = G_TRUNC [[EXT]](s32) + ; CHECK-NOT: G_CONSTANT i1 + %r0 = COPY %0(s32) BX_RET 14, _, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index d3b93e488ef4..ffca431d96ea 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -35,6 +35,8 @@ define void @test_trunc_s32_16() { ret void } define void @test_icmp_eq_s32() { ret void } + define void @test_fcmp_one_s32() #0 { ret void } + define void @test_fcmp_ugt_s64() #0 { ret void } define void @test_select_s32() { ret void } @@ -743,6 +745,62 @@ body: | ... --- +name: test_fcmp_one_s32 +# CHECK-LABEL: name: test_fcmp_one_s32 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +# CHECK: - { id: 2, class: gprb, preferred-register: '' } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %s0, %s1 + + %0(s32) = COPY %s0 + %1(s32) = COPY %s1 + %2(s1) = G_FCMP floatpred(one), %0(s32), %1 + %3(s32) = G_ZEXT %2(s1) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_fcmp_ugt_s64 +# CHECK-LABEL: name: test_fcmp_ugt_s64 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } +# CHECK: - { id: 2, class: gprb, preferred-register: '' } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %d0, %d1 + + %0(s64) = COPY %d0 + %1(s64) = COPY %d1 + %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 + %3(s32) = G_ZEXT %2(s1) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- name: test_select_s32 # CHECK-LABEL: name: test_select_s32 legalized: true diff --git a/test/CodeGen/ARM/arguments-nosplit-double.ll b/test/CodeGen/ARM/arguments-nosplit-double.ll index 8e4dee45ddf2..bb3710842d34 100644 --- a/test/CodeGen/ARM/arguments-nosplit-double.ll +++ b/test/CodeGen/ARM/arguments-nosplit-double.ll @@ -8,5 +8,6 @@ define i32 @f(i64 %z, i32 %a, double %b) { ret i32 %tmp } +; CHECK-LABEL: f: ; CHECK-NOT: r3 diff --git a/test/CodeGen/ARM/arguments-nosplit-i64.ll b/test/CodeGen/ARM/arguments-nosplit-i64.ll index 4a08d0a0406a..02bdc6cc227a 100644 --- a/test/CodeGen/ARM/arguments-nosplit-i64.ll +++ b/test/CodeGen/ARM/arguments-nosplit-i64.ll @@ -8,5 +8,6 @@ define i32 @f(i64 %z, i32 %a, i64 %b) { ret i32 %tmp } +; CHECK-LABEL: f: ; CHECK-NOT: r3 diff --git a/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll index d54848a6bcf1..0ae2d5f6f2f2 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll @@ -13,13 +13,13 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 4 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=3 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=3 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=4 define i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize { %1 = load i32, i32* @a, align 4 diff --git a/test/CodeGen/ARM/cortex-a57-misched-ldm.ll b/test/CodeGen/ARM/cortex-a57-misched-ldm.ll index 9cb076651f5b..bc7a14b1028e 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-ldm.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-ldm.ll @@ -8,9 +8,9 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 3 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=3 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=3 define i32 @foo(i32* %a) nounwind optsize { diff --git a/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll index 774b0a907e39..67cddc14d047 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll @@ -10,7 +10,7 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 2 ; CHECK: Successors -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 define i32 @bar(i32 %v0, i32 %v1, i32 %v2, i32* %addr) { diff --git a/test/CodeGen/ARM/cortex-a57-misched-vfma.ll b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll index e234e179ed07..372b2e2f5dc9 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vfma.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll @@ -11,7 +11,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMULS common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMULS read-advanced latency to VMLAS = 0 ; CHECK-SAME: Latency=0 @@ -20,7 +20,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMLAS common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS read-advanced latency to the next VMLAS = 4 ; CHECK-SAME: Latency=4 @@ -28,7 +28,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float ; CHECK-FAST: VFMAS ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 @@ -50,7 +50,7 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMULfd common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; VMULfd read-advanced latency to VMLAfd = 0 ; CHECK-SAME: Latency=0 @@ -59,7 +59,7 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMLAfd common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAfd read-advanced latency to the next VMLAfd = 4 ; CHECK-SAME: Latency=4 @@ -67,7 +67,7 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; CHECK-FAST: VFMAfd ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAfd not-optimized latency to VMOVRRD = 9 ; CHECK-SAME: Latency=9 @@ -88,7 +88,7 @@ define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMULS common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMULS read-advanced latency to VMLSS = 0 ; CHECK-SAME: Latency=0 @@ -97,7 +97,7 @@ define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMLSS common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSS read-advanced latency to the next VMLSS = 4 ; CHECK-SAME: Latency=4 @@ -105,7 +105,7 @@ define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float ; CHECK-FAST: VFMSS ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 @@ -127,7 +127,7 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMULfd common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; VMULfd read-advanced latency to VMLSfd = 0 ; CHECK-SAME: Latency=0 @@ -136,7 +136,7 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMLSfd common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSfd read-advanced latency to the next VMLSfd = 4 ; CHECK-SAME: Latency=4 @@ -144,7 +144,7 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; CHECK-FAST: VFMSfd ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSfd not-optimized latency to VMOVRRD = 9 ; CHECK-SAME: Latency=9 @@ -165,7 +165,7 @@ define float @Test5(float %f1, float %f2, float %f3) { ; CHECK-FAST: VFNMS ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 @@ -184,7 +184,7 @@ define float @Test6(float %f1, float %f2, float %f3) { ; CHECK-FAST: VFNMA ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 diff --git a/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll index 6cfa823fb969..b5edcc304229 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll @@ -13,15 +13,15 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 6 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=1 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=6 define i32 @bar(i32* %iptr) minsize optsize { %1 = load double, double* @a, align 8 diff --git a/test/CodeGen/ARM/cortex-a57-misched-vldm.ll b/test/CodeGen/ARM/cortex-a57-misched-vldm.ll index 218b5b41a7e4..12c7b3270c3b 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vldm.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vldm.ll @@ -8,11 +8,11 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 6 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=6 define double @foo(double* %a) nounwind optsize { diff --git a/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll index af1c469d4443..05c498eee49f 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll @@ -9,7 +9,7 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 4 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 @a = global double 0.0, align 4 diff --git a/test/CodeGen/ARM/fence-singlethread.ll b/test/CodeGen/ARM/fence-singlethread.ll index ec032ccac423..536b6cc7c9d0 100644 --- a/test/CodeGen/ARM/fence-singlethread.ll +++ b/test/CodeGen/ARM/fence-singlethread.ll @@ -11,6 +11,6 @@ define void @fence_singlethread() { ; CHECK: @ COMPILER BARRIER ; CHECK-NOT: dmb - fence singlethread seq_cst + fence syncscope("singlethread") seq_cst ret void } diff --git a/test/CodeGen/ARM/ror.ll b/test/CodeGen/ARM/ror.ll new file mode 100644 index 000000000000..0f699a8dd29d --- /dev/null +++ b/test/CodeGen/ARM/ror.ll @@ -0,0 +1,33 @@ +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s + +; rotr (rotr x, 4), 6 -> rotr x, 10 -> ror r0, r0, #10 +define i32 @test1(i32 %x) nounwind readnone { +; CHECK-LABEL: test1: +; CHECK: ror r0, r0, #10 +; CHECK: bx lr +entry: + %high_part.i = shl i32 %x, 28 + %low_part.i = lshr i32 %x, 4 + %result.i = or i32 %high_part.i, %low_part.i + %high_part.i.1 = shl i32 %result.i, 26 + %low_part.i.2 = lshr i32 %result.i, 6 + %result.i.3 = or i32 %low_part.i.2, %high_part.i.1 + ret i32 %result.i.3 +} + +; the same vector test +define <2 x i32> @test2(<2 x i32> %x) nounwind readnone { +; CHECK-LABEL: test2: +; CHECK: ror r0, r0, #10 +; CHECK: ror r1, r1, #10 +; CHECK: bx lr +entry: + %high_part.i = shl <2 x i32> %x, <i32 28, i32 28> + %low_part.i = lshr <2 x i32> %x, <i32 4, i32 4> + %result.i = or <2 x i32> %high_part.i, %low_part.i + %high_part.i.1 = shl <2 x i32> %result.i, <i32 26, i32 26> + %low_part.i.2 = lshr <2 x i32> %result.i, <i32 6, i32 6> + %result.i.3 = or <2 x i32> %low_part.i.2, %high_part.i.1 + ret <2 x i32> %result.i.3 +} + diff --git a/test/CodeGen/ARM/scavenging.mir b/test/CodeGen/ARM/scavenging.mir new file mode 100644 index 000000000000..09040a3bd217 --- /dev/null +++ b/test/CodeGen/ARM/scavenging.mir @@ -0,0 +1,66 @@ +# RUN: llc -o - %s -mtriple=arm-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s +--- +# CHECK-LABEL: name: scavengebug0 +# Make sure we are not spilling/using a physreg used in the very last +# instruction of the scavenging range. +# CHECK-NOT: tSTRi {{.*}}%r0,{{.*}}%r0 +# CHECK-NOT: tSTRi {{.*}}%r1,{{.*}}%r1 +# CHECK-NOT: tSTRi {{.*}}%r2,{{.*}}%r2 +# CHECK-NOT: tSTRi {{.*}}%r3,{{.*}}%r3 +# CHECK-NOT: tSTRi {{.*}}%r4,{{.*}}%r4 +# CHECK-NOT: tSTRi {{.*}}%r5,{{.*}}%r5 +# CHECK-NOT: tSTRi {{.*}}%r6,{{.*}}%r6 +# CHECK-NOT: tSTRi {{.*}}%r7,{{.*}}%r7 +name: scavengebug0 +body: | + bb.0: + ; Bring up register pressure to force emergency spilling + %r0 = IMPLICIT_DEF + %r1 = IMPLICIT_DEF + %r2 = IMPLICIT_DEF + %r3 = IMPLICIT_DEF + %r4 = IMPLICIT_DEF + %r5 = IMPLICIT_DEF + %r6 = IMPLICIT_DEF + %r7 = IMPLICIT_DEF + + %0 : tgpr = IMPLICIT_DEF + %0 = tADDhirr %0, %sp, 14, _ + tSTRi %r0, %0, 0, 14, _ + + %1 : tgpr = IMPLICIT_DEF + %1 = tADDhirr %1, %sp, 14, _ + tSTRi %r1, %1, 0, 14, _ + + %2 : tgpr = IMPLICIT_DEF + %2 = tADDhirr %2, %sp, 14, _ + tSTRi %r2, %2, 0, 14, _ + + %3 : tgpr = IMPLICIT_DEF + %3 = tADDhirr %3, %sp, 14, _ + tSTRi %r3, %3, 0, 14, _ + + %4 : tgpr = IMPLICIT_DEF + %4 = tADDhirr %4, %sp, 14, _ + tSTRi %r4, %4, 0, 14, _ + + %5 : tgpr = IMPLICIT_DEF + %5 = tADDhirr %5, %sp, 14, _ + tSTRi %r5, %5, 0, 14, _ + + %6 : tgpr = IMPLICIT_DEF + %6 = tADDhirr %6, %sp, 14, _ + tSTRi %r6, %6, 0, 14, _ + + %7 : tgpr = IMPLICIT_DEF + %7 = tADDhirr %7, %sp, 14, _ + tSTRi %r7, %7, 0, 14, _ + + KILL %r0 + KILL %r1 + KILL %r2 + KILL %r3 + KILL %r4 + KILL %r5 + KILL %r6 + KILL %r7 |