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-rw-r--r--test/CodeGen/AVR/branch-relaxation.ll96
-rw-r--r--test/CodeGen/AVR/ctlz.ll5
-rw-r--r--test/CodeGen/AVR/cttz.ll4
-rw-r--r--test/CodeGen/AVR/frmidx-iterator-bug.ll33
-rw-r--r--test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll15
-rw-r--r--test/CodeGen/AVR/pseudo/ANDIWRdK.mir6
-rw-r--r--test/CodeGen/AVR/pseudo/COMWRd.mir2
-rw-r--r--test/CodeGen/AVR/pseudo/ORIWRdK.mir2
-rw-r--r--test/CodeGen/AVR/pseudo/SBCIWRdK.mir2
-rw-r--r--test/CodeGen/AVR/pseudo/SUBIWRdK.mir2
-rw-r--r--test/CodeGen/AVR/select-mbb-placement-bug.ll6
11 files changed, 159 insertions, 14 deletions
diff --git a/test/CodeGen/AVR/branch-relaxation.ll b/test/CodeGen/AVR/branch-relaxation.ll
new file mode 100644
index 000000000000..d6f07f653576
--- /dev/null
+++ b/test/CodeGen/AVR/branch-relaxation.ll
@@ -0,0 +1,96 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+; CHECKC-LABEL: relax_breq
+; CHECK: cpi r{{[0-9]+}}, 0
+; CHECK: brne LBB0_1
+; CHECK: rjmp LBB0_2
+; LBB0_1:
+
+define i8 @relax_breq(i1 %a) {
+entry-block:
+ br i1 %a, label %hello, label %finished
+
+hello:
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ br label %finished
+finished:
+ ret i8 3
+}
+
+; CHECKC-LABEL: no_relax_breq
+; CHECK: cpi r{{[0-9]+}}, 0
+; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]]
+; CHECK: nop
+; ...
+; LBB0_1:
+define i8 @no_relax_breq(i1 %a) {
+entry-block:
+ br i1 %a, label %hello, label %finished
+
+hello:
+ ; There are not enough NOPs to require relaxation.
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ call void asm sideeffect "nop", ""()
+ br label %finished
+finished:
+ ret i8 3
+}
+
diff --git a/test/CodeGen/AVR/ctlz.ll b/test/CodeGen/AVR/ctlz.ll
index 4f73e846b1f1..8659550baf90 100644
--- a/test/CodeGen/AVR/ctlz.ll
+++ b/test/CodeGen/AVR/ctlz.ll
@@ -10,7 +10,8 @@ declare i8 @llvm.ctlz.i8(i8)
; CHECK-LABEL: count_leading_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0
-; CHECK: breq LBB0_1
+; CHECK: brne LBB0_1
+; CHECK: rjmp LBB0_2
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: lsr {{.*}}[[SCRATCH]]
; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
@@ -43,6 +44,6 @@ declare i8 @llvm.ctlz.i8(i8)
; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
; CHECK: andi {{.*}}[[RESULT]], 15
; CHECK: ret
-; CHECK: LBB0_1:
+; CHECK: LBB0_2:
; CHECK: ldi {{.*}}[[RESULT]], 8
; CHECK: ret
diff --git a/test/CodeGen/AVR/cttz.ll b/test/CodeGen/AVR/cttz.ll
index 2501566275ea..02d36954f526 100644
--- a/test/CodeGen/AVR/cttz.ll
+++ b/test/CodeGen/AVR/cttz.ll
@@ -10,7 +10,7 @@ declare i8 @llvm.cttz.i8(i8)
; CHECK-LABEL: count_trailing_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0
-; CHECK: breq LBB0_1
+; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]]
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: dec {{.*}}[[SCRATCH]]
; CHECK: com {{.*}}[[RESULT]]
@@ -34,7 +34,7 @@ declare i8 @llvm.cttz.i8(i8)
; CHECK: andi {{.*}}[[SCRATCH]], 15
; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
; CHECK: ret
-; CHECK: LBB0_1:
+; CHECK: [[END_BB]]:
; CHECK: ldi {{.*}}[[SCRATCH]], 8
; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
; CHECK: ret
diff --git a/test/CodeGen/AVR/frmidx-iterator-bug.ll b/test/CodeGen/AVR/frmidx-iterator-bug.ll
new file mode 100644
index 000000000000..f9e2f0688faf
--- /dev/null
+++ b/test/CodeGen/AVR/frmidx-iterator-bug.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
+
+%str_slice = type { i8*, i16 }
+%Machine = type { i16, [0 x i8], i16, [0 x i8], [16 x i8], [0 x i8] }
+
+; CHECK-LABEL: step
+define void @step(%Machine*) {
+ ret void
+}
+
+; CHECK-LABEL: main
+define void @main() {
+start:
+ %machine = alloca %Machine, align 8
+ %v0 = bitcast %Machine* %machine to i8*
+ %v1 = getelementptr inbounds %Machine, %Machine* %machine, i16 0, i32 2
+ %v2 = load i16, i16* %v1, align 2
+ br label %bb2.i5
+
+bb2.i5:
+ %v18 = load volatile i8, i8* inttoptr (i16 77 to i8*), align 1
+ %v19 = icmp sgt i8 %v18, -1
+ br i1 %v19, label %bb2.i5, label %bb.exit6
+
+bb.exit6:
+ %v20 = load volatile i8, i8* inttoptr (i16 78 to i8*), align 2
+ br label %bb7
+
+bb7:
+ call void @step(%Machine* %machine)
+ br label %bb7
+}
+
diff --git a/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll b/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
new file mode 100644
index 000000000000..17ac29e2cdb8
--- /dev/null
+++ b/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mattr=lpm,lpmw < %s -march=avr | FileCheck %s
+
+declare void @callback(i16 zeroext)
+
+; CHECK-LABEL: foo
+define void @foo() {
+entry:
+ ; CHECK: ldi r{{[0-9]+}}, pm_lo8(callback)
+ ; CHECK-NEXT: ldi r{{[0-9]+}}, pm_hi8(callback)
+ call void @bar(i8 zeroext undef, void (i16)* @callback)
+ ret void
+}
+
+declare void @bar(i8 zeroext, void (i16)*)
+
diff --git a/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
index bcea4e6dfe27..4d58c85f4f23 100644
--- a/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_andiwrdrr
- ; CHECK: %r20 = ANDIRdK %r20, 175, implicit-def dead %sreg
- ; CHECK-NEXT: %r21 = ANDIRdK %r21, 250, implicit-def %sreg
+ ; CHECK: %r16 = ANDIRdK %r16, 175, implicit-def dead %sreg
+ ; CHECK-NEXT: %r17 = ANDIRdK %r17, 250, implicit-def %sreg
- %r21r20 = ANDIWRdK %r17r16, 64175, implicit-def %sreg
+ %r17r16 = ANDIWRdK %r17r16, 64175, implicit-def %sreg
...
diff --git a/test/CodeGen/AVR/pseudo/COMWRd.mir b/test/CodeGen/AVR/pseudo/COMWRd.mir
index 58ff7af7cb3c..db68a4082b73 100644
--- a/test/CodeGen/AVR/pseudo/COMWRd.mir
+++ b/test/CodeGen/AVR/pseudo/COMWRd.mir
@@ -20,5 +20,5 @@ body: |
; CHECK: %r14 = COMRd %r14, implicit-def dead %sreg
; CHECK-NEXT: %r15 = COMRd %r15, implicit-def %sreg
- %r15r14 = COMWRd %r9r8, implicit-def %sreg
+ %r15r14 = COMWRd %r15r14, implicit-def %sreg
...
diff --git a/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/test/CodeGen/AVR/pseudo/ORIWRdK.mir
index d77a6ba88488..eaa12842df42 100644
--- a/test/CodeGen/AVR/pseudo/ORIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/ORIWRdK.mir
@@ -20,5 +20,5 @@ body: |
; CHECK: %r20 = ORIRdK %r20, 175, implicit-def dead %sreg
; CHECK-NEXT: %r21 = ORIRdK %r21, 250, implicit-def %sreg
- %r21r20 = ORIWRdK %r17r16, 64175, implicit-def %sreg
+ %r21r20 = ORIWRdK %r21r20, 64175, implicit-def %sreg
...
diff --git a/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
index 644e6106ee79..a92f6951798b 100644
--- a/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
@@ -20,5 +20,5 @@ body: |
; CHECK: %r20 = SBCIRdK %r20, 175, implicit-def %sreg, implicit killed %sreg
; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
- %r21r20 = SBCIWRdK %r17r16, 64175, implicit-def %sreg, implicit %sreg
+ %r21r20 = SBCIWRdK %r21r20, 64175, implicit-def %sreg, implicit %sreg
...
diff --git a/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
index c7d88d7ab3f6..38ff880a5172 100644
--- a/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
@@ -20,5 +20,5 @@ body: |
; CHECK: %r20 = SUBIRdK %r20, 175, implicit-def %sreg
; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
- %r21r20 = SUBIWRdK %r17r16, 64175, implicit-def %sreg
+ %r21r20 = SUBIWRdK %r21r20, 64175, implicit-def %sreg
...
diff --git a/test/CodeGen/AVR/select-mbb-placement-bug.ll b/test/CodeGen/AVR/select-mbb-placement-bug.ll
index ca7ec1ab831c..aca9502b5dfb 100644
--- a/test/CodeGen/AVR/select-mbb-placement-bug.ll
+++ b/test/CodeGen/AVR/select-mbb-placement-bug.ll
@@ -8,9 +8,9 @@ define internal fastcc void @loopy() {
;
; https://github.com/avr-rust/rust/issues/49
-; CHECK: LBB0_1:
-; CHECK: LBB0_2:
-; CHECK-NOT: LBB0_3:
+; CHECK: LBB0_{{[0-9]+}}:
+; CHECK: LBB0_{{[0-9]+}}:
+; CHECK-NOT: LBB0_{{[0-9]+}}:
start:
br label %bb7.preheader
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-05 00:38:25 +0000