summaryrefslogtreecommitdiff
path: root/test/CodeGen/MIR
diff options
context:
space:
mode:
Diffstat (limited to 'test/CodeGen/MIR')
-rw-r--r--test/CodeGen/MIR/AArch64/atomic-memoperands.mir4
-rw-r--r--test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir19
-rw-r--r--test/CodeGen/MIR/AArch64/target-memoperands.mir22
-rw-r--r--test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir20
-rw-r--r--test/CodeGen/MIR/AMDGPU/syncscopes.mir98
-rw-r--r--test/CodeGen/MIR/AMDGPU/target-flags.mir29
-rw-r--r--test/CodeGen/MIR/Generic/runPass.mir2
-rw-r--r--test/CodeGen/MIR/Hexagon/target-flags.mir36
-rw-r--r--test/CodeGen/MIR/X86/tied-physical-regs-match.mir22
9 files changed, 240 insertions, 12 deletions
diff --git a/test/CodeGen/MIR/AArch64/atomic-memoperands.mir b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
index 1fe42a731488..1c81f580bee5 100644
--- a/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
+++ b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
@@ -14,7 +14,7 @@
# CHECK: %3(s16) = G_LOAD %0(p0) :: (load acquire 2)
# CHECK: G_STORE %3(s16), %0(p0) :: (store release 2)
# CHECK: G_STORE %2(s32), %0(p0) :: (store acq_rel 4)
-# CHECK: G_STORE %1(s64), %0(p0) :: (store singlethread seq_cst 8)
+# CHECK: G_STORE %1(s64), %0(p0) :: (store syncscope("singlethread") seq_cst 8)
name: atomic_memoperands
body: |
bb.0:
@@ -25,6 +25,6 @@ body: |
%3:_(s16) = G_LOAD %0(p0) :: (load acquire 2)
G_STORE %3(s16), %0(p0) :: (store release 2)
G_STORE %2(s32), %0(p0) :: (store acq_rel 4)
- G_STORE %1(s64), %0(p0) :: (store singlethread seq_cst 8)
+ G_STORE %1(s64), %0(p0) :: (store syncscope("singlethread") seq_cst 8)
RET_ReallyLR
...
diff --git a/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir b/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir
new file mode 100644
index 000000000000..731d7165b9df
--- /dev/null
+++ b/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir
@@ -0,0 +1,19 @@
+# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+ define void @target_memoperands_error() {
+ ret void
+ }
+
+...
+---
+name: target_memoperands_error
+body: |
+ bb.0:
+
+ %0:_(p0) = COPY %x0
+ ; CHECK: [[@LINE+1]]:35: use of undefined target MMO flag 'aarch64-invalid'
+ %1:_(s64) = G_LOAD %0(p0) :: ("aarch64-invalid" load 8)
+ RET_ReallyLR
+...
diff --git a/test/CodeGen/MIR/AArch64/target-memoperands.mir b/test/CodeGen/MIR/AArch64/target-memoperands.mir
new file mode 100644
index 000000000000..f853b551e098
--- /dev/null
+++ b/test/CodeGen/MIR/AArch64/target-memoperands.mir
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
+
+--- |
+
+ define void @target_memoperands() {
+ ret void
+ }
+
+...
+---
+# CHECK-LABEL: name: target_memoperands
+# CHECK: %1(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
+# CHECK: G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8)
+name: target_memoperands
+body: |
+ bb.0:
+
+ %0:_(p0) = COPY %x0
+ %1:_(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
+ G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8)
+ RET_ReallyLR
+...
diff --git a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
index 7cef01c9d12d..c0251232fd5c 100644
--- a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
+++ b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
@@ -171,8 +171,8 @@ body: |
# CHECK-LABEL: name: add_f32_1.0_multi_f16_use
# CHECK: %13 = V_MOV_B32_e32 1065353216, implicit %exec
-# CHECK: %14 = V_ADD_F16_e32 %13, killed %11, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 killed %13, killed %12, implicit %exec
+# CHECK: %14 = V_ADD_F16_e32 killed %11, %13, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 killed %12, killed %13, implicit %exec
name: add_f32_1.0_multi_f16_use
@@ -307,8 +307,8 @@ body: |
# CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
# CHECK: %14 = V_MOV_B32_e32 1065353216, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 %14, %11, implicit %exec
-# CHECK: %16 = V_ADD_F16_e32 %14, %12, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 %11, %14, implicit %exec
+# CHECK: %16 = V_ADD_F16_e32 %12, %14, implicit %exec
# CHECK: %17 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
name: add_f32_1.0_one_f32_use_multi_f16_use
@@ -514,8 +514,8 @@ body: |
# CHECK-LABEL: name: add_f16_1.0_multi_f32_use
# CHECK: %13 = V_MOV_B32_e32 15360, implicit %exec
-# CHECK: %14 = V_ADD_F32_e32 %13, %11, implicit %exec
-# CHECK: %15 = V_ADD_F32_e32 %13, %12, implicit %exec
+# CHECK: %14 = V_ADD_F32_e32 %11, %13, implicit %exec
+# CHECK: %15 = V_ADD_F32_e32 %12, %13, implicit %exec
name: add_f16_1.0_multi_f32_use
alignment: 0
@@ -581,8 +581,8 @@ body: |
# CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
# CHECK: %13 = V_MOV_B32_e32 80886784, implicit %exec
-# CHECK: %14 = V_ADD_F16_e32 %13, %11, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 %13, %12, implicit %exec
+# CHECK: %14 = V_ADD_F16_e32 %11, %13, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 %12, %13, implicit %exec
name: add_f16_1.0_other_high_bits_multi_f16_use
alignment: 0
@@ -648,8 +648,8 @@ body: |
# CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
# CHECK: %13 = V_MOV_B32_e32 305413120, implicit %exec
-# CHECK: %14 = V_ADD_F32_e32 %13, %11, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 %13, %12, implicit %exec
+# CHECK: %14 = V_ADD_F32_e32 %11, %13, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 %12, %13, implicit %exec
name: add_f16_1.0_other_high_bits_use_f16_f32
alignment: 0
exposesReturnsTwice: false
diff --git a/test/CodeGen/MIR/AMDGPU/syncscopes.mir b/test/CodeGen/MIR/AMDGPU/syncscopes.mir
new file mode 100644
index 000000000000..83506257d8bf
--- /dev/null
+++ b/test/CodeGen/MIR/AMDGPU/syncscopes.mir
@@ -0,0 +1,98 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -run-pass=none %s -o - | FileCheck --check-prefix=GCN %s
+
+--- |
+ ; ModuleID = '<stdin>'
+ source_filename = "<stdin>"
+ target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+ target triple = "amdgcn-amd-amdhsa"
+
+ define void @syncscopes(i32 %agent, i32 addrspace(4)* %agent_out, i32 %workgroup, i32 addrspace(4)* %workgroup_out, i32 %wavefront, i32 addrspace(4)* %wavefront_out) #0 {
+ entry:
+ store atomic i32 %agent, i32 addrspace(4)* %agent_out syncscope("agent") seq_cst, align 4
+ store atomic i32 %workgroup, i32 addrspace(4)* %workgroup_out syncscope("workgroup") seq_cst, align 4
+ store atomic i32 %wavefront, i32 addrspace(4)* %wavefront_out syncscope("wavefront") seq_cst, align 4
+ ret void
+ }
+
+ ; Function Attrs: convergent nounwind
+ declare { i1, i64 } @llvm.amdgcn.if(i1) #1
+
+ ; Function Attrs: convergent nounwind
+ declare { i1, i64 } @llvm.amdgcn.else(i64) #1
+
+ ; Function Attrs: convergent nounwind readnone
+ declare i64 @llvm.amdgcn.break(i64) #2
+
+ ; Function Attrs: convergent nounwind readnone
+ declare i64 @llvm.amdgcn.if.break(i1, i64) #2
+
+ ; Function Attrs: convergent nounwind readnone
+ declare i64 @llvm.amdgcn.else.break(i64, i64) #2
+
+ ; Function Attrs: convergent nounwind
+ declare i1 @llvm.amdgcn.loop(i64) #1
+
+ ; Function Attrs: convergent nounwind
+ declare void @llvm.amdgcn.end.cf(i64) #1
+
+ attributes #0 = { "target-cpu"="gfx803" }
+ attributes #1 = { convergent nounwind }
+ attributes #2 = { convergent nounwind readnone }
+
+# GCN-LABEL: name: syncscopes
+# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
+# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
+# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
+...
+---
+name: syncscopes
+alignment: 0
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+liveins:
+ - { reg: '%sgpr4_sgpr5' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+body: |
+ bb.0.entry:
+ liveins: %sgpr4_sgpr5
+
+ S_WAITCNT 0
+ %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM %sgpr4_sgpr5, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ %sgpr6 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
+ %sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM %sgpr4_sgpr5, 24, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ %sgpr7 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 16, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
+ %sgpr8 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 32, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
+ S_WAITCNT 127
+ %vgpr0 = V_MOV_B32_e32 %sgpr0, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr0_sgpr1
+ %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 40, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ %vgpr1 = V_MOV_B32_e32 killed %sgpr1, implicit %exec, implicit killed %sgpr0_sgpr1, implicit %sgpr0_sgpr1, implicit %exec
+ %vgpr2 = V_MOV_B32_e32 killed %sgpr6, implicit %exec, implicit %exec
+ FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
+ S_WAITCNT 112
+ %vgpr0 = V_MOV_B32_e32 %sgpr2, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr2_sgpr3
+ %vgpr1 = V_MOV_B32_e32 killed %sgpr3, implicit %exec, implicit killed %sgpr2_sgpr3, implicit %sgpr2_sgpr3, implicit %exec
+ %vgpr2 = V_MOV_B32_e32 killed %sgpr7, implicit %exec, implicit %exec
+ FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
+ S_WAITCNT 112
+ %vgpr0 = V_MOV_B32_e32 %sgpr4, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr4_sgpr5
+ %vgpr1 = V_MOV_B32_e32 killed %sgpr5, implicit %exec, implicit killed %sgpr4_sgpr5, implicit %sgpr4_sgpr5, implicit %exec
+ %vgpr2 = V_MOV_B32_e32 killed %sgpr8, implicit %exec, implicit %exec
+ FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
+ S_ENDPGM
+
+...
diff --git a/test/CodeGen/MIR/AMDGPU/target-flags.mir b/test/CodeGen/MIR/AMDGPU/target-flags.mir
new file mode 100644
index 000000000000..7d288dd1b045
--- /dev/null
+++ b/test/CodeGen/MIR/AMDGPU/target-flags.mir
@@ -0,0 +1,29 @@
+# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s
+--- |
+ define amdgpu_kernel void @flags() {
+ ret void
+ }
+
+ declare void @foo()
+...
+---
+
+# CHECK: SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
+# CHECK: %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+
+name: flags
+liveins:
+ - { reg: '%sgpr0_sgpr1' }
+frameInfo:
+ maxAlignment: 8
+registers:
+ - { id: 0, class: sreg_64, preferred-register: '' }
+ - { id: 1, class: sreg_64, preferred-register: '' }
+body: |
+ bb.0:
+ liveins: %sgpr0_sgpr1
+ %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
+ %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+
+ S_ENDPGM
+...
diff --git a/test/CodeGen/MIR/Generic/runPass.mir b/test/CodeGen/MIR/Generic/runPass.mir
index 33380d4c6bb4..54c1dd221bdb 100644
--- a/test/CodeGen/MIR/Generic/runPass.mir
+++ b/test/CodeGen/MIR/Generic/runPass.mir
@@ -1,5 +1,6 @@
# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s | FileCheck %s
# RUN: llc -run-pass=regallocbasic -debug-pass=Arguments -o - %s | FileCheck %s
+# RUN: llc -run-pass=regallocfast -debug-pass=Arguments -o - %s | FileCheck %s
# Check that passes are initialized correctly, so that it's possible to
# use -run-pass.
@@ -7,6 +8,7 @@
---
# CHECK: name: foo
name: foo
+tracksRegLiveness: true
body: |
bb.0:
...
diff --git a/test/CodeGen/MIR/Hexagon/target-flags.mir b/test/CodeGen/MIR/Hexagon/target-flags.mir
new file mode 100644
index 000000000000..656e0a6ea859
--- /dev/null
+++ b/test/CodeGen/MIR/Hexagon/target-flags.mir
@@ -0,0 +1,36 @@
+# RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s
+---
+name: fred
+
+body: |
+ bb.0:
+
+ ; CHECK: target-flags(hexagon-pcrel)
+ %r0 = A2_tfrsi target-flags (hexagon-pcrel) 0
+ ; CHECK: target-flags(hexagon-got)
+ %r0 = A2_tfrsi target-flags (hexagon-got) 0
+ ; CHECK: target-flags(hexagon-lo16)
+ %r0 = A2_tfrsi target-flags (hexagon-lo16) 0
+ ; CHECK: target-flags(hexagon-hi16)
+ %r0 = A2_tfrsi target-flags (hexagon-hi16) 0
+ ; CHECK: target-flags(hexagon-gprel)
+ %r0 = A2_tfrsi target-flags (hexagon-gprel) 0
+ ; CHECK: target-flags(hexagon-gdgot)
+ %r0 = A2_tfrsi target-flags (hexagon-gdgot) 0
+ ; CHECK: target-flags(hexagon-gdplt)
+ %r0 = A2_tfrsi target-flags (hexagon-gdplt) 0
+ ; CHECK: target-flags(hexagon-ie)
+ %r0 = A2_tfrsi target-flags (hexagon-ie) 0
+ ; CHECK: target-flags(hexagon-iegot)
+ %r0 = A2_tfrsi target-flags (hexagon-iegot) 0
+ ; CHECK: target-flags(hexagon-tprel)
+ %r0 = A2_tfrsi target-flags (hexagon-tprel) 0
+
+ ; CHECK: target-flags(hexagon-ext)
+ %r0 = A2_tfrsi target-flags (hexagon-ext) 0
+ ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
+ %r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
+ ; CHECK: target-flags(hexagon-ie, hexagon-ext)
+ %r0 = A2_tfrsi target-flags (hexagon-ie,hexagon-ext) 0
+...
+
diff --git a/test/CodeGen/MIR/X86/tied-physical-regs-match.mir b/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
new file mode 100644
index 000000000000..1ddf649f76a7
--- /dev/null
+++ b/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
@@ -0,0 +1,22 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that the Machine Verifier detects tied physical registers
+# that doesn't match.
+
+--- |
+
+ define i32 @foo() {
+ entry:
+ ret i32 0
+ }
+
+...
+---
+name: foo
+body: |
+ bb.0.entry:
+ liveins: %rdi
+
+ ; CHECK: Tied physical registers must match.
+ %rbx = AND64rm killed %rdx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags
+ RETQ %rbx
+...
generated by cgit v1.3 (git 2.53.0) at 2026-07-30 20:50:23 +0000