diff options
Diffstat (limited to 'test/CodeGen/Mips')
63 files changed, 3238 insertions, 124 deletions
diff --git a/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll deleted file mode 100644 index 994e19af4f87..000000000000 --- a/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc -O0 -march=mips -asm-verbose < %s | FileCheck %s -; Check that DEBUG_VALUE comments come through on a variety of targets. - -define i32 @main() nounwind ssp { -entry: -; CHECK: DEBUG_VALUE - call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 - ret i32 0, !dbg !10 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone - -!llvm.dbg.sp = !{!0} - -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 0} -!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!9 = metadata !{i32 3, i32 11, metadata !8, null} -!10 = metadata !{i32 4, i32 2, metadata !8, null} - diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll index 261fe9db1732..38d7b7e25592 100644 --- a/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -1,6 +1,11 @@ -; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s -check-prefix=STATIC-O32 -; RUN: llc < %s -march=mips -relocation-model=pic | FileCheck %s -check-prefix=PIC-O32 -; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=PIC-N64 +; RUN: llc < %s -march=mips -relocation-model=static | \ +; RUN: FileCheck %s -check-prefix=STATIC-O32 +; RUN: llc < %s -march=mips -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefix=PIC-O32 +; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 | \ +; RUN: FileCheck %s -check-prefix=N64 +; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips64 | \ +; RUN: FileCheck %s -check-prefix=N64 define i32 @main() nounwind readnone { entry: @@ -17,12 +22,12 @@ entry: ; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]]) ; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]] ; PIC-O32: jr $[[R5]] -; PIC-N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3 -; PIC-N64: ld $[[R1:[0-9]+]], %got_page($JTI0_0) -; PIC-N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]] -; PIC-N64: ld $[[R4:[0-9]+]], %got_ofst($JTI0_0)($[[R2]]) -; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] -; PIC-N64: jr $[[R5]] +; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3 +; N64: ld $[[R1:[0-9]+]], %got_page($JTI0_0) +; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]] +; N64: ld $[[R4:[0-9]+]], %got_ofst($JTI0_0)($[[R2]]) +; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] +; N64: jr $[[R5]] switch i32 %0, label %bb4 [ i32 0, label %bb5 i32 1, label %bb1 @@ -58,10 +63,10 @@ bb5: ; preds = %entry ; PIC-O32: .gpword ; PIC-O32: .gpword ; PIC-O32: .gpword -; PIC-N64: .align 3 -; PIC-N64: $JTI0_0: -; PIC-N64: .gpdword -; PIC-N64: .gpdword -; PIC-N64: .gpdword -; PIC-N64: .gpdword +; N64: .align 3 +; N64: $JTI0_0: +; N64: .gpdword +; N64: .gpdword +; N64: .gpdword +; N64: .gpdword diff --git a/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll b/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll new file mode 100644 index 000000000000..9d4daee696db --- /dev/null +++ b/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s + +@.str = private unnamed_addr constant [7 x i8] c"hello\0A\00", align 1 + +define void @t(i8* %ptr) { +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %ptr, i8* getelementptr inbounds ([7 x i8]* @.str, i64 0, i64 0), i64 7, i32 1, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/Mips/DbgValueOtherTargets.test b/test/CodeGen/Mips/DbgValueOtherTargets.test new file mode 100644 index 000000000000..da20e7ef5224 --- /dev/null +++ b/test/CodeGen/Mips/DbgValueOtherTargets.test @@ -0,0 +1 @@ +RUN: llc -O0 -march=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/Mips/addi.ll b/test/CodeGen/Mips/addi.ll new file mode 100644 index 000000000000..8f70a469c44f --- /dev/null +++ b/test/CodeGen/Mips/addi.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=16 + +@i = global i32 6, align 4 +@j = global i32 12, align 4 +@k = global i32 15, align 4 +@l = global i32 20, align 4 +@.str = private unnamed_addr constant [13 x i8] c"%i %i %i %i\0A\00", align 1 + +define void @foo() nounwind { +entry: + %0 = load i32* @i, align 4 + %add = add nsw i32 %0, 5 + store i32 %add, i32* @i, align 4 + %1 = load i32* @j, align 4 + %sub = sub nsw i32 %1, 5 + store i32 %sub, i32* @j, align 4 + %2 = load i32* @k, align 4 + %add1 = add nsw i32 %2, 10000 + store i32 %add1, i32* @k, align 4 + %3 = load i32* @l, align 4 + %sub2 = sub nsw i32 %3, 10000 + store i32 %sub2, i32* @l, align 4 +; 16: addiu ${{[0-9]+}}, 5 # 16 bit inst +; 16: addiu ${{[0-9]+}}, -5 # 16 bit inst +; 16: addiu ${{[0-9]+}}, 10000 +; 16: addiu ${{[0-9]+}}, -10000 + ret void +} + + diff --git a/test/CodeGen/Mips/addressing-mode.ll b/test/CodeGen/Mips/addressing-mode.ll new file mode 100644 index 000000000000..ea76dde82dc3 --- /dev/null +++ b/test/CodeGen/Mips/addressing-mode.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +@g0 = common global i32 0, align 4 +@g1 = common global i32 0, align 4 + +; Check that LSR doesn't choose a solution with a formula "reg + 4*reg". +; +; CHECK: $BB0_2: +; CHECK-NOT: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 + +define i32 @f0(i32 %n, i32 %m, [256 x i32]* nocapture %a, [256 x i32]* nocapture %b) nounwind readonly { +entry: + br label %for.cond1.preheader + +for.cond1.preheader: + %s.022 = phi i32 [ 0, %entry ], [ %add7, %for.inc9 ] + %i.021 = phi i32 [ 0, %entry ], [ %add10, %for.inc9 ] + br label %for.body3 + +for.body3: + %s.120 = phi i32 [ %s.022, %for.cond1.preheader ], [ %add7, %for.body3 ] + %j.019 = phi i32 [ 0, %for.cond1.preheader ], [ %add8, %for.body3 ] + %arrayidx4 = getelementptr inbounds [256 x i32]* %a, i32 %i.021, i32 %j.019 + %0 = load i32* %arrayidx4, align 4 + %arrayidx6 = getelementptr inbounds [256 x i32]* %b, i32 %i.021, i32 %j.019 + %1 = load i32* %arrayidx6, align 4 + %add = add i32 %0, %s.120 + %add7 = add i32 %add, %1 + %add8 = add nsw i32 %j.019, %m + %cmp2 = icmp slt i32 %add8, 64 + br i1 %cmp2, label %for.body3, label %for.inc9 + +for.inc9: + %add10 = add nsw i32 %i.021, %n + %cmp = icmp slt i32 %add10, 64 + br i1 %cmp, label %for.cond1.preheader, label %for.end11 + +for.end11: + ret i32 %add7 +} + diff --git a/test/CodeGen/Mips/align16.ll b/test/CodeGen/Mips/align16.ll new file mode 100644 index 000000000000..99139abbe848 --- /dev/null +++ b/test/CodeGen/Mips/align16.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=16 + +@i = global i32 25, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @p(i32* %i) nounwind { +entry: + ret void +} + + +define void @foo() nounwind { +entry: + %y = alloca [512 x i32], align 4 + %x = alloca i32, align 8 + %zz = alloca i32, align 4 + %z = alloca i32, align 4 + %0 = load i32* @i, align 4 + %arrayidx = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10 + store i32 %0, i32* %arrayidx, align 4 + %1 = load i32* @i, align 4 + store i32 %1, i32* %x, align 8 + call void @p(i32* %x) + %arrayidx1 = getelementptr inbounds [512 x i32]* %y, i32 0, i32 10 + call void @p(i32* %arrayidx1) + ret void +} +; 16: save $ra, $s0, $s1, 2040 +; 16: addiu $sp, -48 # 16 bit inst +; 16: addiu $sp, 48 # 16 bit inst +; 16: restore $ra, $s0, $s1, 2040
\ No newline at end of file diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll index 29f43c8afa18..d79ea9193d28 100644 --- a/test/CodeGen/Mips/alloca.ll +++ b/test/CodeGen/Mips/alloca.ll @@ -3,11 +3,11 @@ define i32 @twoalloca(i32 %size) nounwind { entry: ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] -; CHECK: addu $sp, $zero, $[[T0]] +; CHECK: move $sp, $[[T0]] ; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]] -; CHECK: addu $sp, $zero, $[[T2]] -; CHECK: addu $4, $zero, $[[T0]] -; CHECK: addu $4, $zero, $[[T2]] +; CHECK: move $sp, $[[T2]] +; CHECK: move $4, $[[T0]] +; CHECK: move $4, $[[T2]] %tmp1 = alloca i8, i32 %size, align 4 %add.ptr = getelementptr inbounds i8* %tmp1, i32 5 store i8 97, i8* %add.ptr, align 1 @@ -29,7 +29,7 @@ define i32 @alloca2(i32 %size) nounwind { entry: ; CHECK: alloca2 ; CHECK: subu $[[T0:[0-9]+]], $sp -; CHECK: addu $sp, $zero, $[[T0]] +; CHECK: move $sp, $[[T0]] %tmp1 = alloca i8, i32 %size, align 4 %0 = bitcast i8* %tmp1 to i32* diff --git a/test/CodeGen/Mips/alloca16.ll b/test/CodeGen/Mips/alloca16.ll index 731edae43cbb..5ae9a847917b 100644 --- a/test/CodeGen/Mips/alloca16.ll +++ b/test/CodeGen/Mips/alloca16.ll @@ -68,8 +68,8 @@ entry: %21 = load i32** %ip, align 4 %arrayidx6 = getelementptr inbounds i32* %21, i32 %20 %22 = load i32* %arrayidx6, align 4 -; 16: save 16 +; 16: addiu $sp, -16 call void @temp(i32 %22) -; 16: restore 16 +; 16: addiu $sp, 16 ret void } diff --git a/test/CodeGen/Mips/br-jmp.ll b/test/CodeGen/Mips/br-jmp.ll index 1b5513ab394d..9ca8d159614f 100644 --- a/test/CodeGen/Mips/br-jmp.ll +++ b/test/CodeGen/Mips/br-jmp.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC16 +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 define void @count(i32 %x, i32 %y, i32 %z) noreturn nounwind readnone { entry: @@ -11,3 +13,6 @@ bosco: ; preds = %bosco, %entry ; CHECK-PIC: b $BB0_1 ; CHECK-STATIC: j $BB0_1 +; CHECK-PIC16: b $BB0_1 +; CHECK-STATIC16: b $BB0_1 + diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll index 2fdb736dc886..2deb037c9c39 100644 --- a/test/CodeGen/Mips/brdelayslot.ll +++ b/test/CodeGen/Mips/brdelayslot.ll @@ -1,5 +1,12 @@ ; RUN: llc -march=mipsel -O0 < %s | FileCheck %s -check-prefix=None ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=Default +; RUN: llc -march=mipsel -O1 -relocation-model=static < %s | \ +; RUN: FileCheck %s -check-prefix=STATICO1 +; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \ +; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD +; RUN: llc -march=mipsel -disable-mips-df-backward-search \ +; RUN: -disable-mips-df-succbb-search=false < %s | \ +; RUN: FileCheck %s -check-prefix=SUCCBB define void @foo1() nounwind { entry: @@ -35,3 +42,137 @@ entry: declare void @foo4(double) +@g2 = external global i32 +@g1 = external global i32 +@g3 = external global i32 + +; Check that branch delay slot can be filled with an instruction with operand +; $1. +; +; Default: foo5: +; Default-NOT: nop + +define void @foo5(i32 %a) nounwind { +entry: + %0 = load i32* @g2, align 4 + %tobool = icmp eq i32 %a, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: + %1 = load i32* @g1, align 4 + %add = add nsw i32 %1, %0 + store i32 %add, i32* @g1, align 4 + br label %if.end + +if.else: + %2 = load i32* @g3, align 4 + %sub = sub nsw i32 %2, %0 + store i32 %sub, i32* @g3, align 4 + br label %if.end + +if.end: + ret void +} + +; Check that delay slot filler can place mov.s or mov.d in delay slot. +; +; Default: foo6: +; Default-NOT: nop +; Default: .end foo6 + +define void @foo6(float %a0, double %a1) nounwind { +entry: + tail call void @foo7(double %a1, float %a0) nounwind + ret void +} + +declare void @foo7(double, float) + +; Check that a store can move past other memory instructions. +; +; STATICO1: foo8: +; STATICO1: jalr ${{[0-9]+}} +; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1) + +@foo9 = common global void ()* null, align 4 + +define i32 @foo8(i32 %a) nounwind { +entry: + store i32 %a, i32* @g1, align 4 + %0 = load void ()** @foo9, align 4 + tail call void %0() nounwind + %1 = load i32* @g1, align 4 + %add = add nsw i32 %1, %a + ret i32 %add +} + +; Test searchForward. Check that the second jal's slot is filled with another +; instruction in the same block. +; +; FORWARD: foo10: +; FORWARD: jal foo11 +; FORWARD: jal foo11 +; FORWARD-NOT: nop +; FORWARD: end foo10 + +define void @foo10() nounwind { +entry: + tail call void @foo11() nounwind + tail call void @foo11() nounwind + store i32 0, i32* @g1, align 4 + tail call void @foo11() nounwind + store i32 0, i32* @g1, align 4 + ret void +} + +declare void @foo11() + +; Check that delay slots of branches in both the entry block and loop body are +; filled. +; +; SUCCBB: succbbs_loop1: +; SUCCBB: bne ${{[0-9]+}}, $zero, $BB +; SUCCBB-NEXT: addiu +; SUCCBB: bne ${{[0-9]+}}, $zero, $BB +; SUCCBB-NEXT: addiu + +define i32 @succbbs_loop1(i32* nocapture %a, i32 %n) { +entry: + %cmp4 = icmp sgt i32 %n, 0 + br i1 %cmp4, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.body + %s.06 = phi i32 [ %add, %for.body ], [ 0, %entry ] + %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i32 %i.05 + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %s.06 + %inc = add nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + %s.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ] + ret i32 %s.0.lcssa +} + +; Check that the first branch has its slot filled. +; +; SUCCBB: succbbs_br1: +; SUCCBB: beq ${{[0-9]+}}, $zero, $BB +; SUCCBB-NEXT: lw $25, %call16(foo100) + +define void @succbbs_br1(i32 %a) { +entry: + %tobool = icmp eq i32 %a, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + tail call void @foo100() #1 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +} + +declare void @foo100() diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index 3af899a4e258..81925a4953ce 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -59,3 +59,140 @@ entry: ret i64 %cond } +; slti and conditional move. +; +; Check that, pattern +; (select (setgt a, N), t, f) +; turns into +; (movz t, (setlt a, N + 1), f) +; if N + 1 fits in 16-bit. + +; O32: slti0: +; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @slti0(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, 32766 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: slti1: +; O32: slt ${{[0-9]+}} + +define i32 @slti1(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, 32767 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: slti2: +; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @slti2(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, -32769 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: slti3: +; O32: slt ${{[0-9]+}} + +define i32 @slti3(i32 %a) { +entry: + %cmp = icmp sgt i32 %a, -32770 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; 64-bit patterns. + +; N64: slti64_0: +; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767 +; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i64 @slti64_0(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, 32766 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; N64: slti64_1: +; N64: slt ${{[0-9]+}} + +define i64 @slti64_1(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, 32767 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; N64: slti64_2: +; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768 +; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i64 @slti64_2(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, -32769 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; N64: slti64_3: +; N64: slt ${{[0-9]+}} + +define i64 @slti64_3(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, -32770 + %conv = select i1 %cmp, i64 3, i64 4 + ret i64 %conv +} + +; sltiu instructions. + +; O32: sltiu0: +; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @sltiu0(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, 32766 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: sltiu1: +; O32: sltu ${{[0-9]+}} + +define i32 @sltiu1(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, 32767 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: sltiu2: +; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] + +define i32 @sltiu2(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, -32769 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} + +; O32: sltiu3: +; O32: sltu ${{[0-9]+}} + +define i32 @sltiu3(i32 %a) { +entry: + %cmp = icmp ugt i32 %a, -32770 + %cond = select i1 %cmp, i32 3, i32 4 + ret i32 %cond +} diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll new file mode 100644 index 000000000000..0752f69c3e9e --- /dev/null +++ b/test/CodeGen/Mips/dsp-patterns.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s + +; CHECK: test_lbux: +; CHECK: lbux ${{[0-9]+}} + +define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) { +entry: + %add.ptr = getelementptr inbounds i8* %b, i32 %i + %0 = load i8* %add.ptr, align 1 + ret i8 %0 +} + +; CHECK: test_lhx: +; CHECK: lhx ${{[0-9]+}} + +define signext i16 @test_lhx(i16* nocapture %b, i32 %i) { +entry: + %add.ptr = getelementptr inbounds i16* %b, i32 %i + %0 = load i16* %add.ptr, align 2 + ret i16 %0 +} + +; CHECK: test_lwx: +; CHECK: lwx ${{[0-9]+}} + +define i32 @test_lwx(i32* nocapture %b, i32 %i) { +entry: + %add.ptr = getelementptr inbounds i32* %b, i32 %i + %0 = load i32* %add.ptr, align 4 + ret i32 %0 +} diff --git a/test/CodeGen/Mips/eh-return32.ll b/test/CodeGen/Mips/eh-return32.ll new file mode 100644 index 000000000000..c3003b34b162 --- /dev/null +++ b/test/CodeGen/Mips/eh-return32.ll @@ -0,0 +1,85 @@ +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s + +declare void @llvm.eh.return.i32(i32, i8*) +declare void @foo(...) + +define i8* @f1(i32 %offset, i8* %handler) { +entry: + call void (...)* @foo() + call void @llvm.eh.return.i32(i32 %offset, i8* %handler) + unreachable + +; CHECK: f1 +; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]] + +; check that $a0-$a3 are saved on stack. +; CHECK: sw $4, [[offset0:[0-9]+]]($sp) +; CHECK: sw $5, [[offset1:[0-9]+]]($sp) +; CHECK: sw $6, [[offset2:[0-9]+]]($sp) +; CHECK: sw $7, [[offset3:[0-9]+]]($sp) + +; check that .cfi_offset directives are emitted for $a0-$a3. +; CHECK: .cfi_offset 4, +; CHECK: .cfi_offset 5, +; CHECK: .cfi_offset 6, +; CHECK: .cfi_offset 7, + +; check that stack adjustment and handler are put in $v1 and $v0. +; CHECK: move $[[R0:[a-z0-9]+]], $5 +; CHECK: move $[[R1:[a-z0-9]+]], $4 +; CHECK: move $3, $[[R1]] +; CHECK: move $2, $[[R0]] + +; check that $a0-$a3 are restored from stack. +; CHECK: lw $4, [[offset0]]($sp) +; CHECK: lw $5, [[offset1]]($sp) +; CHECK: lw $6, [[offset2]]($sp) +; CHECK: lw $7, [[offset3]]($sp) + +; check that stack is adjusted by $v1 and that code returns to address in $v0 +; also check that $25 contains handler value +; CHECK: addiu $sp, $sp, [[spoffset]] +; CHECK: move $25, $2 +; CHECK: move $ra, $2 +; CHECK: jr $ra +; CHECK: addu $sp, $sp, $3 +} + +define i8* @f2(i32 %offset, i8* %handler) { +entry: + call void @llvm.eh.return.i32(i32 %offset, i8* %handler) + unreachable + +; CHECK: f2 +; CHECK: addiu $sp, $sp, -[[spoffset:[0-9]+]] + +; check that $a0-$a3 are saved on stack. +; CHECK: sw $4, [[offset0:[0-9]+]]($sp) +; CHECK: sw $5, [[offset1:[0-9]+]]($sp) +; CHECK: sw $6, [[offset2:[0-9]+]]($sp) +; CHECK: sw $7, [[offset3:[0-9]+]]($sp) + +; check that .cfi_offset directives are emitted for $a0-$a3. +; CHECK: .cfi_offset 4, +; CHECK: .cfi_offset 5, +; CHECK: .cfi_offset 6, +; CHECK: .cfi_offset 7, + +; check that stack adjustment and handler are put in $v1 and $v0. +; CHECK: move $3, $4 +; CHECK: move $2, $5 + +; check that $a0-$a3 are restored from stack. +; CHECK: lw $4, [[offset0]]($sp) +; CHECK: lw $5, [[offset1]]($sp) +; CHECK: lw $6, [[offset2]]($sp) +; CHECK: lw $7, [[offset3]]($sp) + +; check that stack is adjusted by $v1 and that code returns to address in $v0 +; also check that $25 contains handler value +; CHECK: addiu $sp, $sp, [[spoffset]] +; CHECK: move $25, $2 +; CHECK: move $ra, $2 +; CHECK: jr $ra +; CHECK: addu $sp, $sp, $3 +} diff --git a/test/CodeGen/Mips/eh-return64.ll b/test/CodeGen/Mips/eh-return64.ll new file mode 100644 index 000000000000..373a9a114453 --- /dev/null +++ b/test/CodeGen/Mips/eh-return64.ll @@ -0,0 +1,87 @@ +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s + +declare void @llvm.eh.return.i64(i64, i8*) +declare void @foo(...) + +define void @f1(i64 %offset, i8* %handler) { +entry: + call void (...)* @foo() + call void @llvm.eh.return.i64(i64 %offset, i8* %handler) + unreachable + +; CHECK: f1 +; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]] + +; check that $a0-$a3 are saved on stack. +; CHECK: sd $4, [[offset0:[0-9]+]]($sp) +; CHECK: sd $5, [[offset1:[0-9]+]]($sp) +; CHECK: sd $6, [[offset2:[0-9]+]]($sp) +; CHECK: sd $7, [[offset3:[0-9]+]]($sp) + +; check that .cfi_offset directives are emitted for $a0-$a3. +; CHECK: .cfi_offset 4, +; CHECK: .cfi_offset 5, +; CHECK: .cfi_offset 6, +; CHECK: .cfi_offset 7, + +; check that stack adjustment and handler are put in $v1 and $v0. +; CHECK: move $[[R0:[a-z0-9]+]], $5 +; CHECK: move $[[R1:[a-z0-9]+]], $4 +; CHECK: move $3, $[[R1]] +; CHECK: move $2, $[[R0]] + +; check that $a0-$a3 are restored from stack. +; CHECK: ld $4, [[offset0]]($sp) +; CHECK: ld $5, [[offset1]]($sp) +; CHECK: ld $6, [[offset2]]($sp) +; CHECK: ld $7, [[offset3]]($sp) + +; check that stack is adjusted by $v1 and that code returns to address in $v0 +; also check that $25 contains handler value +; CHECK: daddiu $sp, $sp, [[spoffset]] +; CHECK: move $25, $2 +; CHECK: move $ra, $2 +; CHECK: jr $ra +; CHECK: daddu $sp, $sp, $3 + +} + +define void @f2(i64 %offset, i8* %handler) { +entry: + call void @llvm.eh.return.i64(i64 %offset, i8* %handler) + unreachable + +; CHECK: f2 +; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]] + +; check that $a0-$a3 are saved on stack. +; CHECK: sd $4, [[offset0:[0-9]+]]($sp) +; CHECK: sd $5, [[offset1:[0-9]+]]($sp) +; CHECK: sd $6, [[offset2:[0-9]+]]($sp) +; CHECK: sd $7, [[offset3:[0-9]+]]($sp) + +; check that .cfi_offset directives are emitted for $a0-$a3. +; CHECK: .cfi_offset 4, +; CHECK: .cfi_offset 5, +; CHECK: .cfi_offset 6, +; CHECK: .cfi_offset 7, + +; check that stack adjustment and handler are put in $v1 and $v0. +; CHECK: move $3, $4 +; CHECK: move $2, $5 + +; check that $a0-$a3 are restored from stack. +; CHECK: ld $4, [[offset0]]($sp) +; CHECK: ld $5, [[offset1]]($sp) +; CHECK: ld $6, [[offset2]]($sp) +; CHECK: ld $7, [[offset3]]($sp) + +; check that stack is adjusted by $v1 and that code returns to address in $v0 +; also check that $25 contains handler value +; CHECK: daddiu $sp, $sp, [[spoffset]] +; CHECK: move $25, $2 +; CHECK: move $ra, $2 +; CHECK: jr $ra +; CHECK: daddu $sp, $sp, $3 + +} diff --git a/test/CodeGen/Mips/ex2.ll b/test/CodeGen/Mips/ex2.ll new file mode 100644 index 000000000000..67d19e4b84ca --- /dev/null +++ b/test/CodeGen/Mips/ex2.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 +@_ZTIPKc = external constant i8* + +define i32 @main() { +; 16: main: +; 16: .cfi_startproc +; 16: save $ra, $s0, $s1, 32 +; 16: .cfi_offset 17, -8 +; 16: .cfi_offset 16, -12 +; 16: .cfi_offset 31, -4 +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %exception = call i8* @__cxa_allocate_exception(i32 4) nounwind + %0 = bitcast i8* %exception to i8** + store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** %0 + call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIPKc to i8*), i8* null) noreturn + unreachable + +return: ; No predecessors! + %1 = load i32* %retval + ret i32 %1 +} + +declare i8* @__cxa_allocate_exception(i32) + +declare void @__cxa_throw(i8*, i8*, i8*) diff --git a/test/CodeGen/Mips/fp16static.ll b/test/CodeGen/Mips/fp16static.ll new file mode 100644 index 000000000000..240ec75a36b6 --- /dev/null +++ b/test/CodeGen/Mips/fp16static.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 + +@x = common global float 0.000000e+00, align 4 + +define void @foo() nounwind { +entry: + %0 = load float* @x, align 4 + %1 = load float* @x, align 4 + %mul = fmul float %0, %1 + store float %mul, float* @x, align 4 +; CHECK-STATIC16: jal __mips16_mulsf3 + ret void +} diff --git a/test/CodeGen/Mips/frame-address.ll b/test/CodeGen/Mips/frame-address.ll index 9df1808fde53..92946d9ffd68 100644 --- a/test/CodeGen/Mips/frame-address.ll +++ b/test/CodeGen/Mips/frame-address.ll @@ -7,6 +7,6 @@ entry: %0 = call i8* @llvm.frameaddress(i32 0) ret i8* %0 -; CHECK: addu $fp, $sp, $zero -; CHECK: addu $2, $zero, $fp +; CHECK: move $fp, $sp +; CHECK: move $2, $fp } diff --git a/test/CodeGen/Mips/gpreg-lazy-binding.ll b/test/CodeGen/Mips/gpreg-lazy-binding.ll new file mode 100644 index 000000000000..88e596b3bb0d --- /dev/null +++ b/test/CodeGen/Mips/gpreg-lazy-binding.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | FileCheck %s + +@g = external global i32 + +; CHECK: move $gp +; CHECK: jalr $25 +; CHECK: nop +; CHECK-NOT: move $gp +; CHECK: jalr $25 + +define void @f0() nounwind { +entry: + tail call void @externalFunc() nounwind + tail call fastcc void @internalFunc() + ret void +} + +declare void @externalFunc() + +define internal fastcc void @internalFunc() nounwind noinline { +entry: + %0 = load i32* @g, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* @g, align 4 + ret void +} + diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll index aee58b650e7a..56ee60785f46 100644 --- a/test/CodeGen/Mips/helloworld.ll +++ b/test/CodeGen/Mips/helloworld.ll @@ -1,9 +1,11 @@ ; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 ; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 ; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1 +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST2 ; -; re-enable this when mips16's jalr is fixed. -; DISABLED: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR32 @.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 @@ -15,7 +17,15 @@ entry: ; SR: .set mips16 # @main -; SR: save $ra, [[FS:[0-9]+]] +; SR32: .set nomips16 +; SR32: .ent main +; SR-NOT: .set noreorder +; SR-NOT: .set nomacro +; SR-NOT: .set noat +; SR32: .set noreorder +; SR32: .set nomacro +; SR32: .set noat +; SR: save $ra, $s0, $s1, [[FS:[0-9]+]] ; PE: li $[[T1:[0-9]+]], %hi(_gp_disp) ; PE: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp) ; PE: sll $[[T3:[0-9]+]], $[[T1]], 16 @@ -25,10 +35,23 @@ entry: ; C2: move $25, ${{[0-9]+}} ; C1: move $gp, ${{[0-9]+}} ; C1: jalrc ${{[0-9]+}} -; SR: restore $ra, [[FS]] +; SR: restore $ra, $s0, $s1, [[FS]] ; PE: li $2, 0 ; PE: jrc $ra +; ST1: li ${{[0-9]+}}, %hi($.str) +; ST1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16 +; ST1: addiu ${{[0-9]+}}, %lo($.str) +; ST2: li ${{[0-9]+}}, %hi($.str) +; ST2: jal printf } +; SR-NOT: .set at +; SR-NOT: .set macro +; SR-NOT: .set reorder +; SR32: .set at +; SR32: .set macro +; SR32: .set reorder +; SR: .end main +; SR32: .end main declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/hf16_1.ll b/test/CodeGen/Mips/hf16_1.ll new file mode 100644 index 000000000000..c7454ee0a8dd --- /dev/null +++ b/test/CodeGen/Mips/hf16_1.ll @@ -0,0 +1,256 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -soft-float -mips16-hard-float -O3 < %s | FileCheck %s -check-prefix=1 +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -soft-float -mips16-hard-float -O3 < %s | FileCheck %s -check-prefix=2 + + +@x = common global float 0.000000e+00, align 4 +@xd = common global double 0.000000e+00, align 8 +@y = common global float 0.000000e+00, align 4 +@yd = common global double 0.000000e+00, align 8 +@xy = common global { float, float } zeroinitializer, align 4 +@xyd = common global { double, double } zeroinitializer, align 8 + +define void @foo() nounwind { +entry: + %0 = load float* @x, align 4 + call void @v_sf(float %0) + %1 = load double* @xd, align 8 + call void @v_df(double %1) + %2 = load float* @x, align 4 + %3 = load float* @y, align 4 + call void @v_sf_sf(float %2, float %3) + %4 = load double* @xd, align 8 + %5 = load float* @x, align 4 + call void @v_df_sf(double %4, float %5) + %6 = load double* @xd, align 8 + %7 = load double* @yd, align 8 + call void @v_df_df(double %6, double %7) + %call = call float @sf_v() + %8 = load float* @x, align 4 + %call1 = call float @sf_sf(float %8) + %9 = load double* @xd, align 8 + %call2 = call float @sf_df(double %9) + %10 = load float* @x, align 4 + %11 = load float* @y, align 4 + %call3 = call float @sf_sf_sf(float %10, float %11) + %12 = load double* @xd, align 8 + %13 = load float* @x, align 4 + %call4 = call float @sf_df_sf(double %12, float %13) + %14 = load double* @xd, align 8 + %15 = load double* @yd, align 8 + %call5 = call float @sf_df_df(double %14, double %15) + %call6 = call double @df_v() + %16 = load float* @x, align 4 + %call7 = call double @df_sf(float %16) + %17 = load double* @xd, align 8 + %call8 = call double @df_df(double %17) + %18 = load float* @x, align 4 + %19 = load float* @y, align 4 + %call9 = call double @df_sf_sf(float %18, float %19) + %20 = load double* @xd, align 8 + %21 = load float* @x, align 4 + %call10 = call double @df_df_sf(double %20, float %21) + %22 = load double* @xd, align 8 + %23 = load double* @yd, align 8 + %call11 = call double @df_df_df(double %22, double %23) + %call12 = call { float, float } @sc_v() + %24 = extractvalue { float, float } %call12, 0 + %25 = extractvalue { float, float } %call12, 1 + %26 = load float* @x, align 4 + %call13 = call { float, float } @sc_sf(float %26) + %27 = extractvalue { float, float } %call13, 0 + %28 = extractvalue { float, float } %call13, 1 + %29 = load double* @xd, align 8 + %call14 = call { float, float } @sc_df(double %29) + %30 = extractvalue { float, float } %call14, 0 + %31 = extractvalue { float, float } %call14, 1 + %32 = load float* @x, align 4 + %33 = load float* @y, align 4 + %call15 = call { float, float } @sc_sf_sf(float %32, float %33) + %34 = extractvalue { float, float } %call15, 0 + %35 = extractvalue { float, float } %call15, 1 + %36 = load double* @xd, align 8 + %37 = load float* @x, align 4 + %call16 = call { float, float } @sc_df_sf(double %36, float %37) + %38 = extractvalue { float, float } %call16, 0 + %39 = extractvalue { float, float } %call16, 1 + %40 = load double* @xd, align 8 + %41 = load double* @yd, align 8 + %call17 = call { float, float } @sc_df_df(double %40, double %41) + %42 = extractvalue { float, float } %call17, 0 + %43 = extractvalue { float, float } %call17, 1 + %call18 = call { double, double } @dc_v() + %44 = extractvalue { double, double } %call18, 0 + %45 = extractvalue { double, double } %call18, 1 + %46 = load float* @x, align 4 + %call19 = call { double, double } @dc_sf(float %46) + %47 = extractvalue { double, double } %call19, 0 + %48 = extractvalue { double, double } %call19, 1 + %49 = load double* @xd, align 8 + %call20 = call { double, double } @dc_df(double %49) + %50 = extractvalue { double, double } %call20, 0 + %51 = extractvalue { double, double } %call20, 1 + %52 = load float* @x, align 4 + %53 = load float* @y, align 4 + %call21 = call { double, double } @dc_sf_sf(float %52, float %53) + %54 = extractvalue { double, double } %call21, 0 + %55 = extractvalue { double, double } %call21, 1 + %56 = load double* @xd, align 8 + %57 = load float* @x, align 4 + %call22 = call { double, double } @dc_df_sf(double %56, float %57) + %58 = extractvalue { double, double } %call22, 0 + %59 = extractvalue { double, double } %call22, 1 + %60 = load double* @xd, align 8 + %61 = load double* @yd, align 8 + %call23 = call { double, double } @dc_df_df(double %60, double %61) + %62 = extractvalue { double, double } %call23, 0 + %63 = extractvalue { double, double } %call23, 1 + ret void +} + +declare void @v_sf(float) + +declare void @v_df(double) + +declare void @v_sf_sf(float, float) + +declare void @v_df_sf(double, float) + +declare void @v_df_df(double, double) + +declare float @sf_v() + +declare float @sf_sf(float) + +declare float @sf_df(double) + +declare float @sf_sf_sf(float, float) + +declare float @sf_df_sf(double, float) + +declare float @sf_df_df(double, double) + +declare double @df_v() + +declare double @df_sf(float) + +declare double @df_df(double) + +declare double @df_sf_sf(float, float) + +declare double @df_df_sf(double, float) + +declare double @df_df_df(double, double) + +declare { float, float } @sc_v() + +declare { float, float } @sc_sf(float) + +declare { float, float } @sc_df(double) + +declare { float, float } @sc_sf_sf(float, float) + +declare { float, float } @sc_df_sf(double, float) + +declare { float, float } @sc_df_df(double, double) + +declare { double, double } @dc_v() + +declare { double, double } @dc_sf(float) + +declare { double, double } @dc_df(double) + +declare { double, double } @dc_sf_sf(float, float) + +declare { double, double } @dc_df_sf(double, float) + +declare { double, double } @dc_df_df(double, double) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_1)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(v_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_2)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(v_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_5)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(v_sf_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_6)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(v_df_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_10)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(v_df_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_0)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sf_v)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sf_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_2)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sf_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_5)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sf_sf_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_6)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sf_df_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sf_10)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sf_df_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_0)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(df_v)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_1)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(df_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(df_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_5)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(df_sf_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_6)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(df_df_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_df_10)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(df_df_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sc_0)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sc_v)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sc_1)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sc_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sc_2)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sc_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sc_5)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sc_sf_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sc_6)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sc_df_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_sc_10)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(sc_df_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_dc_0)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(dc_v)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_dc_1)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(dc_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_dc_2)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(dc_df)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_dc_5)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(dc_sf_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_dc_6)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(dc_df_sf)(${{[0-9]+}}) + +; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_dc_10)(${{[0-9]+}}) +; 2: lw ${{[0-9]+}}, %call16(dc_df_df)(${{[0-9]+}}) + + + diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index 8b1f71b69f19..704014cba010 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -2,8 +2,8 @@ define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: -; CHECK: addu $[[R1:[0-9]+]], $zero, $5 -; CHECK: addu $[[R0:[0-9]+]], $zero, $4 +; CHECK: move $[[R1:[0-9]+]], $5 +; CHECK: move $[[R0:[0-9]+]], $4 ; CHECK: ori $6, ${{[0-9]+}}, 3855 ; CHECK: ori $7, ${{[0-9]+}}, 22136 ; CHECK: lw $25, %call16(ff1) @@ -12,16 +12,16 @@ entry: ; CHECK: lw $25, %call16(ff2) ; CHECK: lw $[[R2:[0-9]+]], 80($sp) ; CHECK: lw $[[R3:[0-9]+]], 84($sp) -; CHECK: addu $4, $zero, $[[R2]] -; CHECK: addu $5, $zero, $[[R3]] +; CHECK: move $4, $[[R2]] +; CHECK: move $5, $[[R3]] ; CHECK: jalr $25 tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind %sub = add nsw i32 %i, -1 +; CHECK: lw $25, %call16(ff3) ; CHECK: sw $[[R1]], 28($sp) ; CHECK: sw $[[R0]], 24($sp) -; CHECK: lw $25, %call16(ff3) -; CHECK: addu $6, $zero, $[[R2]] -; CHECK: addu $7, $zero, $[[R3]] +; CHECK: move $6, $[[R2]] +; CHECK: move $7, $[[R3]] ; CHECK: jalr $25 tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind ret void diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll index 5adec3bb29ea..8d30f45d84e3 100644 --- a/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -51,5 +51,14 @@ entry: ; CHECK: #NO_APP tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind +; Now R Which takes the address of c + %c = alloca i32, align 4 + store i32 -4469539, i32* %c, align 4 + %8 = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1 +; CHECK: #APP +; CHECK: lwl ${{[0-9]+}}, 1 + 0(${{[0-9]+}}) +; CHECK: lwr ${{[0-9]+}}, 2 + 0(${{[0-9]+}}) +; CHECK: #NO_APP + ret i32 0 } diff --git a/test/CodeGen/Mips/jtstat.ll b/test/CodeGen/Mips/jtstat.ll new file mode 100644 index 000000000000..01afc080c2ed --- /dev/null +++ b/test/CodeGen/Mips/jtstat.ll @@ -0,0 +1,71 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 + +@s = global i8 115, align 1 +@c = common global i8 0, align 1 +@.str = private unnamed_addr constant [5 x i8] c"%c \0A\00", align 1 + +define void @test(i32 %i) nounwind { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %0 = load i32* %i.addr, align 4 + switch i32 %0, label %sw.epilog [ + i32 115, label %sw.bb + i32 105, label %sw.bb1 + i32 100, label %sw.bb2 + i32 108, label %sw.bb3 + i32 99, label %sw.bb4 + i32 68, label %sw.bb5 + i32 81, label %sw.bb6 + i32 76, label %sw.bb7 + ] + +sw.bb: ; preds = %entry + store i8 115, i8* @c, align 1 + br label %sw.epilog + +sw.bb1: ; preds = %entry + store i8 105, i8* @c, align 1 + br label %sw.epilog + +sw.bb2: ; preds = %entry + store i8 100, i8* @c, align 1 + br label %sw.epilog + +sw.bb3: ; preds = %entry + store i8 108, i8* @c, align 1 + br label %sw.epilog + +sw.bb4: ; preds = %entry + store i8 99, i8* @c, align 1 + br label %sw.epilog + +sw.bb5: ; preds = %entry + store i8 68, i8* @c, align 1 + br label %sw.epilog + +sw.bb6: ; preds = %entry + store i8 81, i8* @c, align 1 + br label %sw.epilog + +sw.bb7: ; preds = %entry + store i8 76, i8* @c, align 1 + br label %sw.epilog + +sw.epilog: ; preds = %entry, %sw.bb7, %sw.bb6, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb + ret void +} + +; CHECK-STATIC16: li ${{[0-9]+}}, %hi($JTI{{[0-9]+}}_{{[0-9]+}}) +; CHECK-STATIC16: lw ${{[0-9]+}}, %lo($JTI{{[0-9]+}}_{{[0-9]+}})(${{[0-9]+}}) +; CHECK-STATIC16: $JTI{{[0-9]+}}_{{[0-9]+}}: +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) +; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}}) diff --git a/test/CodeGen/Mips/largefr1.ll b/test/CodeGen/Mips/largefr1.ll new file mode 100644 index 000000000000..0fe89f71d9f3 --- /dev/null +++ b/test/CodeGen/Mips/largefr1.ll @@ -0,0 +1,61 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=1 + +@i = common global i32 0, align 4 +@j = common global i32 0, align 4 +@.str = private unnamed_addr constant [8 x i8] c"%i %i \0A\00", align 1 + +define void @foo(i32* %p, i32 %i, i32 %j) nounwind { +entry: + %p.addr = alloca i32*, align 4 + %i.addr = alloca i32, align 4 + %j.addr = alloca i32, align 4 + store i32* %p, i32** %p.addr, align 4 + store i32 %i, i32* %i.addr, align 4 + store i32 %j, i32* %j.addr, align 4 + %0 = load i32* %j.addr, align 4 + %1 = load i32** %p.addr, align 4 + %2 = load i32* %i.addr, align 4 + %add.ptr = getelementptr inbounds i32* %1, i32 %2 + store i32 %0, i32* %add.ptr, align 4 + ret void +} + +define i32 @main() nounwind { +entry: +; 1: main: +; 1: 1: .word -797992 +; 1: li ${{[0-9]+}}, 12 +; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16 +; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; 2: move $sp, ${{[0-9]+}} +; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; 1: li ${{[0-9]+}}, 6 +; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16 +; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; 2: move $sp, ${{[0-9]+}} +; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; 1: addiu ${{[0-9]+}}, ${{[0-9]+}}, 6800 +; 1: li ${{[0-9]+}}, 1 +; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16 +; 2: li ${{[0-9]+}}, 34463 + %retval = alloca i32, align 4 + %one = alloca [100000 x i32], align 4 + %two = alloca [100000 x i32], align 4 + store i32 0, i32* %retval + %arrayidx = getelementptr inbounds [100000 x i32]* %one, i32 0, i32 0 + call void @foo(i32* %arrayidx, i32 50, i32 9999) + %arrayidx1 = getelementptr inbounds [100000 x i32]* %two, i32 0, i32 0 + call void @foo(i32* %arrayidx1, i32 99999, i32 5555) + %arrayidx2 = getelementptr inbounds [100000 x i32]* %one, i32 0, i32 50 + %0 = load i32* %arrayidx2, align 4 + store i32 %0, i32* @i, align 4 + %arrayidx3 = getelementptr inbounds [100000 x i32]* %two, i32 0, i32 99999 + %1 = load i32* %arrayidx3, align 4 + store i32 %1, i32* @j, align 4 + %2 = load i32* @i, align 4 + %3 = load i32* @j, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/lit.local.cfg b/test/CodeGen/Mips/lit.local.cfg index 0587d3243e6b..e157c540b538 100644 --- a/test/CodeGen/Mips/lit.local.cfg +++ b/test/CodeGen/Mips/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'Mips' in targets: diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll index 0aeabb30e289..0dbb2c27b8f9 100644 --- a/test/CodeGen/Mips/madd-msub.ll +++ b/test/CodeGen/Mips/madd-msub.ll @@ -1,6 +1,9 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=DSP +; RUN: llc -march=mips -mcpu=mips16 < %s -; CHECK: madd +; 32: madd ${{[0-9]+}} +; DSP: madd $ac define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 @@ -11,7 +14,8 @@ entry: ret i64 %add } -; CHECK: maddu +; 32: maddu ${{[0-9]+}} +; DSP: maddu $ac define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = zext i32 %a to i64 @@ -22,7 +26,8 @@ entry: ret i64 %add } -; CHECK: madd +; 32: madd ${{[0-9]+}} +; DSP: madd $ac define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 @@ -32,7 +37,8 @@ entry: ret i64 %add } -; CHECK: msub +; 32: msub ${{[0-9]+}} +; DSP: msub $ac define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = sext i32 %c to i64 @@ -43,7 +49,8 @@ entry: ret i64 %sub } -; CHECK: msubu +; 32: msubu ${{[0-9]+}} +; DSP: msubu $ac define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = zext i32 %c to i64 @@ -54,7 +61,8 @@ entry: ret i64 %sub } -; CHECK: msub +; 32: msub ${{[0-9]+}} +; DSP: msub $ac define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 diff --git a/test/CodeGen/Mips/mips16ex.ll b/test/CodeGen/Mips/mips16ex.ll new file mode 100644 index 000000000000..ecb30b5c63b8 --- /dev/null +++ b/test/CodeGen/Mips/mips16ex.ll @@ -0,0 +1,87 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +;16: $eh_func_begin0=. +@.str = private unnamed_addr constant [7 x i8] c"hello\0A\00", align 1 +@_ZTIi = external constant i8* +@.str1 = private unnamed_addr constant [15 x i8] c"exception %i \0A\00", align 1 + +define i32 @main() { +entry: + %retval = alloca i32, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %e = alloca i32, align 4 + store i32 0, i32* %retval + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0)) + %exception = call i8* @__cxa_allocate_exception(i32 4) nounwind + %0 = bitcast i8* %exception to i32* + store i32 20, i32* %0 + invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn + to label %unreachable unwind label %lpad + +lpad: ; preds = %entry + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* bitcast (i8** @_ZTIi to i8*) + %2 = extractvalue { i8*, i32 } %1, 0 + store i8* %2, i8** %exn.slot + %3 = extractvalue { i8*, i32 } %1, 1 + store i32 %3, i32* %ehselector.slot + br label %catch.dispatch + +catch.dispatch: ; preds = %lpad + %sel = load i32* %ehselector.slot + %4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) nounwind + %matches = icmp eq i32 %sel, %4 + br i1 %matches, label %catch, label %eh.resume + +catch: ; preds = %catch.dispatch + %exn = load i8** %exn.slot + %5 = call i8* @__cxa_begin_catch(i8* %exn) nounwind + %6 = bitcast i8* %5 to i32* + %exn.scalar = load i32* %6 + store i32 %exn.scalar, i32* %e, align 4 + %7 = load i32* %e, align 4 + %call2 = invoke i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([15 x i8]* @.str1, i32 0, i32 0), i32 %7) + to label %invoke.cont unwind label %lpad1 + +invoke.cont: ; preds = %catch + call void @__cxa_end_catch() nounwind + br label %try.cont + +try.cont: ; preds = %invoke.cont + ret i32 0 + +lpad1: ; preds = %catch + %8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + %9 = extractvalue { i8*, i32 } %8, 0 + store i8* %9, i8** %exn.slot + %10 = extractvalue { i8*, i32 } %8, 1 + store i32 %10, i32* %ehselector.slot + call void @__cxa_end_catch() nounwind + br label %eh.resume + +eh.resume: ; preds = %lpad1, %catch.dispatch + %exn3 = load i8** %exn.slot + %sel4 = load i32* %ehselector.slot + %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn3, 0 + %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %sel4, 1 + resume { i8*, i32 } %lpad.val5 + +unreachable: ; preds = %entry + unreachable +} + +declare i32 @printf(i8*, ...) + +declare i8* @__cxa_allocate_exception(i32) + +declare i32 @__gxx_personality_v0(...) + +declare void @__cxa_throw(i8*, i8*, i8*) + +declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() diff --git a/test/CodeGen/Mips/mips16fpe.ll b/test/CodeGen/Mips/mips16fpe.ll new file mode 100644 index 000000000000..433543607967 --- /dev/null +++ b/test/CodeGen/Mips/mips16fpe.ll @@ -0,0 +1,381 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 -soft-float -mips16-hard-float < %s | FileCheck %s -check-prefix=16hf + +@x = global float 5.000000e+00, align 4 +@y = global float 1.500000e+01, align 4 +@xd = global double 6.000000e+00, align 8 +@yd = global double 1.800000e+01, align 8 +@two = global i32 2, align 4 +@addsf3_result = common global float 0.000000e+00, align 4 +@adddf3_result = common global double 0.000000e+00, align 8 +@subsf3_result = common global float 0.000000e+00, align 4 +@subdf3_result = common global double 0.000000e+00, align 8 +@mulsf3_result = common global float 0.000000e+00, align 4 +@muldf3_result = common global double 0.000000e+00, align 8 +@divsf3_result = common global float 0.000000e+00, align 4 +@divdf3_result = common global double 0.000000e+00, align 8 +@extendsfdf2_result = common global double 0.000000e+00, align 8 +@xd2 = global double 0x40147E6B74B4CF6A, align 8 +@truncdfsf2_result = common global float 0.000000e+00, align 4 +@fix_truncsfsi_result = common global i32 0, align 4 +@fix_truncdfsi_result = common global i32 0, align 4 +@si = global i32 -9, align 4 +@ui = global i32 9, align 4 +@floatsisf_result = common global float 0.000000e+00, align 4 +@floatsidf_result = common global double 0.000000e+00, align 8 +@floatunsisf_result = common global float 0.000000e+00, align 4 +@floatunsidf_result = common global double 0.000000e+00, align 8 +@xx = global float 5.000000e+00, align 4 +@eqsf2_result = common global i32 0, align 4 +@xxd = global double 6.000000e+00, align 8 +@eqdf2_result = common global i32 0, align 4 +@nesf2_result = common global i32 0, align 4 +@nedf2_result = common global i32 0, align 4 +@gesf2_result = common global i32 0, align 4 +@gedf2_result = common global i32 0, align 4 +@ltsf2_result = common global i32 0, align 4 +@ltdf2_result = common global i32 0, align 4 +@lesf2_result = common global i32 0, align 4 +@ledf2_result = common global i32 0, align 4 +@gtsf2_result = common global i32 0, align 4 +@gtdf2_result = common global i32 0, align 4 + +define void @test_addsf3() nounwind { +entry: +;16hf: test_addsf3: + %0 = load float* @x, align 4 + %1 = load float* @y, align 4 + %add = fadd float %0, %1 + store float %add, float* @addsf3_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_addsf3)(${{[0-9]+}}) + ret void +} + +define void @test_adddf3() nounwind { +entry: +;16hf: test_adddf3: + %0 = load double* @xd, align 8 + %1 = load double* @yd, align 8 + %add = fadd double %0, %1 + store double %add, double* @adddf3_result, align 8 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_adddf3)(${{[0-9]+}}) + ret void +} + +define void @test_subsf3() nounwind { +entry: +;16hf: test_subsf3: + %0 = load float* @x, align 4 + %1 = load float* @y, align 4 + %sub = fsub float %0, %1 + store float %sub, float* @subsf3_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_subsf3)(${{[0-9]+}}) + ret void +} + +define void @test_subdf3() nounwind { +entry: +;16hf: test_subdf3: + %0 = load double* @xd, align 8 + %1 = load double* @yd, align 8 + %sub = fsub double %0, %1 + store double %sub, double* @subdf3_result, align 8 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_subdf3)(${{[0-9]+}}) + ret void +} + +define void @test_mulsf3() nounwind { +entry: +;16hf: test_mulsf3: + %0 = load float* @x, align 4 + %1 = load float* @y, align 4 + %mul = fmul float %0, %1 + store float %mul, float* @mulsf3_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_mulsf3)(${{[0-9]+}}) + ret void +} + +define void @test_muldf3() nounwind { +entry: +;16hf: test_muldf3: + %0 = load double* @xd, align 8 + %1 = load double* @yd, align 8 + %mul = fmul double %0, %1 + store double %mul, double* @muldf3_result, align 8 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_muldf3)(${{[0-9]+}}) + ret void +} + +define void @test_divsf3() nounwind { +entry: +;16hf: test_divsf3: + %0 = load float* @y, align 4 + %1 = load float* @x, align 4 + %div = fdiv float %0, %1 + store float %div, float* @divsf3_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_divsf3)(${{[0-9]+}}) + ret void +} + +define void @test_divdf3() nounwind { +entry: +;16hf: test_divdf3: + %0 = load double* @yd, align 8 + %mul = fmul double %0, 2.000000e+00 + %1 = load double* @xd, align 8 + %div = fdiv double %mul, %1 + store double %div, double* @divdf3_result, align 8 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_divdf3)(${{[0-9]+}}) + ret void +} + +define void @test_extendsfdf2() nounwind { +entry: +;16hf: test_extendsfdf2: + %0 = load float* @x, align 4 + %conv = fpext float %0 to double + store double %conv, double* @extendsfdf2_result, align 8 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_extendsfdf2)(${{[0-9]+}}) + ret void +} + +define void @test_truncdfsf2() nounwind { +entry: +;16hf: test_truncdfsf2: + %0 = load double* @xd2, align 8 + %conv = fptrunc double %0 to float + store float %conv, float* @truncdfsf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_truncdfsf2)(${{[0-9]+}}) + ret void +} + +define void @test_fix_truncsfsi() nounwind { +entry: +;16hf: test_fix_truncsfsi: + %0 = load float* @x, align 4 + %conv = fptosi float %0 to i32 + store i32 %conv, i32* @fix_truncsfsi_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_fix_truncsfsi)(${{[0-9]+}}) + ret void +} + +define void @test_fix_truncdfsi() nounwind { +entry: +;16hf: test_fix_truncdfsi: + %0 = load double* @xd, align 8 + %conv = fptosi double %0 to i32 + store i32 %conv, i32* @fix_truncdfsi_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_fix_truncdfsi)(${{[0-9]+}}) + ret void +} + +define void @test_floatsisf() nounwind { +entry: +;16hf: test_floatsisf: + %0 = load i32* @si, align 4 + %conv = sitofp i32 %0 to float + store float %conv, float* @floatsisf_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_floatsisf)(${{[0-9]+}}) + ret void +} + +define void @test_floatsidf() nounwind { +entry: +;16hf: test_floatsidf: + %0 = load i32* @si, align 4 + %conv = sitofp i32 %0 to double + store double %conv, double* @floatsidf_result, align 8 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_floatsidf)(${{[0-9]+}}) + ret void +} + +define void @test_floatunsisf() nounwind { +entry: +;16hf: test_floatunsisf: + %0 = load i32* @ui, align 4 + %conv = uitofp i32 %0 to float + store float %conv, float* @floatunsisf_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_floatunsisf)(${{[0-9]+}}) + ret void +} + +define void @test_floatunsidf() nounwind { +entry: +;16hf: test_floatunsidf: + %0 = load i32* @ui, align 4 + %conv = uitofp i32 %0 to double + store double %conv, double* @floatunsidf_result, align 8 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_floatunsidf)(${{[0-9]+}}) + ret void +} + +define void @test_eqsf2() nounwind { +entry: +;16hf: test_eqsf2: + %0 = load float* @x, align 4 + %1 = load float* @xx, align 4 + %cmp = fcmp oeq float %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @eqsf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_eqsf2)(${{[0-9]+}}) + ret void +} + +define void @test_eqdf2() nounwind { +entry: +;16hf: test_eqdf2: + %0 = load double* @xd, align 8 + %1 = load double* @xxd, align 8 + %cmp = fcmp oeq double %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @eqdf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_eqdf2)(${{[0-9]+}}) + ret void +} + +define void @test_nesf2() nounwind { +entry: +;16hf: test_nesf2: + %0 = load float* @x, align 4 + %1 = load float* @y, align 4 + %cmp = fcmp une float %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @nesf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_nesf2)(${{[0-9]+}}) + ret void +} + +define void @test_nedf2() nounwind { +entry: +;16hf: test_nedf2: + %0 = load double* @xd, align 8 + %1 = load double* @yd, align 8 + %cmp = fcmp une double %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @nedf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_nedf2)(${{[0-9]+}}) + ret void +} + +define void @test_gesf2() nounwind { +entry: +;16hf: test_gesf2: + %0 = load float* @x, align 4 + %1 = load float* @xx, align 4 + %cmp = fcmp oge float %0, %1 + %2 = load float* @y, align 4 + %cmp1 = fcmp oge float %2, %0 + %and3 = and i1 %cmp, %cmp1 + %and = zext i1 %and3 to i32 + store i32 %and, i32* @gesf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_gesf2)(${{[0-9]+}}) + ret void +} + +define void @test_gedf2() nounwind { +entry: +;16hf: test_gedf2: + %0 = load double* @xd, align 8 + %1 = load double* @xxd, align 8 + %cmp = fcmp oge double %0, %1 + %2 = load double* @yd, align 8 + %cmp1 = fcmp oge double %2, %0 + %and3 = and i1 %cmp, %cmp1 + %and = zext i1 %and3 to i32 + store i32 %and, i32* @gedf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_gedf2)(${{[0-9]+}}) + ret void +} + +define void @test_ltsf2() nounwind { +entry: +;16hf: test_ltsf2: + %0 = load float* @x, align 4 + %1 = load float* @xx, align 4 + %lnot = fcmp uge float %0, %1 + %2 = load float* @y, align 4 + %cmp1 = fcmp olt float %0, %2 + %and2 = and i1 %lnot, %cmp1 + %and = zext i1 %and2 to i32 + store i32 %and, i32* @ltsf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_unordsf2)(${{[0-9]+}}) +;16hf: lw ${{[0-9]+}}, %call16(__mips16_ltsf2)(${{[0-9]+}}) + ret void +} + +define void @test_ltdf2() nounwind { +entry: +;16hf: test_ltdf2: + %0 = load double* @xd, align 8 + %1 = load double* @xxd, align 8 + %lnot = fcmp uge double %0, %1 + %2 = load double* @yd, align 8 + %cmp1 = fcmp olt double %0, %2 + %and2 = and i1 %lnot, %cmp1 + %and = zext i1 %and2 to i32 + store i32 %and, i32* @ltdf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_unorddf2)(${{[0-9]+}}) +;16hf: lw ${{[0-9]+}}, %call16(__mips16_ltdf2)(${{[0-9]+}}) + ret void +} + +define void @test_lesf2() nounwind { +entry: +;16hf: test_lesf2: + %0 = load float* @x, align 4 + %1 = load float* @xx, align 4 + %cmp = fcmp ole float %0, %1 + %2 = load float* @y, align 4 + %cmp1 = fcmp ole float %0, %2 + %and3 = and i1 %cmp, %cmp1 + %and = zext i1 %and3 to i32 + store i32 %and, i32* @lesf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_lesf2)(${{[0-9]+}}) + ret void +} + +define void @test_ledf2() nounwind { +entry: +;16hf: test_ledf2: + %0 = load double* @xd, align 8 + %1 = load double* @xxd, align 8 + %cmp = fcmp ole double %0, %1 + %2 = load double* @yd, align 8 + %cmp1 = fcmp ole double %0, %2 + %and3 = and i1 %cmp, %cmp1 + %and = zext i1 %and3 to i32 + store i32 %and, i32* @ledf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_ledf2)(${{[0-9]+}}) + ret void +} + +define void @test_gtsf2() nounwind { +entry: +;16hf: test_gtsf2: + %0 = load float* @x, align 4 + %1 = load float* @xx, align 4 + %lnot = fcmp ule float %0, %1 + %2 = load float* @y, align 4 + %cmp1 = fcmp ogt float %2, %0 + %and2 = and i1 %lnot, %cmp1 + %and = zext i1 %and2 to i32 + store i32 %and, i32* @gtsf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_gtsf2)(${{[0-9]+}}) + ret void +} + +define void @test_gtdf2() nounwind { +entry: +;16hf: test_gtdf2: + %0 = load double* @xd, align 8 + %1 = load double* @xxd, align 8 + %lnot = fcmp ule double %0, %1 + %2 = load double* @yd, align 8 + %cmp1 = fcmp ogt double %2, %0 + %and2 = and i1 %lnot, %cmp1 + %and = zext i1 %and2 to i32 + store i32 %and, i32* @gtdf2_result, align 4 +;16hf: lw ${{[0-9]+}}, %call16(__mips16_gtdf2)(${{[0-9]+}}) + ret void +} + + diff --git a/test/CodeGen/Mips/mips64-f128-call.ll b/test/CodeGen/Mips/mips64-f128-call.ll new file mode 100644 index 000000000000..455e540e5df1 --- /dev/null +++ b/test/CodeGen/Mips/mips64-f128-call.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s + +@gld0 = external global fp128 +@gld1 = external global fp128 + +; CHECK: foo0 +; CHECK: sdc1 $f13, 8(${{[0-9]+}}) +; CHECK: sdc1 $f12, 0(${{[0-9]+}}) + +define void @foo0(fp128 %a0) { +entry: + store fp128 %a0, fp128* @gld0, align 16 + ret void +} + +; CHECK: foo1 +; CHECK: ldc1 $f13, 8(${{[0-9]+}}) +; CHECK: ldc1 $f12, 0(${{[0-9]+}}) + +define void @foo1() { +entry: + %0 = load fp128* @gld0, align 16 + tail call void @foo2(fp128 %0) + ret void +} + +declare void @foo2(fp128) + +; CHECK: foo3 +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld0) +; CHECK: sdc1 $f2, 8($[[R0]]) +; CHECK: sdc1 $f0, 0($[[R0]]) +; CHECK: ld $[[R1:[0-9]+]], %got_disp(gld1) +; CHECK: ldc1 $f0, 0($[[R1]]) +; CHECK: ldc1 $f2, 8($[[R1]]) + +define fp128 @foo3() { +entry: + %call = tail call fp128 @foo4() + store fp128 %call, fp128* @gld0, align 16 + %0 = load fp128* @gld1, align 16 + ret fp128 %0 +} + +declare fp128 @foo4() diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll new file mode 100644 index 000000000000..5892cab4f8ea --- /dev/null +++ b/test/CodeGen/Mips/mips64-f128.ll @@ -0,0 +1,646 @@ +; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -soft-float -O1 \ +; RUN: -disable-mips-delay-filler < %s | FileCheck %s + +@gld0 = external global fp128 +@gld1 = external global fp128 +@gld2 = external global fp128 +@gf1 = external global float +@gd1 = external global double + +; CHECK: addLD: +; CHECK: ld $25, %call16(__addtf3) + +define fp128 @addLD() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld1, align 16 + %add = fadd fp128 %0, %1 + ret fp128 %add +} + +; CHECK: subLD: +; CHECK: ld $25, %call16(__subtf3) + +define fp128 @subLD() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld1, align 16 + %sub = fsub fp128 %0, %1 + ret fp128 %sub +} + +; CHECK: mulLD: +; CHECK: ld $25, %call16(__multf3) + +define fp128 @mulLD() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld1, align 16 + %mul = fmul fp128 %0, %1 + ret fp128 %mul +} + +; CHECK: divLD: +; CHECK: ld $25, %call16(__divtf3) + +define fp128 @divLD() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld1, align 16 + %div = fdiv fp128 %0, %1 + ret fp128 %div +} + +; CHECK: conv_LD_char: +; CHECK: ld $25, %call16(__floatsitf) + +define fp128 @conv_LD_char(i8 signext %a) { +entry: + %conv = sitofp i8 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_short: +; CHECK: ld $25, %call16(__floatsitf) + +define fp128 @conv_LD_short(i16 signext %a) { +entry: + %conv = sitofp i16 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_int: +; CHECK: ld $25, %call16(__floatsitf) + +define fp128 @conv_LD_int(i32 %a) { +entry: + %conv = sitofp i32 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_LL: +; CHECK: ld $25, %call16(__floatditf) + +define fp128 @conv_LD_LL(i64 %a) { +entry: + %conv = sitofp i64 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_UChar: +; CHECK: ld $25, %call16(__floatunsitf) + +define fp128 @conv_LD_UChar(i8 zeroext %a) { +entry: + %conv = uitofp i8 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_UShort: +; CHECK: ld $25, %call16(__floatunsitf) + +define fp128 @conv_LD_UShort(i16 zeroext %a) { +entry: + %conv = uitofp i16 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_UInt: +; CHECK: ld $25, %call16(__floatunsitf) + +define fp128 @conv_LD_UInt(i32 %a) { +entry: + %conv = uitofp i32 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_ULL: +; CHECK: ld $25, %call16(__floatunditf) + +define fp128 @conv_LD_ULL(i64 %a) { +entry: + %conv = uitofp i64 %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_char_LD: +; CHECK: ld $25, %call16(__fixtfsi) + +define signext i8 @conv_char_LD(fp128 %a) { +entry: + %conv = fptosi fp128 %a to i8 + ret i8 %conv +} + +; CHECK: conv_short_LD: +; CHECK: ld $25, %call16(__fixtfsi) + +define signext i16 @conv_short_LD(fp128 %a) { +entry: + %conv = fptosi fp128 %a to i16 + ret i16 %conv +} + +; CHECK: conv_int_LD: +; CHECK: ld $25, %call16(__fixtfsi) + +define i32 @conv_int_LD(fp128 %a) { +entry: + %conv = fptosi fp128 %a to i32 + ret i32 %conv +} + +; CHECK: conv_LL_LD: +; CHECK: ld $25, %call16(__fixtfdi) + +define i64 @conv_LL_LD(fp128 %a) { +entry: + %conv = fptosi fp128 %a to i64 + ret i64 %conv +} + +; CHECK: conv_UChar_LD: +; CHECK: ld $25, %call16(__fixtfsi) + +define zeroext i8 @conv_UChar_LD(fp128 %a) { +entry: + %conv = fptoui fp128 %a to i8 + ret i8 %conv +} + +; CHECK: conv_UShort_LD: +; CHECK: ld $25, %call16(__fixtfsi) + +define zeroext i16 @conv_UShort_LD(fp128 %a) { +entry: + %conv = fptoui fp128 %a to i16 + ret i16 %conv +} + +; CHECK: conv_UInt_LD: +; CHECK: ld $25, %call16(__fixunstfsi) + +define i32 @conv_UInt_LD(fp128 %a) { +entry: + %conv = fptoui fp128 %a to i32 + ret i32 %conv +} + +; CHECK: conv_ULL_LD: +; CHECK: ld $25, %call16(__fixunstfdi) + +define i64 @conv_ULL_LD(fp128 %a) { +entry: + %conv = fptoui fp128 %a to i64 + ret i64 %conv +} + +; CHECK: conv_LD_float: +; CHECK: ld $25, %call16(__extendsftf2) + +define fp128 @conv_LD_float(float %a) { +entry: + %conv = fpext float %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_LD_double: +; CHECK: ld $25, %call16(__extenddftf2) + +define fp128 @conv_LD_double(double %a) { +entry: + %conv = fpext double %a to fp128 + ret fp128 %conv +} + +; CHECK: conv_float_LD: +; CHECK: ld $25, %call16(__trunctfsf2) + +define float @conv_float_LD(fp128 %a) { +entry: + %conv = fptrunc fp128 %a to float + ret float %conv +} + +; CHECK: conv_double_LD: +; CHECK: ld $25, %call16(__trunctfdf2) + +define double @conv_double_LD(fp128 %a) { +entry: + %conv = fptrunc fp128 %a to double + ret double %conv +} + +; CHECK: libcall1_fabsl: +; CHECK: ld $[[R0:[0-9]+]], 8($[[R4:[0-9]+]]) +; CHECK: daddiu $[[R1:[0-9]+]], $zero, 1 +; CHECK: dsll $[[R2:[0-9]+]], $[[R1]], 63 +; CHECK: daddiu $[[R3:[0-9]+]], $[[R2]], -1 +; CHECK: and $4, $[[R0]], $[[R3]] +; CHECK: ld $2, 0($[[R4]]) + +define fp128 @libcall1_fabsl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @fabsl(fp128 %0) nounwind readnone + ret fp128 %call +} + +declare fp128 @fabsl(fp128) #1 + +; CHECK: libcall1_ceill: +; CHECK: ld $25, %call16(ceill) + +define fp128 @libcall1_ceill() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @ceill(fp128 %0) nounwind readnone + ret fp128 %call +} + +declare fp128 @ceill(fp128) #1 + +; CHECK: libcall1_sinl: +; CHECK: ld $25, %call16(sinl) + +define fp128 @libcall1_sinl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @sinl(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @sinl(fp128) #2 + +; CHECK: libcall1_cosl: +; CHECK: ld $25, %call16(cosl) + +define fp128 @libcall1_cosl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @cosl(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @cosl(fp128) #2 + +; CHECK: libcall1_expl: +; CHECK: ld $25, %call16(expl) + +define fp128 @libcall1_expl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @expl(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @expl(fp128) #2 + +; CHECK: libcall1_exp2l: +; CHECK: ld $25, %call16(exp2l) + +define fp128 @libcall1_exp2l() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @exp2l(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @exp2l(fp128) #2 + +; CHECK: libcall1_logl: +; CHECK: ld $25, %call16(logl) + +define fp128 @libcall1_logl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @logl(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @logl(fp128) #2 + +; CHECK: libcall1_log2l: +; CHECK: ld $25, %call16(log2l) + +define fp128 @libcall1_log2l() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @log2l(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @log2l(fp128) #2 + +; CHECK: libcall1_log10l: +; CHECK: ld $25, %call16(log10l) + +define fp128 @libcall1_log10l() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @log10l(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @log10l(fp128) #2 + +; CHECK: libcall1_nearbyintl: +; CHECK: ld $25, %call16(nearbyintl) + +define fp128 @libcall1_nearbyintl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @nearbyintl(fp128 %0) nounwind readnone + ret fp128 %call +} + +declare fp128 @nearbyintl(fp128) #1 + +; CHECK: libcall1_floorl: +; CHECK: ld $25, %call16(floorl) + +define fp128 @libcall1_floorl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @floorl(fp128 %0) nounwind readnone + ret fp128 %call +} + +declare fp128 @floorl(fp128) #1 + +; CHECK: libcall1_sqrtl: +; CHECK: ld $25, %call16(sqrtl) + +define fp128 @libcall1_sqrtl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @sqrtl(fp128 %0) nounwind + ret fp128 %call +} + +declare fp128 @sqrtl(fp128) #2 + +; CHECK: libcall1_rintl: +; CHECK: ld $25, %call16(rintl) + +define fp128 @libcall1_rintl() { +entry: + %0 = load fp128* @gld0, align 16 + %call = tail call fp128 @rintl(fp128 %0) nounwind readnone + ret fp128 %call +} + +declare fp128 @rintl(fp128) #1 + +; CHECK: libcall_powil: +; CHECK: ld $25, %call16(__powitf2) + +define fp128 @libcall_powil(fp128 %a, i32 %b) { +entry: + %0 = tail call fp128 @llvm.powi.f128(fp128 %a, i32 %b) + ret fp128 %0 +} + +declare fp128 @llvm.powi.f128(fp128, i32) #3 + +; CHECK: libcall2_copysignl: +; CHECK: daddiu $[[R2:[0-9]+]], $zero, 1 +; CHECK: dsll $[[R3:[0-9]+]], $[[R2]], 63 +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1) +; CHECK: ld $[[R1:[0-9]+]], 8($[[R0]]) +; CHECK: and $[[R4:[0-9]+]], $[[R1]], $[[R3]] +; CHECK: ld $[[R5:[0-9]+]], %got_disp(gld0) +; CHECK: ld $[[R6:[0-9]+]], 8($[[R5]]) +; CHECK: daddiu $[[R7:[0-9]+]], $[[R3]], -1 +; CHECK: and $[[R8:[0-9]+]], $[[R6]], $[[R7]] +; CHECK: or $4, $[[R8]], $[[R4]] +; CHECK: ld $2, 0($[[R5]]) + +define fp128 @libcall2_copysignl() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld1, align 16 + %call = tail call fp128 @copysignl(fp128 %0, fp128 %1) nounwind readnone + ret fp128 %call +} + +declare fp128 @copysignl(fp128, fp128) #1 + +; CHECK: libcall2_powl: +; CHECK: ld $25, %call16(powl) + +define fp128 @libcall2_powl() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld1, align 16 + %call = tail call fp128 @powl(fp128 %0, fp128 %1) nounwind + ret fp128 %call +} + +declare fp128 @powl(fp128, fp128) #2 + +; CHECK: libcall2_fmodl: +; CHECK: ld $25, %call16(fmodl) + +define fp128 @libcall2_fmodl() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld1, align 16 + %call = tail call fp128 @fmodl(fp128 %0, fp128 %1) nounwind + ret fp128 %call +} + +declare fp128 @fmodl(fp128, fp128) #2 + +; CHECK: libcall3_fmal: +; CHECK: ld $25, %call16(fmal) + +define fp128 @libcall3_fmal() { +entry: + %0 = load fp128* @gld0, align 16 + %1 = load fp128* @gld2, align 16 + %2 = load fp128* @gld1, align 16 + %3 = tail call fp128 @llvm.fma.f128(fp128 %0, fp128 %2, fp128 %1) + ret fp128 %3 +} + +declare fp128 @llvm.fma.f128(fp128, fp128, fp128) #4 + +; CHECK: cmp_lt: +; CHECK: ld $25, %call16(__lttf2) + +define i32 @cmp_lt(fp128 %a, fp128 %b) { +entry: + %cmp = fcmp olt fp128 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; CHECK: cmp_le: +; CHECK: ld $25, %call16(__letf2) + +define i32 @cmp_le(fp128 %a, fp128 %b) { +entry: + %cmp = fcmp ole fp128 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; CHECK: cmp_gt: +; CHECK: ld $25, %call16(__gttf2) + +define i32 @cmp_gt(fp128 %a, fp128 %b) { +entry: + %cmp = fcmp ogt fp128 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; CHECK: cmp_ge: +; CHECK: ld $25, %call16(__getf2) + +define i32 @cmp_ge(fp128 %a, fp128 %b) { +entry: + %cmp = fcmp oge fp128 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; CHECK: cmp_eq: +; CHECK: ld $25, %call16(__eqtf2) + +define i32 @cmp_eq(fp128 %a, fp128 %b) { +entry: + %cmp = fcmp oeq fp128 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; CHECK: cmp_ne: +; CHECK: ld $25, %call16(__netf2) + +define i32 @cmp_ne(fp128 %a, fp128 %b) { +entry: + %cmp = fcmp une fp128 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; CHECK: load_LD_LD: +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1) +; CHECK: ld $2, 0($[[R0]]) +; CHECK: ld $4, 8($[[R0]]) + +define fp128 @load_LD_LD() { +entry: + %0 = load fp128* @gld1, align 16 + ret fp128 %0 +} + +; CHECK: load_LD_float: +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gf1) +; CHECK: lw $4, 0($[[R0]]) +; CHECK: ld $25, %call16(__extendsftf2) +; CHECK: jalr $25 + +define fp128 @load_LD_float() { +entry: + %0 = load float* @gf1, align 4 + %conv = fpext float %0 to fp128 + ret fp128 %conv +} + +; CHECK: load_LD_double: +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gd1) +; CHECK: ld $4, 0($[[R0]]) +; CHECK: ld $25, %call16(__extenddftf2) +; CHECK: jalr $25 + +define fp128 @load_LD_double() { +entry: + %0 = load double* @gd1, align 8 + %conv = fpext double %0 to fp128 + ret fp128 %conv +} + +; CHECK: store_LD_LD: +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1) +; CHECK: ld $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: ld $[[R2:[0-9]+]], 8($[[R0]]) +; CHECK: ld $[[R3:[0-9]+]], %got_disp(gld0) +; CHECK: sd $[[R2]], 8($[[R3]]) +; CHECK: sd $[[R1]], 0($[[R3]]) + +define void @store_LD_LD() { +entry: + %0 = load fp128* @gld1, align 16 + store fp128 %0, fp128* @gld0, align 16 + ret void +} + +; CHECK: store_LD_float: +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1) +; CHECK: ld $4, 0($[[R0]]) +; CHECK: ld $5, 8($[[R0]]) +; CHECK: ld $25, %call16(__trunctfsf2) +; CHECK: jalr $25 +; CHECK: ld $[[R1:[0-9]+]], %got_disp(gf1) +; CHECK: sw $2, 0($[[R1]]) + +define void @store_LD_float() { +entry: + %0 = load fp128* @gld1, align 16 + %conv = fptrunc fp128 %0 to float + store float %conv, float* @gf1, align 4 + ret void +} + +; CHECK: store_LD_double: +; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1) +; CHECK: ld $4, 0($[[R0]]) +; CHECK: ld $5, 8($[[R0]]) +; CHECK: ld $25, %call16(__trunctfdf2) +; CHECK: jalr $25 +; CHECK: ld $[[R1:[0-9]+]], %got_disp(gd1) +; CHECK: sd $2, 0($[[R1]]) + +define void @store_LD_double() { +entry: + %0 = load fp128* @gld1, align 16 + %conv = fptrunc fp128 %0 to double + store double %conv, double* @gd1, align 8 + ret void +} + +; CHECK: select_LD: +; CHECK: movn $8, $6, $4 +; CHECK: movn $9, $7, $4 +; CHECK: move $2, $8 +; CHECK: move $4, $9 + +define fp128 @select_LD(i32 %a, i64, fp128 %b, fp128 %c) { +entry: + %tobool = icmp ne i32 %a, 0 + %cond = select i1 %tobool, fp128 %b, fp128 %c + ret fp128 %cond +} + +; CHECK: selectCC_LD: +; CHECK: move $[[R0:[0-9]+]], $11 +; CHECK: move $[[R1:[0-9]+]], $10 +; CHECK: move $[[R2:[0-9]+]], $9 +; CHECK: move $[[R3:[0-9]+]], $8 +; CHECK: ld $25, %call16(__gttf2)($gp) +; CHECK: jalr $25 +; CHECK: slti $1, $2, 1 +; CHECK: movz $[[R1]], $[[R3]], $1 +; CHECK: movz $[[R0]], $[[R2]], $1 +; CHECK: move $2, $[[R1]] +; CHECK: move $4, $[[R0]] + +define fp128 @selectCC_LD(fp128 %a, fp128 %b, fp128 %c, fp128 %d) { +entry: + %cmp = fcmp ogt fp128 %a, %b + %cond = select i1 %cmp, fp128 %c, fp128 %d + ret fp128 %cond +} diff --git a/test/CodeGen/Mips/mips64-libcall.ll b/test/CodeGen/Mips/mips64-libcall.ll new file mode 100644 index 000000000000..d54598be70d8 --- /dev/null +++ b/test/CodeGen/Mips/mips64-libcall.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=mips64el -mcpu=mips64r2 -O3 < %s |\ +; RUN: FileCheck %s -check-prefix=HARD +; RUN: llc -march=mips64el -mcpu=mips64r2 -soft-float < %s |\ +; RUN: FileCheck %s -check-prefix=SOFT + +; Check that %add is not passed in an integer register. +; +; HARD: callfloor: +; HARD-NOT: dmfc1 $4 + +define double @callfloor(double %d) nounwind readnone { +entry: + %add = fadd double %d, 1.000000e+00 + %call = tail call double @floor(double %add) nounwind readnone + ret double %call +} + +declare double @floor(double) nounwind readnone + +; Check call16. +; +; SOFT: f64add: +; SOFT: ld $25, %call16(__adddf3) + +define double @f64add(double %a, double %b) { +entry: + %add = fadd double %a, %b + ret double %add +} diff --git a/test/CodeGen/Mips/mips64-sret.ll b/test/CodeGen/Mips/mips64-sret.ll index e26b0223b447..e01609f3b1e4 100644 --- a/test/CodeGen/Mips/mips64-sret.ll +++ b/test/CodeGen/Mips/mips64-sret.ll @@ -6,7 +6,7 @@ define void @f(%struct.S* noalias sret %agg.result) nounwind { entry: -; CHECK: daddu $2, $zero, $4 +; CHECK: move $2, $4 %0 = bitcast %struct.S* %agg.result to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.S* @g to i8*), i64 32, i32 4, i1 false) diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index 5558ba6e10f4..0a8f85f4825d 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -12,20 +12,20 @@ define void @f1() nounwind { entry: ; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1) ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) +; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) +; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) +; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) +; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) ; CHECK: sw $[[R6]], 36($sp) -; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: sw $[[R5]], 32($sp) -; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) ; CHECK: sw $[[R4]], 28($sp) -; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) ; CHECK: sw $[[R3]], 24($sp) -; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) ; CHECK: sw $[[R7]], 20($sp) ; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) ; CHECK: sw $[[R2]], 16($sp) -; CHECK: lw $7, 4($[[R0]]) ; CHECK: lw $6, %lo(f1.s1)($[[R1]]) +; CHECK: lw $7, 4($[[R0]]) %agg.tmp10 = alloca %struct.S3, align 4 call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind call void @callee2(%struct.S2* byval @f1.s2) nounwind diff --git a/test/CodeGen/Mips/return-vector-float4.ll b/test/CodeGen/Mips/return-vector-float4.ll deleted file mode 100644 index ae10f123e4d2..000000000000 --- a/test/CodeGen/Mips/return-vector-float4.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: llc -march=mipsel -mattr=+android < %s | FileCheck %s - -define <4 x float> @retvec4() nounwind readnone { -entry: -; CHECK: lwc1 $f0 -; CHECK: lwc1 $f2 -; CHECK: lwc1 $f1 -; CHECK: lwc1 $f3 - - ret <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00> -} - diff --git a/test/CodeGen/Mips/return_address.ll b/test/CodeGen/Mips/return_address.ll index e1c9241984ca..34b72baa6d25 100644 --- a/test/CodeGen/Mips/return_address.ll +++ b/test/CodeGen/Mips/return_address.ll @@ -5,7 +5,7 @@ entry: %0 = call i8* @llvm.returnaddress(i32 0) ret i8* %0 -; CHECK: addu $2, $zero, $ra +; CHECK: move $2, $ra } define i8* @f2() nounwind { @@ -14,9 +14,9 @@ entry: %0 = call i8* @llvm.returnaddress(i32 0) ret i8* %0 -; CHECK: addu $[[R0:[0-9]+]], $zero, $ra +; CHECK: move $[[R0:[0-9]+]], $ra ; CHECK: jal -; CHECK: addu $2, $zero, $[[R0]] +; CHECK: move $2, $[[R0]] } declare i8* @llvm.returnaddress(i32) nounwind readnone diff --git a/test/CodeGen/Mips/selTBteqzCmpi.ll b/test/CodeGen/Mips/selTBteqzCmpi.ll new file mode 100644 index 000000000000..9cb8227f9d2b --- /dev/null +++ b/test/CodeGen/Mips/selTBteqzCmpi.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@i = global i32 1, align 4 +@j = global i32 2, align 4 +@a = global i32 5, align 4 +@.str = private unnamed_addr constant [8 x i8] c"%i = 2\0A\00", align 1 +@k = common global i32 0, align 4 + +define void @t() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp eq i32 %0, 10 + %1 = load i32* @i, align 4 + %2 = load i32* @j, align 4 + %cond = select i1 %cmp, i32 %1, i32 %2 + store i32 %cond, i32* @i, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } + + +; 16: cmpi ${{[0-9]+}}, 10 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + + diff --git a/test/CodeGen/Mips/selTBtnezCmpi.ll b/test/CodeGen/Mips/selTBtnezCmpi.ll new file mode 100644 index 000000000000..bd334f59d33b --- /dev/null +++ b/test/CodeGen/Mips/selTBtnezCmpi.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@i = global i32 1, align 4 +@j = global i32 2, align 4 +@a = global i32 5, align 4 +@.str = private unnamed_addr constant [8 x i8] c"%i = 1\0A\00", align 1 +@k = common global i32 0, align 4 + +define void @t() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp ne i32 %0, 10 + %1 = load i32* @i, align 4 + %2 = load i32* @j, align 4 + %cond = select i1 %cmp, i32 %1, i32 %2 + store i32 %cond, i32* @i, align 4 + ret void +} + +; 16: cmpi ${{[0-9]+}}, 10 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } + + diff --git a/test/CodeGen/Mips/selTBtnezSlti.ll b/test/CodeGen/Mips/selTBtnezSlti.ll new file mode 100644 index 000000000000..593f6f274eb3 --- /dev/null +++ b/test/CodeGen/Mips/selTBtnezSlti.ll @@ -0,0 +1,25 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@i = global i32 1, align 4 +@j = global i32 2, align 4 +@a = global i32 5, align 4 +@.str = private unnamed_addr constant [9 x i8] c"%i = 2 \0A\00", align 1 +@k = common global i32 0, align 4 + +define void @t() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp slt i32 %0, 10 + %1 = load i32* @j, align 4 + %2 = load i32* @i, align 4 + %cond = select i1 %cmp, i32 %1, i32 %2 + store i32 %cond, i32* @i, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: slti ${{[0-9]+}}, 10 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + + diff --git a/test/CodeGen/Mips/seleq.ll b/test/CodeGen/Mips/seleq.ll new file mode 100644 index 000000000000..190baad0b1db --- /dev/null +++ b/test/CodeGen/Mips/seleq.ll @@ -0,0 +1,95 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 1, align 4 +@b = global i32 10, align 4 +@c = global i32 1, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 + +define void @calc_seleq() nounwind "target-cpu"="mips32" "target-features"="+o32,+mips32" { +entry: + %0 = load i32* @a, align 4 + %1 = load i32* @b, align 4 + %cmp = icmp eq i32 %0, %1 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %2 = load i32* @f, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %3 = load i32* @t, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %4 = load i32* @b, align 4 + %5 = load i32* @a, align 4 + %cmp1 = icmp eq i32 %4, %5 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %6 = load i32* @f, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %7 = load i32* @t, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %8 = load i32* @c, align 4 + %9 = load i32* @a, align 4 + %cmp6 = icmp eq i32 %8, %9 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %10 = load i32* @t, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %11 = load i32* @f, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %12 = load i32* @a, align 4 + %13 = load i32* @c, align 4 + %cmp11 = icmp eq i32 %12, %13 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %14 = load i32* @t, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %15 = load i32* @f, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %14, %cond.true12 ], [ %15, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips32" "target-features"="+o32,+mips32" } + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + diff --git a/test/CodeGen/Mips/seleqk.ll b/test/CodeGen/Mips/seleqk.ll new file mode 100644 index 000000000000..3ca622d5d8fe --- /dev/null +++ b/test/CodeGen/Mips/seleqk.ll @@ -0,0 +1,91 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 1, align 4 +@b = global i32 1000, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_seleqk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp eq i32 %0, 1 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %1 = load i32* @t, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %2 = load i32* @f, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %3 = load i32* @a, align 4 + %cmp1 = icmp eq i32 %3, 1000 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %4 = load i32* @f, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %5 = load i32* @t, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %6 = load i32* @b, align 4 + %cmp6 = icmp eq i32 %6, 3 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %7 = load i32* @f, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %8 = load i32* @t, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %9 = load i32* @b, align 4 + %cmp11 = icmp eq i32 %9, 1000 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %10 = load i32* @t, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %11 = load i32* @f, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: cmpi ${{[0-9]+}}, 1 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmpi ${{[0-9]+}}, 1000 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmpi ${{[0-9]+}}, 3 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmpi ${{[0-9]+}}, 1000 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} diff --git a/test/CodeGen/Mips/selgek.ll b/test/CodeGen/Mips/selgek.ll new file mode 100644 index 000000000000..8ab4046e92cb --- /dev/null +++ b/test/CodeGen/Mips/selgek.ll @@ -0,0 +1,94 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 2, align 4 +@b = global i32 1000, align 4 +@c = global i32 2, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp sge i32 %0, 1000 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %1 = load i32* @f, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %2 = load i32* @t, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %3 = load i32* @b, align 4 + %cmp1 = icmp sge i32 %3, 1 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %4 = load i32* @t, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %5 = load i32* @f, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %6 = load i32* @c, align 4 + %cmp6 = icmp sge i32 %6, 2 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %7 = load i32* @t, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %8 = load i32* @f, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %9 = load i32* @a, align 4 + %cmp11 = icmp sge i32 %9, 2 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %10 = load i32* @t, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %11 = load i32* @f, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: slti ${{[0-9]+}}, 1000 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 1 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 2 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 2 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + + diff --git a/test/CodeGen/Mips/selgt.ll b/test/CodeGen/Mips/selgt.ll new file mode 100644 index 000000000000..67b9b498709b --- /dev/null +++ b/test/CodeGen/Mips/selgt.ll @@ -0,0 +1,98 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 1, align 4 +@b = global i32 10, align 4 +@c = global i32 1, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [9 x i8] c"%i = %i\0A\00", align 1 + +define i32 @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %retval = alloca i32, align 4 + %0 = load i32* @a, align 4 + %1 = load i32* @b, align 4 + %cmp = icmp sgt i32 %0, %1 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %2 = load i32* @f, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %3 = load i32* @t, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %4 = load i32* @b, align 4 + %5 = load i32* @a, align 4 + %cmp1 = icmp sgt i32 %4, %5 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %6 = load i32* @t, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %7 = load i32* @f, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %8 = load i32* @c, align 4 + %9 = load i32* @a, align 4 + %cmp6 = icmp sgt i32 %8, %9 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %10 = load i32* @f, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %11 = load i32* @t, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %12 = load i32* @a, align 4 + %13 = load i32* @c, align 4 + %cmp11 = icmp sgt i32 %12, %13 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %14 = load i32* @f, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %15 = load i32* @t, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %14, %cond.true12 ], [ %15, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + %16 = load i32* %retval + ret i32 %16 +} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } diff --git a/test/CodeGen/Mips/selle.ll b/test/CodeGen/Mips/selle.ll new file mode 100644 index 000000000000..b27df45e6739 --- /dev/null +++ b/test/CodeGen/Mips/selle.ll @@ -0,0 +1,96 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 1, align 4 +@b = global i32 10, align 4 +@c = global i32 1, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %1 = load i32* @b, align 4 + %cmp = icmp sle i32 %0, %1 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %2 = load i32* @t, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %3 = load i32* @f, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %4 = load i32* @b, align 4 + %5 = load i32* @a, align 4 + %cmp1 = icmp sle i32 %4, %5 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %6 = load i32* @f, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %7 = load i32* @t, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %8 = load i32* @c, align 4 + %9 = load i32* @a, align 4 + %cmp6 = icmp sle i32 %8, %9 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %10 = load i32* @t, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %11 = load i32* @f, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %12 = load i32* @a, align 4 + %13 = load i32* @c, align 4 + %cmp11 = icmp sle i32 %12, %13 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %14 = load i32* @t, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %15 = load i32* @f, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %14, %cond.true12 ], [ %15, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } diff --git a/test/CodeGen/Mips/selltk.ll b/test/CodeGen/Mips/selltk.ll new file mode 100644 index 000000000000..1471b892c92a --- /dev/null +++ b/test/CodeGen/Mips/selltk.ll @@ -0,0 +1,93 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 2, align 4 +@b = global i32 1000, align 4 +@c = global i32 2, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_selltk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp slt i32 %0, 1000 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %1 = load i32* @t, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %2 = load i32* @f, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %3 = load i32* @b, align 4 + %cmp1 = icmp slt i32 %3, 2 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %4 = load i32* @f, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %5 = load i32* @t, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %6 = load i32* @c, align 4 + %cmp6 = icmp sgt i32 %6, 2 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %7 = load i32* @f, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %8 = load i32* @t, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %9 = load i32* @a, align 4 + %cmp11 = icmp sgt i32 %9, 2 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %10 = load i32* @f, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %11 = load i32* @t, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 3 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 3 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + diff --git a/test/CodeGen/Mips/selne.ll b/test/CodeGen/Mips/selne.ll new file mode 100644 index 000000000000..e3d82b8cf5d0 --- /dev/null +++ b/test/CodeGen/Mips/selne.ll @@ -0,0 +1,97 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 1, align 4 +@b = global i32 10, align 4 +@c = global i32 1, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_seleq() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %1 = load i32* @b, align 4 + %cmp = icmp ne i32 %0, %1 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %2 = load i32* @f, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %3 = load i32* @t, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %4 = load i32* @b, align 4 + %5 = load i32* @a, align 4 + %cmp1 = icmp ne i32 %4, %5 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %6 = load i32* @f, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %7 = load i32* @t, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %8 = load i32* @c, align 4 + %9 = load i32* @a, align 4 + %cmp6 = icmp ne i32 %8, %9 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %10 = load i32* @t, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %11 = load i32* @f, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %12 = load i32* @a, align 4 + %13 = load i32* @c, align 4 + %cmp11 = icmp ne i32 %12, %13 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %14 = load i32* @t, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %15 = load i32* @f, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %14, %cond.true12 ], [ %15, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + diff --git a/test/CodeGen/Mips/selnek.ll b/test/CodeGen/Mips/selnek.ll new file mode 100644 index 000000000000..26015523106d --- /dev/null +++ b/test/CodeGen/Mips/selnek.ll @@ -0,0 +1,107 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 1, align 4 +@b = global i32 1000, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp ne i32 %0, 1 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %1 = load i32* @f, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %2 = load i32* @t, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %3 = load i32* @a, align 4 + %cmp1 = icmp ne i32 %3, 1000 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %4 = load i32* @t, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %5 = load i32* @f, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %6 = load i32* @b, align 4 + %cmp6 = icmp ne i32 %6, 3 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %7 = load i32* @t, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %8 = load i32* @f, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %9 = load i32* @b, align 4 + %cmp11 = icmp ne i32 %9, 1000 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %10 = load i32* @f, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %11 = load i32* @t, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +define i32 @main() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + call void @calc_z() "target-cpu"="mips16" "target-features"="+mips16,+o32" + %0 = load i32* @z1, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %0) "target-cpu"="mips16" "target-features"="+mips16,+o32" + %1 = load i32* @z2, align 4 + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) "target-cpu"="mips16" "target-features"="+mips16,+o32" + %2 = load i32* @z3, align 4 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %2) "target-cpu"="mips16" "target-features"="+mips16,+o32" + %3 = load i32* @z4, align 4 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %3) "target-cpu"="mips16" "target-features"="+mips16,+o32" + ret i32 0 +} + +declare i32 @printf(i8*, ...) "target-cpu"="mips16" "target-features"="+mips16,+o32" + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: cmpi ${{[0-9]+}}, 1 # 16 bit inst +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmpi ${{[0-9]+}}, 1000 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmpi ${{[0-9]+}}, 3 # 16 bit inst +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmpi ${{[0-9]+}}, 1000 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
\ No newline at end of file diff --git a/test/CodeGen/Mips/selpat.ll b/test/CodeGen/Mips/selpat.ll index cda0c96ef4be..8eda8de45e08 100644 --- a/test/CodeGen/Mips/selpat.ll +++ b/test/CodeGen/Mips/selpat.ll @@ -20,7 +20,7 @@ entry: %cond = select i1 %cmp, i32 %2, i32 %3 store i32 %cond, i32* @z1, align 4 ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} -; 16: bteqz .+4 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} store i32 %cond, i32* @z2, align 4 %4 = load i32* @c, align 4 @@ -41,7 +41,7 @@ entry: %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 ; 16: cmpi ${{[0-9]+}}, 1 -; 16: bteqz .+4 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp1 = icmp eq i32 %0, 10 %cond5 = select i1 %cmp1, i32 %2, i32 %1 @@ -51,7 +51,7 @@ entry: %cond10 = select i1 %cmp6, i32 %2, i32 %1 store i32 %cond10, i32* @z3, align 4 ; 16: cmpi ${{[0-9]+}}, 10 -; 16: bteqz .+4 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp11 = icmp eq i32 %3, 10 %cond15 = select i1 %cmp11, i32 %1, i32 %2 @@ -67,7 +67,7 @@ entry: %2 = load i32* @f, align 4 %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: beqz ${{[0-9]+}}, .+4 +; 16: beqz ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %cmp1 = icmp eq i32 %3, 0 @@ -91,7 +91,7 @@ entry: %cond = select i1 %cmp, i32 %2, i32 %3 store i32 %cond, i32* @z1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: bteqz .+4 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp1 = icmp sge i32 %1, %0 %cond5 = select i1 %cmp1, i32 %3, i32 %2 @@ -112,7 +112,7 @@ entry: %1 = load i32* @b, align 4 %cmp = icmp sgt i32 %0, %1 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: btnez .+4 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %2 = load i32* @f, align 4 %3 = load i32* @t, align 4 @@ -141,7 +141,7 @@ entry: %cond = select i1 %cmp, i32 %2, i32 %3 store i32 %cond, i32* @z1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: bteqz .+4 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp1 = icmp sle i32 %1, %0 %cond5 = select i1 %cmp1, i32 %3, i32 %2 @@ -165,7 +165,7 @@ entry: %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 ; 16: slti ${{[0-9]+}}, {{[0-9]+}} -; 16: btnez .+4 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %cmp1 = icmp slt i32 %3, 2 @@ -192,7 +192,7 @@ entry: %cond = select i1 %cmp, i32 %2, i32 %3 store i32 %cond, i32* @z1, align 4 ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} -; 16: btnez .+4 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} store i32 %cond, i32* @z2, align 4 %4 = load i32* @c, align 4 @@ -212,7 +212,7 @@ entry: %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 ; 16: cmpi ${{[0-9]+}}, 1 -; 16: btnez .+4 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp1 = icmp ne i32 %0, 10 %cond5 = select i1 %cmp1, i32 %2, i32 %1 @@ -222,7 +222,7 @@ entry: %cond10 = select i1 %cmp6, i32 %2, i32 %1 store i32 %cond10, i32* @z3, align 4 ; 16: cmpi ${{[0-9]+}}, 10 -; 16: btnez .+4 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp11 = icmp ne i32 %3, 10 %cond15 = select i1 %cmp11, i32 %1, i32 %2 @@ -238,7 +238,7 @@ entry: %2 = load i32* @t, align 4 %cond = select i1 %cmp, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: bnez ${{[0-9]+}}, .+4 +; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %cmp1 = icmp ne i32 %3, 0 @@ -260,7 +260,7 @@ entry: %2 = load i32* @t, align 4 %cond = select i1 %tobool, i32 %1, i32 %2 store i32 %cond, i32* @z1, align 4 -; 16: bnez ${{[0-9]+}}, .+4 +; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %3 = load i32* @b, align 4 %tobool1 = icmp ne i32 %3, 0 @@ -284,7 +284,7 @@ entry: %cond = select i1 %cmp, i32 %2, i32 %3 store i32 %cond, i32* @z1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: bteqz .+4 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp1 = icmp uge i32 %1, %0 %cond5 = select i1 %cmp1, i32 %3, i32 %2 @@ -309,7 +309,7 @@ entry: %cond = select i1 %cmp, i32 %2, i32 %3 store i32 %cond, i32* @z1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: btnez .+4 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp1 = icmp ugt i32 %1, %0 %cond5 = select i1 %cmp1, i32 %3, i32 %2 @@ -334,7 +334,7 @@ entry: %cond = select i1 %cmp, i32 %2, i32 %3 store i32 %cond, i32* @z1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: bteqz .+4 +; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}} %cmp1 = icmp ule i32 %1, %0 %cond5 = select i1 %cmp1, i32 %3, i32 %2 diff --git a/test/CodeGen/Mips/seteq.ll b/test/CodeGen/Mips/seteq.ll index da840c83a2b4..5fadf78d57a0 100644 --- a/test/CodeGen/Mips/seteq.ll +++ b/test/CodeGen/Mips/seteq.ll @@ -15,7 +15,7 @@ entry: store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/seteqz.ll b/test/CodeGen/Mips/seteqz.ll index d445be6aedb0..80dc3120a6a1 100644 --- a/test/CodeGen/Mips/seteqz.ll +++ b/test/CodeGen/Mips/seteqz.ll @@ -12,13 +12,13 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltiu ${{[0-9]+}}, 1 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 %1 = load i32* @j, align 4 %cmp1 = icmp eq i32 %1, 99 %conv2 = zext i1 %cmp1 to i32 store i32 %conv2, i32* @r2, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setge.ll b/test/CodeGen/Mips/setge.ll index 94b499bc31e9..8869eb8fc547 100644 --- a/test/CodeGen/Mips/setge.ll +++ b/test/CodeGen/Mips/setge.ll @@ -17,7 +17,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp sge i32 %0, %2 diff --git a/test/CodeGen/Mips/setgek.ll b/test/CodeGen/Mips/setgek.ll index b6bae09bcb5b..18a0fcf62130 100644 --- a/test/CodeGen/Mips/setgek.ll +++ b/test/CodeGen/Mips/setgek.ll @@ -12,7 +12,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slti ${{[0-9]+}}, -32768 -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ; 16: xor ${{[0-9]+}}, ${{[0-9]+}} ret void } diff --git a/test/CodeGen/Mips/setle.ll b/test/CodeGen/Mips/setle.ll index f36fb4392d76..2df6774c1fad 100644 --- a/test/CodeGen/Mips/setle.ll +++ b/test/CodeGen/Mips/setle.ll @@ -16,7 +16,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp sle i32 %2, %1 diff --git a/test/CodeGen/Mips/setlt.ll b/test/CodeGen/Mips/setlt.ll index 435be8e2334a..3dac74bf2e01 100644 --- a/test/CodeGen/Mips/setlt.ll +++ b/test/CodeGen/Mips/setlt.ll @@ -16,6 +16,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setltk.ll b/test/CodeGen/Mips/setltk.ll index c0b610e37784..ecebc7e578e1 100644 --- a/test/CodeGen/Mips/setltk.ll +++ b/test/CodeGen/Mips/setltk.ll @@ -15,6 +15,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: slti $[[REGISTER:[0-9]+]], 10 -; 16: move $[[REGISTER]], $t8 +; 16: move $[[REGISTER]], $24 ret void } diff --git a/test/CodeGen/Mips/setne.ll b/test/CodeGen/Mips/setne.ll index 6460c83c7b0b..9e66901e32b5 100644 --- a/test/CodeGen/Mips/setne.ll +++ b/test/CodeGen/Mips/setne.ll @@ -15,6 +15,6 @@ entry: store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, $[[REGISTER]] -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setuge.ll b/test/CodeGen/Mips/setuge.ll index ac72b66e9fb0..1c9b5bbe8114 100644 --- a/test/CodeGen/Mips/setuge.ll +++ b/test/CodeGen/Mips/setuge.ll @@ -16,7 +16,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp uge i32 %0, %2 diff --git a/test/CodeGen/Mips/setugt.ll b/test/CodeGen/Mips/setugt.ll index 328f0e3be34a..f10b47ae7178 100644 --- a/test/CodeGen/Mips/setugt.ll +++ b/test/CodeGen/Mips/setugt.ll @@ -16,6 +16,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setule.ll b/test/CodeGen/Mips/setule.ll index 792f2ae0fa29..a6d6bf064052 100644 --- a/test/CodeGen/Mips/setule.ll +++ b/test/CodeGen/Mips/setule.ll @@ -16,7 +16,7 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move $[[REGISTER:[0-9]+]], $t8 +; 16: move $[[REGISTER:[0-9]+]], $24 ; 16: xor $[[REGISTER]], ${{[0-9]+}} %2 = load i32* @m, align 4 %cmp1 = icmp ule i32 %2, %1 diff --git a/test/CodeGen/Mips/setult.ll b/test/CodeGen/Mips/setult.ll index 56d2e8daa3e0..00ee437a2ffe 100644 --- a/test/CodeGen/Mips/setult.ll +++ b/test/CodeGen/Mips/setult.ll @@ -16,6 +16,6 @@ entry: %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setultk.ll b/test/CodeGen/Mips/setultk.ll index 75b270ed8428..eb9edbaad7f8 100644 --- a/test/CodeGen/Mips/setultk.ll +++ b/test/CodeGen/Mips/setultk.ll @@ -14,7 +14,7 @@ entry: %cmp = icmp ult i32 %0, 10 %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 -; 16: sltiu $[[REGISTER:[0-9]+]], 10 -; 16: move $[[REGISTER]], $t8 +; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst +; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 72d30dc36912..b86d25e5e5e8 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -21,9 +21,9 @@ entry: ; PIC: jalr $25 ; PIC: lw $2, 0($2) -; STATIC: rdhwr $3, $29 ; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1) ; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1) +; STATIC: rdhwr $3, $29 ; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]] ; STATIC: lw $2, 0($[[R2]]) } diff --git a/test/CodeGen/Mips/vector-setcc.ll b/test/CodeGen/Mips/vector-setcc.ll new file mode 100644 index 000000000000..aeff4918c8bb --- /dev/null +++ b/test/CodeGen/Mips/vector-setcc.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=mipsel < %s + +@a = common global <4 x i32> zeroinitializer, align 16 +@b = common global <4 x i32> zeroinitializer, align 16 +@g0 = common global <4 x i32> zeroinitializer, align 16 + +define void @foo0() nounwind { +entry: + %0 = load <4 x i32>* @a, align 16 + %1 = load <4 x i32>* @b, align 16 + %cmp = icmp slt <4 x i32> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i32> + store <4 x i32> %sext, <4 x i32>* @g0, align 16 + ret void +} + |