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-rw-r--r--test/CodeGen/Mips/Fast-ISel/icmpbr1.ll3
-rw-r--r--test/CodeGen/Mips/Fast-ISel/pr40325.ll23
-rw-r--r--test/CodeGen/Mips/abiflags32.ll8
-rw-r--r--test/CodeGen/Mips/llvm-ir/fptosi.ll418
-rw-r--r--test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll63
-rw-r--r--test/CodeGen/Mips/pseudo-jump-fill.ll68
6 files changed, 582 insertions, 1 deletions
diff --git a/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll b/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
index ef8e1c2b0140..e44ab36532c5 100644
--- a/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
+++ b/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
@@ -17,7 +17,8 @@ bb0:
bb1:
; CHECK: # %bb.1: # %bb1
; CHECK-NEXT: lw $[[REG2:[0-9]+]], [[SPILL]]($sp) # 4-byte Folded Reload
-; CHECK-NEXT: bgtz $[[REG2]], $BB0_3
+; CHECK-NEXT: andi $[[REG3:[0-9]+]], $[[REG2]], 1
+; CHECK-NEXT: bgtz $[[REG3]], $BB0_3
br i1 %2, label %bb2, label %bb3
bb2:
; CHECK: $BB0_3: # %bb2
diff --git a/test/CodeGen/Mips/Fast-ISel/pr40325.ll b/test/CodeGen/Mips/Fast-ISel/pr40325.ll
new file mode 100644
index 000000000000..a9ce70fe8afc
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/pr40325.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -mcpu=mips32 < %s | FileCheck %s
+
+define void @test(i32 %x, i1* %p) nounwind {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: move $1, $4
+; CHECK-NEXT: andi $4, $4, 1
+; CHECK-NEXT: sb $4, 0($5)
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: bgtz $1, $BB0_1
+; CHECK-NEXT: nop
+; CHECK-NEXT: # %bb.1: # %foo
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
+ %y = and i32 %x, 1
+ %c = icmp eq i32 %y, 1
+ store i1 %c, i1* %p
+ br i1 %c, label %foo, label %foo
+
+foo:
+ ret void
+}
diff --git a/test/CodeGen/Mips/abiflags32.ll b/test/CodeGen/Mips/abiflags32.ll
index 39e2a90151e3..65201ec03814 100644
--- a/test/CodeGen/Mips/abiflags32.ll
+++ b/test/CodeGen/Mips/abiflags32.ll
@@ -1,6 +1,12 @@
; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck %s
; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr=fp64 %s -o - | FileCheck -check-prefix=CHECK-64 %s
; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n32 %s -o - | FileCheck -check-prefix=CHECK-64n %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 \
+; RUN: -mattr=soft-float %s -o - | FileCheck -check-prefix=SOFT %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32r6 \
+; RUN: -mattr=soft-float %s -o - | FileCheck -check-prefix=SOFT %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips64 \
+; RUN: -mattr=soft-float -target-abi n64 %s -o - | FileCheck -check-prefix=SOFT %s
; CHECK: .nan legacy
; We don't emit '.module fp=32' for compatibility with binutils 2.24 which
@@ -15,3 +21,5 @@
; We don't emit '.module fp=64' for compatibility with binutils 2.24 which
; doesn't accept .module.
; CHECK-64n-NOT: .module fp=64
+
+; SOFT: .module softfloat
diff --git a/test/CodeGen/Mips/llvm-ir/fptosi.ll b/test/CodeGen/Mips/llvm-ir/fptosi.ll
new file mode 100644
index 000000000000..03a0de746645
--- /dev/null
+++ b/test/CodeGen/Mips/llvm-ir/fptosi.ll
@@ -0,0 +1,418 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M32
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M32
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M32R2-FP64
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M32R2-SF
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M32R3R5
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M32R3R5
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M32R6
+; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M64
+; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M64
+; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M64
+; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=M64R6
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=MMR2-FP32
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=MMR2-FP64
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=MMR2-SF
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=MMR6
+; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\
+; RUN: FileCheck %s -check-prefixes=MMR6-SF
+
+; Test that fptosi can be matched for MIPS targets for various FPU
+; configurations
+
+define i32 @test1(float %t) {
+; M32-LABEL: test1:
+; M32: # %bb.0: # %entry
+; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
+; M32-NEXT: # <MCOperand Reg:147>
+; M32-NEXT: # <MCOperand Reg:159>>
+; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32-NEXT: # <MCOperand Reg:19>>
+; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32-NEXT: # <MCOperand Reg:321>
+; M32-NEXT: # <MCOperand Reg:147>>
+;
+; M32R2-FP64-LABEL: test1:
+; M32R2-FP64: # %bb.0: # %entry
+; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
+; M32R2-FP64-NEXT: # <MCOperand Reg:147>
+; M32R2-FP64-NEXT: # <MCOperand Reg:159>>
+; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
+; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32R2-FP64-NEXT: # <MCOperand Reg:321>
+; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
+;
+; M32R2-SF-LABEL: test1:
+; M32R2-SF: # %bb.0: # %entry
+; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
+; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
+; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
+; M32R2-SF-NEXT: # <MCOperand Reg:19>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:20>>
+; M32R2-SF-NEXT: .cfi_offset 31, -4
+; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL
+; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
+; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
+; M32R2-SF-NEXT: # <MCOperand Reg:21>
+; M32R2-SF-NEXT: # <MCOperand Reg:21>
+; M32R2-SF-NEXT: # <MCOperand Imm:0>>
+; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
+; M32R2-SF-NEXT: # <MCOperand Reg:19>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:20>>
+; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32R2-SF-NEXT: # <MCOperand Reg:19>>
+; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:24>>
+;
+; M32R3R5-LABEL: test1:
+; M32R3R5: # %bb.0: # %entry
+; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
+; M32R3R5-NEXT: # <MCOperand Reg:147>
+; M32R3R5-NEXT: # <MCOperand Reg:159>>
+; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32R3R5-NEXT: # <MCOperand Reg:19>>
+; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32R3R5-NEXT: # <MCOperand Reg:321>
+; M32R3R5-NEXT: # <MCOperand Reg:147>>
+;
+; M32R6-LABEL: test1:
+; M32R6: # %bb.0: # %entry
+; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
+; M32R6-NEXT: # <MCOperand Reg:147>
+; M32R6-NEXT: # <MCOperand Reg:159>>
+; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
+; M32R6-NEXT: # <MCOperand Reg:21>
+; M32R6-NEXT: # <MCOperand Reg:19>>
+; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32R6-NEXT: # <MCOperand Reg:321>
+; M32R6-NEXT: # <MCOperand Reg:147>>
+;
+; M64-LABEL: test1:
+; M64: # %bb.0: # %entry
+; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
+; M64-NEXT: # <MCOperand Reg:147>
+; M64-NEXT: # <MCOperand Reg:159>>
+; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M64-NEXT: # <MCOperand Reg:301>>
+; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M64-NEXT: # <MCOperand Reg:321>
+; M64-NEXT: # <MCOperand Reg:147>>
+;
+; M64R6-LABEL: test1:
+; M64R6: # %bb.0: # %entry
+; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
+; M64R6-NEXT: # <MCOperand Reg:147>
+; M64R6-NEXT: # <MCOperand Reg:159>>
+; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
+; M64R6-NEXT: # <MCOperand Reg:355>
+; M64R6-NEXT: # <MCOperand Reg:301>>
+; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M64R6-NEXT: # <MCOperand Reg:321>
+; M64R6-NEXT: # <MCOperand Reg:147>>
+;
+; MMR2-FP32-LABEL: test1:
+; MMR2-FP32: # %bb.0: # %entry
+; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:147>
+; MMR2-FP32-NEXT: # <MCOperand Reg:159>>
+; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
+; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:321>
+; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
+;
+; MMR2-FP64-LABEL: test1:
+; MMR2-FP64: # %bb.0: # %entry
+; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:147>
+; MMR2-FP64-NEXT: # <MCOperand Reg:159>>
+; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
+; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:321>
+; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
+;
+; MMR2-SF-LABEL: test1:
+; MMR2-SF: # %bb.0: # %entry
+; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
+; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
+; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:19>
+; MMR2-SF-NEXT: # <MCOperand Reg:20>
+; MMR2-SF-NEXT: # <MCOperand Imm:20>>
+; MMR2-SF-NEXT: .cfi_offset 31, -4
+; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL_MM
+; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
+; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
+; MMR2-SF-NEXT: # <MCOperand Reg:21>
+; MMR2-SF-NEXT: # <MCOperand Reg:21>
+; MMR2-SF-NEXT: # <MCOperand Imm:0>>
+; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:19>
+; MMR2-SF-NEXT: # <MCOperand Reg:20>
+; MMR2-SF-NEXT: # <MCOperand Imm:20>>
+; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: # <MCOperand Imm:24>>
+; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:19>>
+;
+; MMR6-LABEL: test1:
+; MMR6: # %bb.0: # %entry
+; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MMR6
+; MMR6-NEXT: # <MCOperand Reg:147>
+; MMR6-NEXT: # <MCOperand Reg:159>>
+; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
+; MMR6-NEXT: # <MCOperand Reg:321>
+; MMR6-NEXT: # <MCOperand Reg:147>>
+; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:19>>
+;
+; MMR6-SF-LABEL: test1:
+; MMR6-SF: # %bb.0: # %entry
+; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
+; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
+; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
+; MMR6-SF-NEXT: # <MCOperand Reg:19>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:20>>
+; MMR6-SF-NEXT: .cfi_offset 31, -4
+; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
+; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
+; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
+; MMR6-SF-NEXT: # <MCOperand Reg:19>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:20>>
+; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:24>>
+; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-SF-NEXT: # <MCOperand Reg:19>>
+entry:
+ %conv = fptosi float %t to i32
+ ret i32 %conv
+}
+
+define i32 @test2(double %t) {
+; M32-LABEL: test2:
+; M32: # %bb.0: # %entry
+; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
+; M32-NEXT: # <MCOperand Reg:147>
+; M32-NEXT: # <MCOperand Reg:133>>
+; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32-NEXT: # <MCOperand Reg:19>>
+; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32-NEXT: # <MCOperand Reg:321>
+; M32-NEXT: # <MCOperand Reg:147>>
+;
+; M32R2-FP64-LABEL: test2:
+; M32R2-FP64: # %bb.0: # %entry
+; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
+; M32R2-FP64-NEXT: # <MCOperand Reg:147>
+; M32R2-FP64-NEXT: # <MCOperand Reg:373>>
+; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
+; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32R2-FP64-NEXT: # <MCOperand Reg:321>
+; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
+;
+; M32R2-SF-LABEL: test2:
+; M32R2-SF: # %bb.0: # %entry
+; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
+; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
+; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
+; M32R2-SF-NEXT: # <MCOperand Reg:19>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:20>>
+; M32R2-SF-NEXT: .cfi_offset 31, -4
+; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL
+; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
+; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
+; M32R2-SF-NEXT: # <MCOperand Reg:21>
+; M32R2-SF-NEXT: # <MCOperand Reg:21>
+; M32R2-SF-NEXT: # <MCOperand Imm:0>>
+; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
+; M32R2-SF-NEXT: # <MCOperand Reg:19>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:20>>
+; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32R2-SF-NEXT: # <MCOperand Reg:19>>
+; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Reg:20>
+; M32R2-SF-NEXT: # <MCOperand Imm:24>>
+;
+; M32R3R5-LABEL: test2:
+; M32R3R5: # %bb.0: # %entry
+; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
+; M32R3R5-NEXT: # <MCOperand Reg:147>
+; M32R3R5-NEXT: # <MCOperand Reg:133>>
+; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M32R3R5-NEXT: # <MCOperand Reg:19>>
+; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32R3R5-NEXT: # <MCOperand Reg:321>
+; M32R3R5-NEXT: # <MCOperand Reg:147>>
+;
+; M32R6-LABEL: test2:
+; M32R6: # %bb.0: # %entry
+; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
+; M32R6-NEXT: # <MCOperand Reg:147>
+; M32R6-NEXT: # <MCOperand Reg:373>>
+; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
+; M32R6-NEXT: # <MCOperand Reg:21>
+; M32R6-NEXT: # <MCOperand Reg:19>>
+; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M32R6-NEXT: # <MCOperand Reg:321>
+; M32R6-NEXT: # <MCOperand Reg:147>>
+;
+; M64-LABEL: test2:
+; M64: # %bb.0: # %entry
+; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
+; M64-NEXT: # <MCOperand Reg:147>
+; M64-NEXT: # <MCOperand Reg:373>>
+; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
+; M64-NEXT: # <MCOperand Reg:301>>
+; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M64-NEXT: # <MCOperand Reg:321>
+; M64-NEXT: # <MCOperand Reg:147>>
+;
+; M64R6-LABEL: test2:
+; M64R6: # %bb.0: # %entry
+; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
+; M64R6-NEXT: # <MCOperand Reg:147>
+; M64R6-NEXT: # <MCOperand Reg:373>>
+; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
+; M64R6-NEXT: # <MCOperand Reg:355>
+; M64R6-NEXT: # <MCOperand Reg:301>>
+; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
+; M64R6-NEXT: # <MCOperand Reg:321>
+; M64R6-NEXT: # <MCOperand Reg:147>>
+;
+; MMR2-FP32-LABEL: test2:
+; MMR2-FP32: # %bb.0: # %entry
+; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:147>
+; MMR2-FP32-NEXT: # <MCOperand Reg:133>>
+; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
+; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:321>
+; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
+;
+; MMR2-FP64-LABEL: test2:
+; MMR2-FP64: # %bb.0: # %entry
+; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #{{[0-9]+}} CVT_W_D64_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:147>
+; MMR2-FP64-NEXT: # <MCOperand Reg:373>>
+; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
+; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:321>
+; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
+;
+; MMR2-SF-LABEL: test2:
+; MMR2-SF: # %bb.0: # %entry
+; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
+; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
+; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:19>
+; MMR2-SF-NEXT: # <MCOperand Reg:20>
+; MMR2-SF-NEXT: # <MCOperand Imm:20>>
+; MMR2-SF-NEXT: .cfi_offset 31, -4
+; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL_MM
+; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
+; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
+; MMR2-SF-NEXT: # <MCOperand Reg:21>
+; MMR2-SF-NEXT: # <MCOperand Reg:21>
+; MMR2-SF-NEXT: # <MCOperand Imm:0>>
+; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:19>
+; MMR2-SF-NEXT: # <MCOperand Reg:20>
+; MMR2-SF-NEXT: # <MCOperand Imm:20>>
+; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: # <MCOperand Imm:24>>
+; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:19>>
+;
+; MMR6-LABEL: test2:
+; MMR6: # %bb.0: # %entry
+; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D_MMR6
+; MMR6-NEXT: # <MCOperand Reg:147>
+; MMR6-NEXT: # <MCOperand Reg:373>>
+; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
+; MMR6-NEXT: # <MCOperand Reg:321>
+; MMR6-NEXT: # <MCOperand Reg:147>>
+; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:19>>
+;
+; MMR6-SF-LABEL: test2:
+; MMR6-SF: # %bb.0: # %entry
+; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
+; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
+; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
+; MMR6-SF-NEXT: # <MCOperand Reg:19>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:20>>
+; MMR6-SF-NEXT: .cfi_offset 31, -4
+; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
+; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
+; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
+; MMR6-SF-NEXT: # <MCOperand Reg:19>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:20>>
+; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Reg:20>
+; MMR6-SF-NEXT: # <MCOperand Imm:24>>
+; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR6-SF-NEXT: # <MCOperand Reg:19>>
+entry:
+ %conv = fptosi double %t to i32
+ ret i32 %conv
+}
diff --git a/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll b/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
new file mode 100644
index 000000000000..3f86bd24f34f
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst < %s |\
+; RUN: FileCheck %s -check-prefixes=MMR2
+; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips -asm-show-inst < %s |\
+; RUN: FileCheck %s -check-prefixes=MMR2-DSP
+
+define i64 @test(i32 signext %a, i32 signext %b) {
+; MMR2-LABEL: test:
+; MMR2: # %bb.0: # %entry
+; MMR2-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
+; MMR2-NEXT: # <MCOperand Reg:321>
+; MMR2-NEXT: # <MCOperand Imm:0>>
+; MMR2-NEXT: li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
+; MMR2-NEXT: # <MCOperand Reg:322>
+; MMR2-NEXT: # <MCOperand Imm:1>>
+; MMR2-NEXT: mtlo $3 # <MCInst #{{[0-9]+}} MTLO_MM
+; MMR2-NEXT: # <MCOperand Reg:322>>
+; MMR2-NEXT: mthi $2 # <MCInst #{{[0-9]+}} MTHI_MM
+; MMR2-NEXT: # <MCOperand Reg:321>>
+; MMR2-NEXT: madd $4, $5 # <MCInst #{{[0-9]+}} MADD
+; MMR2-NEXT: # <MCOperand Reg:22>
+; MMR2-NEXT: # <MCOperand Reg:23>>
+; MMR2-NEXT: mflo16 $2 # <MCInst #{{[0-9]+}} MFLO16_MM
+; MMR2-NEXT: # <MCOperand Reg:321>>
+; MMR2-NEXT: mfhi16 $3 # <MCInst #{{[0-9]+}} MFHI16_MM
+; MMR2-NEXT: # <MCOperand Reg:322>>
+; MMR2-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
+; MMR2-NEXT: # <MCOperand Reg:19>>
+;
+; MMR2-DSP-LABEL: test:
+; MMR2-DSP: # %bb.0: # %entry
+; MMR2-DSP-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
+; MMR2-DSP-NEXT: # <MCOperand Reg:321>
+; MMR2-DSP-NEXT: # <MCOperand Imm:0>>
+; MMR2-DSP-NEXT: li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
+; MMR2-DSP-NEXT: # <MCOperand Reg:322>
+; MMR2-DSP-NEXT: # <MCOperand Imm:1>>
+; MMR2-DSP-NEXT: mtlo $3, $ac0 # <MCInst #{{[0-9]+}} MTLO_DSP
+; MMR2-DSP-NEXT: # <MCOperand Reg:291>
+; MMR2-DSP-NEXT: # <MCOperand Reg:322>>
+; MMR2-DSP-NEXT: mthi $2, $ac0 # <MCInst #{{[0-9]+}} MTHI_DSP
+; MMR2-DSP-NEXT: # <MCOperand Reg:253>
+; MMR2-DSP-NEXT: # <MCOperand Reg:321>>
+; MMR2-DSP-NEXT: madd $ac0, $4, $5 # <MCInst #{{[0-9]+}} MADD_DSP
+; MMR2-DSP-NEXT: # <MCOperand Reg:26>
+; MMR2-DSP-NEXT: # <MCOperand Reg:22>
+; MMR2-DSP-NEXT: # <MCOperand Reg:23>
+; MMR2-DSP-NEXT: # <MCOperand Reg:26>>
+; MMR2-DSP-NEXT: mflo $2, $ac0 # <MCInst #{{[0-9]+}} MFLO_DSP
+; MMR2-DSP-NEXT: # <MCOperand Reg:321>
+; MMR2-DSP-NEXT: # <MCOperand Reg:26>>
+; MMR2-DSP-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
+; MMR2-DSP-NEXT: # <MCOperand Reg:19>>
+; MMR2-DSP-NEXT: mfhi $3, $ac0 # <MCInst #{{[0-9]+}} MFHI_DSP
+; MMR2-DSP-NEXT: # <MCOperand Reg:322>
+; MMR2-DSP-NEXT: # <MCOperand Reg:26>>
+entry:
+ %conv = sext i32 %a to i64
+ %conv1 = sext i32 %b to i64
+ %mul = mul nsw i64 %conv, %conv1
+ %add = add nsw i64 %mul, 1
+ ret i64 %add
+}
diff --git a/test/CodeGen/Mips/pseudo-jump-fill.ll b/test/CodeGen/Mips/pseudo-jump-fill.ll
new file mode 100644
index 000000000000..31f077d57a93
--- /dev/null
+++ b/test/CodeGen/Mips/pseudo-jump-fill.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s
+
+; Test that the delay slot filler correctly handles indirect branches for
+; microMIPS in regard to incorrectly using 16bit instructions in delay slots of
+; 32bit instructions.
+
+define i32 @test(i32 signext %x, i32 signext %c) {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $2, %hi(_gp_disp)
+; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
+; CHECK-NEXT: addiur2 $5, $5, -1
+; CHECK-NEXT: sltiu $1, $5, 4
+; CHECK-NEXT: beqz $1, $BB0_3
+; CHECK-NEXT: addu $3, $2, $25
+; CHECK-NEXT: $BB0_1: # %entry
+; CHECK-NEXT: li16 $2, 0
+; CHECK-NEXT: sll16 $5, $5, 2
+; CHECK-NEXT: lw $6, %got($JTI0_0)($3)
+; CHECK-NEXT: addu16 $5, $5, $6
+; CHECK-NEXT: lw $5, %lo($JTI0_0)($5)
+; CHECK-NEXT: addu16 $3, $5, $3
+; CHECK-NEXT: jr $3
+; CHECK-NEXT: nop
+; CHECK-NEXT: $BB0_2: # %sw.bb2
+; CHECK-NEXT: addiur2 $2, $4, 1
+; CHECK-NEXT: jrc $ra
+; CHECK-NEXT: $BB0_3:
+; CHECK-NEXT: move $2, $4
+; CHECK-NEXT: jrc $ra
+; CHECK-NEXT: $BB0_4: # %sw.bb3
+; CHECK-NEXT: addius5 $4, 2
+; CHECK-NEXT: move $2, $4
+; CHECK-NEXT: jrc $ra
+; CHECK-NEXT: $BB0_5: # %sw.bb5
+; CHECK-NEXT: addius5 $4, 3
+; CHECK-NEXT: move $2, $4
+; CHECK-NEXT: $BB0_6: # %for.cond.cleanup
+; CHECK-NEXT: jrc $ra
+entry:
+ switch i32 %c, label %sw.epilog [
+ i32 4, label %sw.bb5
+ i32 1, label %for.cond.cleanup
+ i32 2, label %sw.bb2
+ i32 3, label %sw.bb3
+ ]
+
+sw.bb2:
+ %add = add nsw i32 %x, 1
+ br label %sw.epilog
+
+sw.bb3:
+ %add4 = add nsw i32 %x, 2
+ br label %sw.epilog
+
+sw.bb5:
+ %add6 = add nsw i32 %x, 3
+ br label %sw.epilog
+
+sw.epilog:
+ %a.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add, %sw.bb2 ], [ %x, %entry ]
+ br label %for.cond.cleanup
+
+for.cond.cleanup:
+ %a.028 = phi i32 [ %a.0, %sw.epilog ], [ 0, %entry ]
+ ret i32 %a.028
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-10 05:26:05 +0000