diff options
Diffstat (limited to 'test/CodeGen/PowerPC/anon_aggr.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/anon_aggr.ll | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll index 9b32a8f55f34..2c1735844477 100644 --- a/test/CodeGen/PowerPC/anon_aggr.ll +++ b/test/CodeGen/PowerPC/anon_aggr.ll @@ -1,6 +1,6 @@ ; RUN: llc -verify-machineinstrs -O0 -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s -; RUN: llc -verify-machineinstrs -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s +; RUN: llc -verify-machineinstrs -O0 -mcpu=970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s ; Test case for PR 14779: anonymous aggregates are not handled correctly. ; Darwin bug report PR 15821 is similar. @@ -22,7 +22,7 @@ unequal: ; CHECK-LABEL: func1: ; CHECK: cmpld {{([0-9]+,)?}}4, 5 -; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]] +; CHECK-DAG: std 3, -[[OFFSET1:[0-9]+]] ; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) @@ -31,19 +31,19 @@ unequal: ; DARWIN32: mr ; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] -; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]] +; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]] ; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]] ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]] -; DARWIN32: lwz r3, -[[OFFSET1]] ; DARWIN32: lwz r3, -[[OFFSET2]] +; DARWIN32: lwz r3, -[[OFFSET1]] ; DARWIN64: _func1: ; DARWIN64: mr ; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] -; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]] -; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]] -; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] +; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]] +; DARWIN64: std r[[REG1]], -[[OFFSET2:[0-9]+]] +; DARWIN64: std r[[REG2]], -[[OFFSET1:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] ; DARWIN64: ld r3, -[[OFFSET2]] @@ -61,19 +61,19 @@ unequal: ret i8* %array2_ptr } ; CHECK-LABEL: func2: -; CHECK: cmpld {{([0-9]+,)?}}4, 6 +; CHECK-DAG: cmpld {{([0-9]+,)?}}4, 6 ; CHECK-DAG: std 6, 72(1) ; CHECK-DAG: std 5, 64(1) ; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]] -; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] +; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) ; DARWIN32-LABEL: _func2 -; DARWIN32-DAG: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36 -; DARWIN32-DAG: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]]) ; DARWIN32: mr +; DARWIN32: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36 ; DARWIN32: mr r[[REG7:[0-9]+]], r5 +; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]]) ; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r5, r[[REG2]] ; DARWIN32-DAG: stw r[[REG7]], -[[OFFSET1:[0-9]+]] ; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET2:[0-9]+]] @@ -82,9 +82,9 @@ unequal: ; DARWIN64: _func2: -; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1) ; DARWIN64: mr ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] +; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1) ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]] ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] @@ -107,9 +107,9 @@ unequal: } ; CHECK-LABEL: func3: -; CHECK: cmpld {{([0-9]+,)?}}4, 6 -; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]](1) -; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]](1) +; CHECK-DAG: cmpld {{([0-9]+,)?}}3, 4 +; CHECK-DAG: std 3, -[[OFFSET2:[0-9]+]](1) +; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) @@ -127,13 +127,13 @@ unequal: ; DARWIN32-DAG: lwz r3, -[[OFFSET2:[0-9]+]] ; DARWIN64: _func3: -; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1) -; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1) +; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 72(r1) +; DARWIN64-DAG: ld r[[REG4:[0-9]+]], 56(r1) ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] -; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] -; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]] -; DARWIN64: ld r3, -[[OFFSET2]] +; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] +; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] +; DARWIN64: ld r3, -[[OFFSET2]] define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4, @@ -152,31 +152,31 @@ unequal: } ; CHECK-LABEL: func4: -; CHECK: ld [[REG3:[0-9]+]], 136(1) -; CHECK: ld [[REG2:[0-9]+]], 120(1) -; CHECK: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]] -; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1) +; CHECK-DAG: ld [[REG2:[0-9]+]], 120(1) +; CHECK-DAG: ld [[REG3:[0-9]+]], 136(1) +; CHECK-DAG: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]] ; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1) +; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) ; DARWIN32: _func4: ; DARWIN32: lwz r[[REG4:[0-9]+]], 96(r1) ; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100 -; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1) ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]] +; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1) ; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] -; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]] -; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]] -; DARWIN32: lwz r[[REG1]], -[[OFFSET1]] -; DARWIN32: lwz r[[REG1]], -[[OFFSET2]] +; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET1:[0-9]+]] +; DARWIN32-DAG: stw r[[REG3]], -[[OFFSET2:[0-9]+]] +; DARWIN32: lwz r3, -[[OFFSET1]] +; DARWIN32: lwz r3, -[[OFFSET2]] ; DARWIN64: _func4: ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1) -; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1) -; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]] +; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 136(r1) +; DARWIN64-DAG: mr r[[REG4:[0-9]+]], r[[REG2]] ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG2]], r[[REG3]] -; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]] +; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] ; DARWIN64: ld r3, -[[OFFSET2]] |