diff options
Diffstat (limited to 'test/CodeGen/X86/GlobalISel/select-add-v128.mir')
-rw-r--r-- | test/CodeGen/X86/GlobalISel/select-add-v128.mir | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/test/CodeGen/X86/GlobalISel/select-add-v128.mir b/test/CodeGen/X86/GlobalISel/select-add-v128.mir index a39702340bc2..4f7b6ec72d52 100644 --- a/test/CodeGen/X86/GlobalISel/select-add-v128.mir +++ b/test/CodeGen/X86/GlobalISel/select-add-v128.mir @@ -32,19 +32,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128 } -# AVX512VL-NEXT: - { id: 1, class: vr128 } -# AVX512VL-NEXT: - { id: 2, class: vr128 } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -74,19 +74,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128 } -# AVX512VL-NEXT: - { id: 1, class: vr128 } -# AVX512VL-NEXT: - { id: 2, class: vr128 } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -116,19 +116,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -158,19 +158,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } |