diff options
Diffstat (limited to 'test/CodeGen')
37 files changed, 1384 insertions, 226 deletions
diff --git a/test/CodeGen/2008-07-17-no-emit-on-error.c b/test/CodeGen/2008-07-17-no-emit-on-error.c index 855ede7ab02b..2cae57b3d89f 100644 --- a/test/CodeGen/2008-07-17-no-emit-on-error.c +++ b/test/CodeGen/2008-07-17-no-emit-on-error.c @@ -1,9 +1,9 @@ // RUN: rm -f %t1.bc // RUN: %clang_cc1 -DPASS %s -emit-llvm-bc -o %t1.bc -// RUN: test -f %t1.bc +// RUN: opt %t1.bc -disable-output // RUN: rm -f %t1.bc // RUN: not %clang_cc1 %s -emit-llvm-bc -o %t1.bc -// RUN: not test -f %t1.bc +// RUN: not opt %t1.bc -disable-output void f() { } diff --git a/test/CodeGen/altivec.c b/test/CodeGen/altivec.c index 9e38df50930c..ec1efd9ba197 100644 --- a/test/CodeGen/altivec.c +++ b/test/CodeGen/altivec.c @@ -1,4 +1,31 @@ // RUN: %clang_cc1 -faltivec -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// CHECK: @test0 = global <4 x i32> <i32 1, i32 1, i32 1, i32 1> -vector int test0 = (vector int)(1); +// Check initialization + +vector int test0 = (vector int)(1); // CHECK: @test0 = global <4 x i32> <i32 1, i32 1, i32 1, i32 1> +vector float test1 = (vector float)(1.0); // CHECK: @test1 = global <4 x float> <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}> + +void test2() +{ + vector int vi; + vector float vf; + vi = (vector int)(1); // CHECK: <i32 1, i32 1, i32 1, i32 1> + vf = (vector float)(1.0); // CHECK: <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}> + vi = (vector int)(1, 2, 3, 4); // CHECK: <i32 1, i32 2, i32 3, i32 4> + vi = (vector int)(1, 2, 3, 4, 5); // CHECK: <i32 1, i32 2, i32 3, i32 4> + + vi = (vector int){1}; // CHECK: <i32 1, i32 0, i32 0, i32 0> + vi = (vector int){1, 2}; // CHECK: <i32 1, i32 2, i32 0, i32 0> + vi = (vector int){1, 2, 3, 4}; // CHECK: <i32 1, i32 2, i32 3, i32 4> + +} + +// Check pre/post increment/decrement +void test3() { + vector int vi; + vi++; // CHECK: add nsw <4 x i32> {{.*}} <i32 1, i32 1, i32 1, i32 1> + vector unsigned int vui; + --vui; // CHECK: add <4 x i32> {{.*}} <i32 -1, i32 -1, i32 -1, i32 -1> + vector float vf; + vf++; // CHECK: fadd <4 x float> {{.*}} <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}> +} diff --git a/test/CodeGen/arm-clear.c b/test/CodeGen/arm-clear.c new file mode 100644 index 000000000000..eda64ce99ee4 --- /dev/null +++ b/test/CodeGen/arm-clear.c @@ -0,0 +1,21 @@ +// RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -w -o - %s | FileCheck %s + +void clear0(void *ptr) { + // CHECK: clear0 + // CHECK-NOT: load i8** + __clear_cache(); +} + +void clear1(void *ptr) { + // CHECK: clear1 + // CHECK: load i8** + // CHECK-NOT: load i8** + __clear_cache(ptr); +} + +void clear2(void *ptr, void *ptr2) { + // CHECK: clear2 + // CHECK: load i8** + // CHECK: load i8** + __clear_cache(ptr, ptr2); +} diff --git a/test/CodeGen/arm-pcs.c b/test/CodeGen/arm-pcs.c new file mode 100644 index 000000000000..d722f84cebd7 --- /dev/null +++ b/test/CodeGen/arm-pcs.c @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -triple arm-none-linux-gnueabi -emit-llvm -w -o - < %s | FileCheck %s +typedef int __attribute__((pcs("aapcs"))) (*aapcs_fn)(void); +typedef int __attribute__((pcs("aapcs-vfp"))) (*aapcs_vfp_fn)(void); + +aapcs_fn bar; + +int foo(aapcs_vfp_fn baz) { +// CHECK: define i32 @foo +// CHECK: call arm_aapcscc +// CHECK: call arm_aapcs_vfpcc + return bar() + baz(); +} diff --git a/test/CodeGen/arm-vector-align.c b/test/CodeGen/arm-vector-align.c new file mode 100644 index 000000000000..c1119cb5b736 --- /dev/null +++ b/test/CodeGen/arm-vector-align.c @@ -0,0 +1,19 @@ +// RUN: %clang_cc1 -triple thumbv7-apple-darwin \ +// RUN: -target-abi apcs-gnu \ +// RUN: -target-cpu cortex-a8 \ +// RUN: -mfloat-abi soft \ +// RUN: -target-feature +soft-float-abi \ +// RUN: -ffreestanding \ +// RUN: -emit-llvm -w -o - %s | FileCheck %s + +#include <arm_neon.h> + +// Radar 9311427: Check that alignment specifier is used in Neon load/store +// intrinsics. +typedef float AlignedAddr __attribute__ ((aligned (16))); +void t1(AlignedAddr *addr1, AlignedAddr *addr2) { +// CHECK: call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %{{.*}}, i32 16) + float32x4_t a = vld1q_f32(addr1); +// CHECK: call void @llvm.arm.neon.vst1.v4f32(i8* %{{.*}}, <4 x float> %{{.*}}, i32 16) + vst1q_f32(addr2, a); +} diff --git a/test/CodeGen/atomic.c b/test/CodeGen/atomic.c index 4a7c13f03c41..8ce2d96043f2 100644 --- a/test/CodeGen/atomic.c +++ b/test/CodeGen/atomic.c @@ -44,6 +44,11 @@ int atomic(void) { // CHECK: call i32 @llvm.atomic.swap.i32.p0i32(i32* %val, i32 7) // CHECK: call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + old = __sync_swap(&val, 8); + // CHECK: call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + // CHECK: call i32 @llvm.atomic.swap.i32.p0i32(i32* %val, i32 8) + // CHECK: call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + old = __sync_val_compare_and_swap(&val, 4, 1976); // CHECK: call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) // CHECK: call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %val, i32 4, i32 1976) diff --git a/test/CodeGen/attr-availability.c b/test/CodeGen/attr-availability.c new file mode 100644 index 000000000000..6f9c045a3f17 --- /dev/null +++ b/test/CodeGen/attr-availability.c @@ -0,0 +1,31 @@ +// RUN: %clang_cc1 -fvisibility hidden "-triple" "x86_64-apple-darwin8.0.0" -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-10_4 %s +// RUN: %clang_cc1 -fvisibility hidden "-triple" "x86_64-apple-darwin9.0.0" -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-10_5 %s +// RUN: %clang_cc1 -fvisibility hidden "-triple" "x86_64-apple-darwin10.0.0" -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-10_6 %s + +// CHECK-10_4: define hidden void @f2 +// CHECK-10_5: define hidden void @f2 +// CHECK-10_6: define hidden void @f2 +void f2(); +void f2() { } + +// CHECK-10_4: define void @f3 +// CHECK-10_5: define void @f3 +// CHECK-10_6: define void @f3 +void f3() __attribute__((availability(macosx,introduced=10.5))); +void f3() { } + +// CHECK-10_4: declare extern_weak void @f0 +// CHECK-10_5: declare void @f0 +// CHECK-10_6: declare void @f0 +void f0() __attribute__((availability(macosx,introduced=10.5))); + +// CHECK-10_4: declare extern_weak void @f1 +// CHECK-10_5: declare extern_weak void @f1 +// CHECK-10_6: declare void @f1 +void f1() __attribute__((availability(macosx,introduced=10.6))); + +void test() { + f0(); + f1(); + f2(); +} diff --git a/test/CodeGen/block-byref-aggr.c b/test/CodeGen/block-byref-aggr.c new file mode 100644 index 000000000000..3027df04861c --- /dev/null +++ b/test/CodeGen/block-byref-aggr.c @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 %s -emit-llvm -o - -fblocks -triple x86_64-apple-darwin10 | FileCheck %s +// rdar://9309454 + +typedef struct { int v; } RetType; + +RetType func(); + +int main () { + __attribute__((__blocks__(byref))) RetType a = {100}; + + a = func(); +} +// CHECK: [[C1:%.*]] = call i32 (...)* @func() +// CHECK-NEXT: [[CO:%.*]] = getelementptr +// CHECK-NEXT: store i32 [[C1]], i32* [[CO]] +// CHECK-NEXT: [[FORWARDING:%.*]] = getelementptr inbounds [[BR:%.*]]* [[A:%.*]], i32 0, i32 1 +// CHECK-NEXT: [[O:%.*]] = load [[BR]]** [[FORWARDING]] diff --git a/test/CodeGen/builtin-attributes.c b/test/CodeGen/builtin-attributes.c index afde3fab8481..822b8eecf7d7 100644 --- a/test/CodeGen/builtin-attributes.c +++ b/test/CodeGen/builtin-attributes.c @@ -10,3 +10,8 @@ void f0() { void f1() { exit(1); } + +// CHECK: call i8* @strstr{{.*}} nounwind +char* f2(char* a, char* b) { + return __builtin_strstr(a, b); +} diff --git a/test/CodeGen/builtin-expect.c b/test/CodeGen/builtin-expect.c index 8f02c4da78a4..88479d90a092 100644 --- a/test/CodeGen/builtin-expect.c +++ b/test/CodeGen/builtin-expect.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s int x; int y(void); @@ -9,3 +9,13 @@ void FUNC() { foo (); } +// rdar://9330105 +void isigprocmask(void); +long bar(); + +int main() { + (void) __builtin_expect((isigprocmask(), 0), bar()); +} + +// CHECK: call void @isigprocmask() +// CHECK: [[C:%.*]] = call i64 (...)* @bar() diff --git a/test/CodeGen/builtin-memfns.c b/test/CodeGen/builtin-memfns.c index e8c407fd6f27..fb4d7200752d 100644 --- a/test/CodeGen/builtin-memfns.c +++ b/test/CodeGen/builtin-memfns.c @@ -1,12 +1,13 @@ // RUN: %clang_cc1 -triple i386-pc-linux-gnu -emit-llvm < %s| FileCheck %s +// CHECK: @test1 // CHECK: call void @llvm.memset.p0i8.i32 // CHECK: call void @llvm.memset.p0i8.i32 // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32 // CHECK: call void @llvm.memmove.p0i8.p0i8.i32 // CHECK-NOT: __builtin // CHECK: ret -int main(int argc, char **argv) { +int test1(int argc, char **argv) { unsigned char a = 0x11223344; unsigned char b = 0x11223344; __builtin_bzero(&a, sizeof(a)); @@ -15,3 +16,35 @@ int main(int argc, char **argv) { __builtin_memmove(&a, &b, sizeof(a)); return 0; } + +// rdar://9289468 + +// CHECK: @test2 +// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32 +char* test2(char* a, char* b) { + return __builtin_memcpy(a, b, 4); +} + +// CHECK: @test3 +// CHECK: call void @llvm.memset +void test3(char *P) { + __builtin___memset_chk(P, 42, 128, 128); +} + +// CHECK: @test4 +// CHECK: call void @llvm.memcpy +void test4(char *P, char *Q) { + __builtin___memcpy_chk(P, Q, 128, 128); +} + +// CHECK: @test5 +// CHECK: call void @llvm.memmove +void test5(char *P, char *Q) { + __builtin___memmove_chk(P, Q, 128, 128); +} + +// CHECK: @test6 +// CHECK: call void @llvm.memcpy +int test6(char *X) { + return __builtin___memcpy_chk(X, X, 42, 42) != 0; +} diff --git a/test/CodeGen/builtinmemcpy.c b/test/CodeGen/builtinmemcpy.c deleted file mode 100644 index 93253c5a8a48..000000000000 --- a/test/CodeGen/builtinmemcpy.c +++ /dev/null @@ -1,3 +0,0 @@ -// RUN: %clang_cc1 -emit-llvm < %s -o - | grep "llvm.memcpy" - -char* x(char* a, char* b) {return __builtin_memcpy(a, b, 4);} diff --git a/test/CodeGen/builtins-ppc-altivec.c b/test/CodeGen/builtins-ppc-altivec.c index e03e69c28cfe..586f1133a8dc 100644 --- a/test/CodeGen/builtins-ppc-altivec.c +++ b/test/CodeGen/builtins-ppc-altivec.c @@ -1789,23 +1789,23 @@ void test6() { /* vec_lvlx */ res_vsc = vec_lvlx(0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vsc = vec_lvlx(0, &vsc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vuc = vec_lvlx(0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vuc = vec_lvlx(0, &vuc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbc = vec_lvlx(0, &vbc); // CHECK: @llvm.ppc.altivec.lvx @@ -1814,23 +1814,23 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm res_vs = vec_lvlx(0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vs = vec_lvlx(0, &vs); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vus = vec_lvlx(0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vus = vec_lvlx(0, &vus); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbs = vec_lvlx(0, &vbs); // CHECK: @llvm.ppc.altivec.lvx @@ -1844,23 +1844,23 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm res_vi = vec_lvlx(0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vi = vec_lvlx(0, &vi); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vui = vec_lvlx(0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vui = vec_lvlx(0, &vui); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbi = vec_lvlx(0, &vbi); // CHECK: @llvm.ppc.altivec.lvx @@ -1869,29 +1869,29 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm res_vf = vec_lvlx(0, &vf); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm /* vec_lvlxl */ res_vsc = vec_lvlxl(0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vsc = vec_lvlxl(0, &vsc); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vuc = vec_lvlxl(0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vuc = vec_lvlxl(0, &vuc); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbc = vec_lvlxl(0, &vbc); // CHECK: @llvm.ppc.altivec.lvxl @@ -1900,23 +1900,23 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm res_vs = vec_lvlxl(0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vs = vec_lvlxl(0, &vs); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vus = vec_lvlxl(0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vus = vec_lvlxl(0, &vus); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbs = vec_lvlxl(0, &vbs); // CHECK: @llvm.ppc.altivec.lvxl @@ -1930,23 +1930,23 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm res_vi = vec_lvlxl(0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vi = vec_lvlxl(0, &vi); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vui = vec_lvlxl(0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vui = vec_lvlxl(0, &vui); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbi = vec_lvlxl(0, &vbi); // CHECK: @llvm.ppc.altivec.lvxl @@ -1955,29 +1955,29 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm res_vf = vec_lvlxl(0, &vf); // CHECK: @llvm.ppc.altivec.lvxl - // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm /* vec_lvrx */ - res_vsc = vec_lvrx(0, ¶m_sc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vsc = vec_lvrx(0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vsc = vec_lvrx(0, &vsc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vsc = vec_lvrx(0, &vsc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vuc = vec_lvrx(0, ¶m_uc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vuc = vec_lvrx(0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vuc = vec_lvrx(0, &vuc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vuc = vec_lvrx(0, &vuc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbc = vec_lvrx(0, &vbc); // CHECK: store <16 x i8> zeroinitializer @@ -1985,24 +1985,24 @@ void test6() { // CHECK: @llvm.ppc.altivec.lvsl // CHECK: @llvm.ppc.altivec.vperm - res_vs = vec_lvrx(0, ¶m_s); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vs = vec_lvrx(0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vs = vec_lvrx(0, &vs); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vs = vec_lvrx(0, &vs); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vus = vec_lvrx(0, ¶m_us); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vus = vec_lvrx(0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vus = vec_lvrx(0, &vus); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vus = vec_lvrx(0, &vus); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbs = vec_lvrx(0, &vbs); // CHECK: store <8 x i16> zeroinitializer @@ -2015,24 +2015,24 @@ void test6() { // CHECK: @llvm.ppc.altivec.lvsl // CHECK: @llvm.ppc.altivec.vperm - res_vi = vec_lvrx(0, ¶m_i); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vi = vec_lvrx(0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vi = vec_lvrx(0, &vi); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vi = vec_lvrx(0, &vi); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vui = vec_lvrx(0, ¶m_ui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vui = vec_lvrx(0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vui = vec_lvrx(0, &vui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vui = vec_lvrx(0, &vui); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbi = vec_lvrx(0, &vbi); // CHECK: store <4 x i32> zeroinitializer @@ -2040,30 +2040,30 @@ void test6() { // CHECK: @llvm.ppc.altivec.lvsl // CHECK: @llvm.ppc.altivec.vperm - res_vf = vec_lvrx(0, &vf); // CHECK: store <4 x float> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + res_vf = vec_lvrx(0, &vf); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm /* vec_lvrxl */ - res_vsc = vec_lvrxl(0, ¶m_sc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vsc = vec_lvrxl(0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vsc = vec_lvrxl(0, &vsc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vsc = vec_lvrxl(0, &vsc); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vuc = vec_lvrxl(0, ¶m_uc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vuc = vec_lvrxl(0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vuc = vec_lvrxl(0, &vuc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vuc = vec_lvrxl(0, &vuc); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbc = vec_lvrxl(0, &vbc); // CHECK: store <16 x i8> zeroinitializer @@ -2071,24 +2071,24 @@ void test6() { // CHECK: @llvm.ppc.altivec.lvsl // CHECK: @llvm.ppc.altivec.vperm - res_vs = vec_lvrxl(0, ¶m_s); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vs = vec_lvrxl(0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vs = vec_lvrxl(0, &vs); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vs = vec_lvrxl(0, &vs); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vus = vec_lvrxl(0, ¶m_us); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vus = vec_lvrxl(0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vus = vec_lvrxl(0, &vus); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vus = vec_lvrxl(0, &vus); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbs = vec_lvrxl(0, &vbs); // CHECK: store <8 x i16> zeroinitializer @@ -2101,24 +2101,24 @@ void test6() { // CHECK: @llvm.ppc.altivec.lvsl // CHECK: @llvm.ppc.altivec.vperm - res_vi = vec_lvrxl(0, ¶m_i); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vi = vec_lvrxl(0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vi = vec_lvrxl(0, &vi); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vi = vec_lvrxl(0, &vi); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vui = vec_lvrxl(0, ¶m_ui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vui = vec_lvrxl(0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm - res_vui = vec_lvrxl(0, &vui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vui = vec_lvrxl(0, &vui); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm res_vbi = vec_lvrxl(0, &vbi); // CHECK: store <4 x i32> zeroinitializer @@ -2126,39 +2126,39 @@ void test6() { // CHECK: @llvm.ppc.altivec.lvsl // CHECK: @llvm.ppc.altivec.vperm - res_vf = vec_lvrxl(0, &vf); // CHECK: store <4 x float> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvxl + res_vf = vec_lvrxl(0, &vf); // CHECK: @llvm.ppc.altivec.lvxl // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm /* vec_stvlx */ - vec_stvlx(vsc, 0, ¶m_sc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vsc, 0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vsc, 0, &vsc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vsc, 0, &vsc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vuc, 0, ¶m_uc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vuc, 0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vuc, 0, &vuc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vuc, 0, &vuc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2172,33 +2172,33 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vs, 0, ¶m_s); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vs, 0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vs, 0, &vs); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vs, 0, &vs); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vus, 0, ¶m_us); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vus, 0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vus, 0, &vus); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vus, 0, &vus); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2220,33 +2220,33 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vi, 0, ¶m_i); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vi, 0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vi, 0, &vi); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vi, 0, &vi); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vui, 0, ¶m_ui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vui, 0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vui, 0, &vui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vui, 0, &vui); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2260,42 +2260,42 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx - vec_stvlx(vf, 0, &vf); // CHECK: store <4 x float> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlx(vf, 0, &vf); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx /* vec_stvlxl */ - vec_stvlxl(vsc, 0, ¶m_sc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vsc, 0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vsc, 0, &vsc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vsc, 0, &vsc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vuc, 0, ¶m_uc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vuc, 0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vuc, 0, &vuc); // CHECK: store <16 x i8> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vuc, 0, &vuc); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2309,33 +2309,33 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vs, 0, ¶m_s); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vs, 0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vs, 0, &vs); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vs, 0, &vs); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vus, 0, ¶m_us); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vus, 0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vus, 0, &vus); // CHECK: store <8 x i16> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vus, 0, &vus); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2357,33 +2357,33 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vi, 0, ¶m_i); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vi, 0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vi, 0, &vi); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vi, 0, &vi); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vui, 0, ¶m_ui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vui, 0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vui, 0, &vui); // CHECK: store <4 x i32> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vui, 0, &vui); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2397,9 +2397,9 @@ void test6() { // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl - vec_stvlxl(vf, 0, &vf); // CHECK: store <4 x float> zeroinitializer - // CHECK: @llvm.ppc.altivec.lvx + vec_stvlxl(vf, 0, &vf); // CHECK: @llvm.ppc.altivec.lvx // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2407,32 +2407,32 @@ void test6() { /* vec_stvrx */ vec_stvrx(vsc, 0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vsc, 0, &vsc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vuc, 0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vuc, 0, &vuc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2447,32 +2447,32 @@ void test6() { // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vs, 0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vs, 0, &vs); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vus, 0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vus, 0, &vus); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2495,32 +2495,32 @@ void test6() { // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vi, 0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vi, 0, &vi); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vui, 0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vui, 0, &vui); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2535,8 +2535,8 @@ void test6() { // CHECK: @llvm.ppc.altivec.stvx vec_stvrx(vf, 0, &vf); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2544,32 +2544,32 @@ void test6() { /* vec_stvrxl */ vec_stvrxl(vsc, 0, ¶m_sc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vsc, 0, &vsc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vuc, 0, ¶m_uc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vuc, 0, &vuc); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <16 x i8> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2584,32 +2584,32 @@ void test6() { // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vs, 0, ¶m_s); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vs, 0, &vs); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vus, 0, ¶m_us); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vus, 0, &vus); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <8 x i16> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2632,32 +2632,32 @@ void test6() { // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vi, 0, ¶m_i); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vi, 0, &vi); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vui, 0, ¶m_ui); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vui, 0, &vui); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x i32> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -2672,8 +2672,8 @@ void test6() { // CHECK: @llvm.ppc.altivec.stvxl vec_stvrxl(vf, 0, &vf); // CHECK: @llvm.ppc.altivec.lvx - // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.lvsl + // CHECK: store <4 x float> zeroinitializer // CHECK: @llvm.ppc.altivec.vperm // CHECK: @llvm.ppc.altivec.lvsr // CHECK: @llvm.ppc.altivec.vperm @@ -3053,7 +3053,7 @@ void test6() { res_i = vec_any_out(vf, vf); // CHECK: @llvm.ppc.altivec.vcmpbfp.p } -/* ------------------------------ Relational Operators------------------------------- */ +/* ------------------------------ Relational Operators ------------------------------ */ // CHECK: define void @test7 void test7() { vector signed char vsc1 = (vector signed char)(-1); @@ -3113,14 +3113,3 @@ void test7() { res_i = (vf1 <= vf2); // CHECK: @llvm.ppc.altivec.vcmpgefp.p(i32 2 res_i = (vf1 >= vf2); // CHECK: @llvm.ppc.altivec.vcmpgefp.p(i32 2 } - -/* ------------------------------- increment/decrement: ----------------------------- */ -// CHECK: define void @test8 -void test8() { - vector int vi; - vi++; // CHECK: add nsw <4 x i32> {{.*}} <i32 1, i32 1, i32 1, i32 1> - vector unsigned int vui; - --vui; // CHECK: add <4 x i32> {{.*}} <i32 -1, i32 -1, i32 -1, i32 -1> - vector float vf; - vf++; // CHECK: fadd <4 x float> {{.*}} <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}> -} diff --git a/test/CodeGen/builtins-ptx.c b/test/CodeGen/builtins-ptx.c new file mode 100644 index 000000000000..6dd10188e9fb --- /dev/null +++ b/test/CodeGen/builtins-ptx.c @@ -0,0 +1,99 @@ +// RUN: %clang_cc1 -triple ptx32-unknown-unknown -emit-llvm -o %t %s +// RUN: %clang_cc1 -triple ptx64-unknown-unknown -emit-llvm -o %t %s + + +int read_tid() { + + int x = __builtin_ptx_read_tid_x(); + int y = __builtin_ptx_read_tid_y(); + int z = __builtin_ptx_read_tid_z(); + int w = __builtin_ptx_read_tid_w(); + + return x + y + z + w; + +} + +int read_ntid() { + + int x = __builtin_ptx_read_ntid_x(); + int y = __builtin_ptx_read_ntid_y(); + int z = __builtin_ptx_read_ntid_z(); + int w = __builtin_ptx_read_ntid_w(); + + return x + y + z + w; + +} + +int read_ctaid() { + + int x = __builtin_ptx_read_ctaid_x(); + int y = __builtin_ptx_read_ctaid_y(); + int z = __builtin_ptx_read_ctaid_z(); + int w = __builtin_ptx_read_ctaid_w(); + + return x + y + z + w; + +} + +int read_nctaid() { + + int x = __builtin_ptx_read_nctaid_x(); + int y = __builtin_ptx_read_nctaid_y(); + int z = __builtin_ptx_read_nctaid_z(); + int w = __builtin_ptx_read_nctaid_w(); + + return x + y + z + w; + +} + +int read_ids() { + + int a = __builtin_ptx_read_laneid(); + int b = __builtin_ptx_read_warpid(); + int c = __builtin_ptx_read_nwarpid(); + int d = __builtin_ptx_read_smid(); + int e = __builtin_ptx_read_nsmid(); + int f = __builtin_ptx_read_gridid(); + + return a + b + c + d + e + f; + +} + +int read_lanemasks() { + + int a = __builtin_ptx_read_lanemask_eq(); + int b = __builtin_ptx_read_lanemask_le(); + int c = __builtin_ptx_read_lanemask_lt(); + int d = __builtin_ptx_read_lanemask_ge(); + int e = __builtin_ptx_read_lanemask_gt(); + + return a + b + c + d + e; + +} + + +long read_clocks() { + + int a = __builtin_ptx_read_clock(); + long b = __builtin_ptx_read_clock64(); + + return (long)a + b; + +} + +int read_pms() { + + int a = __builtin_ptx_read_pm0(); + int b = __builtin_ptx_read_pm1(); + int c = __builtin_ptx_read_pm2(); + int d = __builtin_ptx_read_pm3(); + + return a + b + c + d; + +} + +void sync() { + + __builtin_ptx_bar_sync(0); + +} diff --git a/test/CodeGen/builtins-x86.c b/test/CodeGen/builtins-x86.c index 56f220b8a6e8..bb63048b6166 100644 --- a/test/CodeGen/builtins-x86.c +++ b/test/CodeGen/builtins-x86.c @@ -273,7 +273,6 @@ void f0() { #endif tmp_V2i = __builtin_ia32_cvttps2pi(tmp_V4f); (void) __builtin_ia32_maskmovq(tmp_V8c, tmp_V8c, tmp_cp); - tmp_V4f = __builtin_ia32_loadups(tmp_fCp); (void) __builtin_ia32_storeups(tmp_fp, tmp_V4f); (void) __builtin_ia32_storehps(tmp_V2ip, tmp_V4f); (void) __builtin_ia32_storelps(tmp_V2ip, tmp_V4f); @@ -291,7 +290,6 @@ void f0() { tmp_V4f = __builtin_ia32_sqrtps(tmp_V4f); tmp_V4f = __builtin_ia32_sqrtss(tmp_V4f); (void) __builtin_ia32_maskmovdqu(tmp_V16c, tmp_V16c, tmp_cp); - tmp_V2d = __builtin_ia32_loadupd(tmp_dCp); (void) __builtin_ia32_storeupd(tmp_dp, tmp_V2d); tmp_i = __builtin_ia32_movmskpd(tmp_V2d); tmp_i = __builtin_ia32_pmovmskb128(tmp_V16c); @@ -481,4 +479,33 @@ void f0() { __builtin_ia32_maskstoreps(tmp_V4fp, tmp_V4f, tmp_V4f); __builtin_ia32_maskstorepd256(tmp_V4dp, tmp_V4d, tmp_V4d); __builtin_ia32_maskstoreps256(tmp_V8fp, tmp_V8f, tmp_V8f); + +#ifdef USE_3DNOW + tmp_V8c = __builtin_ia32_pavgusb(tmp_V8c, tmp_V8c); + tmp_V2i = __builtin_ia32_pf2id(tmp_V2f); + tmp_V2f = __builtin_ia32_pfacc(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfadd(tmp_V2f, tmp_V2f); + tmp_V2i = __builtin_ia32_pfcmpeq(tmp_V2f, tmp_V2f); + tmp_V2i = __builtin_ia32_pfcmpge(tmp_V2f, tmp_V2f); + tmp_V2i = __builtin_ia32_pfcmpgt(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfmax(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfmin(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfmul(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfrcp(tmp_V2f); + tmp_V2f = __builtin_ia32_pfrcpit1(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfrcpit2(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfrsqrt(tmp_V2f); + tmp_V2f = __builtin_ia32_pfrsqit1(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfrsqrtit1(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfsub(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfsubr(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pi2fd(tmp_V2i); + tmp_V4s = __builtin_ia32_pmulhrw(tmp_V4s, tmp_V4s); + tmp_V2i = __builtin_ia32_pf2iw(tmp_V2f); + tmp_V2f = __builtin_ia32_pfnacc(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pfpnacc(tmp_V2f, tmp_V2f); + tmp_V2f = __builtin_ia32_pi2fw(tmp_V2i); + tmp_V2f = __builtin_ia32_pswapdsf(tmp_V2f); + tmp_V2i = __builtin_ia32_pswapdsi(tmp_V2i); +#endif } diff --git a/test/CodeGen/builtins.c b/test/CodeGen/builtins.c index 40f77249f918..fca087e197fc 100644 --- a/test/CodeGen/builtins.c +++ b/test/CodeGen/builtins.c @@ -138,7 +138,7 @@ void bar() { // LLVM's hex representation of float constants is really unfortunate; // basically it does a float-to-double "conversion" and then prints the - // hex form of that. That gives us wierd artifacts like exponents + // hex form of that. That gives us weird artifacts like exponents // that aren't numerically similar to the original exponent and // significand bit-patterns that are offset by three bits (because // the exponent was expanded from 8 bits to 11). diff --git a/test/CodeGen/char-literal.c b/test/CodeGen/char-literal.c index aff76d280d30..322041c0049a 100644 --- a/test/CodeGen/char-literal.c +++ b/test/CodeGen/char-literal.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -x c++ -triple i386-unknown-unkown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s // Runs in c++ mode so that wchar_t is available. int main() { diff --git a/test/CodeGen/conditional.c b/test/CodeGen/conditional.c index d079aafd787a..15e15f11e35f 100644 --- a/test/CodeGen/conditional.c +++ b/test/CodeGen/conditional.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm %s -o %t +// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s float test1(int cond, float a, float b) { return cond ? a : b; @@ -47,3 +47,22 @@ void test9(struct test9 *p) { p ? p : test9spare(); } +// CHECK: @test10 +// CHECK: select i1 {{.*}}, i32 4, i32 5 +int test10(int c) { + return c ? 4 : 5; +} +enum { Gronk = 5 }; + +// rdar://9289603 +// CHECK: @test11 +// CHECK: select i1 {{.*}}, i32 4, i32 5 +int test11(int c) { + return c ? 4 : Gronk; +} + +// CHECK: @test12 +// CHECK: select i1 {{.*}}, double 4.0{{.*}}, double 2.0 +double test12(int c) { + return c ? 4.0 : 2.0; +} diff --git a/test/CodeGen/const-init.c b/test/CodeGen/const-init.c index 32b762d646e6..c6778630a0a0 100644 --- a/test/CodeGen/const-init.c +++ b/test/CodeGen/const-init.c @@ -4,6 +4,10 @@ // Brace-enclosed string array initializers char a[] = { "asdf" }; +// CHECK: @a = global [5 x i8] c"asdf\00" + +char a2[2][5] = { "asdf" }; +// CHECK: @a2 = global [2 x [5 x i8]] {{\[}}[5 x i8] c"asdf\00", [5 x i8] zeroinitializer] // Double-implicit-conversions of array/functions (not legal C, but // clang accepts it for gcc compat). diff --git a/test/CodeGen/darwin-string-literals.c b/test/CodeGen/darwin-string-literals.c index ef5601e8f224..6f9e0d2a63ed 100644 --- a/test/CodeGen/darwin-string-literals.c +++ b/test/CodeGen/darwin-string-literals.c @@ -1,13 +1,13 @@ // RUN: %clang_cc1 -triple i386-apple-darwin9 -emit-llvm %s -o - | FileCheck -check-prefix LSB %s // CHECK-LSB: @.str = private unnamed_addr constant [8 x i8] c"string0\00" -// CHECK-LSB: @.str1 = private unnamed_addr constant [8 x i8] c"string1\00" +// CHECK-LSB: @.str1 = linker_private unnamed_addr constant [8 x i8] c"string1\00" // CHECK-LSB: @.str2 = internal unnamed_addr constant [36 x i8] c"h\00e\00l\00l\00o\00 \00\92! \00\03& \00\90! \00w\00o\00r\00l\00d\00\00\00", align 2 // RUN: %clang_cc1 -triple powerpc-apple-darwin9 -emit-llvm %s -o - | FileCheck -check-prefix MSB %s // CHECK-MSB: @.str = private unnamed_addr constant [8 x i8] c"string0\00" -// CHECK-MSB: @.str1 = private unnamed_addr constant [8 x i8] c"string1\00" +// CHECK-MSB: @.str1 = linker_private unnamed_addr constant [8 x i8] c"string1\00" // CHECK-MSB: @.str2 = internal unnamed_addr constant [36 x i8] c"\00h\00e\00l\00l\00o\00 !\92\00 &\03\00 !\90\00 \00w\00o\00r\00l\00d\00\00", align 2 const char *g0 = "string0"; diff --git a/test/CodeGen/debug-info-line2.c b/test/CodeGen/debug-info-line2.c new file mode 100644 index 000000000000..b5eba8a1a060 --- /dev/null +++ b/test/CodeGen/debug-info-line2.c @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 -triple x86_64-darwin-apple -g -emit-llvm -o - %s | FileCheck %s +// Radar 9199234 + +int bar(); +int foo(int i) { + int j = 0; + if (i) { + j = bar(); +//CHECK: store i32 +//CHECK-NOT: br label %{{%[a-zA-Z0-9\.]+}}, !dbg + } + else + { + j = bar() + 2; + } + return j; +} diff --git a/test/CodeGen/decl.c b/test/CodeGen/decl.c index 5be421623616..7a9971ee1812 100644 --- a/test/CodeGen/decl.c +++ b/test/CodeGen/decl.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -w -emit-llvm < %s | FileCheck %s -// CHECK: @test1.x = private constant [12 x i32] [i32 1 +// CHECK: @test1.x = internal constant [12 x i32] [i32 1 // CHECK: @test2.x = internal constant [13 x i32] [i32 1, // CHECK: @test5w = global %0 { i32 2, [4 x i8] undef } // CHECK: @test5y = global %union.test5u { double 7.300000e+0{{[0]*}}1 } diff --git a/test/CodeGen/ext-vector.c b/test/CodeGen/ext-vector.c index daa18265a49f..1abd9f27ae12 100644 --- a/test/CodeGen/ext-vector.c +++ b/test/CodeGen/ext-vector.c @@ -1,13 +1,18 @@ -// RUN: %clang_cc1 -emit-llvm-only %s +// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s typedef __attribute__(( ext_vector_type(4) )) float float4; typedef __attribute__(( ext_vector_type(2) )) float float2; typedef __attribute__(( ext_vector_type(4) )) int int4; +typedef __attribute__(( ext_vector_type(4) )) unsigned int uint4; +// CHECK: @foo = global <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00> float4 foo = (float4){ 1.0, 2.0, 3.0, 4.0 }; +// CHECK: @bar = constant <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 0x7FF0000000000000> const float4 bar = (float4){ 1.0, 2.0, 3.0, __builtin_inff() }; +// CHECK: @test1 +// CHECK: fadd <4 x float> float4 test1(float4 V) { return V.wzyx+V; } @@ -16,6 +21,12 @@ float2 vec2, vec2_2; float4 vec4, vec4_2; float f; +// CHECK: @test2 +// CHECK: shufflevector {{.*}} <i32 0, i32 1> +// CHECK: extractelement +// CHECK: shufflevector {{.*}} <i32 1, i32 1, i32 1, i32 1> +// CHECK: insertelement +// CHECK: shufflevector {{.*}} <i32 1, i32 0> void test2() { vec2 = vec4.xy; // shorten f = vec2.x; // extract elt @@ -25,10 +36,15 @@ void test2() { vec2.yx = vec2; // reverse } +// CHECK: @test3 +// CHECK: store <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00> void test3(float4 *out) { *out = ((float4) {1.0f, 2.0f, 3.0f, 4.0f }); } +// CHECK: @test4 +// CHECK: store <4 x float> +// CHECK: store <4 x float> void test4(float4 *out) { float a = 1.0f; float b = 2.0f; @@ -37,6 +53,12 @@ void test4(float4 *out) { *out = ((float4) {a,b,c,d}); } +// CHECK: @test5 +// CHECK: shufflevector {{.*}} <4 x i32> zeroinitializer +// CHECK: fmul <4 x float> +// CHECK: fmul <4 x float> +// CHECK: shufflevector {{.*}} <4 x i32> zeroinitializer +// CHECK: fmul <4 x float> void test5(float4 *out) { float a; float4 b; @@ -50,25 +72,42 @@ void test5(float4 *out) { *out = b; } +// CHECK: @test6 void test6(float4 *ap, float4 *bp, float c) { float4 a = *ap; float4 b = *bp; - + + // CHECK: fadd <4 x float> + // CHECK: fsub <4 x float> + // CHECK: fmul <4 x float> + // CHECK: fdiv <4 x float> a = a + b; a = a - b; a = a * b; a = a / b; - + + // CHECK: fadd <4 x float> + // CHECK: fsub <4 x float> + // CHECK: fmul <4 x float> + // CHECK: fdiv <4 x float> a = a + c; a = a - c; a = a * c; a = a / c; + // CHECK: fadd <4 x float> + // CHECK: fsub <4 x float> + // CHECK: fmul <4 x float> + // CHECK: fdiv <4 x float> a += b; a -= b; a *= b; a /= b; - + + // CHECK: fadd <4 x float> + // CHECK: fsub <4 x float> + // CHECK: fmul <4 x float> + // CHECK: fdiv <4 x float> a += c; a -= c; a *= c; @@ -87,76 +126,153 @@ void test6(float4 *ap, float4 *bp, float c) { #endif } +// CHECK: @test7 void test7(int4 *ap, int4 *bp, int c) { int4 a = *ap; int4 b = *bp; - + + // CHECK: add nsw <4 x i32> + // CHECK: sub nsw <4 x i32> + // CHECK: mul nsw <4 x i32> + // CHECK: sdiv <4 x i32> + // CHECK: srem <4 x i32> a = a + b; a = a - b; a = a * b; a = a / b; a = a % b; - + + // CHECK: add nsw <4 x i32> + // CHECK: sub nsw <4 x i32> + // CHECK: mul nsw <4 x i32> + // CHECK: sdiv <4 x i32> + // CHECK: srem <4 x i32> a = a + c; a = a - c; a = a * c; a = a / c; a = a % c; + // CHECK: add nsw <4 x i32> + // CHECK: sub nsw <4 x i32> + // CHECK: mul nsw <4 x i32> + // CHECK: sdiv <4 x i32> + // CHECK: srem <4 x i32> a += b; a -= b; a *= b; a /= b; a %= b; - + + // CHECK: add nsw <4 x i32> + // CHECK: sub nsw <4 x i32> + // CHECK: mul nsw <4 x i32> + // CHECK: sdiv <4 x i32> + // CHECK: srem <4 x i32> a += c; a -= c; a *= c; a /= c; a %= c; + // Vector comparisons. + // CHECK: icmp slt + // CHECK: icmp sle + // CHECK: icmp sgt + // CHECK: icmp sge + // CHECK: icmp eq + // CHECK: icmp ne int4 cmp; cmp = a < b; cmp = a <= b; - cmp = a < b; + cmp = a > b; cmp = a >= b; cmp = a == b; cmp = a != b; } +// CHECK: @test8 void test8(float4 *ap, float4 *bp, int c) { float4 a = *ap; float4 b = *bp; // Vector comparisons. + // CHECK: fcmp olt + // CHECK: fcmp ole + // CHECK: fcmp ogt + // CHECK: fcmp oge + // CHECK: fcmp oeq + // CHECK: fcmp une int4 cmp; cmp = a < b; cmp = a <= b; - cmp = a < b; + cmp = a > b; cmp = a >= b; cmp = a == b; cmp = a != b; } +// CHECK: @test9 +// CHECK: extractelement <4 x i32> int test9(int4 V) { return V.xy.x; } +// CHECK: @test10 +// CHECK: add nsw <4 x i32> +// CHECK: extractelement <4 x i32> int test10(int4 V) { return (V+V).x; } +// CHECK: @test11 +// CHECK: extractelement <4 x i32> int4 test11a(); int test11() { return test11a().x; } +// CHECK: @test12 +// CHECK: shufflevector {{.*}} <i32 2, i32 1, i32 0> +// CHECK: shufflevector {{.*}} <i32 0, i32 1, i32 2, i32 undef> +// CHECK: shufflevector {{.*}} <i32 4, i32 5, i32 6, i32 3> int4 test12(int4 V) { V.xyz = V.zyx; return V; } +// CHECK: @test13 +// CHECK: shufflevector {{.*}} <i32 2, i32 1, i32 0, i32 3> int4 test13(int4 *V) { return V->zyxw; } + +// CHECK: @test14 +void test14(uint4 *ap, uint4 *bp, unsigned c) { + uint4 a = *ap; + uint4 b = *bp; + + // CHECK: udiv <4 x i32> + // CHECK: urem <4 x i32> + a = a / b; + a = a % b; + + // CHECK: udiv <4 x i32> + // CHECK: urem <4 x i32> + a = a / c; + a = a % c; + + // CHECK: icmp ult + // CHECK: icmp ule + // CHECK: icmp ugt + // CHECK: icmp uge + // CHECK: icmp eq + // CHECK: icmp ne + a = a < b; + a = a <= b; + a = a > b; + a = a >= b; + a = a == b; + a = a != b; +} diff --git a/test/CodeGen/integer-overflow.c b/test/CodeGen/integer-overflow.c index 103cc8427bb0..1d460656a1c7 100644 --- a/test/CodeGen/integer-overflow.c +++ b/test/CodeGen/integer-overflow.c @@ -49,4 +49,18 @@ void test1() { // TRAPV: llvm.sadd.with.overflow.i32({{.*}}, i32 -1) // TRAPV_HANDLER: foo( --a; + + // -fwrapv should turn off inbounds for GEP's, PR9256 + extern int* P; + ++P; + // DEFAULT: getelementptr inbounds i32* + // WRAPV: getelementptr i32* + // TRAPV: getelementptr inbounds i32* + + // PR9350: char increment never overflows. + extern volatile signed char PR9350; + // DEFAULT: add i8 {{.*}}, 1 + // WRAPV: add i8 {{.*}}, 1 + // TRAPV: add i8 {{.*}}, 1 + ++PR9350; } diff --git a/test/CodeGen/mangle.c b/test/CodeGen/mangle.c index 3bbd9c8b807e..46ef512f6950 100644 --- a/test/CodeGen/mangle.c +++ b/test/CodeGen/mangle.c @@ -63,3 +63,12 @@ int func(void) { // CHECK: @_Z4foo9Dv4_f typedef __attribute__(( vector_size(16) )) float float4; void __attribute__((__overloadable__)) foo9(float4 f) {} + +// Intrinsic calls. +extern int llvm_cas(volatile int*, int, int) + __asm__("llvm.atomic.cmp.swap.i32.p0i32"); + +int foo10(volatile int* add, int from, int to) { + // CHECK: call i32 @llvm.atomic.cmp.swap.i32.p0i32 + return llvm_cas(add, from, to); +} diff --git a/test/CodeGen/mmx-inline-asm.c b/test/CodeGen/mmx-inline-asm.c new file mode 100644 index 000000000000..c473a930ecc8 --- /dev/null +++ b/test/CodeGen/mmx-inline-asm.c @@ -0,0 +1,22 @@ +// RUN: %clang -mmmx -ccc-host-triple i386-unknown-unknown -emit-llvm -S %s -o - | FileCheck %s +// <rdar://problem/9091220> +#include <mmintrin.h> + +// CHECK: type { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx } + +void foo(long long fill) { + __m64 vfill = _mm_cvtsi64_m64(fill); + __m64 v1, v2, v3, v4, v5, v6, v7; + + __asm__ __volatile__ ( + "\tmovq %7, %0\n" + "\tmovq %7, %1\n" + "\tmovq %7, %2\n" + "\tmovq %7, %3\n" + "\tmovq %7, %4\n" + "\tmovq %7, %5\n" + "\tmovq %7, %6" + : "=&y" (v1), "=&y" (v2), "=&y" (v3), + "=&y" (v4), "=&y" (v5), "=&y" (v6), "=y" (v7) + : "y" (vfill)); +} diff --git a/test/CodeGen/mrtd.c b/test/CodeGen/mrtd.c new file mode 100644 index 000000000000..2cc71bb0086f --- /dev/null +++ b/test/CodeGen/mrtd.c @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -mrtd -triple i386-unknown-freebsd9.0 -emit-llvm -o - %s | FileCheck %s + +void baz(int arg); + +// CHECK: define x86_stdcallcc void @foo(i32 %arg) nounwind +void foo(int arg) { +// CHECK: call x86_stdcallcc i32 (...)* @bar(i32 + bar(arg); +// CHECK: call x86_stdcallcc void @baz(i32 + baz(arg); +} + +// CHECK: declare x86_stdcallcc i32 @bar(...) + +// CHECK: declare x86_stdcallcc void @baz(i32) diff --git a/test/CodeGen/ms_struct-bitfield-init.c b/test/CodeGen/ms_struct-bitfield-init.c new file mode 100644 index 000000000000..7a483fb84b8b --- /dev/null +++ b/test/CodeGen/ms_struct-bitfield-init.c @@ -0,0 +1,68 @@ +// RUN: %clang_cc1 -emit-llvm-only -triple x86_64-apple-darwin9 %s +// rdar://8823265 + +extern void abort(void); +#define ATTR __attribute__((__ms_struct__)) + +struct +{ + char foo; + long : 0; + char : 0; + int : 0; + char bar; +} ATTR t1 = {'a', 'b'}; + +struct +{ + char bar0; + long : 0; + int : 0; + char bar1; + char bar2; + long : 0; + char bar3; + char bar4; + char : 0; + char bar5; + char bar6; + char : 0; + char bar7; + char bar8; +} ATTR t2 = {'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i'}; + +struct { + int : 0; + int i1; + int : 0; + int i2; + int : 0; + int i3; + int : 0; + int i4; +} t3 = {1,2,3,4}; + +int main() { + if (sizeof(t1) != 2) + abort(); + if (t1.foo != 'a') + abort(); + if (t1.bar != 'b') + abort(); + t1.foo = 'c'; + t1.bar = 'd'; + if (t1.foo != 'c') + abort(); + if (t1.bar != 'd') + abort(); + if (sizeof(t2) != 9) + abort(); + if (t2.bar0 != 'a' || t2.bar8 != 'i') + abort(); + if (sizeof(t3) != 16) + abort(); + if (t3.i1 != 1 || t3.i4 != 4) + abort(); + return 0; +} + diff --git a/test/CodeGen/ms_struct-bitfield.c b/test/CodeGen/ms_struct-bitfield.c new file mode 100644 index 000000000000..a8f4c91a4937 --- /dev/null +++ b/test/CodeGen/ms_struct-bitfield.c @@ -0,0 +1,131 @@ +// RUN: %clang_cc1 -emit-llvm-only -triple x86_64-apple-darwin9 %s +// rdar://8823265 + +#define ATTR __attribute__((__ms_struct__)) + +struct +{ + char foo; + long : 0; + char bar; +} ATTR t1; + +struct +{ + char foo; + long : 0; + char : 0; + int : 0; + char bar; +} ATTR t2; + +struct +{ + char foo; + long : 0; + char : 0; + int : 0; + char bar; + long : 0; + char : 0; +} ATTR t3; + +struct +{ + long : 0; + char bar; +} ATTR t4; + +struct +{ + long : 0; + long : 0; + char : 0; + char bar; +} ATTR t5; + +struct +{ + long : 0; + long : 0; + char : 0; + char bar; +} ATTR t6; + +struct +{ + char foo; + long : 0; + int : 0; + char bar; + char bar1; + long : 0; + char bar2; + char bar3; + char : 0; + char bar4; + char bar5; + char : 0; + char bar6; + char bar7; +} ATTR t7; + +struct +{ + long : 0; + long : 0; + char : 0; +} ATTR t8; + +struct +{ + char foo; + long : 0; + int : 0; + char bar; + char bar1; + long : 0; + char bar2; + char bar3; + char : 0; + char bar4; + char bar5; + char : 0; + char bar6; + char bar7; + int i1; + char : 0; + long : 0; + char :4; + char bar8; + char : 0; + char bar9; + char bar10; + int i2; + char : 0; + long : 0; + char :4; +} ATTR t9; + +struct +{ + char foo: 8; + long : 0; + char bar; +} ATTR t10; + +static int arr1[(sizeof(t1) == 2) -1]; +static int arr2[(sizeof(t2) == 2) -1]; +static int arr3[(sizeof(t3) == 2) -1]; +static int arr4[(sizeof(t4) == 1) -1]; +static int arr5[(sizeof(t5) == 1) -1]; +static int arr6[(sizeof(t6) == 1) -1]; +static int arr7[(sizeof(t7) == 9) -1]; +static int arr8[(sizeof(t8) == 0) -1]; +static int arr9[(sizeof(t9) == 28) -1]; +static int arr10[(sizeof(t10) == 16) -1]; + +int main() { + return 0; +} + diff --git a/test/CodeGen/mult-alt-x86.c b/test/CodeGen/mult-alt-x86.c index 84011f2d5303..4e2a69d85bdd 100644 --- a/test/CodeGen/mult-alt-x86.c +++ b/test/CodeGen/mult-alt-x86.c @@ -194,70 +194,70 @@ void single_Z() void multi_R() { // CHECK: asm "foo $1,$0", "=*r|R|m,r|R|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=R,=m" (mout0) : "r,R,m" (min1)); + asm("foo %1,%0" : "=r,R,m" (mout0) : "r,R,m" (min1)); } // CHECK: @multi_q void multi_q() { // CHECK: asm "foo $1,$0", "=*r|q|m,r|q|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=q,=m" (mout0) : "r,q,m" (min1)); + asm("foo %1,%0" : "=r,q,m" (mout0) : "r,q,m" (min1)); } // CHECK: @multi_Q void multi_Q() { // CHECK: asm "foo $1,$0", "=*r|Q|m,r|Q|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=Q,=m" (mout0) : "r,Q,m" (min1)); + asm("foo %1,%0" : "=r,Q,m" (mout0) : "r,Q,m" (min1)); } // CHECK: @multi_a void multi_a() { // CHECK: asm "foo $1,$0", "=*r|{ax}|m,r|{ax}|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=a,=m" (mout0) : "r,a,m" (min1)); + asm("foo %1,%0" : "=r,a,m" (mout0) : "r,a,m" (min1)); } // CHECK: @multi_b void multi_b() { // CHECK: asm "foo $1,$0", "=*r|{bx}|m,r|{bx}|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=b,=m" (mout0) : "r,b,m" (min1)); + asm("foo %1,%0" : "=r,b,m" (mout0) : "r,b,m" (min1)); } // CHECK: @multi_c void multi_c() { // CHECK: asm "foo $1,$0", "=*r|{cx}|m,r|{cx}|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=c,=m" (mout0) : "r,c,m" (min1)); + asm("foo %1,%0" : "=r,c,m" (mout0) : "r,c,m" (min1)); } // CHECK: @multi_d void multi_d() { - // CHECK: asm "foo $1,$0", "=*r|{dx}|m,r|{dx}[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=d,=m" (mout0) : "r,d" (min1)); + // CHECK: asm "foo $1,$0", "=*r|{dx}|m,r|{dx}|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) + asm("foo %1,%0" : "=r,d,m" (mout0) : "r,d,m" (min1)); } // CHECK: @multi_S void multi_S() { // CHECK: asm "foo $1,$0", "=*r|{si}|m,r|{si}|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=S,=m" (mout0) : "r,S,m" (min1)); + asm("foo %1,%0" : "=r,S,m" (mout0) : "r,S,m" (min1)); } // CHECK: @multi_D void multi_D() { // CHECK: asm "foo $1,$0", "=*r|{di}|m,r|{di}|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=D,=m" (mout0) : "r,D,m" (min1)); + asm("foo %1,%0" : "=r,D,m" (mout0) : "r,D,m" (min1)); } // CHECK: @multi_A void multi_A() { // CHECK: asm "foo $1,$0", "=*r|A|m,r|A|m[[CLOBBERS]](i32* @mout0, i32 {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=A,=m" (mout0) : "r,A,m" (min1)); + asm("foo %1,%0" : "=r,A,m" (mout0) : "r,A,m" (min1)); } // CHECK: @multi_f @@ -282,93 +282,93 @@ void multi_u() void multi_y() { // CHECK: asm "foo $1,$0", "=*r|y|m,r|y|m[[CLOBBERS]](double* @dout0, double {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=y,=m" (dout0) : "r,y,m" (din1)); + asm("foo %1,%0" : "=r,y,m" (dout0) : "r,y,m" (din1)); } // CHECK: @multi_x void multi_x() { // CHECK: asm "foo $1,$0", "=*r|x|m,r|x|m[[CLOBBERS]](double* @dout0, double {{[a-zA-Z0-9@%]+}}) - asm("foo %1,%0" : "=r,=x,=m" (dout0) : "r,x,m" (din1)); + asm("foo %1,%0" : "=r,x,m" (dout0) : "r,x,m" (din1)); } // CHECK: @multi_Y void multi_Y0() { // Y constraint currently broken. - //asm("foo %1,%0" : "=r,=Y0,=m" (mout0) : "r,Y0,m" (min1)); - //asm("foo %1,%0" : "=r,=Yz,=m" (mout0) : "r,Yz,m" (min1)); - //asm("foo %1,%0" : "=r,=Yt,=m" (mout0) : "r,Yt,m" (min1)); - //asm("foo %1,%0" : "=r,=Yi,=m" (mout0) : "r,Yi,m" (min1)); - //asm("foo %1,%0" : "=r,=Ym,=m" (mout0) : "r,Ym,m" (min1)); + //asm("foo %1,%0" : "=r,Y0,m" (mout0) : "r,Y0,m" (min1)); + //asm("foo %1,%0" : "=r,Yz,m" (mout0) : "r,Yz,m" (min1)); + //asm("foo %1,%0" : "=r,Yt,m" (mout0) : "r,Yt,m" (min1)); + //asm("foo %1,%0" : "=r,Yi,m" (mout0) : "r,Yi,m" (min1)); + //asm("foo %1,%0" : "=r,Ym,m" (mout0) : "r,Ym,m" (min1)); } // CHECK: @multi_I void multi_I() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|I|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,I,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,I,m" (1)); } // CHECK: @multi_J void multi_J() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|J|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,J,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,J,m" (1)); } // CHECK: @multi_K void multi_K() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|K|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,K,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,K,m" (1)); } // CHECK: @multi_L void multi_L() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|L|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,L,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,L,m" (1)); } // CHECK: @multi_M void multi_M() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|M|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,M,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,M,m" (1)); } // CHECK: @multi_N void multi_N() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|N|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,N,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,N,m" (1)); } // CHECK: @multi_G void multi_G() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|G|m[[CLOBBERS]](i32* @mout0, double {{1.[0]+e[+]*[0]+}}) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,G,m" (1.0)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,G,m" (1.0)); } // CHECK: @multi_C void multi_C() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|C|m[[CLOBBERS]](i32* @mout0, double {{1.[0]+e[+]*[0]+}}) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,C,m" (1.0)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,C,m" (1.0)); } // CHECK: @multi_e void multi_e() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|e|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,e,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,e,m" (1)); } // CHECK: @multi_Z void multi_Z() { // CHECK: asm "foo $1,$0", "=*r|m|m,r|Z|m[[CLOBBERS]](i32* @mout0, i32 1) - asm("foo %1,%0" : "=r,=m,=m" (mout0) : "r,Z,m" (1)); + asm("foo %1,%0" : "=r,m,m" (mout0) : "r,Z,m" (1)); } diff --git a/test/CodeGen/packed-arrays.c b/test/CodeGen/packed-arrays.c new file mode 100644 index 000000000000..785db4d2dde2 --- /dev/null +++ b/test/CodeGen/packed-arrays.c @@ -0,0 +1,157 @@ +// RUN: %clang_cc1 -triple x86_64-unk-unk -emit-llvm -Os -o %t %s +// RUN: FileCheck < %t %s + +struct s0 { + unsigned int x[2] __attribute__((packed)); +}; + +struct s1 { + unsigned int x[2] __attribute__((packed)); + unsigned int y; + unsigned int z __attribute__((packed)); +}; + +struct s2 { + unsigned int x[2] __attribute__((packed)); + unsigned int y __attribute__((packed)); + unsigned int z __attribute__((packed)); +}; + +struct __attribute__((packed)) s3 { + unsigned int x[2]; + unsigned int y; + unsigned int z; +}; + +// CHECK: @align0 = global i32 1 +int align0 = __alignof(struct s0); +// CHECK: @align1 = global i32 4 +int align1 = __alignof(struct s1); +// CHECK: @align2 = global i32 1 +int align2 = __alignof(struct s2); +// CHECK: @align3 = global i32 1 +int align3 = __alignof(struct s3); + +// CHECK: @align0_x = global i32 1 +int align0_x = __alignof(((struct s0*) 0)->x); +// We are currently incompatible with GCC here. <rdar://problem/9217290> +// +// CHECK-XFAIL: @align1_x = global i32 1 +// CHECK: @align1_x = global i32 4 +int align1_x = __alignof(((struct s1*) 0)->x); +// CHECK: @align2_x = global i32 1 +int align2_x = __alignof(((struct s2*) 0)->x); +// CHECK: @align3_x = global i32 1 +int align3_x = __alignof(((struct s3*) 0)->x); + +// CHECK: @align0_x0 = global i32 4 +int align0_x0 = __alignof(((struct s0*) 0)->x[0]); +// CHECK: @align1_x0 = global i32 4 +int align1_x0 = __alignof(((struct s1*) 0)->x[0]); +// CHECK: @align2_x0 = global i32 4 +int align2_x0 = __alignof(((struct s2*) 0)->x[0]); +// CHECK: @align3_x0 = global i32 4 +int align3_x0 = __alignof(((struct s3*) 0)->x[0]); + +// CHECK: define i32 @f0_a +// CHECK: load i32* %{{.*}}, align 1 +// CHECK: } +// CHECK: define i32 @f0_b +// CHECK: load i32* %{{.*}}, align 4 +// CHECK: } +int f0_a(struct s0 *a) { + return a->x[1]; +} +int f0_b(struct s0 *a) { + return *(a->x + 1); +} + +// CHECK: define i32 @f1_a +// CHECK: load i32* %{{.*}}, align 4 +// CHECK: } +// CHECK: define i32 @f1_b +// CHECK: load i32* %{{.*}}, align 4 +// CHECK: } + +// Note that we are incompatible with GCC on these two examples. +// +// CHECK: define i32 @f1_c +// CHECK-XFAIL: load i32* %{{.*}}, align 1 +// CHECK: load i32* %{{.*}}, align 4 +// CHECK: } +// CHECK: define i32 @f1_d +// CHECK-XFAIL: load i32* %{{.*}}, align 1 +// CHECK: load i32* %{{.*}}, align 4 +// CHECK: } +int f1_a(struct s1 *a) { + return a->x[1]; +} +int f1_b(struct s1 *a) { + return *(a->x + 1); +} +int f1_c(struct s1 *a) { + return a->y; +} +int f1_d(struct s1 *a) { + return a->z; +} + +// CHECK: define i32 @f2_a +// CHECK: load i32* %{{.*}}, align 1 +// CHECK: } +// CHECK: define i32 @f2_b +// CHECK: load i32* %{{.*}}, align 4 +// CHECK: } +// CHECK: define i32 @f2_c +// CHECK: load i32* %{{.*}}, align 1 +// CHECK: } +// CHECK: define i32 @f2_d +// CHECK: load i32* %{{.*}}, align 1 +// CHECK: } +int f2_a(struct s2 *a) { + return a->x[1]; +} +int f2_b(struct s2 *a) { + return *(a->x + 1); +} +int f2_c(struct s2 *a) { + return a->y; +} +int f2_d(struct s2 *a) { + return a->z; +} + +// CHECK: define i32 @f3_a +// CHECK: load i32* %{{.*}}, align 1 +// CHECK: } +// CHECK: define i32 @f3_b +// CHECK: load i32* %{{.*}}, align 4 +// CHECK: } +// CHECK: define i32 @f3_c +// CHECK: load i32* %{{.*}}, align 1 +// CHECK: } +// CHECK: define i32 @f3_d +// CHECK: load i32* %{{.*}}, align 1 +// CHECK: } +int f3_a(struct s3 *a) { + return a->x[1]; +} +int f3_b(struct s3 *a) { + return *(a->x + 1); +} +int f3_c(struct s3 *a) { + return a->y; +} +int f3_d(struct s3 *a) { + return a->z; +} + +// Verify we don't claim things are overaligned. +// +// CHECK: define double @f4 +// CHECK: load double* {{.*}}, align 8 +// CHECK: } +extern double g4[5] __attribute__((aligned(16))); +double f4() { + return g4[1]; +} diff --git a/test/CodeGen/ptx-cc.c b/test/CodeGen/ptx-cc.c new file mode 100644 index 000000000000..2212d4260b35 --- /dev/null +++ b/test/CodeGen/ptx-cc.c @@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -triple ptx32-unknown-unknown -O3 -S -o %t %s -emit-llvm +// RUN: %clang_cc1 -triple ptx64-unknown-unknown -O3 -S -o %t %s -emit-llvm + +// Just make sure Clang uses the proper calling convention for the PTX back-end. +// If something is wrong, the back-end will fail. +void foo(float* a, + float* b) { + a[0] = b[0]; +} diff --git a/test/CodeGen/regparm-flag.c b/test/CodeGen/regparm-flag.c index f37239e473cd..8ecf53950805 100644 --- a/test/CodeGen/regparm-flag.c +++ b/test/CodeGen/regparm-flag.c @@ -4,12 +4,17 @@ void f1(int a, int b, int c, int d, int e, int f, int g, int h); +void f2(int a, int b) __attribute((regparm(0))); + void f0() { // CHECK: call void @f1(i32 inreg 1, i32 inreg 2, i32 inreg 3, i32 inreg 4, // CHECK: i32 5, i32 6, i32 7, i32 8) f1(1, 2, 3, 4, 5, 6, 7, 8); +// CHECK: call void @f2(i32 1, i32 2) + f2(1, 2); } // CHECK: declare void @f1(i32 inreg, i32 inreg, i32 inreg, i32 inreg, // CHECK: i32, i32, i32, i32) +// CHECK: declare void @f2(i32, i32) diff --git a/test/CodeGen/switch-dce.c b/test/CodeGen/switch-dce.c new file mode 100644 index 000000000000..bbb5f7e5aa36 --- /dev/null +++ b/test/CodeGen/switch-dce.c @@ -0,0 +1,247 @@ +// RUN: %clang_cc1 -triple i386-unknown-unknown -O0 %s -emit-llvm -o - | FileCheck %s + +// PR9322 and rdar://6970405 + +// CHECK: @test1 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: add nsw i32 {{.*}}, 1 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +int i; +void dead(); + +void test1() { + switch (1) + case 1: + ++i; + + switch (0) + case 1: + dead(); +} + + +// CHECK: @test2 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: add nsw i32 {{.*}}, 2 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +void test2() { + switch (4) { + case 1: + dead(); + break; + case 4: + i += 2; + // Fall off the end of the switch. + } +} + + +// CHECK: @test3 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: add nsw i32 {{.*}}, 2 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +void test3() { + switch (4) { + case 1: + dead(); + break; + case 4: { + i += 2; + break; + } + } +} + +// CHECK: @test4 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: add nsw i32 {{.*}}, 2 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +void test4() { + switch (4) { + case 1: + dead(); + break; + default: { + i += 2; + break; + } + } +} + +// This shouldn't crash codegen, but we don't have to optimize out the switch +// in this case. +void test5() { + switch (1) { + int x; // eliding var decl? + case 1: + x = 4; + i = x; + break; + } +} + +// CHECK: @test6 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +void test6() { + // Neither case is reachable. + switch (40) { + case 1: + dead(); + break; + case 4: { + dead(); + break; + } + } +} + +// CHECK: @test7 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: add nsw i32 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +void test7() { + switch (4) { + case 1: + dead(); + break; + { + case 4: // crazy brace scenario + ++i; + } + break; + } +} + +// CHECK: @test8 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: add nsw i32 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +void test8() { + switch (4) { + case 1: + dead(); + break; + case 4: + ++i; + // Fall off the end of the switch. + } +} + +// CHECK: @test9 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: add nsw i32 +// CHECK: add nsw i32 +// CHECK-NOT: switch +// CHECK-NOT: @dead +// CHECK: ret void +void test9(int i) { + switch (1) { + case 5: + dead(); + case 1: + ++i; + // Fall through is fine. + case 4: + ++i; + break; + } +} + +// CHECK: @test10 +// CHECK-NOT: switch +// CHECK: ret i32 +int test10(void) { + switch(8) { + case 8: + break; + case 4: + break; + default: + dead(); + } + + return 0; +} + +// CHECK: @test11 +// CHECK-NOT: switch +// CHECK: ret void +void test11() { + switch (1) { + case 1: + break; + case 42: ; + int x; // eliding var decl? + x = 4; + break; + } +} + +// CHECK: @test12 +// CHECK-NOT: switch +// CHECK: ret void +void test12() { + switch (1) { + case 2: { + int a; // Ok to skip this vardecl. + a = 42; + } + case 1: + break; + case 42: ; + int x; // eliding var decl? + x = 4; + break; + } +} + + +// rdar://9289524 - Check that the empty cases don't produce an empty block. +// CHECK: @test13 +// CHECK: switch +// CHECK: i32 42, label [[EPILOG:%[0-9.a-z]+]] +// CHECK: i32 11, label [[EPILOG]] +void test13(int x) { + switch (x) { + case 42: break; // No empty block please. + case 11: break; // No empty block please. + default: test13(42); break; + } +} + + +// Verify that case 42 only calls test14 once. +// CHECK: @test14 +// CHECK: call void @test14(i32 97) +// CHECK-NEXT: br label [[EPILOG2:%[0-9.a-z]+]] +// CHECK: call void @test14(i32 42) +// CHECK-NEXT: br label [[EPILOG2]] +void test14(int x) { + switch (x) { + case 42: test14(97); // fallthrough + case 11: break; + default: test14(42); break; + } +} + diff --git a/test/CodeGen/union.c b/test/CodeGen/union.c index 1883ca639b7e..5c89e2d72a7e 100644 --- a/test/CodeGen/union.c +++ b/test/CodeGen/union.c @@ -42,3 +42,5 @@ int RRF(void) {return RRU.a;} // PR6164 typedef union T0 { unsigned int : 0; } T0; T0 t0; + +union { int large_bitfield: 31; char c } u2; diff --git a/test/CodeGen/x86_64-arguments-darwin.c b/test/CodeGen/x86_64-arguments-darwin.c new file mode 100644 index 000000000000..2f804e6efc03 --- /dev/null +++ b/test/CodeGen/x86_64-arguments-darwin.c @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s| FileCheck %s + +// rdar://9122143 +// CHECK: declare void @func(i64, double) +typedef struct _str { + union { + long double a; + long c; + }; +} str; + +void func(str s); +str ss; +void f9122143() +{ + func(ss); +} diff --git a/test/CodeGen/x86_64-arguments.c b/test/CodeGen/x86_64-arguments.c index 51a234d993ca..ebde884d78d6 100644 --- a/test/CodeGen/x86_64-arguments.c +++ b/test/CodeGen/x86_64-arguments.c @@ -1,8 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s| FileCheck %s #include <stdarg.h> -// CHECK: %0 = type { i64, double } - // CHECK: define signext i8 @f0() char f0(void) { return 0; @@ -44,8 +42,8 @@ void f7(e7 a0) { // Test merging/passing of upper eightbyte with X87 class. // -// CHECK: define %0 @f8_1() -// CHECK: define void @f8_2(i64 %a0.coerce0, double %a0.coerce1) +// CHECK: define void @f8_1(%struct.s19* sret %agg.result) +// CHECK: define void @f8_2(%struct.s19* byval align 16 %a0) union u8 { long double a; int b; @@ -245,3 +243,19 @@ v1i64 f34(v1i64 arg) { return arg; } typedef unsigned long v1i64_2 __attribute__((__vector_size__(8))); v1i64_2 f35(v1i64_2 arg) { return arg+arg; } +// rdar://9122143 +// CHECK: declare void @func(%struct._str* byval align 16) +typedef struct _str { + union { + long double a; + long c; + }; +} str; + +void func(str s); +str ss; +void f9122143() +{ + func(ss); +} + |