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-rw-r--r--test/Transforms/InstCombine/debuginfo-dce.ll12
-rw-r--r--test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll30
-rw-r--r--test/Transforms/InstCombine/ffs-1.ll156
-rw-r--r--test/Transforms/InstCombine/lshr.ll19
-rw-r--r--test/Transforms/InstCombine/onehot_merge.ll76
-rw-r--r--test/Transforms/InstCombine/or-xor.ll44
-rw-r--r--test/Transforms/InstCombine/select-with-bitwise-ops.ll268
-rw-r--r--test/Transforms/InstCombine/shift.ll10
-rw-r--r--test/Transforms/InstCombine/xor2.ll33
9 files changed, 573 insertions, 75 deletions
diff --git a/test/Transforms/InstCombine/debuginfo-dce.ll b/test/Transforms/InstCombine/debuginfo-dce.ll
index 086743e80820..50b8f1c6068e 100644
--- a/test/Transforms/InstCombine/debuginfo-dce.ll
+++ b/test/Transforms/InstCombine/debuginfo-dce.ll
@@ -93,12 +93,12 @@ entry:
ret void, !dbg !32
}
-; CHECK: ![[LOAD_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_plus, 0)
-; CHECK: ![[BITCAST_EXPR]] = !DIExpression(DW_OP_plus, 0)
-; CHECK: ![[GEP0_EXPR]] = !DIExpression(DW_OP_minus, 8, DW_OP_plus, 0, DW_OP_stack_value)
-; CHECK: ![[GEP1_EXPR]] = !DIExpression(DW_OP_minus, 8, DW_OP_stack_value,
+; CHECK: ![[LOAD_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 0)
+; CHECK: ![[BITCAST_EXPR]] = !DIExpression(DW_OP_plus_uconst, 0)
+; CHECK: ![[GEP0_EXPR]] = !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_plus_uconst, 0, DW_OP_stack_value)
+; CHECK: ![[GEP1_EXPR]] = !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_stack_value,
; CHECK-SAME: DW_OP_LLVM_fragment, 0, 32)
-; CHECK: ![[GEP2_EXPR]] = !DIExpression(DW_OP_minus, 8, DW_OP_stack_value)
+; CHECK: ![[GEP2_EXPR]] = !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_stack_value)
; Function Attrs: nounwind readnone
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
@@ -130,7 +130,7 @@ attributes #1 = { nounwind readnone }
!17 = !{!18}
!18 = !DILocalVariable(name: "entry", scope: !14, file: !1, line: 6, type: !4)
!19 = !DILocation(line: 6, column: 17, scope: !14)
-!20 = !DIExpression(DW_OP_plus, 0)
+!20 = !DIExpression(DW_OP_plus_uconst, 0)
!21 = !DILocation(line: 11, column: 1, scope: !14)
!22 = distinct !DISubprogram(name: "scan", scope: !1, file: !1, line: 4, type: !15, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !17)
!23 = !DILocation(line: 6, column: 17, scope: !22)
diff --git a/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll b/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll
index 107440f10a5a..230ac1796671 100644
--- a/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll
+++ b/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll
@@ -1,10 +1,11 @@
; RUN: opt -instcombine -unfold-element-atomic-memcpy-max-elements=8 -S < %s | FileCheck %s
+; Temporarily an expected failure until inst combine is updated in the next patch
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-; Test basic unfolding
-define void @test1(i8* %Src, i8* %Dst) {
-; CHECK-LABEL: test1
-; CHECK-NOT: llvm.memcpy.element.atomic
+; Test basic unfolding -- unordered load & store
+define void @test1a(i8* %Src, i8* %Dst) {
+; CHECK-LABEL: test1a
+; CHECK-NOT: llvm.memcpy.element.unordered.atomic
; CHECK-DAG: %memcpy_unfold.src_casted = bitcast i8* %Src to i32*
; CHECK-DAG: %memcpy_unfold.dst_casted = bitcast i8* %Dst to i32*
@@ -21,7 +22,7 @@ define void @test1(i8* %Src, i8* %Dst) {
; CHECK-DAG: [[VAL4:%[^\s]+]] = load atomic i32, i32* %{{[^\s]+}} unordered, align 4
; CHECK-DAG: store atomic i32 [[VAL4]], i32* %{{[^\s]+}} unordered, align 4
entry:
- call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %Dst, i8* align 8 %Src, i64 4, i32 4)
+ call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %Dst, i8* align 4 %Src, i32 16, i32 4)
ret void
}
@@ -31,9 +32,9 @@ define void @test2(i8* %Src, i8* %Dst) {
; CHECK-NOT: load
; CHECK-NOT: store
-; CHECK: llvm.memcpy.element.atomic
+; CHECK: llvm.memcpy.element.unordered.atomic
entry:
- call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %Dst, i8* align 4 %Src, i64 1000, i32 4)
+ call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %Dst, i8* align 4 %Src, i32 256, i32 4)
ret void
}
@@ -43,16 +44,16 @@ define void @test3(i8* %Src, i8* %Dst) {
; CHECK-NOT: load
; CHECK-NOT: store
-; CHECK: llvm.memcpy.element.atomic
+; CHECK: llvm.memcpy.element.unordered.atomic
entry:
- call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 64 %Dst, i8* align 64 %Src, i64 4, i32 64)
+ call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 64 %Dst, i8* align 64 %Src, i32 64, i32 64)
ret void
}
; Test that we will eliminate redundant bitcasts
define void @test4(i64* %Src, i64* %Dst) {
; CHECK-LABEL: test4
-; CHECK-NOT: llvm.memcpy.element.atomic
+; CHECK-NOT: llvm.memcpy.element.unordered.atomic
; CHECK-NOT: bitcast
@@ -76,17 +77,18 @@ define void @test4(i64* %Src, i64* %Dst) {
entry:
%Src.casted = bitcast i64* %Src to i8*
%Dst.casted = bitcast i64* %Dst to i8*
- call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 16 %Dst.casted, i8* align 16 %Src.casted, i64 4, i32 8)
+ call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %Dst.casted, i8* align 16 %Src.casted, i32 32, i32 8)
ret void
}
+; Test that 0-length unordered atomic memcpy gets removed.
define void @test5(i8* %Src, i8* %Dst) {
; CHECK-LABEL: test5
-; CHECK-NOT: llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 64 %Dst, i8* align 64 %Src, i64 0, i32 64)
+; CHECK-NOT: llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 64 %Dst, i8* align 64 %Src, i32 0, i32 8)
entry:
- call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 64 %Dst, i8* align 64 %Src, i64 0, i32 64)
+ call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 64 %Dst, i8* align 64 %Src, i32 0, i32 8)
ret void
}
-declare void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* nocapture, i8* nocapture, i64, i32)
+declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind
diff --git a/test/Transforms/InstCombine/ffs-1.ll b/test/Transforms/InstCombine/ffs-1.ll
index d27fb5d89f09..af4ee85216ef 100644
--- a/test/Transforms/InstCombine/ffs-1.ll
+++ b/test/Transforms/InstCombine/ffs-1.ll
@@ -1,12 +1,12 @@
; Test that the ffs* library call simplifier works correctly.
;
-; RUN: opt < %s -instcombine -S | FileCheck %s
-; RUN: opt < %s -mtriple i386-pc-linux -instcombine -S | FileCheck %s -check-prefix=CHECK-FFS
-; RUN: opt -instcombine -mtriple=arm64-apple-ios9.0 -S %s | FileCheck --check-prefix=CHECK-FFS %s
-; RUN: opt -instcombine -mtriple=arm64-apple-tvos9.0 -S %s | FileCheck --check-prefix=CHECK-FFS %s
-; RUN: opt -instcombine -mtriple=thumbv7k-apple-watchos2.0 -S %s | FileCheck --check-prefix=CHECK-FFS %s
-; RUN: opt -instcombine -mtriple=x86_64-apple-macosx10.11 -S %s | FileCheck --check-prefix=CHECK-FFS %s
-; RUN: opt -instcombine -mtriple=x86_64-freebsd-gnu -S %s | FileCheck --check-prefix=CHECK-FFS %s
+; RUN: opt < %s -instcombine -S | FileCheck %s --check-prefix=ALL --check-prefix=GENERIC
+; RUN: opt < %s -instcombine -mtriple i386-pc-linux -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET
+; RUN: opt < %s -instcombine -mtriple=arm64-apple-ios9.0 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET
+; RUN: opt < %s -instcombine -mtriple=arm64-apple-tvos9.0 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET
+; RUN: opt < %s -instcombine -mtriple=thumbv7k-apple-watchos2.0 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET
+; RUN: opt < %s -instcombine -mtriple=x86_64-apple-macosx10.11 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET
+; RUN: opt < %s -instcombine -mtriple=x86_64-freebsd-gnu -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET
declare i32 @ffs(i32)
declare i32 @ffsl(i32)
@@ -15,123 +15,179 @@ declare i32 @ffsll(i64)
; Check ffs(0) -> 0.
define i32 @test_simplify1() {
-; CHECK-LABEL: @test_simplify1(
+; ALL-LABEL: @test_simplify1(
+; ALL-NEXT: ret i32 0
+;
%ret = call i32 @ffs(i32 0)
ret i32 %ret
-; CHECK-NEXT: ret i32 0
}
define i32 @test_simplify2() {
-; CHECK-FFS-LABEL: @test_simplify2(
+; GENERIC-LABEL: @test_simplify2(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsl(i32 0)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify2(
+; TARGET-NEXT: ret i32 0
+;
%ret = call i32 @ffsl(i32 0)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 0
}
define i32 @test_simplify3() {
-; CHECK-FFS-LABEL: @test_simplify3(
+; GENERIC-LABEL: @test_simplify3(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 0)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify3(
+; TARGET-NEXT: ret i32 0
+;
%ret = call i32 @ffsll(i64 0)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 0
}
; Check ffs(c) -> cttz(c) + 1, where 'c' is a constant.
define i32 @test_simplify4() {
-; CHECK-LABEL: @test_simplify4(
+; ALL-LABEL: @test_simplify4(
+; ALL-NEXT: ret i32 1
+;
%ret = call i32 @ffs(i32 1)
ret i32 %ret
-; CHECK-NEXT: ret i32 1
}
define i32 @test_simplify5() {
-; CHECK-LABEL: @test_simplify5(
+; ALL-LABEL: @test_simplify5(
+; ALL-NEXT: ret i32 12
+;
%ret = call i32 @ffs(i32 2048)
ret i32 %ret
-; CHECK-NEXT: ret i32 12
}
define i32 @test_simplify6() {
-; CHECK-LABEL: @test_simplify6(
+; ALL-LABEL: @test_simplify6(
+; ALL-NEXT: ret i32 17
+;
%ret = call i32 @ffs(i32 65536)
ret i32 %ret
-; CHECK-NEXT: ret i32 17
}
define i32 @test_simplify7() {
-; CHECK-FFS-LABEL: @test_simplify7(
+; GENERIC-LABEL: @test_simplify7(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsl(i32 65536)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify7(
+; TARGET-NEXT: ret i32 17
+;
%ret = call i32 @ffsl(i32 65536)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 17
}
define i32 @test_simplify8() {
-; CHECK-FFS-LABEL: @test_simplify8(
+; GENERIC-LABEL: @test_simplify8(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 1024)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify8(
+; TARGET-NEXT: ret i32 11
+;
%ret = call i32 @ffsll(i64 1024)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 11
}
define i32 @test_simplify9() {
-; CHECK-FFS-LABEL: @test_simplify9(
+; GENERIC-LABEL: @test_simplify9(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 65536)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify9(
+; TARGET-NEXT: ret i32 17
+;
%ret = call i32 @ffsll(i64 65536)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 17
}
define i32 @test_simplify10() {
-; CHECK-FFS-LABEL: @test_simplify10(
+; GENERIC-LABEL: @test_simplify10(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 17179869184)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify10(
+; TARGET-NEXT: ret i32 35
+;
%ret = call i32 @ffsll(i64 17179869184)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 35
}
define i32 @test_simplify11() {
-; CHECK-FFS-LABEL: @test_simplify11(
+; GENERIC-LABEL: @test_simplify11(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 281474976710656)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify11(
+; TARGET-NEXT: ret i32 49
+;
%ret = call i32 @ffsll(i64 281474976710656)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 49
}
define i32 @test_simplify12() {
-; CHECK-FFS-LABEL: @test_simplify12(
+; GENERIC-LABEL: @test_simplify12(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 1152921504606846976)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify12(
+; TARGET-NEXT: ret i32 61
+;
%ret = call i32 @ffsll(i64 1152921504606846976)
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 61
}
; Check ffs(x) -> x != 0 ? (i32)llvm.cttz(x) + 1 : 0.
define i32 @test_simplify13(i32 %x) {
-; CHECK-LABEL: @test_simplify13(
+; ALL-LABEL: @test_simplify13(
+; ALL-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+; ALL-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
+; ALL-NEXT: [[TMP2:%.*]] = icmp ne i32 %x, 0
+; ALL-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0
+; ALL-NEXT: ret i32 [[TMP3]]
+;
%ret = call i32 @ffs(i32 %x)
-; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
-; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
-; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0
-; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
ret i32 %ret
-; CHECK-NEXT: ret i32 [[RET]]
}
define i32 @test_simplify14(i32 %x) {
-; CHECK-FFS-LABEL: @test_simplify14(
+; GENERIC-LABEL: @test_simplify14(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsl(i32 %x)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify14(
+; TARGET-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
+; TARGET-NEXT: [[TMP2:%.*]] = icmp ne i32 %x, 0
+; TARGET-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0
+; TARGET-NEXT: ret i32 [[TMP3]]
+;
%ret = call i32 @ffsl(i32 %x)
-; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
-; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
-; CHECK-FFS-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0
-; CHECK-FFS-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 [[RET]]
}
define i32 @test_simplify15(i64 %x) {
-; CHECK-FFS-LABEL: @test_simplify15(
+; GENERIC-LABEL: @test_simplify15(
+; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 %x)
+; GENERIC-NEXT: ret i32 [[RET]]
+;
+; TARGET-LABEL: @test_simplify15(
+; TARGET-NEXT: [[CTTZ:%.*]] = call i64 @llvm.cttz.i64(i64 %x, i1 true)
+; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[CTTZ]], 1
+; TARGET-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
+; TARGET-NEXT: [[TMP3:%.*]] = icmp ne i64 %x, 0
+; TARGET-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 0
+; TARGET-NEXT: ret i32 [[TMP4]]
+;
%ret = call i32 @ffsll(i64 %x)
-; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 true)
-; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1
-; CHECK-FFS-NEXT: [[TRUNC:%[a-z0-9]+]] = trunc i64 [[INC]] to i32
-; CHECK-FFS-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i64 %x, 0
-; CHECK-FFS-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[TRUNC]], i32 0
ret i32 %ret
-; CHECK-FFS-NEXT: ret i32 [[RET]]
}
+
diff --git a/test/Transforms/InstCombine/lshr.ll b/test/Transforms/InstCombine/lshr.ll
index 71b25177162b..4cdcb98f730c 100644
--- a/test/Transforms/InstCombine/lshr.ll
+++ b/test/Transforms/InstCombine/lshr.ll
@@ -122,10 +122,19 @@ define <2 x i8> @bool_zext_splat(<2 x i1> %x) {
ret <2 x i8> %hibit
}
-; FIXME: The replicated sign bits are all that's left. This could be ashr+zext.
-
-define i16 @smear_sign_and_widen(i4 %x) {
+define i32 @smear_sign_and_widen(i8 %x) {
; CHECK-LABEL: @smear_sign_and_widen(
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 7
+; CHECK-NEXT: [[HIBIT:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT: ret i32 [[HIBIT]]
+;
+ %sext = sext i8 %x to i32
+ %hibit = lshr i32 %sext, 24
+ ret i32 %hibit
+}
+
+define i16 @smear_sign_and_widen_should_not_change_type(i4 %x) {
+; CHECK-LABEL: @smear_sign_and_widen_should_not_change_type(
; CHECK-NEXT: [[SEXT:%.*]] = sext i4 %x to i16
; CHECK-NEXT: [[HIBIT:%.*]] = lshr i16 [[SEXT]], 12
; CHECK-NEXT: ret i16 [[HIBIT]]
@@ -137,8 +146,8 @@ define i16 @smear_sign_and_widen(i4 %x) {
define <2 x i8> @smear_sign_and_widen_splat(<2 x i6> %x) {
; CHECK-LABEL: @smear_sign_and_widen_splat(
-; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i6> %x to <2 x i8>
-; CHECK-NEXT: [[HIBIT:%.*]] = lshr <2 x i8> [[SEXT]], <i8 2, i8 2>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i6> %x, <i6 2, i6 2>
+; CHECK-NEXT: [[HIBIT:%.*]] = zext <2 x i6> [[TMP1]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[HIBIT]]
;
%sext = sext <2 x i6> %x to <2 x i8>
diff --git a/test/Transforms/InstCombine/onehot_merge.ll b/test/Transforms/InstCombine/onehot_merge.ll
index 496d847b5321..47a4ca4b628b 100644
--- a/test/Transforms/InstCombine/onehot_merge.ll
+++ b/test/Transforms/InstCombine/onehot_merge.ll
@@ -33,3 +33,79 @@ bb:
ret i1 %or
}
+; Same as above but with operands commuted one of the ands, but not the other.
+define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) {
+; CHECK-LABEL: @foo1_and_commuted(
+; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
+; CHECK-NEXT: [[TMP:%.*]] = shl i32 1, [[C1:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
+; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[TMP]], [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K2]], [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %k2 = mul i32 %k, %k ; to trick the complexity sorting
+ %tmp = shl i32 1, %c1
+ %tmp4 = lshr i32 -2147483648, %c2
+ %tmp1 = and i32 %k2, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ %tmp5 = and i32 %tmp4, %k2
+ %tmp6 = icmp eq i32 %tmp5, 0
+ %or = or i1 %tmp2, %tmp6
+ ret i1 %or
+}
+
+define i1 @or_consts(i32 %k, i32 %c1, i32 %c2) {
+; CHECK-LABEL: @or_consts(
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 12
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+ %tmp1 = and i32 4, %k
+ %tmp2 = icmp ne i32 %tmp1, 0
+ %tmp5 = and i32 8, %k
+ %tmp6 = icmp ne i32 %tmp5, 0
+ %or = and i1 %tmp2, %tmp6
+ ret i1 %or
+}
+
+define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) {
+; CHECK-LABEL: @foo1_or(
+; CHECK-NEXT: [[TMP:%.*]] = shl i32 1, [[C1:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP]], [[TMP4]]
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[TMP3]]
+;
+ %tmp = shl i32 1, %c1
+ %tmp4 = lshr i32 -2147483648, %c2
+ %tmp1 = and i32 %tmp, %k
+ %tmp2 = icmp ne i32 %tmp1, 0
+ %tmp5 = and i32 %tmp4, %k
+ %tmp6 = icmp ne i32 %tmp5, 0
+ %or = and i1 %tmp2, %tmp6
+ ret i1 %or
+}
+
+; Same as above but with operands commuted one of the ors, but not the other.
+define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) {
+; CHECK-LABEL: @foo1_or_commuted(
+; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]
+; CHECK-NEXT: [[TMP:%.*]] = shl i32 1, [[C1:%.*]]
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 -2147483648, [[C2:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP]], [[TMP4]]
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT: ret i1 [[TMP3]]
+;
+ %k2 = mul i32 %k, %k ; to trick the complexity sorting
+ %tmp = shl i32 1, %c1
+ %tmp4 = lshr i32 -2147483648, %c2
+ %tmp1 = and i32 %k2, %tmp
+ %tmp2 = icmp ne i32 %tmp1, 0
+ %tmp5 = and i32 %tmp4, %k2
+ %tmp6 = icmp ne i32 %tmp5, 0
+ %or = and i1 %tmp2, %tmp6
+ ret i1 %or
+}
diff --git a/test/Transforms/InstCombine/or-xor.ll b/test/Transforms/InstCombine/or-xor.ll
index f2bc290d79a4..485f9612376a 100644
--- a/test/Transforms/InstCombine/or-xor.ll
+++ b/test/Transforms/InstCombine/or-xor.ll
@@ -114,6 +114,17 @@ define i32 @test10(i32 %A, i32 %B) {
ret i32 %or
}
+define i32 @test10_commuted(i32 %A, i32 %B) {
+; CHECK-LABEL: @test10_commuted(
+; CHECK-NEXT: ret i32 -1
+;
+ %xor1 = xor i32 %B, %A
+ %not = xor i32 %A, -1
+ %xor2 = xor i32 %not, %B
+ %or = or i32 %xor2, %xor1
+ ret i32 %or
+}
+
; (x | y) & ((~x) ^ y) -> (x & y)
define i32 @test11(i32 %x, i32 %y) {
; CHECK-LABEL: @test11(
@@ -300,3 +311,36 @@ define i8 @or_xor_or(i8 %x) {
ret i8 %or2
}
+define i8 @test17(i8 %A, i8 %B) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
+; CHECK-NEXT: [[OR:%.*]] = or i8 [[XOR1]], [[XOR2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i8 [[OR]], [[XOR2]]
+; CHECK-NEXT: ret i8 [[RES]]
+;
+ %xor1 = xor i8 %B, %A
+ %not = xor i8 %A, 33
+ %xor2 = xor i8 %not, %B
+ %or = or i8 %xor1, %xor2
+ %res = mul i8 %or, %xor2 ; to increase the use count for the xor
+ ret i8 %res
+}
+
+define i8 @test18(i8 %A, i8 %B) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
+; CHECK-NEXT: [[OR:%.*]] = or i8 [[XOR2]], [[XOR1]]
+; CHECK-NEXT: [[RES:%.*]] = mul i8 [[OR]], [[XOR2]]
+; CHECK-NEXT: ret i8 [[RES]]
+;
+ %xor1 = xor i8 %B, %A
+ %not = xor i8 %A, 33
+ %xor2 = xor i8 %not, %B
+ %or = or i8 %xor2, %xor1
+ %res = mul i8 %or, %xor2 ; to increase the use count for the xor
+ ret i8 %res
+}
diff --git a/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/test/Transforms/InstCombine/select-with-bitwise-ops.ll
index 68b73af21a8d..faeb4e046aca 100644
--- a/test/Transforms/InstCombine/select-with-bitwise-ops.ll
+++ b/test/Transforms/InstCombine/select-with-bitwise-ops.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "n8:16:32:64"
+
define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2(
; CHECK-NEXT: [[AND:%.*]] = shl i32 %x, 1
@@ -295,3 +297,269 @@ define i32 @test67(i16 %x) {
ret i32 %3
}
+define i32 @test68(i32 %x, i32 %y) {
+; CHECK-LABEL: @test68(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[TMP1]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define i32 @test69(i32 %x, i32 %y) {
+; CHECK-LABEL: @test69(
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[SELECT]]
+;
+ %and = and i32 %x, 128
+ %cmp = icmp ne i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %select
+}
+
+define i32 @shift_no_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_no_xor_multiuse_or(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @no_shift_xor_multiuse_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+; TODO this increased the number of instructions
+define i32 @shift_xor_multiuse_or(i32 %x, i32 %y) {
+; CHECK-LABEL: @shift_xor_multiuse_or(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2048
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2048
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP3]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %res = mul i32 %select, %or ; to bump up use count of the Or
+ ret i32 %res
+}
+
+define i32 @shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+define i32 @no_shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+; TODO this increased the number of instructions
+define i32 @shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[AND]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2048
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP3]], [[SELECT2]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ ret i32 %res
+}
+
+; TODO this increased the number of instructions
+define i32 @shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_no_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 1
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 2
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
+
+define i32 @no_shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp eq i32 %and, 0
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
+
+; TODO this increased the number of instructions
+define i32 @no_shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @no_shift_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
+; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 4096
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
+
+; TODO this increased the number of instructions
+define i32 @shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) {
+; CHECK-LABEL: @shift_xor_multiuse_cmp_or(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
+; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[AND]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2048
+; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP3]], [[SELECT2]]
+; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
+; CHECK-NEXT: ret i32 [[RES2]]
+;
+ %and = and i32 %x, 4096
+ %cmp = icmp ne i32 0, %and
+ %or = or i32 %y, 2048
+ %select = select i1 %cmp, i32 %y, i32 %or
+ %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp
+ %res = mul i32 %select, %select2
+ %res2 = mul i32 %res, %or ; to bump up the use count of the or
+ ret i32 %res2
+}
diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll
index ce8e2fcd38b9..68bbf35d1e65 100644
--- a/test/Transforms/InstCombine/shift.ll
+++ b/test/Transforms/InstCombine/shift.ll
@@ -1306,3 +1306,13 @@ define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) {
ret <2 x i8> %shr
}
+; Make sure known bits works correctly with non power of 2 bit widths.
+define i7 @test65(i7 %a, i7 %b) {
+; CHECK-LABEL: @test65(
+; CHECK-NEXT: ret i7 0
+;
+ %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width.
+ %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit.
+ %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0.
+ ret i7 %y
+}
diff --git a/test/Transforms/InstCombine/xor2.ll b/test/Transforms/InstCombine/xor2.ll
index 3afbf632f6e1..49e6b999fbce 100644
--- a/test/Transforms/InstCombine/xor2.ll
+++ b/test/Transforms/InstCombine/xor2.ll
@@ -325,3 +325,36 @@ define i32 @test14(i32 %a, i32 %b, i32 %c) {
ret i32 %xor
}
+define i8 @test15(i8 %A, i8 %B) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[XOR1]], [[XOR2]]
+; CHECK-NEXT: [[RES:%.*]] = mul i8 [[AND]], [[XOR2]]
+; CHECK-NEXT: ret i8 [[RES]]
+;
+ %xor1 = xor i8 %B, %A
+ %not = xor i8 %A, 33
+ %xor2 = xor i8 %not, %B
+ %and = and i8 %xor1, %xor2
+ %res = mul i8 %and, %xor2 ; to increase the use count for the xor
+ ret i8 %res
+}
+
+define i8 @test16(i8 %A, i8 %B) {
+; CHECK-LABEL: @test16(
+; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
+; CHECK-NEXT: [[AND:%.*]] = and i8 [[XOR2]], [[XOR1]]
+; CHECK-NEXT: [[RES:%.*]] = mul i8 [[AND]], [[XOR2]]
+; CHECK-NEXT: ret i8 [[RES]]
+;
+ %xor1 = xor i8 %B, %A
+ %not = xor i8 %A, 33
+ %xor2 = xor i8 %not, %B
+ %and = and i8 %xor2, %xor1
+ %res = mul i8 %and, %xor2 ; to increase the use count for the xor
+ ret i8 %res
+}
generated by cgit v1.3 (git 2.53.0) at 2026-09-04 22:11:24 +0000