diff options
Diffstat (limited to 'utils/TableGen/CodeGenRegisters.cpp')
| -rw-r--r-- | utils/TableGen/CodeGenRegisters.cpp | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 74a2b078dfb3..f87c6d6c945a 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -1,9 +1,8 @@ //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -740,8 +739,9 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { Record *Type = TypeList[i]; if (!Type->isSubClassOf("ValueType")) - PrintFatalError("RegTypes list member '" + Type->getName() + - "' does not derive from the ValueType class!"); + PrintFatalError(R->getLoc(), + "RegTypes list member '" + Type->getName() + + "' does not derive from the ValueType class!"); VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes())); } assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); @@ -2101,8 +2101,7 @@ void CodeGenRegBank::computeDerivedInfo() { for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) RegUnitSetOrder.push_back(Idx); - std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(), - [this](unsigned ID1, unsigned ID2) { + llvm::stable_sort(RegUnitSetOrder, [this](unsigned ID1, unsigned ID2) { return getRegPressureSet(ID1).Units.size() < getRegPressureSet(ID2).Units.size(); }); |