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-rw-r--r--utils/TableGen/CodeGenSchedule.cpp300
1 files changed, 141 insertions, 159 deletions
diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp
index 50569b2ad989..b753e19a5443 100644
--- a/utils/TableGen/CodeGenSchedule.cpp
+++ b/utils/TableGen/CodeGenSchedule.cpp
@@ -64,9 +64,8 @@ struct InstRegexOp : public SetTheory::Operator {
void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
ArrayRef<SMLoc> Loc) override {
SmallVector<Regex, 4> RegexList;
- for (DagInit::const_arg_iterator
- AI = Expr->arg_begin(), AE = Expr->arg_end(); AI != AE; ++AI) {
- StringInit *SI = dyn_cast<StringInit>(*AI);
+ for (Init *Arg : make_range(Expr->arg_begin(), Expr->arg_end())) {
+ StringInit *SI = dyn_cast<StringInit>(Arg);
if (!SI)
PrintFatalError(Loc, "instregex requires pattern string: "
+ Expr->getAsString());
@@ -162,8 +161,8 @@ void CodeGenSchedModels::collectProcModels() {
// For each processor, find a unique machine model.
DEBUG(dbgs() << "+++ PROCESSOR MODELs (addProcModel) +++\n");
- for (unsigned i = 0, N = ProcRecords.size(); i < N; ++i)
- addProcModel(ProcRecords[i]);
+ for (Record *ProcRecord : ProcRecords)
+ addProcModel(ProcRecord);
}
/// Get a unique processor model based on the defined MachineModel and
@@ -194,20 +193,20 @@ static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
if (!RWSet.insert(RWDef).second)
return;
RWDefs.push_back(RWDef);
- // Reads don't current have sequence records, but it can be added later.
+ // Reads don't currently have sequence records, but it can be added later.
if (RWDef->isSubClassOf("WriteSequence")) {
RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
- for (RecIter I = Seq.begin(), E = Seq.end(); I != E; ++I)
- scanSchedRW(*I, RWDefs, RWSet);
+ for (Record *WSRec : Seq)
+ scanSchedRW(WSRec, RWDefs, RWSet);
}
else if (RWDef->isSubClassOf("SchedVariant")) {
// Visit each variant (guarded by a different predicate).
RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
- for (RecIter VI = Vars.begin(), VE = Vars.end(); VI != VE; ++VI) {
+ for (Record *Variant : Vars) {
// Visit each RW in the sequence selected by the current variant.
- RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
- for (RecIter I = Selected.begin(), E = Selected.end(); I != E; ++I)
- scanSchedRW(*I, RWDefs, RWSet);
+ RecVec Selected = Variant->getValueAsListOfDefs("Selected");
+ for (Record *SelDef : Selected)
+ scanSchedRW(SelDef, RWDefs, RWSet);
}
}
}
@@ -228,42 +227,40 @@ void CodeGenSchedModels::collectSchedRW() {
if (SchedDef->isValueUnset("SchedRW"))
continue;
RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
- for (RecIter RWI = RWs.begin(), RWE = RWs.end(); RWI != RWE; ++RWI) {
- if ((*RWI)->isSubClassOf("SchedWrite"))
- scanSchedRW(*RWI, SWDefs, RWSet);
+ for (Record *RW : RWs) {
+ if (RW->isSubClassOf("SchedWrite"))
+ scanSchedRW(RW, SWDefs, RWSet);
else {
- assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
- scanSchedRW(*RWI, SRDefs, RWSet);
+ assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
+ scanSchedRW(RW, SRDefs, RWSet);
}
}
}
// Find all ReadWrites referenced by InstRW.
RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
- for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI) {
+ for (Record *InstRWDef : InstRWDefs) {
// For all OperandReadWrites.
- RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
- for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
- RWI != RWE; ++RWI) {
- if ((*RWI)->isSubClassOf("SchedWrite"))
- scanSchedRW(*RWI, SWDefs, RWSet);
+ RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");
+ for (Record *RWDef : RWDefs) {
+ if (RWDef->isSubClassOf("SchedWrite"))
+ scanSchedRW(RWDef, SWDefs, RWSet);
else {
- assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
- scanSchedRW(*RWI, SRDefs, RWSet);
+ assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
+ scanSchedRW(RWDef, SRDefs, RWSet);
}
}
}
// Find all ReadWrites referenced by ItinRW.
RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
- for (RecIter II = ItinRWDefs.begin(), IE = ItinRWDefs.end(); II != IE; ++II) {
+ for (Record *ItinRWDef : ItinRWDefs) {
// For all OperandReadWrites.
- RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites");
- for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
- RWI != RWE; ++RWI) {
- if ((*RWI)->isSubClassOf("SchedWrite"))
- scanSchedRW(*RWI, SWDefs, RWSet);
+ RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");
+ for (Record *RWDef : RWDefs) {
+ if (RWDef->isSubClassOf("SchedWrite"))
+ scanSchedRW(RWDef, SWDefs, RWSet);
else {
- assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
- scanSchedRW(*RWI, SRDefs, RWSet);
+ assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
+ scanSchedRW(RWDef, SRDefs, RWSet);
}
}
}
@@ -271,50 +268,49 @@ void CodeGenSchedModels::collectSchedRW() {
// for the loop below that initializes Alias vectors.
RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");
std::sort(AliasDefs.begin(), AliasDefs.end(), LessRecord());
- for (RecIter AI = AliasDefs.begin(), AE = AliasDefs.end(); AI != AE; ++AI) {
- Record *MatchDef = (*AI)->getValueAsDef("MatchRW");
- Record *AliasDef = (*AI)->getValueAsDef("AliasRW");
+ for (Record *ADef : AliasDefs) {
+ Record *MatchDef = ADef->getValueAsDef("MatchRW");
+ Record *AliasDef = ADef->getValueAsDef("AliasRW");
if (MatchDef->isSubClassOf("SchedWrite")) {
if (!AliasDef->isSubClassOf("SchedWrite"))
- PrintFatalError((*AI)->getLoc(), "SchedWrite Alias must be SchedWrite");
+ PrintFatalError(ADef->getLoc(), "SchedWrite Alias must be SchedWrite");
scanSchedRW(AliasDef, SWDefs, RWSet);
}
else {
assert(MatchDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
if (!AliasDef->isSubClassOf("SchedRead"))
- PrintFatalError((*AI)->getLoc(), "SchedRead Alias must be SchedRead");
+ PrintFatalError(ADef->getLoc(), "SchedRead Alias must be SchedRead");
scanSchedRW(AliasDef, SRDefs, RWSet);
}
}
// Sort and add the SchedReadWrites directly referenced by instructions or
// itinerary resources. Index reads and writes in separate domains.
std::sort(SWDefs.begin(), SWDefs.end(), LessRecord());
- for (RecIter SWI = SWDefs.begin(), SWE = SWDefs.end(); SWI != SWE; ++SWI) {
- assert(!getSchedRWIdx(*SWI, /*IsRead=*/false) && "duplicate SchedWrite");
- SchedWrites.emplace_back(SchedWrites.size(), *SWI);
+ for (Record *SWDef : SWDefs) {
+ assert(!getSchedRWIdx(SWDef, /*IsRead=*/false) && "duplicate SchedWrite");
+ SchedWrites.emplace_back(SchedWrites.size(), SWDef);
}
std::sort(SRDefs.begin(), SRDefs.end(), LessRecord());
- for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) {
- assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite");
- SchedReads.emplace_back(SchedReads.size(), *SRI);
+ for (Record *SRDef : SRDefs) {
+ assert(!getSchedRWIdx(SRDef, /*IsRead-*/true) && "duplicate SchedWrite");
+ SchedReads.emplace_back(SchedReads.size(), SRDef);
}
// Initialize WriteSequence vectors.
- for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
- WE = SchedWrites.end(); WI != WE; ++WI) {
- if (!WI->IsSequence)
+ for (CodeGenSchedRW &CGRW : SchedWrites) {
+ if (!CGRW.IsSequence)
continue;
- findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
+ findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
/*IsRead=*/false);
}
// Initialize Aliases vectors.
- for (RecIter AI = AliasDefs.begin(), AE = AliasDefs.end(); AI != AE; ++AI) {
- Record *AliasDef = (*AI)->getValueAsDef("AliasRW");
+ for (Record *ADef : AliasDefs) {
+ Record *AliasDef = ADef->getValueAsDef("AliasRW");
getSchedRW(AliasDef).IsAlias = true;
- Record *MatchDef = (*AI)->getValueAsDef("MatchRW");
+ Record *MatchDef = ADef->getValueAsDef("MatchRW");
CodeGenSchedRW &RW = getSchedRW(MatchDef);
if (RW.IsAlias)
- PrintFatalError((*AI)->getLoc(), "Cannot Alias an Alias");
- RW.Aliases.push_back(*AI);
+ PrintFatalError(ADef->getLoc(), "Cannot Alias an Alias");
+ RW.Aliases.push_back(ADef);
}
DEBUG(
dbgs() << "\n+++ SCHED READS and WRITES (collectSchedRW) +++\n";
@@ -329,12 +325,11 @@ void CodeGenSchedModels::collectSchedRW() {
dbgs() << '\n';
}
RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");
- for (RecIter RI = RWDefs.begin(), RE = RWDefs.end();
- RI != RE; ++RI) {
- if (!getSchedRWIdx(*RI, (*RI)->isSubClassOf("SchedRead"))) {
- const std::string &Name = (*RI)->getName();
+ for (Record *RWDef : RWDefs) {
+ if (!getSchedRWIdx(RWDef, RWDef->isSubClassOf("SchedRead"))) {
+ const std::string &Name = RWDef->getName();
if (Name != "NoWrite" && Name != "ReadDefault")
- dbgs() << "Unused SchedReadWrite " << (*RI)->getName() << '\n';
+ dbgs() << "Unused SchedReadWrite " << RWDef->getName() << '\n';
}
});
}
@@ -364,8 +359,8 @@ unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead,
}
bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
- for (unsigned i = 0, e = SchedReads.size(); i < e; ++i) {
- Record *ReadDef = SchedReads[i].TheDef;
+ for (const CodeGenSchedRW &Read : SchedReads) {
+ Record *ReadDef = Read.TheDef;
if (!ReadDef || !ReadDef->isSubClassOf("ProcReadAdvance"))
continue;
@@ -381,12 +376,12 @@ namespace llvm {
void splitSchedReadWrites(const RecVec &RWDefs,
RecVec &WriteDefs, RecVec &ReadDefs) {
- for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) {
- if ((*RWI)->isSubClassOf("SchedWrite"))
- WriteDefs.push_back(*RWI);
+ for (Record *RWDef : RWDefs) {
+ if (RWDef->isSubClassOf("SchedWrite"))
+ WriteDefs.push_back(RWDef);
else {
- assert((*RWI)->isSubClassOf("SchedRead") && "unknown SchedReadWrite");
- ReadDefs.push_back(*RWI);
+ assert(RWDef->isSubClassOf("SchedRead") && "unknown SchedReadWrite");
+ ReadDefs.push_back(RWDef);
}
}
}
@@ -406,8 +401,8 @@ void CodeGenSchedModels::findRWs(const RecVec &RWDefs,
// Call getSchedRWIdx for all elements in a sequence of SchedRW defs.
void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,
bool IsRead) const {
- for (RecIter RI = RWDefs.begin(), RE = RWDefs.end(); RI != RE; ++RI) {
- unsigned Idx = getSchedRWIdx(*RI, IsRead);
+ for (Record *RWDef : RWDefs) {
+ unsigned Idx = getSchedRWIdx(RWDef, IsRead);
assert(Idx && "failed to collect SchedReadWrite");
RWs.push_back(Idx);
}
@@ -423,9 +418,8 @@ void CodeGenSchedModels::expandRWSequence(unsigned RWIdx, IdxVec &RWSeq,
int Repeat =
SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
for (int i = 0; i < Repeat; ++i) {
- for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end();
- I != E; ++I) {
- expandRWSequence(*I, RWSeq, IsRead);
+ for (unsigned I : SchedRW.Sequence) {
+ expandRWSequence(I, RWSeq, IsRead);
}
}
}
@@ -464,9 +458,8 @@ void CodeGenSchedModels::expandRWSeqForProc(
int Repeat =
SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1;
for (int i = 0; i < Repeat; ++i) {
- for (IdxIter I = SchedWrite.Sequence.begin(), E = SchedWrite.Sequence.end();
- I != E; ++I) {
- expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel);
+ for (unsigned I : SchedWrite.Sequence) {
+ expandRWSeqForProc(I, RWSeq, IsRead, ProcModel);
}
}
}
@@ -535,8 +528,8 @@ void CodeGenSchedModels::collectSchedClasses() {
RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
std::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord());
DEBUG(dbgs() << "\n+++ SCHED CLASSES (createInstRWClass) +++\n");
- for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI)
- createInstRWClass(*OI);
+ for (Record *RWDef : InstRWDefs)
+ createInstRWClass(RWDef);
NumInstrSchedClasses = SchedClasses.size();
@@ -575,29 +568,27 @@ void CodeGenSchedModels::collectSchedClasses() {
dbgs() << '\n';
}
const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
- for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
- RWI != RWE; ++RWI) {
+ for (Record *RWDef : RWDefs) {
const CodeGenProcModel &ProcModel =
- getProcModel((*RWI)->getValueAsDef("SchedModel"));
+ getProcModel(RWDef->getValueAsDef("SchedModel"));
ProcIndices.push_back(ProcModel.Index);
dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
IdxVec Writes;
IdxVec Reads;
- findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),
+ findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
Writes, Reads);
- for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
- dbgs() << " " << SchedWrites[*WI].Name;
- for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
- dbgs() << " " << SchedReads[*RI].Name;
+ for (unsigned WIdx : Writes)
+ dbgs() << " " << SchedWrites[WIdx].Name;
+ for (unsigned RIdx : Reads)
+ dbgs() << " " << SchedReads[RIdx].Name;
dbgs() << '\n';
}
// If ProcIndices contains zero, the class applies to all processors.
if (!std::count(ProcIndices.begin(), ProcIndices.end(), 0)) {
- for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
- PE = ProcModels.end(); PI != PE; ++PI) {
- if (!std::count(ProcIndices.begin(), ProcIndices.end(), PI->Index))
+ for (const CodeGenProcModel &PM : ProcModels) {
+ if (!std::count(ProcIndices.begin(), ProcIndices.end(), PM.Index))
dbgs() << "No machine model for " << Inst->TheDef->getName()
- << " on processor " << PI->ModelName << '\n';
+ << " on processor " << PM.ModelName << '\n';
}
}
}
@@ -700,10 +691,10 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
if (InstDefs->empty())
PrintFatalError(InstRWDef->getLoc(), "No matching instruction opcodes");
- for (RecIter I = InstDefs->begin(), E = InstDefs->end(); I != E; ++I) {
- InstClassMapTy::const_iterator Pos = InstrClassMap.find(*I);
+ for (Record *InstDef : make_range(InstDefs->begin(), InstDefs->end())) {
+ InstClassMapTy::const_iterator Pos = InstrClassMap.find(InstDef);
if (Pos == InstrClassMap.end())
- PrintFatalError((*I)->getLoc(), "No sched class for instruction.");
+ PrintFatalError(InstDef->getLoc(), "No sched class for instruction.");
unsigned SCIdx = Pos->second;
unsigned CIdx = 0, CEnd = ClassInstrs.size();
for (; CIdx != CEnd; ++CIdx) {
@@ -714,7 +705,7 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
ClassInstrs.resize(CEnd + 1);
ClassInstrs[CIdx].first = SCIdx;
}
- ClassInstrs[CIdx].second.push_back(*I);
+ ClassInstrs[CIdx].second.push_back(InstDef);
}
// For each set of Instrs, create a new class if necessary, and map or remap
// the Instrs to it.
@@ -729,9 +720,8 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
if (!RWDefs.empty()) {
const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
unsigned OrigNumInstrs = 0;
- for (RecIter I = OrigInstDefs->begin(), E = OrigInstDefs->end();
- I != E; ++I) {
- if (InstrClassMap[*I] == OldSCIdx)
+ for (Record *OIDef : make_range(OrigInstDefs->begin(), OrigInstDefs->end())) {
+ if (InstrClassMap[OIDef] == OldSCIdx)
++OrigNumInstrs;
}
if (OrigNumInstrs == InstDefs.size()) {
@@ -785,9 +775,8 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
// True if collectProcItins found anything.
bool CodeGenSchedModels::hasItineraries() const {
- for (CodeGenSchedModels::ProcIter PI = procModelBegin(), PE = procModelEnd();
- PI != PE; ++PI) {
- if (PI->hasItineraries())
+ for (const CodeGenProcModel &PM : make_range(procModelBegin(),procModelEnd())) {
+ if (PM.hasItineraries())
return true;
}
return false;
@@ -808,8 +797,7 @@ void CodeGenSchedModels::collectProcItins() {
// Insert each itinerary data record in the correct position within
// the processor model's ItinDefList.
- for (unsigned i = 0, N = ItinRecords.size(); i < N; i++) {
- Record *ItinData = ItinRecords[i];
+ for (Record *ItinData : ItinRecords) {
Record *ItinDef = ItinData->getValueAsDef("TheClass");
bool FoundClass = false;
for (SchedClassIter SCI = schedClassBegin(), SCE = schedClassEnd();
@@ -841,16 +829,16 @@ void CodeGenSchedModels::collectProcItins() {
void CodeGenSchedModels::collectProcItinRW() {
RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
std::sort(ItinRWDefs.begin(), ItinRWDefs.end(), LessRecord());
- for (RecIter II = ItinRWDefs.begin(), IE = ItinRWDefs.end(); II != IE; ++II) {
- if (!(*II)->getValueInit("SchedModel")->isComplete())
- PrintFatalError((*II)->getLoc(), "SchedModel is undefined");
- Record *ModelDef = (*II)->getValueAsDef("SchedModel");
+ for (Record *RWDef : ItinRWDefs) {
+ if (!RWDef->getValueInit("SchedModel")->isComplete())
+ PrintFatalError(RWDef->getLoc(), "SchedModel is undefined");
+ Record *ModelDef = RWDef->getValueAsDef("SchedModel");
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
if (I == ProcModelMap.end()) {
- PrintFatalError((*II)->getLoc(), "Undefined SchedMachineModel "
+ PrintFatalError(RWDef->getLoc(), "Undefined SchedMachineModel "
+ ModelDef->getName());
}
- ProcModels[I->second].ItinRWDefs.push_back(*II);
+ ProcModels[I->second].ItinRWDefs.push_back(RWDef);
}
}
@@ -1006,12 +994,11 @@ private:
// conditions implicitly negate any prior condition.
bool PredTransitions::mutuallyExclusive(Record *PredDef,
ArrayRef<PredCheck> Term) {
- for (ArrayRef<PredCheck>::iterator I = Term.begin(), E = Term.end();
- I != E; ++I) {
- if (I->Predicate == PredDef)
+ for (const PredCheck &PC: Term) {
+ if (PC.Predicate == PredDef)
return false;
- const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(I->RWIdx, I->IsRead);
+ const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(PC.RWIdx, PC.IsRead);
assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant");
RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
for (RecIter VI = Variants.begin(), VE = Variants.end(); VI != VE; ++VI) {
@@ -1027,9 +1014,9 @@ static bool hasAliasedVariants(const CodeGenSchedRW &RW,
if (RW.HasVariants)
return true;
- for (RecIter I = RW.Aliases.begin(), E = RW.Aliases.end(); I != E; ++I) {
+ for (Record *Alias : RW.Aliases) {
const CodeGenSchedRW &AliasRW =
- SchedModels.getSchedRW((*I)->getValueAsDef("AliasRW"));
+ SchedModels.getSchedRW(Alias->getValueAsDef("AliasRW"));
if (AliasRW.HasVariants)
return true;
if (AliasRW.IsSequence) {
@@ -1092,8 +1079,8 @@ void PredTransitions::getIntersectingVariants(
}
// Push each variant. Assign TransVecIdx later.
const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
- for (RecIter RI = VarDefs.begin(), RE = VarDefs.end(); RI != RE; ++RI)
- Variants.push_back(TransVariant(*RI, SchedRW.Index, VarProcIdx, 0));
+ for (Record *VarDef : VarDefs)
+ Variants.push_back(TransVariant(VarDef, SchedRW.Index, VarProcIdx, 0));
if (VarProcIdx == 0)
GenericRW = true;
}
@@ -1112,8 +1099,8 @@ void PredTransitions::getIntersectingVariants(
if (AliasRW.HasVariants) {
const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");
- for (RecIter RI = VarDefs.begin(), RE = VarDefs.end(); RI != RE; ++RI)
- Variants.push_back(TransVariant(*RI, AliasRW.Index, AliasProcIdx, 0));
+ for (Record *VD : VarDefs)
+ Variants.push_back(TransVariant(VD, AliasRW.Index, AliasProcIdx, 0));
}
if (AliasRW.IsSequence) {
Variants.push_back(
@@ -1122,12 +1109,11 @@ void PredTransitions::getIntersectingVariants(
if (AliasProcIdx == 0)
GenericRW = true;
}
- for (unsigned VIdx = 0, VEnd = Variants.size(); VIdx != VEnd; ++VIdx) {
- TransVariant &Variant = Variants[VIdx];
+ for (TransVariant &Variant : Variants) {
// Don't expand variants if the processor models don't intersect.
// A zero processor index means any processor.
SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices;
- if (ProcIndices[0] && Variants[VIdx].ProcIdx) {
+ if (ProcIndices[0] && Variant.ProcIdx) {
unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
Variant.ProcIdx);
if (!Cnt)
@@ -1492,37 +1478,36 @@ void CodeGenSchedModels::collectProcResources() {
}
// Add resources separately defined by each subtarget.
RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");
- for (RecIter WRI = WRDefs.begin(), WRE = WRDefs.end(); WRI != WRE; ++WRI) {
- Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
- addWriteRes(*WRI, getProcModel(ModelDef).Index);
+ for (Record *WR : WRDefs) {
+ Record *ModelDef = WR->getValueAsDef("SchedModel");
+ addWriteRes(WR, getProcModel(ModelDef).Index);
}
RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");
- for (RecIter WRI = SWRDefs.begin(), WRE = SWRDefs.end(); WRI != WRE; ++WRI) {
- Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
- addWriteRes(*WRI, getProcModel(ModelDef).Index);
+ for (Record *SWR : SWRDefs) {
+ Record *ModelDef = SWR->getValueAsDef("SchedModel");
+ addWriteRes(SWR, getProcModel(ModelDef).Index);
}
RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");
- for (RecIter RAI = RADefs.begin(), RAE = RADefs.end(); RAI != RAE; ++RAI) {
- Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
- addReadAdvance(*RAI, getProcModel(ModelDef).Index);
+ for (Record *RA : RADefs) {
+ Record *ModelDef = RA->getValueAsDef("SchedModel");
+ addReadAdvance(RA, getProcModel(ModelDef).Index);
}
RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");
- for (RecIter RAI = SRADefs.begin(), RAE = SRADefs.end(); RAI != RAE; ++RAI) {
- if ((*RAI)->getValueInit("SchedModel")->isComplete()) {
- Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
- addReadAdvance(*RAI, getProcModel(ModelDef).Index);
+ for (Record *SRA : SRADefs) {
+ if (SRA->getValueInit("SchedModel")->isComplete()) {
+ Record *ModelDef = SRA->getValueAsDef("SchedModel");
+ addReadAdvance(SRA, getProcModel(ModelDef).Index);
}
}
// Add ProcResGroups that are defined within this processor model, which may
// not be directly referenced but may directly specify a buffer size.
RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");
- for (RecIter RI = ProcResGroups.begin(), RE = ProcResGroups.end();
- RI != RE; ++RI) {
- if (!(*RI)->getValueInit("SchedModel")->isComplete())
+ for (Record *PRG : ProcResGroups) {
+ if (!PRG->getValueInit("SchedModel")->isComplete())
continue;
- CodeGenProcModel &PM = getProcModel((*RI)->getValueAsDef("SchedModel"));
- if (!is_contained(PM.ProcResourceDefs, *RI))
- PM.ProcResourceDefs.push_back(*RI);
+ CodeGenProcModel &PM = getProcModel(PRG->getValueAsDef("SchedModel"));
+ if (!is_contained(PM.ProcResourceDefs, PRG))
+ PM.ProcResourceDefs.push_back(PRG);
}
// Finalize each ProcModel by sorting the record arrays.
for (CodeGenProcModel &PM : ProcModels) {
@@ -1687,7 +1672,8 @@ void CodeGenSchedModels::collectRWResources(ArrayRef<unsigned> Writes,
// Find the processor's resource units for this kind of resource.
Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
- const CodeGenProcModel &PM) const {
+ const CodeGenProcModel &PM,
+ ArrayRef<SMLoc> Loc) const {
if (ProcResKind->isSubClassOf("ProcResourceUnits"))
return ProcResKind;
@@ -1695,34 +1681,30 @@ Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
assert(!ProcResourceDefs.empty());
assert(!ProcResGroups.empty());
- for (RecIter RI = ProcResourceDefs.begin(), RE = ProcResourceDefs.end();
- RI != RE; ++RI) {
-
- if ((*RI)->getValueAsDef("Kind") == ProcResKind
- && (*RI)->getValueAsDef("SchedModel") == PM.ModelDef) {
+ for (Record *ProcResDef : ProcResourceDefs) {
+ if (ProcResDef->getValueAsDef("Kind") == ProcResKind
+ && ProcResDef->getValueAsDef("SchedModel") == PM.ModelDef) {
if (ProcUnitDef) {
- PrintFatalError((*RI)->getLoc(),
+ PrintFatalError(Loc,
"Multiple ProcessorResourceUnits associated with "
+ ProcResKind->getName());
}
- ProcUnitDef = *RI;
+ ProcUnitDef = ProcResDef;
}
}
- for (RecIter RI = ProcResGroups.begin(), RE = ProcResGroups.end();
- RI != RE; ++RI) {
-
- if (*RI == ProcResKind
- && (*RI)->getValueAsDef("SchedModel") == PM.ModelDef) {
+ for (Record *ProcResGroup : ProcResGroups) {
+ if (ProcResGroup == ProcResKind
+ && ProcResGroup->getValueAsDef("SchedModel") == PM.ModelDef) {
if (ProcUnitDef) {
- PrintFatalError((*RI)->getLoc(),
+ PrintFatalError(Loc,
"Multiple ProcessorResourceUnits associated with "
+ ProcResKind->getName());
}
- ProcUnitDef = *RI;
+ ProcUnitDef = ProcResGroup;
}
}
if (!ProcUnitDef) {
- PrintFatalError(ProcResKind->getLoc(),
+ PrintFatalError(Loc,
"No ProcessorResources associated with "
+ ProcResKind->getName());
}
@@ -1731,9 +1713,10 @@ Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
// Iteratively add a resource and its super resources.
void CodeGenSchedModels::addProcResource(Record *ProcResKind,
- CodeGenProcModel &PM) {
+ CodeGenProcModel &PM,
+ ArrayRef<SMLoc> Loc) {
while (true) {
- Record *ProcResUnits = findProcResUnits(ProcResKind, PM);
+ Record *ProcResUnits = findProcResUnits(ProcResKind, PM, Loc);
// See if this ProcResource is already associated with this processor.
if (is_contained(PM.ProcResourceDefs, ProcResUnits))
@@ -1763,7 +1746,7 @@ void CodeGenSchedModels::addWriteRes(Record *ProcWriteResDef, unsigned PIdx) {
RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");
for (RecIter WritePRI = ProcResDefs.begin(), WritePRE = ProcResDefs.end();
WritePRI != WritePRE; ++WritePRI) {
- addProcResource(*WritePRI, ProcModels[PIdx]);
+ addProcResource(*WritePRI, ProcModels[PIdx], ProcWriteResDef->getLoc());
}
}
@@ -1832,9 +1815,8 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
dbgs() << "\n ProcIdx: "; dumpIdxVec(ProcIndices); dbgs() << '\n';
if (!Transitions.empty()) {
dbgs() << "\n Transitions for Proc ";
- for (std::vector<CodeGenSchedTransition>::const_iterator
- TI = Transitions.begin(), TE = Transitions.end(); TI != TE; ++TI) {
- dumpIdxVec(TI->ProcIndices);
+ for (const CodeGenSchedTransition &Transition : Transitions) {
+ dumpIdxVec(Transition.ProcIndices);
}
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-01 21:53:10 +0000